Catlam LLC

United States of America

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2023 3
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Before 2020 18
IPC Class
H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material 18
H05K 3/42 - Plated through-holes 18
H05K 3/46 - Manufacturing multi-layer circuits 16
H05K 1/09 - Use of materials for the metallic pattern 14
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits 12
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Status
Pending 2
Registered / In Force 25
Found results for  patents

1.

Semi-Additive Process for Printed Circuit Boards

      
Application Number 18125667
Status Pending
Filing Date 2023-03-23
First Publication Date 2023-08-03
Owner CATLAM, LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine

Abstract

A circuit board has a dielectric core, a foil top surface, and a thin foil bottom surface with a foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling. A sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step are performed, which provide dot vias of fine linewidth and resolution.

IPC Classes  ?

  • H05K 3/42 - Plated through-holes
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • H05K 3/46 - Manufacturing multi-layer circuits
  • C25D 3/30 - ElectroplatingBaths therefor from solutions of tin
  • C25D 3/38 - ElectroplatingBaths therefor from solutions of copper
  • C25D 5/02 - Electroplating of selected surface areas
  • C25D 5/10 - Electroplating with more than one layer of the same or of different metals
  • C25D 5/48 - After-treatment of electroplated surfaces
  • C25D 5/34 - Pretreatment of metallic surfaces to be electroplated
  • C25D 7/00 - Electroplating characterised by the article coated
  • C23C 18/18 - Pretreatment of the material to be coated
  • C23C 18/38 - Coating with copper
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
  • C23C 28/02 - Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of main groups , or by combinations of methods provided for in subclasses and only coatings of metallic material
  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor

2.

CIRCUIT BOARD TRACES IN CHANNELS USING ELECTROLESS AND ELECTROPLATED DEPOSITIONS

      
Application Number US2022045247
Publication Number 2023/055947
Status In Force
Filing Date 2022-09-29
Publication Date 2023-04-06
Owner CATLAM LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Carney, Steve
  • Singh, Jagdip
  • Dutton, Steve

Abstract

A circuit layer is formed by drilling vias and forming channels in a circuit layer which has catalytic particles exposed on the surfaces, channels, and vias. A first flash electroless deposition is followed by application of dry film, followed by selective laser ablation of the dry film channels and vias. A second electroless solution is applied which provides additional deposition over the first flash electroless deposition but only on the vias and trace channel areas. An electrodeposition follows, using the first deposition as a cathode. The dry film is stripped and the first electroless layer is etched, leaving only depositions in the channels and vias.

IPC Classes  ?

  • C23C 18/54 - Contact plating, i.e. electroless electrochemical plating
  • C23C 18/40 - Coating with copper using reducing agents
  • H05K 3/42 - Plated through-holes
  • H05K 3/46 - Manufacturing multi-layer circuits

3.

Circuit Board Traces in Channels using Electroless and Electroplated Depositions

      
Application Number 17489622
Status Pending
Filing Date 2021-09-29
First Publication Date 2023-03-30
Owner CATLAM, LLC. (USA)
Inventor
  • Bahl, Kenneth S.
  • Carney, Steven
  • Singh, Jagdip
  • Dutton, Steven

Abstract

A circuit layer is formed by drilling vias and forming channels in a circuit layer which has catalytic particles exposed on the surfaces, channels, and vias. A first flash electroless deposition is followed by application of dry film, followed by selective laser ablation of the dry film channels and vias. A second electroless solution is applied which provides additional deposition over the first flash electroless deposition but only on the vias and trace channel areas. An electrodeposition follows, using the first deposition as a cathode. The dry film is stripped and the first electroless layer is etched, leaving only depositions in the channels and vias.

IPC Classes  ?

  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • H05K 3/42 - Plated through-holes
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
  • C25D 5/02 - Electroplating of selected surface areas

4.

Multi-layer circuit board with traces thicker than a circuit board

      
Application Number 17317203
Grant Number 11406024
Status In Force
Filing Date 2021-05-11
First Publication Date 2021-09-09
Grant Date 2022-08-02
Owner CATLAM, LLC (USA)
Inventor Bahl, Kenneth S.

Abstract

A multi-layer circuit board is formed multiple layers of a catalytic layer, each catalytic layer having an exclusion depth below a surface, where the cataltic particles are of sufficient density to provide electroless deposition in channels formed in the surface. A first catalytic layer has channels formed which are plated with electroless copper. Each subsequent catalytic layer is bonded or laminated to an underlying catalytic layer, a channel is formed which extends through the catalytic layer to an underlying electroless copper trace, and electroless copper is deposited into the channel to electrically connect with the underlying electroless copper trace. In this manner, traces may be formed which have a thickness greater than the thickness of a single catalytic layer.

IPC Classes  ?

  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal
  • H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 3/46 - Manufacturing multi-layer circuits
  • H05K 1/02 - Printed circuits Details

5.

Electroless and electrolytic deposition process for forming traces on a catalytic laminate

      
Application Number 17076342
Grant Number 11653453
Status In Force
Filing Date 2020-10-21
First Publication Date 2021-02-18
Grant Date 2023-05-16
Owner CATLAM, LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine

Abstract

A process for making a circuit board modifies a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. The catalytic laminate is subjected to a drilling and resin-rich surface removal operation to expose the catalytic particles, followed by an electroless plating operation which deposits a thin layer of conductive material on the surface. A photo-masking step follows to define circuit traces, after which an electro-plating deposition occurs, followed by a resist strip operation and a quick etch to remove electroless copper which was previously covered by photoresist.

IPC Classes  ?

  • H05K 3/02 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits
  • H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
  • C08K 3/34 - Silicon-containing compounds
  • C08K 3/36 - Silica
  • H05K 3/42 - Plated through-holes
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern

6.

Circuit board using non-catalytic laminate with catalytic adhesive overlay

      
Application Number 17014971
Grant Number 10959329
Status In Force
Filing Date 2020-09-08
First Publication Date 2020-12-24
Grant Date 2021-03-23
Owner CATLAM, LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine

Abstract

A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.

IPC Classes  ?

  • H05K 1/03 - Use of materials for the substrate
  • H05K 1/02 - Printed circuits Details
  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 3/42 - Plated through-holes
  • H05K 3/46 - Manufacturing multi-layer circuits
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material

7.

Process for fabrication of a printed circuit board using a semi-additive process and removable backing foil

      
Application Number 16937579
Grant Number 11638354
Status In Force
Filing Date 2020-07-24
First Publication Date 2020-12-10
Grant Date 2023-04-25
Owner CATLAM, LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine

Abstract

A method for forming a circuit board having a dielectric core, a foil top surface, and a thin foil bottom surface with a removable foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling utilizes a sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step, which provide dot vias of fine linewidth and resolution.

IPC Classes  ?

  • H05K 3/42 - Plated through-holes
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits
  • H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
  • H05K 3/46 - Manufacturing multi-layer circuits

8.

MULTI-LAYER CIRCUIT BOARD WITH TRACES THICKER THAN A CIRCUIT BOARD LAYER

      
Application Number US2019066990
Publication Number 2020/142209
Status In Force
Filing Date 2019-12-17
Publication Date 2020-07-09
Owner CATLAM, LLC (USA)
Inventor Bahl, Kenneth S.

Abstract

A multi-layer circuit board is formed multiple layers of a catalytic layer, each catalytic layer having an exclusion depth below a surface, where the cataltic particles are of sufficient density to provide electroless deposition in channels formed in the surface. A first catalytic layer has channels formed which are plated with electroless copper. Each subsequent catalytic layer is bonded or laminated to an underlying catalytic layer, a channel is formed which extends through the catalytic layer to an underlying electroless copper trace, and electroless copper is deposited into the channel to electrically connect with the underlying electroless copper trace. In this manner, traces may be formed which have a thickness greater than the thickness of a single catalytic layer.

IPC Classes  ?

  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
  • C23C 18/38 - Coating with copper
  • H05K 1/02 - Printed circuits Details
  • H05K 1/03 - Use of materials for the substrate
  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material

9.

Multi-layer circuit board with traces thicker than a circuit board layer

      
Application Number 16237702
Grant Number 11039540
Status In Force
Filing Date 2019-01-01
First Publication Date 2020-07-02
Grant Date 2021-06-15
Owner CATLAM, LLC (USA)
Inventor Bahl, Kenneth S.

Abstract

A multi-layer circuit board is formed multiple layers of a catalytic layer, each catalytic layer having an exclusion depth below a surface, where the cataltic particles are of sufficient density to provide electroless deposition in channels formed in the surface. A first catalytic layer has channels formed which are plated with electroless copper. Each subsequent catalytic layer is bonded or laminated to an underlying catalytic layer, a channel is formed which extends through the catalytic layer to an underlying electroless copper trace, and electroless copper is deposited into the channel to electrically connect with the underlying electroless copper trace. In this manner, traces may be formed which have a thickness greater than the thickness of a single catalytic layer.

IPC Classes  ?

  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
  • H05K 3/46 - Manufacturing multi-layer circuits
  • H05K 1/02 - Printed circuits Details

10.

Method for making a multi-layer circuit board using conductive paste with interposer layer

      
Application Number 16424231
Grant Number 10765003
Status In Force
Filing Date 2019-05-28
First Publication Date 2019-10-17
Grant Date 2020-09-01
Owner CATLAM, LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine

Abstract

A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.

IPC Classes  ?

  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 3/46 - Manufacturing multi-layer circuits
  • H05K 1/03 - Use of materials for the substrate
  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • H05K 3/42 - Plated through-holes

11.

CATALYTIC LAMINATE WITH CONDUCTIVE TRACES FORMED DURING LAMINATION

      
Application Number US2019021503
Publication Number 2019/173807
Status In Force
Filing Date 2019-03-09
Publication Date 2019-09-12
Owner CATLAM, LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine

Abstract

A circuit board is formed from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. Trace channels and apertures are formed into the catalytic laminate, electroless plated with a metal such as copper, filled with a conductive paste containing metallic particles, which are then melted to form traces. In a variation, multiple circuit board layers have channels formed into the surface below the exclusion depth, apertures formed, are electroless plated, and the channels and apertures filled with metal particles. Several such catalytic laminate layers are placed together and pressed together under elevated temperature until the catalytic laminate layers laminate together and metal particles form into traces for a multi-layer circuit board.

IPC Classes  ?

  • C23C 18/38 - Coating with copper
  • H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
  • H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal
  • H05K 3/46 - Manufacturing multi-layer circuits

12.

Catalytic laminate with conductive traces formed during lamination

      
Application Number 15911515
Grant Number 10827624
Status In Force
Filing Date 2018-03-05
First Publication Date 2019-09-05
Grant Date 2020-11-03
Owner CATLAM, LLC (USA)
Inventor
  • Bahl, Kenneth S
  • Karavakis, Konstantine

Abstract

A circuit board is formed from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. Trace channels and apertures are formed into the catalytic laminate, electroless plated with a metal such as copper, filled with a conductive paste containing metallic particles, which are then melted to form traces. In a variation, multiple circuit board layers have channels formed into the surface below the exclusion depth, apertures formed, are electroless plated, and the channels and apertures filled with metal particles. Several such catalytic laminate layers are placed together and pressed together under elevated temperature until the catalytic laminate layers laminate together and metal particles form into traces for a multi-layer circuit board.

IPC Classes  ?

  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
  • C23C 18/20 - Pretreatment of the material to be coated of organic surfaces, e.g. resins
  • C23C 18/38 - Coating with copper
  • H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 3/46 - Manufacturing multi-layer circuits
  • H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern

13.

Catalytic circuit board with traces and vias

      
Application Number 16381823
Grant Number 10806029
Status In Force
Filing Date 2019-04-11
First Publication Date 2019-08-01
Grant Date 2020-10-13
Owner CATLAM, LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine

Abstract

A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.

IPC Classes  ?

  • H05K 1/03 - Use of materials for the substrate
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • H05K 1/02 - Printed circuits Details
  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 3/42 - Plated through-holes
  • H05K 3/46 - Manufacturing multi-layer circuits
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal

14.

Process for printed circuit boards using backing foil

      
Application Number 15645921
Grant Number 10765012
Status In Force
Filing Date 2017-07-10
First Publication Date 2019-01-10
Grant Date 2020-09-01
Owner CATLAM, LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine

Abstract

A method for making a circuit board uses a dielectric core, and at least one thin foil bottom surface with a foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling. A sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step are performed, which provide dot vias of fine linewidth and resolution.

IPC Classes  ?

  • H05K 3/42 - Plated through-holes
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits
  • H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
  • H05K 3/46 - Manufacturing multi-layer circuits

15.

Process for forming traces on a catalytic laminate

      
Application Number 15645957
Grant Number 10849233
Status In Force
Filing Date 2017-07-10
First Publication Date 2019-01-10
Grant Date 2020-11-24
Owner CATLAM, LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine

Abstract

A process for making a circuit board from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth includes drilling holes, etching the surface to expose the catalytic particles, electroless plating the unmasked areas, applying a mask to the etched surface, electroplating the exposed areas using the electroless plating to form a continuous conductor, then stripping the mask and etching away the electroless copper deposition.

IPC Classes  ?

  • H05K 3/02 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits
  • H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
  • C08K 3/34 - Silicon-containing compounds
  • H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
  • C08K 3/36 - Silica
  • H05K 3/42 - Plated through-holes
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material

16.

Multi-layer circuit board using interposer layer and conductive paste

      
Application Number 15635201
Grant Number 10349520
Status In Force
Filing Date 2017-06-28
First Publication Date 2019-01-03
Grant Date 2019-07-09
Owner CATLAM, LLC (USA)
Inventor
  • Karavakis, Konstantine
  • Bahl, Kenneth S.

Abstract

A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.

IPC Classes  ?

  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 1/03 - Use of materials for the substrate
  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • H05K 3/42 - Plated through-holes
  • H05K 3/46 - Manufacturing multi-layer circuits

17.

Circuit board with catalytic adhesive

      
Application Number 15878398
Grant Number 10306756
Status In Force
Filing Date 2018-01-23
First Publication Date 2018-06-14
Grant Date 2019-05-28
Owner CATLAM LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine

Abstract

A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.

IPC Classes  ?

  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal
  • H05K 1/03 - Use of materials for the substrate
  • H05K 1/02 - Printed circuits Details
  • H05K 3/42 - Plated through-holes
  • H05K 3/46 - Manufacturing multi-layer circuits
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material

18.

Method and apparatus for forming contacts on an integrated circuit die using a catalytic adhesive

      
Application Number 15889017
Grant Number 10685931
Status In Force
Filing Date 2018-02-05
First Publication Date 2018-06-07
Grant Date 2020-06-16
Owner CATLAM LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine

Abstract

A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.

IPC Classes  ?

  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/498 - Leads on insulating substrates
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
  • H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
  • C23C 18/20 - Pretreatment of the material to be coated of organic surfaces, e.g. resins
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
  • H05K 3/42 - Plated through-holes
  • C23C 18/38 - Coating with copper

19.

Integrated circuit wafer integration with catalytic laminate or adhesive

      
Application Number 15350019
Grant Number 09922951
Status In Force
Filing Date 2016-11-12
First Publication Date 2018-03-20
Grant Date 2018-03-20
Owner CATLAM LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine

Abstract

A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.

IPC Classes  ?

  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
  • H01L 29/40 - Electrodes
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/498 - Leads on insulating substrates
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

20.

Circuit board apparatus and method

      
Application Number 15603326
Grant Number 09942981
Status In Force
Filing Date 2017-05-23
First Publication Date 2018-02-22
Grant Date 2018-04-10
Owner CATLAM LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine

Abstract

A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.

IPC Classes  ?

  • H05K 1/03 - Use of materials for the substrate
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal
  • H05K 3/42 - Plated through-holes
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 3/46 - Manufacturing multi-layer circuits
  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 1/02 - Printed circuits Details

21.

Catalytic laminate apparatus and method

      
Application Number 15240133
Grant Number 09706650
Status In Force
Filing Date 2016-08-18
First Publication Date 2017-07-11
Grant Date 2017-07-11
Owner CATLAM LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine

Abstract

A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.

IPC Classes  ?

  • H05K 1/03 - Use of materials for the substrate
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • H05K 1/02 - Printed circuits Details
  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 3/42 - Plated through-holes
  • H05K 3/46 - Manufacturing multi-layer circuits
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal

22.

Via in a printed circuit board

      
Application Number 15184426
Grant Number 09674967
Status In Force
Filing Date 2016-06-16
First Publication Date 2016-10-06
Grant Date 2017-06-06
Owner CATLAM LLC (USA)
Inventor
  • Karavakis, Konstantine
  • Bahl, Kenneth S.

Abstract

A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material that has been covered with catalytic adhesive material on both faces of the dielectric laminate material. The layer of catalytic adhesive coats a portion of the dielectric laminate material around the hole. The patterned metal layer is placed over the catalytic adhesive material on both faces of the dielectric laminate material and within the hole.

IPC Classes  ?

  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 3/42 - Plated through-holes
  • H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal
  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits

23.

Method for wafer level packaging

      
Application Number 15009386
Grant Number 10573610
Status In Force
Filing Date 2016-01-28
First Publication Date 2016-05-26
Grant Date 2020-02-25
Owner CATLAM, LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine

Abstract

++ to Cu. Metal traces are formed in trace channels within the first layer of catalytic adhesive. The trace channels extend below a surface of the first layer of the catalytic material. The trace metals traces are also in contact with integrated circuit pads on the surface of the wafer.

IPC Classes  ?

  • H05K 3/02 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
  • H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
  • H01L 23/00 - Details of semiconductor or other solid state devices

24.

Via in a printed circuit board

      
Application Number 15001140
Grant Number 09706667
Status In Force
Filing Date 2016-01-19
First Publication Date 2016-05-12
Grant Date 2017-07-11
Owner CATLAM LLC (USA)
Inventor
  • Karavakis, Konstantine
  • Bahl, Kenneth S.

Abstract

A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material. A layer of catalytic adhesive coats walls within the hole. The patterned metal layer is placed over the catalytic adhesive within the hole.

IPC Classes  ?

  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal
  • H05K 3/42 - Plated through-holes

25.

Method for forming traces of a printed circuit board

      
Application Number 14281631
Grant Number 09380700
Status In Force
Filing Date 2014-05-19
First Publication Date 2015-11-19
Grant Date 2016-06-28
Owner CATLAM LLC (USA)
Inventor
  • Karavakis, Konstantine
  • Bahl, Kenneth S.
  • Carney, Steve

Abstract

A printed circuit board includes a laminate substrate. The laminate substrate includes catalytic material that resists metal plating except where a surface of the catalytic material is ablated. Metal traces are formed within in trace channels within the laminate substrate. The channels extend below the surface of the catalytic material.

IPC Classes  ?

  • H05K 3/02 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
  • H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
  • H05K 1/03 - Use of materials for the substrate
  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 3/08 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by electric discharge, e.g. by spark erosion
  • H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits

26.

Via in a printed circuit board

      
Application Number 14281802
Grant Number 09398703
Status In Force
Filing Date 2014-05-19
First Publication Date 2015-11-19
Grant Date 2016-07-19
Owner CATLAM LLC (USA)
Inventor
  • Karavakis, Konstantine
  • Bahl, Kenneth S.

Abstract

A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material that has been covered with catalytic adhesive material on both faces of the dielectric laminate material. The layer of catalytic adhesive coats a portion of the dielectric laminate material around the hole. The patterned metal layer is placed over the catalytic adhesive material on both faces of the dielectric laminate material and within the hole.

IPC Classes  ?

  • H05K 1/03 - Use of materials for the substrate
  • H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal
  • H05K 3/42 - Plated through-holes

27.

Methods for forming embedded traces

      
Application Number 14297516
Grant Number 09631279
Status In Force
Filing Date 2014-06-05
First Publication Date 2015-11-19
Grant Date 2017-04-25
Owner CATLAM LLC (USA)
Inventor
  • Bahl, Kenneth S.
  • Karavakis, Konstantine
  • Carney, Steve

Abstract

A printed circuit board includes a laminate substrate. The laminate substrate includes catalytic core material that resists metal plating except where a surface of the catalytic material is ablated. Metal traces are formed within in trace channels within the laminate substrate. The channels extend below the surface of the catalytic material.

IPC Classes  ?

  • H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
  • C23C 18/38 - Coating with copper
  • C23C 18/20 - Pretreatment of the material to be coated of organic surfaces, e.g. resins
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • H05K 3/46 - Manufacturing multi-layer circuits