If the two traces of a differential signal trace pair are not of identical length, intra-pair skew occurs as a result of the different flight time for the signal on each trace. Introducing serpentine routing into the shorter trace compensates for the intra-pair skew by increasing the effective length of the trace. However, the serpentine routing may also introduce impedance discontinuities. An impedance discontinuity leads to reflections and resonances, which hamper the transmitted signal in reaching the receiver. Adding extrusions to the serpentine routing may improve the impedance profile of the differential trace and thus lower reflections.
H01R 12/72 - Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures
H01R 13/00 - Details of coupling devices of the kinds covered by groups or
H01R 43/20 - Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for assembling or disassembling contact members with insulating base, case or sleeve
If the two traces of a differential signal trace pair are not of identical length, intra-pair skew occurs as a result of the different flight time for the signal on each trace. Introducing serpentine routing into the shorter trace compensates for the intra-pair skew by increasing the effective length of the trace. However, the serpentine routing may also introduce impedance discontinuities. An impedance discontinuity leads to reflections and resonances, which hamper the transmitted signal in reaching the receiver. Adding extrusions to the serpentine routing may improve the impedance profile of the differential trace and thus lower reflections.
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
A logic block can be relocated without recompilation from a first area to a second area on a field-programmable gate array (FPGA) if the pattern of fabric tiles in the second area is the same as the pattern of fabric tiles in the first area, and if the two areas have the same dimensions. The design system runs synthesis, placement, and routing on a partition of a design at a first location, exports that partition to a persistent on-disk database, imports one or multiple copies of the partition into a larger design, and moves one or more of the copies from the first area to a target area in the larger design. The compatibility of the second area may be identified based on fabric tile signatures of the first area and the second area.
A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.
G06F 7/575 - Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
G06F 1/03 - Digital function generators working, at least partly, by table look-up
G06F 7/504 - AddingSubtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.
G06F 7/53 - Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
A tile of an FPGA fuses memory and arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. The arithmetic unit accesses inputs from a combination of: the switch fabric, the memory circuit, a second memory circuit of the tile, and a cascade input. In some example embodiments, the routing of the connections on the tile is based on post-fabrication configuration. In one configuration, all connections are used by the memory circuit, allowing for higher bandwidth in writing or reading the memory. In another configuration, all connections are used by the arithmetic circuit.
A conflict-free parallel radix sorting algorithm, and devices and systems implementing this algorithm, schedules memory copies of data elements of a large dataset so that there is always a single copy to each target memory each cycle of operation for the system implementing the algorithm. The conflict-free parallel radix sorting algorithm eliminates memory copying conflicts in copying data elements from different source memories to the same target memory and in this way maintains maximum throughput for the copying of data elements from source memories to target memories, reducing the time required to sort the data elements of the large dataset.
A conflict-free parallel radix sorting algorithm, and devices and systems implementing this algorithm, schedules memory copies of data elements of a large dataset so that there is always a single copy to each target memory each cycle of operation for the system implementing the algorithm. The conflict-free parallel radix sorting algorithm eliminates memory copying conflicts in copying data elements from different source memories to the same target memory and in this way maintains maximum throughput for the copying of data elements from source memories to target memories, reducing the time required to sort the data elements of the large dataset.
A logic block can be relocated without recompilation from a first area to a second area on a field-programmable gate array (FPGA) if the pattern of fabric tiles in the second area is the same as the pattern of fabric tiles in the first area, and if the two areas have the same dimensions. The design system runs synthesis, placement, and routing on a partition of a design at a first location, exports that partition to a persistent on-disk database, imports one or multiple copies of the partition into a larger design, and moves one or more of the copies from the first area to a target area in the larger design. The compatibility of the second area may be identified based on fabric tile signatures of the first area and the second area.
A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.
A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.
G06F 7/575 - Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
G06F 1/03 - Digital function generators working, at least partly, by table look-up
G06F 7/504 - AddingSubtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.
G06F 7/53 - Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
A receiving device uses an elastic buffer that is wider than the number of data elements transferred in each cycle. To compensate for frequency differences between the transmitter and the receiver, the transmitting device periodically sends a skip request with a default number of skip data elements. If the elastic buffer is filling, the receiving device ignores one or more of the skip data elements. If the elastic buffer is emptying, the receiving device adds one or more skip data elements to the skip request. To maintain the ordering of data despite the manipulation of the skip data elements, two rows of the wide elastic buffer are read at a time. This allows construction of a one-row result from any combination of the data elements of the two rows. The column pointers are adjusted appropriately, to ensure that they continue to point to the next data to be read.
Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.
H04L 49/40 - Constructional details, e.g. power supply, mechanical construction or backplane
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
H04L 47/30 - Flow controlCongestion control in combination with information about buffer occupancy at either end or at transit nodes
H04L 47/41 - Flow controlCongestion control by acting on aggregated flows or links
H04L 47/722 - Admission controlResource allocation using reservation actions during connection setup at the destination endpoint, e.g. reservation of terminal resources or buffer space
H04L 49/351 - Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.
A logic block can be relocated without recompilation from a first area to a second area on a field-programmable gate array (FPGA) if the pattern of fabric tiles in the second area is the same as the pattern of fabric tiles in the first area, and if the two areas have the same dimensions. The design system runs synthesis, placement, and routing on a partition of a design at a first location, exports that partition to a persistent on-disk database, imports one or multiple copies of the partition into a larger design, and moves one or more of the copies from the first area to a target area in the larger design. The compatibility of the second area may be identified based on fabric tile signatures of the first area and the second area.
A logic block can be relocated without recompilation from a first area to a second area on a field-programmable gate array (FPGA) if the pattern of fabric tiles in the second area is the same as the pattern of fabric tiles in the first area, and if the two areas have the same dimensions. The design system runs synthesis, placement, and routing on a partition of a design at a first location, exports that partition to a persistent on-disk database, imports one or multiple copies of the partition into a larger design, and moves one or more of the copies from the first area to a target area in the larger design. The compatibility of the second area may be identified based on fabric tile signatures of the first area and the second area.
Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.
Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
G06F 1/06 - Clock generators producing several clock signals
G06F 1/08 - Clock generators with changeable or programmable clock frequency
An S-parameter of a reference impedance is determined and converted to a desired mode of operation. Example modes of operation include a single-ended input output mode, a differential input output mode, and a common input output mode. The complex values of the impedance at each port as a function of frequency can be computed using the novel closed-form quadratic S-parameter equation which utilizes the concept of matched networks by setting the reflections and re-reflections to zero through S-parameter renormalization. Using the S-parameter renormalization, the insertion loss corresponding to zero reflections and re-reflections is calculated. Based on the determination of the matching impedance used to reduce the reflections and re-reflections to zero, a parameter of a circuit comprising the network may be modified to reduce noise.
G01R 27/32 - Measuring attenuation, gain, phase shift, or derived characteristics of electric four-pole networks, i.e. two-port networksMeasuring transient response in circuits having distributed constants
G01R 27/06 - Measuring reflection coefficientsMeasuring standing-wave ratio
21.
Processing of ethernet packets at a programmable integrated circuit
Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.
H04L 47/41 - Flow controlCongestion control by acting on aggregated flows or links
H04L 47/30 - Flow controlCongestion control in combination with information about buffer occupancy at either end or at transit nodes
H04L 47/722 - Admission controlResource allocation using reservation actions during connection setup at the destination endpoint, e.g. reservation of terminal resources or buffer space
H04L 49/351 - Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
A four-input lookup table ("LUT4") is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table ("LUT6") is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.
A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.
G06F 7/575 - Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
G06F 7/504 - AddingSubtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
G06F 1/03 - Digital function generators working, at least partly, by table look-up
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
25.
Capacitive compensation for vertical interconnect accesses
Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 3/00 - Apparatus or processes for manufacturing printed circuits
H05K 3/04 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06F 7/53 - Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
27.
Capacitive compensation for vertical interconnect accesses
Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.
H05K 3/04 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
H05K 3/00 - Apparatus or processes for manufacturing printed circuits
Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.
A receiving device uses an elastic buffer that is wider than the number of data elements transferred in each cycle. To compensate for frequency differences between the transmitter and the receiver, the transmitting device periodically sends a skip request with a default number of skip data elements. If the elastic buffer is filling, the recei ving device ignores one or more of the skip data elements, if the elastic buffer is emptying, the receiving device adds one or more skip data elements to the skip request. To maintain the ordering of data despite the manipulation of the skip data elements, two rows of the wide elastic buffer are read at a time. This allows construction of a one-row result from any combination of the data elements of the two rows. The column pointers are adjusted appropriately, to ensure that they continue to point to the next data to be read.
A receiving device uses an elastic buffer that is wider than the number of data elements transferred in each cycle. To compensate for frequency differences between the transmitter and the receiver, the transmitting device periodically sends a skip request with a default number of skip data elements. If the elastic buffer is filling, the receiving device ignores one or more of the skip data elements. If the elastic buffer is emptying, the receiving device adds one or more skip data elements to the skip request. To maintain the ordering of data despite the manipulation of the skip data elements, two rows of the wide elastic buffer are read at a time. This allows construction of a one-row result from any combination of the data elements of the two rows. The column pointers are adjusted appropriately, to ensure that they continue to point to the next data to be read.
Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns, clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.
H04L 47/41 - Flow controlCongestion control by acting on aggregated flows or links
H04L 47/30 - Flow controlCongestion control in combination with information about buffer occupancy at either end or at transit nodes
H04L 47/722 - Admission controlResource allocation using reservation actions during connection setup at the destination endpoint, e.g. reservation of terminal resources or buffer space
H04L 49/351 - Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
32.
NOISE-INDEPENDENT LOSS CHARACTERIZATION OF NETWORKS
An S -parameter of a reference impedance is determined and converted to a desired mode of operation. Example modes of operation include a single-ended input output mode, a differential input output mode, and a common input output mode. The complex values of the impedance at each port as a function of frequency can be computed using the novel closed-form quadratic S-parameter equation which utilizes the concept of matched networks by setting the reflections and re-reflections to zero through S-parameter renormalization. Using the S-parameter renormalization, the insertion loss corresponding to zero reflections and re- reflections is calculated. Based on the determination of the matching impedance used to reduce the reflections and re-reflections to zero, a parameter of a circuit comprising the network may be modified to reduce noise.
G01R 15/00 - Details of measuring arrangements of the types provided for in groups , or
G01R 27/32 - Measuring attenuation, gain, phase shift, or derived characteristics of electric four-pole networks, i.e. two-port networksMeasuring transient response in circuits having distributed constants
G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)
A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.
A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.
A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.
A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06F 7/53 - Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
A tile of an FPGA fuses memory and arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. The arithmetic unit accesses inputs from a combination of: the switch fabric, the memory circuit, a second memory circuit of the tile, and a cascade input. In some example embodiments, the routing of the connections on the tile is based on post-fabrication configuration. In one configuration, all connections are used by the memory circuit, allowing for higher bandwidth in writing or reading the memory. In another configuration, all connections are used by the arithmetic circuit.
A tile of an FPGA fuses memory and arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. The arithmetic unit accesses inputs from a combination of: the switch fabric, the memory circuit, a second memory circuit of the tile, and a cascade input. In some example embodiments, the routing of the connections on the tile is based on post-fabrication configuration. In one configuration, all connections are used by the memory circuit, allowing for higher bandwidth in writing or reading the memory. In another configuration, all connections are used by the arithmetic circuit.
H03K 19/17736 - Structural details of routing resources
H03K 19/17728 - Reconfigurable logic blocks, e.g. lookup tables
H03K 19/17704 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
H03K 19/17796 - Structural details for adapting physical parameters for physical disposition of blocks
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
39.
ON-CHIP NETWORK IN PROGRAMMABLE INTEGRATED CIRCUIT
Methods, systems, and computer programs are presented for implementing a network on chip (NOC). One programmable integrated circuit comprises a plurality of clusters, an internal network on chip (iNOC), and an external network on chip (eNOC) outside the plurality of clusters. The plurality of clusters is disposed on a plurality of cluster row's and a plurality of cluster columns, each cluster comprising programmable logic. Further, the iNOC comprises iNOC row's and iNOC columns. Each iNOC row is configured for transporting data and comprising connections to clusters in a cluster row and the eNOC, and each iNOC column is configured for transporting data and comprising connections to clusters in a cluster column and the eNOC.
Methods, systems, and computer programs are presented for distributing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an iNOC comprising iNOC rows and iNOC columns; a set of clusters coupled to the iNOC, each cluster comprising a vertical network access point (NAP) for iNOC column communications, a horizontal NAP for iNOC row communications, a valid signal, and programmable logic, where the vertical NAP is connected to the horizontal NAP when the valid signal is activated; and an Ethernet controller coupled to the iNOC, the Ethernet controller configurable to send Ethernet-packet segments to the vertical NAPs.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.
An advanced timing mode has a path that originates from a host application-specific integrated circuit (ASIC) and terminates at a register inside an embedded field programmable gate array (FPGA), bypassing interface cluster registers. The terminating register may be present at a boundary between the host ASIC and the embedded FPGA or deep inside the embedded FPGA. In a clock trunk input with internal divergence timing scenario, a clock output from a phase-locked loop (PLL) in the host ASIC is driven through a clock trunk into the embedded FPGA and, from there, diverges into interface cluster registers and the boundary adjacent to the host ASIC. A clock trunk input with external divergence timing scenario is similar to the internal divergence scenario except that a clock divergence occurs before the clock enters a clock trunk of the embedded FPGA. In a boundary clock input scenario, a PLL drives both the host ASIC and the embedded FPGA interface clusters.
An advanced timing mode has a path that originates from a host application-specific integrated circuit (ASIC) and terminates at a register inside an embedded field programmable gate array (FPGA), bypassing interface cluster registers. The terminating register may be present at the boundary between the host ASIC and the embedded FPGA or deep inside the embedded FPGA. In a clock trunk input with internal divergence timing scenario, a clock output from a phase-locked loop (PLL) in the host ASIC is driven through a clock trunk into the embedded FPGA and, from there, diverges into interface cluster registers and the ASIC boundary. A clock trunk input with external divergence timing scenario is similar to the internal divergence scenario except that the clock divergence occurs before the clock enters the embedded FPGA trunk. In a boundary clock input scenario, a PLL drives both the host ASIC and the embedded FPGA interface clusters.
A tile of an FPGA fuses memory and arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. The arithmetic unit accesses inputs from a combination of: the switch fabric, the memory circuit, a second memory circuit of the tile, and a cascade input. In some example embodiments, the routing of the connections on the tile is based on post-fabrication configuration. In one configuration, all connections are used by the memory circuit, allowing for higher bandwidth in writing or reading the memory. In another configuration, all connections are used by the arithmetic circuit.
Methods, systems, and computer programs are presented for routing packets on a network on chip (NOC) within a programmable integrated circuit. One programmable integrated circuit comprises a plurality of clusters disposed on a plurality of cluster rows and a plurality of cluster columns, an internal network on chip (iNOC) comprising iNOC rows and iNOC columns, an external network on chip (eNOC) connected to the iNOC rows and the iNOC columns, and a field programmable gate array Control Unit (FCU) for configuring programmable logic in the plurality of clusters based on a first configuration received by the FCU. The FCU is connected to the eNOC, where the FCU communicates with the plurality of clusters via the iNOC and the eNOC. The FCU is configured for receiving a second configuration from the programmable logic in the plurality of clusters for reconfiguring a component of the programmable integrated circuit.
In some example embodiments a logical block comprising twelve inputs and two six-input lookup tables (LUTs) is provided, wherein four of the twelve inputs are provided as inputs to both of the six-input lookup tables. This configuration supports efficient field programmable gate array (FPGA) implementation of multipliers. Each six-input LUT comprises two five-input lookup tables (LUT5s) that are used to form Booth encoding multiplier building blocks. The five inputs to each LUT5 are two bits from a multiplier and three Booth-encoded bits from a multiplicand. By assembling building blocks, multipliers of arbitrary size may be formed.
Methods, systems, and computer programs are presented for implementing a network on chip (NOC). One programmable integrated circuit comprises a plurality of clusters, an internal network on chip (iNOC), and an external network on chip (eNOC) outside the plurality of clusters. The plurality of clusters is disposed on a plurality of cluster rows and a plurality of cluster columns, each cluster comprising programmable logic. Further, the iNOC comprises iNOC rows and iNOC columns. Each iNOC row is configured for transporting data and comprising connections to clusters in a cluster row and the eNOC, and each iNOC column is configured for transporting data and comprising connections to clusters in a cluster column and the eNOC.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
G06F 13/20 - Handling requests for interconnection or transfer for access to input/output bus
H03K 19/17736 - Structural details of routing resources
H03K 19/1776 - Structural details of configuration resources for memories
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
H03K 19/17796 - Structural details for adapting physical parameters for physical disposition of blocks
H03K 19/17728 - Reconfigurable logic blocks, e.g. lookup tables
In some example embodiments a logical block comprising twelve inputs and two six-input lookup tables (LUTs) is provided, wherein four of the twelve inputs are provided as inputs to both of the six-input lookup tables. This configuration supports efficient field programmable gate array (FPGA) implementation of multipliers. Each six-input LUT comprises two five-input lookup tables (LUT5s) that are used to form Booth encoding multiplier building blocks. The five inputs to each LUT5 are two bits from a multiplier and three Booth-encoded bits from a multiplicand. By assembling building blocks, multipliers of arbitrary size may be formed.
In some example embodiments a logical block comprising twelve inputs and two six-input lookup tables (LUTs) is provided, wherein four of the twelve inputs are provided as inputs to both of the six-input lookup tables. This configuration supports efficient field programmable gate array (FPGA) implementation of multipliers. Each six-input LUT comprises two five-input lookup tables (LUT5s) that are used to form Booth encoding multiplier building blocks. The five inputs to each LUT5 are two bits from a multiplier and three Booth-encoded bits from a multiplicand. By assembling building blocks, multipliers of arbitrary size may be formed.
H03K 19/017 - Modifications for accelerating switching in field-effect transistor circuits
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Custom manufacture of semiconductor chips and field
programmable gate arrays. Product development, namely, development, and design of
semiconductor chips and field programmable gate arrays.
Circuits comprising an asynchronous programmable interconnect with fan out support that include a multi-port switch and a first and second buffer-switch circuit, and methods of forming such circuits, are provided. Additional circuits and methods are disclosed.
Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.
In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed.
In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. One or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.
Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.
In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
65.
Asynchronous conversion circuitry apparatus, systems, and methods
Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed.
Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
Methods, systems, and circuits that implement timing analyses of an asynchronous system are described. A method may include converting a synchronous circuit design into an asynchronous representation, wherein a critical path may be identified. The critical path may be converted to a corresponding path in the synchronous circuit design. Additional methods, systems, and circuits are disclosed.
Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.
Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.
Methods, circuits and systems for balanced distribution of source-synchronous clock signals are described. Multiple data sets together with one or more clock signals associated with the multiple data sets may be received at a number of interface devices. The multiple data sets may be captured in a number of data buffers. The clock signals may be programmably distributed to a group of the multiple data buffers that retain the one or more data sets, using a balanced clock network. Additional methods, circuits, and systems are disclosed.
Methods, systems, and circuits for implementing multi-clock designs in asynchronous logic circuits are described. A method may include associating one or more data tokens with a clock domain of a multi-clock domain netlist. A durational relationship between a clock period associated with the clock domain and one or more other clock domains of the multi-clock domain netlist may be determined. Data tokens used in other clock domains may be transformed based on the determined relationship.
A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and converting one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input. One or more asynchronous outputs at a circuit boundary is converted to an asynchronous output from the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output.
A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and one or more additional tokens into the converted asynchronous circuit. The circuit is initialized with a desired additional number of tokens placed in the asynchronous circuit, or a desired number of tokens are inserted at an input before taking tokens from an output.
Methods, systems, and circuits for forming and operating a crossbar structure in an asynchronous system are described. One or more input ports of a programmable crossbar structure may be connected to send data to one or more output ports. A group of output ports each receiving data from an input port may be connected to send, in response, control signals via a programmable element to the input port. The number of programmable elements used may be determined by the number of input ports being copied to more than one output port. Additional methods, systems, and circuits are disclosed.
Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed.
Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed.
Methods, circuits and systems for converting of a non-predicated asynchronous netlist to a predicated asynchronous netlist are described. These may operate to identify one or more portions of an asynchronous netlist corresponding to a partially utilized portion of an asynchronous circuit. The asynchronous netlist may be modified to control the partially utilized portion. Additional methods, circuits, and systems are disclosed.
Methods, circuits and systems for converting of a non-predicated asynchronous netlist to a predicated asynchronous netlist are described. These may operate to identify one or more portions of an asynchronous netlist corresponding to a partially utilized portion of an asynchronous circuit. The asynchronous netlist may be modified to control the partially utilized portion. Additional methods, circuits, and systems are disclosed.
Circuits comprising an asynchronous programmable interconnect with fan out support that include a multi-port switch and a first and second buffer-switch circuit, and methods of forming such circuits, are provided. Additional circuits and methods are disclosed.
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.
Apparatus, systems, and methods may operate to generate a synchronous netlist from a synchronous circuit design representation, automatically substitute asynchronous components taken from an asynchronous standard cell component library for corresponding standard cell synchronous components in the synchronous netlist to form an asynchronous core, and convert the synchronous netlist to an asynchronous circuit design representation. Additional apparatus, systems, and methods are disclosed.
In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics (302, 304) for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
Methods and systems for converting synchronous circuit designs to asynchronous circuit designs are described. A method may include converting a synchronous circuit design to an asynchronous dataflow design. Functional characteristics of the synchronous circuit design may be determined. The synchronous circuit design may include multiple synchronous logic blocks and a number of connection boxes. Each synchronous logic block may be converted, based on functional characteristics, to corresponding asynchronous dataflow logic blocks. The corresponding asynchronous dataflow logic blocks may provide corresponding asynchronous dataflow logic functions that may use protocol signals. Each connection box, based on the functional characteristics, may be converted to programmable switch points and programmable switches.
Methods and systems for performing automated conversion of synchronous circuit design to asynchronous circuit design representations are described. A synchronous netlist may be generated from a synchronous circuit design. The synchronous netlist may include combinational logic gates and state-holding elements. The synchronous netlist may be converted to an asynchronous circuit design. The converting may include grouping the combinational logic gates by operations into functions.
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.
Apparatus, systems, and methods may operate to generate a synchronous netlist from a synchronous circuit design representation, automatically substitute asynchronous components taken from an asynchronous standard cell component library for corresponding standard cell synchronous components in the synchronous netlist to form an asynchronous core, and convert the synchronous netlist to an asynchronous circuit design representation. Additional apparatus, systems, and methods are disclosed.
Apparatus, systems, and methods may operate to generate a synchronous netlist from a synchronous circuit design representation, automatically substitute asynchronous components taken from an asynchronous standard cell component library for corresponding standard cell synchronous components in the synchronous netlist to form an asynchronous core, and convert the synchronous netlist to an asynchronous circuit design representation. Additional apparatus, systems, and methods are disclosed.
Apparatus, systems, and methods may operate to identify state holding elements and functional logic elements in an original cyclic structure, and to insert additional state holding elements or initial tokens in series with the identified functional logic elements to create a modified cyclic structure, wherein the additional state holding elements or initial tokens have substantially identical functionality to the original state holding elements. Other activities may include coupling additional functional logic elements to output nodes of the modified cyclic structure, wherein the additional functional logic elements have substantially identical functionality to the original functional logic elements. Additional apparatus, systems, and methods are disclosed.
Apparatus, systems, and methods may operate to identify state holding elements and functional logic elements in an original cyclic structure, and to insert additional state holding elements or initial tokens in series with the identified functional logic elements to create a modified cyclic structure, wherein the additional state holding elements or initial tokens have substantially identical functionality to the original state holding elements. Other activities may include coupling additional functional logic elements to output nodes of the modified cyclic structure, wherein the additional functional logic elements have substantially identical functionality to the original functional logic elements. Additional apparatus, systems, and methods are disclosed.
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, such as the type introduced through radiation or, more broadly, single-event effects (SEEs). SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits, among others.
Methods and systems for converting synchronous circuit designs to asynchronous circuit designs, and particularly programmable asynchronous circuit designs. Provide is a systematic, workable and repeatable process for evaluating synchronous circuit designs, converting the wires, switches/connections and logic functions to equivalent-function asynchronous circuit designs and hence implementing a functionally equivalent asynchronous circuit with all the benefits thereof. Further provided are a process for systematically doing the conversion and hardware equivalents (in form or functional description) for the asynchronous components. Using the present invention, any synchronous circuit design can be converted to an asynchronous equivalent, typically with no change to the original design implementation.
Methods and systems for converting synchronous circuit designs to asynchronous circuit designs, and particularly programmable asynchronous circuit designs. Provide is a systematic, workable and repeatable process for evaluating synchronous circuit designs, converting the wires, switches/connections and logic functions to equivalent-function asynchronous circuit designs and hence implementing a functionally equivalent asynchronous circuit with all the benefits thereof. Further provided are a process for systematically doing the conversion and hardware equivalents (in form or functional description) for the asynchronous components. Using the present invention, any synchronous circuit design can be converted to an asynchronous equivalent, typically with no change to the original design implementation.
In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics (302, 304) for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics.
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Custom manufacture of semiconductor chips and field programmable gate arrays. Product development, namely development, design and manufacture of semiconductor chips and field programmable gate arrays.
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.
H03K 19/003 - Modifications for increasing the reliability
98.
SYSTEMS AND METHODS FOR PERFORMING AUTOMATED CONVERSION OF REPRESENTATIONS OF SYNCHRONOUS CIRCUIT DESIGNS TO AND FROM REPRESENTATIONS OF ASYNCHRONOUS CIRCUIT DESIGNS
Methods (700, 800, 900) and systems (Fig. 1) automate an approach to convert a circuit design from a synchronous representation (Fig. 4A) to an asynchronous representation (Fig. 4B) without interaction or redesign. Conversion of representations of synchronous circuit designs (101) to and from representations of asynchronous circuit designs (104) enable traditional electronic design automation tools to process asynchronous designs while allowing synchronous designs to be implemented using asynchronous hardware solutions. Feedback to synchronous design tools (105) in synchronous representation enables optimization while minimizing the need for knowledge of the underlying asynchronous architecture and hardware.
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single - event effects SEE-tolerant configurations (210, 210', 301,404, 510, 520, 800) are shown and described for combinational logic circuits and state-holding logic circuits The invention further provides SEE-tolerant configurations for SRAM memory circuits (700, 800)
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.
