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2024
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Invention
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Relocatable fpga modules.
A logic block can be relocated without recompilation from a first area... |
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Invention
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Intra-pair skew compensation of differential signals. If the two traces of a differential signal ... |
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Invention
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Fused memory and arithmetic circuit.
A tile of an FPGA fuses memory and arithmetic circuits. Con... |
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Invention
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Multiple mode arithmetic circuit.
A tile of an FPGA includes a multiple mode arithmetic circuit.... |
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Invention
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Adder circuit using lookup tables.
A four-input lookup table (“LUT4”) is modified to operate in ... |
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2023
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Invention
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Relocatable fpga modules. A logic block can be relocated without recompilation from a first area ... |
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Invention
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Cascade communications between fpga tiles. A tile of an FPGA provides memory, arithmetic function... |
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Invention
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Conflict-free parallel radix sorting. A conflict-free parallel radix sorting algorithm, and devic... |
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Invention
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Intra-pair skew compensation of differential signals.
If the two traces of a differential signal... |
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Invention
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Adder circuit using lookup tables. A four-input lookup table (“LUT4”) is modified to operate in a... |
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Invention
|
Wide elastic buffer.
A receiving device uses an elastic buffer that is wider than the number of ... |
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Invention
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Multiple mode arithmetic circuit. A tile of an FPGA includes a multiple mode arithmetic circuit. ... |
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Invention
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Processing of ethernet packets at a programmable integrated circuit. Methods, systems, and comput... |
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Invention
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Synchronous reset deassertion circuit.
Distribution of a reset signal across a system-on-chip (S... |
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Invention
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Conflict-free parallel radix sorting device, system and method.
A conflict-free parallel radix s... |
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2022
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Invention
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Noise-independent loss characterization of networks.
An S-parameter of a reference impedance is ... |
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Invention
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Capacitive compensation for vertical interconnect accesses. Multiple designs for a multi-layer ci... |
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2021
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Invention
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Adder circuit using lookup tables. A four-input lookup table ("LUT4") is modified to operate in a... |
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Invention
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Synchronous reset deassertion circuit. Distribution of a reset signal across a system-on-chip (So... |
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Invention
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Wide elastic buffer. A receiving device uses an elastic buffer that is wider than the number of d... |
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2020
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Invention
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Noise-independent loss characterization of networks. An S -parameter of a reference impedance is ... |
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Invention
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Fused memory and arithmetic circuit. A tile of an FPGA fuses memory and arithmetic circuits. Conn... |
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Invention
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Flexible routing of network data within a programmable integrated circuit. Methods, systems, and ... |
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G/S
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Computer hardware. |
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G/S
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Computer hardware. |
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Invention
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On-chip network in programmable integrated circuit. Methods, systems, and computer programs are p... |
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Invention
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Efficient fpga multipliers. In some example embodiments a logical block comprising twelve inputs ... |
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2019
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G/S
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Custom manufacture of semiconductor chips and field
programmable gate arrays. Product developmen... |
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G/S
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Computer hardware |
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Invention
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Reconfigurable programmable integrated circuit with on-chip network. Methods, systems, and comput... |
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Invention
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Embedded fpga timing sign-off. An advanced timing mode has a path that originates from a host app... |
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2015
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Invention
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Asynchronous pipelined interconnect architecture with fanout support. Circuits comprising an asyn... |
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G/S
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Custom manufacture of semiconductor chips and field programmable gate arrays |
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2008
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G/S
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Product development, namely development and design of semiconductor chips and field programmable ... |
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2007
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G/S
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Semiconductors. |
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G/S
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Custom manufacture of semiconductor chips and field programmable gate arrays. Product development... |
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G/S
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Custom manufacture of semiconductor chips and field programmable gate arrays Product development,... |
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G/S
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Semiconductor chips |
