A system and method for a switching network is disclosed. A plurality of first switching assemblies, with each of the first switching assemblies having at least two input ports and two output ports is provided. A plurality of second switching assemblies are provided. Each of the first switching assembly is selectively coupled to at least two second switching assemblies. Each of the second switching assembly is selectively coupled to at least two first switching assemblies. Data received in the input port passes twice in a forward direction, through a selective first switching assembly and a selective second switching assembly. Received data also passes twice in a reverse direction, through a selective second switching assembly and a selective first switching assembly and comes out of a selective one of the first switching assembly as an output.
A system and method for a logic device is disclosed. A first substrate, a second substrate and a third substrate is provided. A first input nanomagnet is disposed over the first substrate, a second input nanomagnet is disposed over the second substrate, and a third input nanomagnet is disposed over the third substrate. The easy axis of the first input nanomagnet, the second input nanomagnet, and the third input nanomagnet are in a first direction perpendicular to the first substrate, the second substrate and the third substrate. A spacer layer is disposed over the first input nanomagnet, the second input nanomagnet, and the third input nanomagnet. A first ferromagnetic layer is disposed over the spacer layer.
H03K 19/16 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using saturable magnetic devices
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Computer chips; Computer memory modules; Computer hardware for namely energy efficient computer chips, energy efficient computer memory modules, computer chips, energy efficient computer systems comprised primarily of computer hardware and neural network systems, downloadable computer operating systems, and systems on a chip (SOC); Computer hardware for namely computer chips and memory modules for use in regulatory compliance and automated reporting, enterprise risk assessment and mitigation, portfolio and asset management, fraud prevention and anomaly detection, and predictive modeling of customer behaviour using artificial intelligence Design of computer chips; Technology advisory services related to computer chips, energy efficient computer memory modules, computer chips, energy efficient computer systems, computer operating systems, downloadable software, and systems on a chip (SOC); Technical support services, namely, troubleshooting of computer software problems; Providing technology information in the field of computer chips, computer memory modules, computer operating systems, downloadable software, and systems on a chip (SOC) for use in regulatory compliance and automated reporting, enterprise risk assessment and mitigation, portfolio and asset management, fraud prevention and anomaly detection, predictive modeling of business markets, and customer behavior using artificial intelligence.
Some embodiments include a method for detecting and interrupting a cache-based side-channel attack. The method includes: (1) at least calibrating one or more chiplets of a network by calculating a threshold; (2) determining one or more device heartbeat vectors of the one or more chiplets, the one or more device heartbeat vectors being derived at least part from one or more measurements of activity of one of more dedicated security processors associated with the one or more chiplets; (3) determining that a particular chiplet of the one or more chiplets is being attacked with a cache-based side-channel attack, the determining being based at least in part on a computed disparity exceeding the threshold; and (4) employing countermeasures against the cache-based side-channel attack of the particular chiplet, the countermeasures including revoking one or more access rights of the particular chiplet on the network.
42 - Scientific, technological and industrial services, research and design
45 - Legal and security services; personal services for individuals.
Goods & Services
Providing technology information in the field of computer chips, computer memory modules, computer operating system software and hardware, and systems on a chip (SOC); Technical support services, namely, providing technical information in relation to design of computer chips, computer memory modules, computer operating system software and hardware, and systems on a chip (SOC) that are used for modelling biological structures using artificial intelligence. Licensing of intellectual property in the field of intellectual property (IP) cores and Hardware Description Language (HDL) code for energy efficient computer chips, energy efficient computer memory modules, computer chips, computer memory modules, energy efficient computer systems, computer operating systems, downloadable software, and systems on a chip (SOC) for modelling biological structures using artificial intelligence.
09 - Scientific and electric apparatus and instruments
Goods & Services
Computer hardware and recorded software systems for quantum computing; Computer systems configured to perform quantum computing; Computer chips, computer hardware, and computer systems configured to perform quantum computing
09 - Scientific and electric apparatus and instruments
37 - Construction and mining; installation and repair services
Goods & Services
Downloadable computer software for maintaining and operating computer systems; Computer systems, Computer chips, Neural networks, Quantum Computing systems, Machine learning systems, Artificial intelligence systems, System on a Chip (SoC), and Downloadable computer operating programs and computer operating systems for performing machine learning, artificial intelligence functions, and cloud computing using interconnected clusters of computing systems; Recorded computer operating system software; Computer hardware and recorded software systems for performing machine learning, artificial intelligence functions, and cloud computing using interconnected clusters of computers; Downloadable computer software applications for using artificial intelligence (AI) for performing machine learning, artificial intelligence functions, and cloud computing using interconnected clusters of computers Technical support services, namely, technical advice related to the installation of computer systems; Technical support services, namely, providing technical information in relation to Quantum Computing systems, computer systems, Computer chips, neural networks, machine learning systems, artificial intelligence systems, computer operating systems, downloadable software, and systems on a chip (SOC) for performing machine learning, artificial intelligence functions, and cloud computing using interconnected clusters of computers
8.
Storage of delay-logic values for enhanced fault recovery for dual processor lock step computing systems
A computational system with a primary processor and a secondary processor executing executable code, the secondary processor executing at least one clock cycle behind the primary processor. The primary processor comprising (i) two primary delay buffers, including a final primary delay buffer, and (ii) a primary historical storage buffers operably linked to the final primary delay buffer. The secondary processor including a secondary delay buffer and a secondary historical storage buffer operably liked with the secondary delay buffer. The system including a circuit for performing a comparison between first data values from the final primary delay buffer and second data values from the secondary delay buffer. The system configured, if the first data values and the second data values do not match, for storing the first data values in the primary historical storage buffer and the second data values in the secondary historical storage buffer.
A multi-stage processor has a pre-fetch stage, and a sequence of pipelined processor stages. A thread map register contains thread identifiers, and a thread map valid register has locations corresponding to the thread map register and indicating whether a value in the thread map register is to be fetched or not, and a thread map length register indicates the number of thread map register locations forming a canonical sequence of thread identifiers to the pre-fetch stage. The pre-fetch stage does not act on a thread identifier with a not valid thread map valid value, thereby saving power in low demand conditions.
09 - Scientific and electric apparatus and instruments
Goods & Services
Class 9 - Electronic components in the nature of Integrated circuits, integrated circuit chips, and integrated circuit modules for performing multiply-accumulate operations using a re-programmable architecture; Integrated circuits, integrated circuit chips, and integrated circuit modules with flexible architecture for multiply accumulate mathematical computations; Electronic components in the nature of integrated circuit modules; Computer hardware units in the nature of multiplier-accumulators with numerical resolution which can be joined to form single large multiplier-accumulators with high precision or many smaller multiplier-accumulators with reduced precision; Computer hardware units in the nature of a configurable array of multiplier accumulators for performing mathematical computations
09 - Scientific and electric apparatus and instruments
Goods & Services
Electronic components in the nature of integrated circuit chips, none of the foregoing for use in or as personal computers or other personal electronics; Integrated circuits, integrated circuit chips, and integrated circuit modules for performing multiply-accumulate operations using a re-programmable architecture, none of the foregoing for use in or as personal computers or other personal electronics; Electronic components in the nature of Integrated circuits, integrated circuit chips, and integrated circuit modules with flexible architecture for multiply-accumulate mathematical computations, none of the foregoing for use in or as personal computers or other personal electronics; Electronic components in the nature of multiplier-accumulators with numerical resolution which can be joined to form single large multiplier-accumulators with high precision or many smaller multiplier-accumulators with reduced precision, none of the foregoing for use in or as personal computers or other personal electronics; Electronic components in the nature of a configurable array of multiplier accumulators for performing mathematical computations, none of the foregoing for use in or as personal computers or other personal electronics
09 - Scientific and electric apparatus and instruments
Goods & Services
Electronic components in the nature of integrated circuit chips; Integrated circuits, integrated circuit chips, and integrated circuit modules for performing high speed interconnections for transmitting and receiving information related to neural networks and intermediate processing results; Integrated circuits, integrated circuit chips, and integrated circuit modules for transmitting and receiving information at data rates greater than 2.4Gbps.
09 - Scientific and electric apparatus and instruments
Goods & Services
Electronic components in the nature of integrated circuit chips; Integrated circuits, integrated circuit chips, and integrated circuit modules for routing information to nodes of a neural network; Integrated circuits, integrated circuit chips, and integrated circuit modules for making route decisions of computational results in a neural network; Electronic components in the nature of integrated circuit chips; Integrated circuits, integrated circuit chips, and integrated circuit modules for performing the routing of data to nodes arranged in a hierarchy; Electronic components in the nature of integrated circuit chips; Integrated circuits, integrated circuit chips, and integrated circuit modules for making routing decisions.
09 - Scientific and electric apparatus and instruments
Goods & Services
Electronic components in the nature of integrated circuit chips; Integrated circuits, integrated circuit chips, and integrated circuit modules for storing and retriving information related to neural networks; Integrated circuits, integrated circuit chips, and integrated circuit modules for cached storage of computational results in a neural network; integrated circuit chips; Electronic components in the nature of Integrated circuits, integrated circuit chips, and integrated circuit modules for storing and retrieving data related to neural network computational results in a hierarchical memory system
15.
System and method for spin orbit torque based memory device
A system and method for a memory device is disclosed. A substrate is provided. A first ferromagnetic layer is disposed over the substrate. A spacer layer is disposed over the first ferromagnetic layer. A second ferromagnetic layer is disposed over the spacer layer and magnetized in a first direction. A first charge current pulse is passed through the substrate, along a direction perpendicular to the first direction and orients the magnetization of the first ferromagnetic layer in a second direction perpendicular to the first direction. A second charge current pulse is passed through the substrate to selectively switch the magnetization of the first ferromagnetic layer either in the first direction or a direction opposite to the first direction based on a direction of the second charge current. The direction of switched orientation of the magnetization of the first ferromagnetic layer indicates a first value or a second value.
G11C 11/18 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using Hall-effect devices
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
16.
PRNG-based chiplet-to-chiplet secure communication using chaining of message blocks
A first chiplet parses at least a message into ordered message blocks that are associated with index values. The first chiplet generates a substitution value by executing a pseudo-random number generator using a seed value that is computed with at least (i) a first random or pseudo-random number and at least (ii) a first message block. The first chiplet generates a sequencing value by executing a pseudo-random number generator using a seed value that is computed with at least (i) a second random or pseudo-random number and at least (ii) an index value for the first message block. The first chiplet generates a first ciphertext block with at least the substitution value and the sequencing value and further generates a second ciphertext block at least partly with the first ciphertext block. The blocks are concatenated and transmitted to a second chiplet.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
A system and method for a device is disclosed. A first logic device and a second logic device are provided. Each of the first logic device and the second logic device include at least three inputs and one output, wherein, the output is based on majority of the inputs. The output of the first logic device is selectively fed to the second logic device, wherein, the first logic device and the second logic device together form an adder circuit.
A computing system includes (1) a primary processor executing executable instructions and generating first instruction data associated with the executable instructions, (2) a secondary processor executing the executable instructions one or more clock cycles behind the primary processor and generating secondary instruction data associated with the executable instructions, (3) a first first-in first-out (FIFO) buffer for the primary processor, (4) a second FIFO buffer for the secondary processor, (5) circuitry storing at least some of the first instruction data in the first FIFO buffer and at least some of the second instruction data in the second FIFO buffer, (6) compare circuitry comparing a first portion of first instruction data and a second portion of second instruction data that are associated with a given clock cycle, and (7) control circuitry halting the primary and secondary processors responsive to a mismatch between the first portion and the second portion.
A system and method for a logic device is disclosed. Three synthetic antiferromagnet (SAF) nanotracks are disposed over a substrate along a first axis. A connector nanotrack connects the three input nanotrack about a second end of the nanotracks. An output nanotrack is disposed about a central portion of the connector nanotrack. An input value is defined at a first end of the input nanotracks by selectively nucleating a SAF skyrmion at the first end. Presence of the skyrmion is indicative of a first value and absence of the skyrmion indictive of a second value. A charge current is passed along the first axis to selectively move nucleated skyrmion to the output nanotrack, with presence of Skyrmion indicating an output value of the first value.
H03K 19/18 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using galvano-magnetic devices, e.g. Hall-effect devices
H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
A system and method for a logic device is disclosed. A substrate is provided. Three nanotracks are disposed over the substrate and intersect in a central portion. Two nanotracks are disposed about a first axis and one nanotrack is disposed about a second axis perpendicular to the first axis. A ground pad is disposed in the central portion. An input value is set by nucleating a skyrmion about a first end of the nanotracks disposed about the first axis. Presence of the skyrmion indicates a first value and absence indicates a second value. A charge current is passed in the substrate, along the first axis to move the nucleated skyrmions towards the central portion. Presence of the skyrmion is sensed in the central portion and indicates a first value when skyrmion is present.
H03K 19/18 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using galvano-magnetic devices, e.g. Hall-effect devices
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
21.
System and method for nanomagnet based logic device
A system and method for a logic device is disclosed. A plurality of substrates are provided. At least one input nanomagnet is disposed over each of the plurality of substrates. The plurality of input nanomagnets are disposed substantially equidistant from each other. The plurality of input nanomagnets are each a single domain nanomagnet. A spacer layer is disposed over the plurality of input nanomagnets. An output magnet is disposed over the spacer layer.
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
G11C 11/18 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using Hall-effect devices
H10N 97/00 - Electric solid-state thin-film or thick-film devices, not otherwise provided for
A system and method for a logic device is disclosed. A first input nanotrack, a second input nanotrack and an output nanotrack are disposed over a substrate along a first axis. Output nanotrack is disposed between the input nanotracks. Each nanotrack have a first end and a second end. A connector nanotrack connects the first input nanotrack, the second input nanotrack, and the output nanotrack. An input value is defined at a first end of the input nanotracks by selectively nucleating a skyrmion at the first end. Presence of the skyrmion is indicative of a first value and absence of the skyrmion indictive of a second value. Nucleated skyrmion moves to the second end of the output nanotrack when a charge current is passed along the first axis. Presence of the skyrmion at the second end indicates an output value of the first value.
H01F 41/30 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates for applying nanostructures, e.g. by molecular beam epitaxy [MBE]
B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
B82Y 25/00 - Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
A system and method for a logic device is disclosed. A plurality of synthetic antoferromagnet (SAF) nanotracks including a first input nanotrack, a second input nanotrack and an output nanotrack are disposed over a substrate along a first axis. Output nanotrack is disposed between the input nanotracks. Each nanotrack have a first end and a second end. A SAF connector nanotrack connects the first input nanotrack, the second input nanotrack, and the output nanotrack. An input value is defined at a first end of the input nanotracks by selectively nucleating a SAF skyrmion at the first end. Presence of the skyrmion is indicative of a first value and absence of the skyrmion indictive of a second value. A charge current is passed along the first axis to move nucleated skyrmion to the second end of the output nanotrack. Skyrmion at the output indicates an output value of the first value.
H03K 19/18 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using galvano-magnetic devices, e.g. Hall-effect devices
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
B82Y 25/00 - Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
An unenrolled lightweight node is on a decentralized network with a trusted node and a plurality of peers. The unenrolled lightweight node and the peers run a lightweight blockchain consensus algorithm. The unenrolled lightweight node includes (a) circuitry for storing a token that includes a signature that includes at least a signature of at least a first identifier signed with a private key of the trusted node, the first identifier being associated with a public key of the unenrolled lightweight node, and (b) circuitry for broadcasting a request for blockchain enrollment of the unenrolled lightweight node to the plurality of peers. The authentication request including at least a second identifier that is associated with at least a public key of the unenrolled lightweight node, a signature created with at least the second identifier and a corresponding private key of the unenrolled lightweight node, and the token.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
H04L 9/00 - Arrangements for secret or secure communicationsNetwork security protocols
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
25.
Dynamic Adjustment of Word Line Timing in Static Dynamic Random Access Memory
A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller which is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.
A system and method for a switching network is disclosed. A plurality of first switching assemblies, second switching assemblies and intermediate switching assemblies with each of the first switching assemblies, second switching assemblies and intermediate switching assemblies having at least two input ports and output ports is provided. Selective one of the two input ports is configured to receive a data to be processed and delivered at a designated one of the output ports. Received data passes through one or more selective first switching assemblies, one or more intermediate switching assemblies and one or more selective second switching assemblies, before the received data is delivered to the designated port. A plurality of additional data is received in one or more of the input ports to be delivered to one or more designated output ports is processed before the received data is delivered to the designated one of the output ports.
A lightweight node in a decentralized network includes stores a blockchain with a plurality of blocks. The lightweight node adds blocks to the blockchain successively. A given block having a header and a body. The header includes a data merkle root generated as a root hash of a data merkle tree with one or more leaf nodes that are one or more hashes. A given hash being a hash of a combination of (1) a public key associated with a lightweight node of the decentralized network and (2) of a validity value associated with the public key indicating whether the public key is a valid public key. The data merkle root being insufficient for restoring the data merkle tree. But with a public key and an intermediate hash the date merkle root is sufficient for at least partly verifying the public key.
H04L 9/00 - Arrangements for secret or secure communicationsNetwork security protocols
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
An exemplary fault-tolerant computing system comprises a secondary processor configured to execute in delayed lock step with a primary processor from a common program store, comparators in the store data and writeback paths to detect a fault based on comparing primary and secondary processor states, and a writeback path delay permitting aborting execution when a fault is detected, before writeback of invalid data. The secondary processor execution and the primary processor store data and writeback may be delayed a predetermined number of cycles, permitting fault detection before writing invalid data. Store data and writeback paths may include triple module redundancy configured to pass only majority data through the store data and writeback path delay stages. Some implementations may forward data from the store data path delay stages to the writeback stage or memory if the load data address matches the address of data in a store data path delay stage.
An exemplary branch predictor apparatus comprises a Pattern History Table (PHT) configured with a PHT allocation multiplexer/demultiplexer (PAMD) configurable to output a prediction logically selected from a portion of the PHT entries selectively allocated among a plurality of threads. The PHT entries may be allocated among a plurality of threads based on control bits read from a Control and Status Register (CSR) at system initialization. The branch predictor may govern a plurality of threads fetching instructions from an address selected from a Branch Target Buffer (BTB) entry indexed based on a per-thread Program Counter (PC) or a PHT entry indexed based on a per-thread Global History Register (GBHR). The PHT entries may be saturating binary counters. The saturating counters may be two-bit counters. An exemplary implementation may permit reduced misprediction rate, increased throughput, or reduced energy consumption resulting from increased allocation of PHT entries to more branch-intensive threads.
A system and method for a logic device is disclosed. A substrate is provided. Three nanotracks are disposed over the substrate and intersect in a central portion. Two nanotracks are disposed about a first axis and one nanotrack is disposed about a second axis perpendicular to the first axis. A ground pad is disposed in the central portion. Nanotrack along the second axis extend beyond the central portion to define an output portion. An input value is set by nucleating a skyrmion about a first end of the nanotracks. Presence of the skyrmion indicates a first value and absence indicates a second value. A charge current is passed in the substrate, along the first axis and the second axis to move the nucleated skyrmions towards the central portion. Presence of the skyrmion is sensed in the output portion and indicates a first value when skyrmion is present.
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
H03K 19/08 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices
31.
PRNG-based chiplet to chiplet secure communication using counter resynchronization
A method is performed with a group of chiplets. The method includes: (1) parsing a message into at least a group of ordered message blocks associated with a group of index values, which are indicative of positions of individual message blocks relative to one another; (2) generating two or more substitution values based at least in part on execution of two or more pseudo-random number generators (PNRG's) using seeds associated with the bits of blocks of the group of message blocks; (3) generating two or more sequencing values based at least in part on execution of two or more PNRG's using seeds associated with index values of the group of index values; (4) generating a group of ciphertext blocks at least in part with XOR operations using at least the substitution values and the sequencing values; (5) concatenating the group of ciphertext blocks; and (6) transmitting.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
H03K 19/17768 - Structural details of configuration resources for security
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
A data storage system has a CPU data bus for reading and writing data to data accelerators. Each data accelerator has a controller which receives the read and write requests and determines whether to read or write a local cache memory in preprocessed form or an attached accelerator memory which has greater size capacity based on entries in an address translation table (ATT) and saves data in a raw unprocessed form. The controller may also include an address translation table for mapping input addresses to memory addresses and indicating the presence of data in preprocessed form.
A multi-stage processor has a pre-fetch stage, and a sequence of pipelined processor stages. A thread map register contains thread identifiers, and a thread map valid register has locations corresponding to the thread map register and indicating whether a value in the thread map register is to be fetched or not, and a thread map length register indicates the number of thread map register locations forming a canonical sequence of thread identifiers to the pre-fetch stage. The pre-fetch stage does not act on a thread identifier with a not valid thread map valid value, thereby saving power in low demand conditions.
A system and method for a memory device is disclosed. A substrate is provided. A nucleation pad is disposed over the substrate. A nanowire is disposed substantially perpendicular, about a center of the nucleation pad. A charge current is selectively passed through the substrate to nucleate a magnetic vortex in the nucleation pad, the magnetic vortex indicative of a magnetic domain and a direction of the magnetic vortex indicative of a polarity of the magnetic domain. A shift current is applied through the nanowire to shift the magnetic domain into the nanowire.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
A system and method for a logic device is disclosed. A first substrate, and a second substrate is provided, which are spaced apart from each other and manifests Spin orbit torque effect. A nanomagnet is disposed over the first substrate and the second substrate. A first charge current is passed through the first substrate and a second charge current is passed through the second substrate. A direction of flow of the first charge current and the second charge current defines an input value of either a first value or a second value. A spin in the nanomagnet is selectively oriented based on the direction of flow of the first charge current and the second charge current. The spin in the nanomagnet is selectively read to determine an output value as the first value or the second value. The logic device is configured as a XOR logic.
H03K 19/18 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using galvano-magnetic devices, e.g. Hall-effect devices
H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
A system and method for a logic device is disclosed. A first nanotrack along a first axis and a second nanotrack along a second axis perpendicular to the first axis are disposed over a substrate. The second nanotrack is disposed over the first nanotrack in a overlap portion. An input value is defined about a first end of the first nanotrack and the second nanotrack by nucleating a skyrmion, wherein a presence of the skyrmion defines a first value and absence of the skyrmion defines a second value. The nucleated skyrmion moves towards the second end of the nanotracks when a charge current is passed through the first nanotrack and the second nanotrack along the second axis. The presence of the skyrmion sensed at the second end of the nanotrack indicates an output value of the first value.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H03K 19/18 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using galvano-magnetic devices, e.g. Hall-effect devices
A decision feedback equalizer includes a summer, a slicer, and a feedback circuit. The summer is configured to receive an input signal and a correction signal from the feedback circuit and generate a summer output signal. The slicer includes a first slicer and a second slicer, both are configured to receive the summer output signal as an input, and output a slicer output signal. The feedback circuit is configured to receive the slicer output signal, and based on the slicer output signal, generate the correction signal. The input signal is received at a first clock rate. The first slicer and the second slicer sample the input signal at a second clock rate, about half the first clock rate.
In some embodiments computing device is configured to perform at least (1) accepting as inputs at least an input feature map having one or more first elements and at least one or more filters having one or more second elements (2) computing at least a first prediction value for a first stride (3) computing at least a second prediction value associated with the at least a second stride, wherein the first prediction value and the at least a second prediction value define a group of prediction values associated with the stride tensor (4) determining the greatest prediction value, the greatest prediction value is associated with one selected stride of the stride tensor and (5) executing a convolution operation only for the selected stride of the stride tensor.
A master processor is configured to execute a first thread and a second thread designated to run a program in sequence. A slave processor is configured to execute a third thread to run the program in sequence. An instruction fetch compare engine is provided. The first thread initiates a first thread instruction fetch for the program and stored in an instruction fetch storage. Retrieved data associated with the fetched first thread instruction is stored in a retrieved data storage. The second thread initiates a second thread instruction fetch for the program. The instruction fetch compare logic compares the second thread instruction fetch for the program with the first thread instruction fetch stored in the instruction fetch storage for a match. When there is a match, the retrieved data associated with the fetched first thread instruction is presented from the retrieved data storage, in response to the second thread instruction fetch.
An exemplary branch predictor apparatus comprises a Pattern History Table (PHT) configured with a PHT allocation multiplexer / demultiplexer (PAMD) configurable to output a prediction logically selected from a portion of the PHT entries selectively allocated among a plurality of threads. The PHT entries may be allocated among a plurality of threads based on control bits read from a Control and Status Register (CSR) at system initialization. The branch predictor may govern a plurality of threads fetching instructions from an address selected from a Branch Target Buffer (BTB) entry indexed based on a per-thread Program Counter (PC) or a PHT entry indexed based on a per-thread Global History Register (GBHR). The PHT entries may be saturating binary counters. The saturating counters may be two-bit counters. An exemplary implementation may permit reduced misprediction rate, increased throughput, or reduced energy consumption resulting from increased allocation of PHT entries to more branch-intensive threads.
A master processor is configured to execute a first thread and a second thread designated to run a program in sequence. A slave processor is configured to execute a third thread to run the program in sequence. An instruction fetch compare engine is provided. The first thread initiates a first thread instruction fetch for the program and stored in an instruction fetch storage. Retrieved data associated with the fetched first thread instruction is stored in a retrieved data storage. The second thread initiates a second thread instruction fetch for the program. The instruction fetch compare logic compares the second thread instruction fetch for the program with the first thread instruction fetch stored in the instruction fetch storage for a match. When there is a match, the retrieved data associated with the fetched first thread instruction is presented from the retrieved data storage, in response to the second thread instruction fetch.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Energy efficient computer chips, energy efficient computer memory modules, computer chips, computer memory modules, energy efficient computer systems, computer operating systems, downloadable software, and systems on a chip (SOC) for use in the life sciences, including modelling biological structures, pharmaceutical drugs, or genetic sequences using artificial intelligence. Technical support services, namely, providing technical information in relation to computer chips, computer memory modules, computer operating systems, downloadable software, and systems on a chip (SOC) that are used in the life sciences for modelling biological structures, pharmaceutical drugs, or genetic sequences using artificial intelligence.
43.
Address dependent wordline timing in asynchronous static random access memory
A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.
A system and method for a logic device is disclosed. A plurality of nanotracks are disposed over a substrate, along a first axis, with at least a left nanotrack, a right nanotrack and a middle nanotrack disposed between the left nanotrack and the right nanotrack. At least one connector nanotrack is disposed to connect two adjacent nanotracks. An input value is defined at a first end of the plurality of nanotracks by selectively nucleating a skyrmion at the first end. Presence of the skyrmion is indicative of a first value and absence of the skyrmion indictive of a second value. The nucleated skyrmion moves towards the second end of the nanotrack when a charge current is passed along the first axis. The presence of the skyrmion sensed at the second end of the middle nanotrack indicates an output value of the first value.
H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Energy efficient computer chips; energy efficient computer memory modules; computer chips; computer memory modules; energy
efficient computer systems primarily comprised of computer hardware; downloadable computer operating system software;
downloadable software and system on a chip (SOC) for modelling biological structures using artificial intelligence Technical support services, namely, providing technology information in relation to computer chips, computer memory modules,
computer operating systems, downloadable software, and systems on a chip (SOC) that are used for modelling biological
structures using artificial intelligence
A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Energy efficient computer chips; energy efficient computer memory modules; computer chips; computer memory modules; energy
efficient computer systems primarily comprised of computer hardware; downloadable computer operating system software;
downloadable software and system on a chip (SOC) for modelling biological structures using artificial intelligence Technical support services, namely, providing technology information in relation to computer chips, computer memory modules,
computer operating systems, downloadable software, and systems on a chip (SOC) that are used for modelling biological
structures using artificial intelligence
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Energy efficient computer chips; energy efficient computer memory modules; computer chips; computer memory modules; energy efficient computer systems primarily comprised of computer hardware; downloadable computer operating system software; downloadable software and system on a chip (SOC) for modelling biological structures using artificial intelligence Technical support services, namely, providing technology information in relation to computer chips, computer memory modules, computer operating systems, downloadable software, and systems on a chip (SOC) that are used for modelling biological structures using artificial intelligence
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Energy efficient computer chips; energy efficient computer memory modules; computer chips; computer memory modules; energy
efficient computer systems primarily comprised of computer hardware; downloadable computer operating system software;
downloadable software and system on a chip (SOC) for modelling biological structures using artificial intelligence Technical support services, namely, providing technology information in relation to computer chips, computer memory modules,
computer operating systems, downloadable software, and systems on a chip (SOC) that are used for modelling biological
structures using artificial intelligence
50.
Programmable multi-level data access address generator
A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.
A cryptographic method includes (1) with the first chiplet, parsing a message into one or more message blocks (2) dynamically generating a first target value that is associated with a first key (3) dynamically generating a second target value that is associated with a second key (4) encrypting at least one message block of the at least one or more message blocks to generate some ciphertext, the encryption being performed with at least one operation that includes at least one XOR operation, the at least one XOR operation performed at least in part with the first target value and with at least the second target value, the first target value and the second target value being accessed via the first and second keys, respectively; and (5) with at least one processing device associated with the first chiplet, transmitting the some ciphertext to a second chiplet.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
H04L 9/14 - Arrangements for secret or secure communicationsNetwork security protocols using a plurality of keys or algorithms
52.
Look up table (LUT) based encryption with tag-based verification
A cryptographic method includes at least (1) receiving a message for encryption, (2) encrypting the message to obtain message ciphertext, the encryption including at least one or more operations that include at least one or more XOR operations, (3) computing a tag on a concatenation that includes at least a nonce, the message ciphertext, and other data, (4) encrypting the tag to obtain one or more ordered blocks of tag ciphertext, the encryption including at least one or more operations that include at least one or more XOR operations, (5) appending the one or more ordered blocks of tag ciphertext to the message ciphertext to obtain final ciphertext, and (6) transmitting the final ciphertext to a second chiplet.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
53.
System for error detection and correction in a multi-thread processor
A system for detecting errors and correcting errors in a multi-thread processor is disclosed. The multi-thread processor includes a first processor and a second processor. First processor executes a first thread and a second thread. Second processor executes a third thread and fourth thread. An instruction execution is initiated in all four threads. Output of the instruction execution from all four threads are compared for a match by a data compare engine to detect an error in execution of the instruction. When output of the instruction execution from one of the four threads does not match, an error in execution is detected and the output is replaced by one of the other three threads whose output does match. When output of the instruction execution by two or more threads does not match, error is detected, but not corrected.
A process for iterating through a multi-dimensional array has an iteration process and an address generation process. In one example of the invention an input address process, a coefficient address process, and an output address process generate addresses for a convolutional neural network (CNN. Each of the input address process, coefficient address process, and output address process is coupled to a plurality of iteration variables generated by an iteration variable process, each iteration variable process having an associated with a bound and stride for each iteration variable, thereby generating an input address, a coefficient address, and an output address.
A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.
A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G11C 8/00 - Arrangements for selecting an address in a digital store
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
57.
Memory management unit for multi-threaded architecture
An exemplary multi-threaded memory management system comprises a memory management unit (MMU) configured with a plurality of physical address (PA) output ports individually dedicated to a respective plurality of threads, wherein the MMU is configured to adjust scheduling of the plurality of threads based on the status of an item requested from a cache. The MMU may be configured to translate a virtual address (VA) input from an individual thread to a PA output on the respective PA output port. The cache may be a translation look-aside buffer. The item requested from the cache may be in transient status when a response is expected or valid status when the response is received. The MMU may signal a thread scheduler to run a thread when a requested item's status becomes valid, permitting stalling individual threads without blocking other threads that continue running using the PA output port dedicated to each thread.
A system and method for a logic device is disclosed. A first substrate, a second substrate and a third substrate is provided. A first input nanomagnet is disposed over the first substrate, a second input nanomagnet is disposed over the second substrate, and a third input nanomagnet is disposed over the third substrate. A spacer layer is disposed over the first input nanomagnet, the second input nanomagnet, and the third input nanomagnet. An output magnet is disposed over the spacer layer.
H03K 19/16 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using saturable magnetic devices
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
An exemplary SIMD computing system comprises a SIMD processing element (SPE) configured to perform a selected operation on a portion of a processor input data word, with the operation selected by control signals read from a control memory location addressed by a decoded instruction. The SPE may comprise one or more adder, multiplier, or multiplexer coupled to the control signals. The control signals may comprise one or more bit read from the control memory. The control memory may be an M×N (M rows by N columns) memory having M possible SIMD operations and N control signals. Each instruction decoded may select an SPE operation from among N rows. A plurality of SPEs may receive the same control signals. The control memory may be rewritable, advantageously permitting customizable SIMD operations that are reconfigurable by storing in the control memory locations control signals designed to cause the SPE to perform selected operations.
G06F 15/00 - Digital computers in generalData processing equipment in general
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
60.
SCAN-CHAIN FOR MEMORY WITH REDUCED POWER CONSUMPTION
A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.
A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable wordline signal pulse width which may be reduced sufficiently to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and a nearly error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline signal pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline signal pulse width with an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.
A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
64.
ONE TRANSISTOR MEMORY BITCELL WITH ARITHMETIC CAPABILITY
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
65.
DYNAMIC ADJUSTMENT OF WORD LINE TIMING IN STATIC RANDOM ACCESS MEMORY
A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. SRAM power consumption of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.
An exemplary fault-tolerant computing system comprises a secondary processor configured to execute in delayed lock step with a primary processor from a common program store, comparators in the store data and writeback paths to detect a fault based on comparing primary and secondary processor states, and a writeback path delay permitting aborting execution when a fault is detected, before writeback of invalid data. The secondary processor execution and the primary processor store data and writeback may be delayed a predetermined number of cycles, permitting fault detection before writing invalid data. Store data and writeback paths may include triple module redundancy configured to pass only majority data through the store data and writeback path delay stages. Some implementations may forward data from the store data path delay stages to the writeback stage or memory if the load data address matches the address of data in a store data path delay stage.
In some embodiments, an edge device is configured to execute machine learning procedures with a sparse dataset. The edge device includes at least (1) one or more sensor interfaces, (2) one or more microcontrollers (MCUs), and one or more memories in communication with the one or more microcontrollers. The one or more memories contain one or more executable instructions that cause the one or more microcontrollers to perform operations that include at least: (a) receiving one or more batches of real-time sensor data via the one or more sensor interfaces, the one or more batches defining the sparse dataset, and creating one or more batches of augmented data with the one or more batches of real-time sensor data and one or more batches of generated synthetic data. In some embodiments the edge device is a resource-constrained edge device.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
68.
Modular analog multiplier-accumulator unit element for multi-layer neural networks
An analog machine learning architecture uses modular analog multiplier-accumulator (AMAC) elements of fixed size to form a machine learning (ML) system with increasing feature map size. A single 3×3×64 AMAC array is arranged to provide a three layer ML architecture with first layer 3×3×64, second layer 3×3×128, and third layer 3×3×256 using arrangements of single 3×3×64 AMACs arranged in parallel, where the bias of each AMAC is separately established in a unique interval of time.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06N 3/04 - Architecture, e.g. interconnection topology
69.
Systems and methods for a lightweight pattern-aware generative adversarial network
A computer-implemented method includes training at least a generative adversarial network, the method operable on one or more processors. The method includes at least (1) applying pattern extraction to a set of training data to extract one or more feature embeddings representing one or more features of the training data, (2) attenuating the one or more feature embeddings to create one or more attenuated feature embeddings, (3) providing the one or more attenuated embeddings to a generator of the generative adversarial network as a condition to at least partly control the generator in generating synthetic data, the providing being performed automatically and dynamically during training of the generator, and (4) with the generator, generating synthetic data based at least in part on the attenuated embeddings.
An analog machine learning architecture uses modular analog multiplier-accumulator (AMAC) elements of fixed size to form a machine learning (ML) system with increasing feature map size. A single 3 x 3 x 64 AMAC array is arranged to provide a three layer ML architecture with first layer 3x3x64, second layer 3x3x128, and third layer 3x3x256 using arrangements of single 3x3x64 AMACs arranged in parallel, where the bias of each AMAC is separately established in a unique interval of time.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
71.
CORE PROCESSOR AND REDUNDANT BRANCH PROCESSOR WITH CONTROL FLOW ATTACK DETECTION
A secure processor with fault detection has a core thread which executes with a redundant branch processor thread. In one configuration, the core thread is operative on a fully functional core processor configured to execute a complete instruction set, and the redundant branch processor thread contains only initialization instructions and flow control instructions such as branch instructions and is operative on a redundant branch processor which is configured to execute a subset of the complete instruction set, specifically a branch control variable initialization and a branch instruction, thereby greatly simplifying the redundant branch processor architecture. Fault conditions are detected by comparing either a history of branch taken/not taken and branch targets, or a comparison of program counter activity for the core thread and redundant branch processor thread.
A secure processor with fault detection has a core thread which executes with a redundant branch processor thread. In one configuration, the core thread is operative on a fully functional core processor configured to execute a complete instruction set, and the redundant branch processor thread contains only initialization instructions and flow control instructions such as branch instructions and is operative on a redundant branch processor which is configured to execute a subset of the complete instruction set, specifically a branch control variable initialization and a branch instruction, thereby greatly simplifying the redundant branch processor architecture. Fault conditions are detected by comparing either a history of branch taken/not taken and branch targets, or a comparison of program counter activity for the core thread and redundant branch processor thread.
G06F 21/52 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
Embodiments are provided for instructions cache system for a hardware multi-thread microprocessor. In some embodiments, a cache controller device includes multiple interfaces connected to a hardware multi-thread microprocessor. A first interface of the multiple interfaces can receive a fetch request from a first execution thread during a first clock cycle. A second interface of the multiple interfaces can receive a fetch request from a second execution thread during a second clock cycle after the first clock cycle. The cache controller device also includes a multiplexer to send first response signals in response to the fetch request from the first execution thread, and also to send second response signals in response to the fetch request from the second execution thread.
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 7/38 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
G06F 9/44 - Arrangements for executing specific programs
74.
Multiple interfaces for multiple threads of a hardware multi-thread microprocessor
Embodiments are provided for instructions cache system for a hardware multi-thread microprocessor. In some embodiments, a cache controller device includes multiple interfaces connected to a hardware multi-thread microprocessor. A first interface of the multiple interfaces can receive a fetch request from a first execution thread during a first clock cycle. A second interface of the multiple interfaces can receive a fetch request from a second execution thread during a second clock cycle after the first clock cycle. The cache controller device also includes a multiplexer to send first response signals in response to the fetch request from the first execution thread, and also to send second response signals in response to the fetch request from the second execution thread.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
75.
Efficient storage of blockchain in embedded device
A lightweight node in a decentralized network includes stores a blockchain with a plurality of blocks. The lightweight node adds blocks to the blockchain successively. A given block having a header and a body. The header includes a data merkle root generated as a root hash of a data merkle tree with one or more leaf nodes that are one or more hashes. A given hash being a hash of a combination of (1) a public key associated with a lightweight node of the decentralized network and (2) of a validity value associated with the public key indicating whether the public key is a valid public key. The data merkle root being insufficient for restoring the data merkle tree. But with a public key and an intermediate hash the date merkle root is sufficient for at least partly verifying the public key.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
H04L 9/00 - Arrangements for secret or secure communicationsNetwork security protocols
An unenrolled lightweight node is on a decentralized network with a trusted node and a plurality of peers. The unenrolled lightweight node and the peers run a lightweight blockchain consensus algorithm. The unenrolled lightweight node includes (a) circuitry for storing a token that includes a signature that includes at least a signature of at least a first identifier signed with a private key of the trusted node, the first identifier being associated with a public key of the unenrolled lightweight node, and (b) circuitry for broadcasting a request for blockchain enrollment of the unenrolled lightweight node to the plurality of peers. The authentication request including at least a second identifier that is associated with at least a public key of the unenrolled lightweight node, a signature created with at least the second identifier and a corresponding private key of the unenrolled lightweight node, and the token.
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
H04L 9/00 - Arrangements for secret or secure communicationsNetwork security protocols
77.
Chip to chip interconnect beyond sealring boundary
A plurality of integrated circuits each have a central interconnect region which is enclosed by an inner sealring, optional intermediate sealrings, and an outer sealring. Each sealring has a sealring gap for passage of a signal trace which connects a central interconnect of a first integrated circuit to a central interconnect of a second integrated circuit. In first example of the invention, the signal trace remains on a single layer and routes through sealring layer gaps between the first and second IC. In a second example of the invention, vias are used in gaps between sealrings for the signal trace to change layers such that the sealring gaps are not on the same layer. In a third example of the invention, the vias of the second example are replaced by capacitors with plates in adjacent layers.
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
78.
POWER SAVING FLOATING POINT MULTIPLIER-ACCUMULATOR WITH PRECISION-AWARE ACCUMULATION
A floating point multiplier-accumulator (MAC) multiplies and accumulates N pairs of floating point values using N MAC processors operating simultaneously, each pair of values comprising an input value and a coefficient value to be multiplied and accumulated. The pairs of floating point values are simultaneously processed by the plurality of MAC processors, each of which outputs a signed integer form fraction and a maximum exponent. A range estimator forms a possible range of values from the exponent differences and determines an adder precision. The integer form fractions are summed using the adder precision, a sign bit is extracted, and a floating point value is output. Each MAC processor provides its integer form fraction with a precision determined by the MAC processor's exponent difference.
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
A plurality of integrated circuits each have a central interconnect region which is enclosed by an inner sealring, optional intermediate sealrings, and an outer sealring. Each sealring has a sealring gap for passage of a signal trace which connects a central interconnect of a first integrated circuit to a central interconnect of a second integrated circuit. In first example of the invention, the signal trace remains on a single layer and routes through sealring layer gaps between the first and second IC. In a second example of the invention, vias are used in gaps between sealrings for the signal trace to change layers such that the sealring gaps are not on the same layer. In a third example of the invention, the vias of the second example are replaced by capacitors with plates in adjacent layers.
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H01L 23/04 - ContainersSeals characterised by the shape
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
80.
Process for performing floating point multiply-accumulate operations with precision based on exponent differences for saving power
A process for a floating point multiplier-accumulator (MAC) is operative on N pairs of floating point values using N MAC processes operating concurrently, each MAC process operating on a pair of values comprising an input value and a coefficient value. Each MAC process simultaneously generates an integer form fraction accompanied by a sign bit and an exponent difference computed by subtracting an exponent sum from a maximum exponent sum of all exponent sums. A range estimating process determines a possible range of values from the exponent differences and determines an adder precision. A summing process adds all of the integer form fractions using the determined adder precision, and converts the sum to a floating point value using the maximum exponent sum, sign bit of the summed integer form fractions, and optionally performs a 2's complement of the summed integer form fraction if the sign bit is negative.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
A process for a floating point multiplier-accumulator (MAC) is operative on N pairs of floating point values using N MAC processes operating concurrently, each MAC process operating on a pair of values comprising an input value and a coefficient value. Each MAC process simultaneously generates: an integer form fraction at a first bitwidth and a second bitwidth greater than the first bitwidth, a sign bit, and an exponent difference computed by subtracting an exponent sum from a maximum exponent sum of all exponent sums. The integer form fractions of the first bitwidths are provided to an adder tree using the first bitwidth, and if the sum has an excess percentage of leading 0s, then the second bitwidth is used by an adder tree using the second bitwidth to form a great precision integer form fraction. The sign, integer form fraction, and maximum exponent are provided to an normalizer which generates a floating point result.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
A floating point multiplier-accumulator (MAC) multiplies and accumulates N pairs of floating point values using N MAC processors operating simultaneously, each pair of values comprising an input value and a coefficient value to be multiplied and accumulated. The pairs of floating point values are simultaneously processed by the plurality of MAC processors, each of which outputs a signed integer form fraction and a maximum exponent. A range estimator forms a possible range of values from the exponent differences and determines an adder precision. The integer form fractions are summed using the adder precision, a sign bit is extracted, and a floating point value is output. Each MAC processor provides its integer form fraction with a precision determined by the MAC processor's exponent difference.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
A floating point multiplier-accumulator (MAC) multiplies and accumulates N pairs of floating point values using N MAC processors operating simultaneously, each pair of values comprising an input value and a coefficient value to be multiplied and accumulated. The pairs of floating point values are simultaneously processed by the plurality of MAC processors, each of which output a signed integer form fraction with a first bitwidth and a second bitwidth, along with a maximum exponent. The first bitwidth signed integer form fractions are summed by an adder tree using the first bitwidth to form a first sum, and when an excess leading 0 condition is detected, a second adder tree operative on the second bitwidth integer form fractions forms a second sum. The first sum or second sum, along with the maximum exponent, is converted into floating point result.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.
A node mesh contains an originating node and several node groups, each node group consisting of one or more nodes with interfaces connected to other nodes of the node group. Each node of a node group has an associated route table with an association between an applied DC voltage and an output interface to couple the input signal to. When the originating node outputs a DC voltage accompanied by differential signaling, each node in turn directs the DC voltage and differential signaling to an output interface as directed by the node local route table to a local termination in a node, which may be coupled to a training processor of inference processor for machine learning applications.
An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.
H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
87.
Bias unit element with binary weighted charge transfer capacitors
A Bias Unit Element (UE) has a digital input and sign input, and comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A Gain Balanced Analog Multiply-Accumulator (AMAC) has an inference memory which outputs subsets of inference data comprising X input values and one or more associated W coefficient values, and a number of Analog Multiplier-Accumulator Unit Elements (AMAC UE) in equal number to the number of X input values in each subset of inference data. The X input values and one or more W coefficient values from the inference memory are applied to each AMAC UE to generate a charge corresponding to the multiplication of X input value and W coefficient value of each AMAC UE which is transferred to a shared analog charge bus. The inference memory applies the X input value and W coefficient values of each subset to a different AMAC UE on subsequent cycles to balance the gain of the AMAC such that gain differences from one AMAC UE to another are not cumulative.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through binary weighted charge transfer capacitors to a positive charge transfer line and negative charge transfer line.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type
H03M 3/04 - Differential modulation with several bits
90.
Chopper stabilized analog multiplier accumulator with binary weighted charge transfer capacitors
An architecture for a chopper stabilized multiplier-accumulator (MAC) uses a chop clock and common Unit Element (UE), the MAC formed as a plurality of MAC UEs receiving X and W values and a sign bit exclusive ORed with the chop clock, a plurality of Bias UEs receiving E value and a sign bit exclusive ORed with the chop clock, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
91.
Chopper stabilized analog multiplier unit element with binary weighted charge transfer capacitors
A Unit Element (UE) has a positive UE and a negative UE, each having a digital X input and a digital W input with a sign bit, the sign bit is exclusive ORed with a chop clock to generate a chopped sign bit. The positive UE is enabled when the chopped sign bit is positive and the negative UE is enabled when the chopped sign bit is negative. Each positive and negative UE comprises groups of NAND gates generating an output and complementary output which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The NAND gate outputs and complementary outputs are coupled through binary weighted charge transfer capacitors the positive charge transfer line and negative charge transfer line.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type
H03M 3/04 - Differential modulation with several bits
92.
Chopper stabilized bias unit element with binary weighted charge transfer capacitors
A Bias Unit Element (UE) has a digital input, a sign input, and a chop clock. The sign input is exclusive ORed with the chop clock to generate a signed chop clock. Each Bias UE comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The chopped sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06G 7/16 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for multiplication or division
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type
H03M 3/04 - Differential modulation with several bits
93.
RECONFIGURABLE MULTI-THREAD PROCESSOR FOR SIMULTANEOUS OPERATIONS ON SPLIT INSTRUCTIONS AND OPERANDS
A superscalar processor has a thread mode of operation for supporting multiple instruction execution threads which are full data path wide instructions, and a micro-thread mode of operation where each thread supports two micro-threads which independently execute instructions. An executed instruction sets a micro-thread mode and an executed instruction sets the thread mode.
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 7/38 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
Embodiments are provided for mitigation of branch misprediction penalty in hardware multi-thread microprocessors. In some embodiments, a hardware multi-thread microprocessor includes first stage circuitry that fetches a pair of consecutive instructions of a program executed in a thread. Such microprocessor also includes second stage circuitry that determines, during a clock cycle, that a first instruction in that pair is a branch instruction. The first stage circuitry fetches, during a second clock cycle after the clock cycle, a pair of branch target instructions of the program using a branch prediction. Such microprocessor further includes third stage circuitry that determines that the branch prediction is a misprediction during the second clock cycle. The first stage circuitry sends the second instruction to the second stage circuitry during a third clock cycle after the second clock cycle. The second stage circuitry decodes the second instruction during the third clock cycle.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Computer chips, computer memory modules, downloadable computer operating systems software, downloadable software, and systems on a chip (SOC) for performing machine learning; Downloadable software using artificial intelligence for performing machine learning functions over neural networks, including pharmaceutical drug development and life sciences applications, robotics applications, and convolutional computations. Technical support services, namely, providing technological information in relation to computer chips, computer memory modules, computer operating systems, downloadable software, and systems on a chip (SOC) that are used for performing machine learning and artificial intelligence functions
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Computer chips, computer memory modules, downloadable computer operating systems software, downloadable software, and systems on a chip (SOC) for performing machine learning and artificial intelligence functions Technical support services, namely, providing technological information in relation to computer chips, computer memory modules, computer operating systems, downloadable software, and systems on a chip (SOC) that are used for performing machine learning and artificial intelligence functions
97.
Reconfigurable multi-thread processor for simultaneous operations on split instructions and operands
A superscalar processor has a thread mode of operation for supporting multiple instruction execution threads which are full data path wide instructions, and a micro-thread mode of operation where each thread supports two micro-threads which independently execute instructions. An executed instruction sets a micro-thread mode and an executed instruction sets the thread mode.
A process for performing vector dot products receives a row vector and a column vector as floating point numbers in a format of sign plus exponent bits plus mantissa bits. The process generates a single dot product value by separately processing the sign bits, exponent bits, and mantissa bits to form a sign bit, a normalized mantissa formed by multiplying pairs multiplicand elements, and exponent information including MAX_EXP and EXP_DIFF. A second pipeline stage receives the multiplied pairs of normalized mantissas, optionally performs an exponent adjustment, pads, complements and shifts the normalized mantissas, and the results are added in a series of stages until a single addition result remains, which is normalized using MAX_EXP to form the floating point output result.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
A vector dot product multiplier receives a row vector and a column vector as floating point numbers in a format of sign plus exponent bits plus mantissa bits. The dot product multiplier generates a single dot product value by separately processing the sign bits, exponent bits, and mantissa bits in a few pipelined stages. A first pipeline stage generates a sign bit, a normalized mantissa formed by multiplying pairs multiplicand elements, and exponent information. A second pipeline stage receives the multiplied pairs of normalized mantissas, performs an adjustment, performs a padding, complement, and shift, and sums the results in an adder stage. The resulting integer is normalized to generate a sign bit, exponent, and mantissa of the floating point result.
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
100.
Differential unit element for multiply-accumulate operations on a shared charge transfer bus
A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to differential charge transfer lines through respective charge transfer capacitor Cu. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through a charge transfer capacitor Cu to charge transfer lines. Multiple Unit Elements may be placed in parallel to sum and scale the charges from the charge transfer lines, the charges coupled to an analog to digital converter which forms the dot product output.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06G 7/16 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for multiplication or division
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
