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2024
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G/S
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Licensing IP cores and Hardware Description Language (HDL) code for energy efficient computer chi... |
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Invention
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Device authentication using blockchain.
An unenrolled lightweight node is on a decentralized net... |
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Invention
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Dynamic adjustment of word line timing in static dynamic random access memory.
A static random a... |
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Invention
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Efficient storage of blockchain in embedded devices.
A lightweight node in a decentralized netwo... |
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2023
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G/S
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Energy efficient computer chips, energy efficient computer memory modules, computer chips, energy... |
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G/S
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Energy efficient computer chips, energy efficient computer memory modules, computer chips, comput... |
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G/S
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Scientific and technological services, namely, research and design in the field of semiconductors... |
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G/S
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Energy efficient computer chips; energy efficient computer memory modules; computer chips; comput... |
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Invention
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Synchronization of asymmetric processors executing in quasi-dual processor lock step computing sy... |
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Invention
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Max-pool prediction for efficient convolutional nuerual network for resource-constrained devices.... |
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Invention
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Process for scan chain in a memory. A scan chain architecture with lowered power consumption comp... |
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Invention
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Fast recovery for dual core lock step. An exemplary fault-tolerant computing system comprises a s... |
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Invention
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Programmable multi-level data access address generator. A programmable address generator has an i... |
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Invention
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System and method for skyrmion based logic device. A system and method for a logic device is disc... |
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Invention
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System and method for antiferromagnet skyrmion based logic device. A system and method for a logi... |
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2022
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Invention
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Scan-chain for memory with reduced power consumption. A scan chain architecture with lowered powe... |
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Invention
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Multi-threaded processor with power granularity and thread granularity. A multi-stage processor h... |
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Invention
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One transistor memory bitcell with arithmetic capability. refref to generate an output which is a... |
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Invention
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Dynamic adjustment of word line timing in static random access memory. A static random access mem... |
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Invention
|
System and method for nanomagnet based adder circuit. A system and method for a device is disclos... |
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G/S
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Computer chips, computer memory modules, downloadable computer operating systems software, downlo... |
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Invention
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Modular analog multiplier-accumulator unit element for multi-layer neural networks. An analog mac... |
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Invention
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System and method for storing and accessing preprocessed data. A data storage system has a CPU da... |
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Invention
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System and method for nanomagnet based logic device. A system and method for a logic device is di... |
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Invention
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System and method for synthetic antiferromagnet skyrmion based logic device. A system and method ... |
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Invention
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System for a decision feedback equalizer. A decision feedback equalizer includes a summer, a slic... |
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Invention
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System for error detection and correction in a multi-thread processor. A master processor is conf... |
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Invention
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Dynamic allocation of pattern history table (pht) for multi-threaded branch predictors. An exempl... |
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Invention
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Prng-based chiplet to chiplet secure communication using counter resynchronization. A method is p... |
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Invention
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Address dependent wordline timing in asynchronous static random access memory. A static random ac... |
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Invention
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Look up table (lut) based chiplet to chiplet secure communication. A cryptographic method include... |
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Invention
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Look up table (lut) based encryption with tag-based verification.
A cryptographic method include... |
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Invention
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System and method for a pipelined multi-layer switching network. A system and method for a switch... |
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Invention
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System and method for current controlled nanowire memory device. A system and method for a memory... |
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Invention
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Process for generation of addresses in multi-level data access.
A process for iterating through ... |
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Invention
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Memory management unit for multi-threaded architecture. An exemplary multi-threaded memory manage... |
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2021
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Invention
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Reconfigurable simd engine. An exemplary SIMD computing system comprises a SIMD processing elemen... |
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Invention
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Scan chain for memory with reduced power consumption. A scan chain architecture with lowered powe... |
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|
Invention
|
Dynamic adjustment of wordline timing in static random access memory. A static random access memo... |
|
|
Invention
|
One transistor memory bitcell with arithmetic capability. ref to generate an output which is at l... |
|
|
Invention
|
System for error detection and correction in a multi-thread processor. A system for detecting err... |
|
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Invention
|
Edge device for executing a lightweight pattern-aware generative adversarial network.
In some em... |
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Invention
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Systems and methods for a lightweight pattern-aware generative adversarial network.
A computer-i... |
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Invention
|
Modular analog multiplier-accumulator unit element for multi-layer neural networks.
An analog ma... |
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Invention
|
Multi-threaded secure processor with control flow attack detection. A fault detecting multi-threa... |
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|
G/S
|
Electronic components in the nature of integrated circuit chips, none of the foregoing for use in... |
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G/S
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Integrated circuits, integrated circuit chips, and integrated circuit modules for performing mult... |
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2018
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G/S
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Wired and Wireless Communication devices for use with internet fabric such as routers and switche... |
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G/S
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Electronic Hardware and Software for use with sensors and computer peripheral hardware. Electroni... |
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2017
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G/S
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Computer hardware, namely, computer chips, integrated circuit modules, computer and communication... |
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2008
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G/S
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Design for others of integrated circuits and integrated circuit cores for use in wireless communi... |
