A semiconductor structure includes an epitaxial layer on a substrate and a doped region extending from the top surface of the epitaxial layer into the epitaxial layer. A gate structure extends from the top surface of the doped region into the epitaxial layer. The gate structure includes a first polysilicon structure, a gate oxide layer surrounding the first polysilicon structure, a second polysilicon structure over the first polysilicon structure and the gate oxide layer, and an insulating layer, which separates the first polysilicon structure and the gate oxide layer from the second polysilicon structure and surrounds the second polysilicon structure, and extends between the top surface of the epitaxial layer and a diode string disposed over the epitaxial layer. A source structure adjoins the doped region and the second polysilicon structure, and is electrically coupled to the diode string. A method of manufacturing the semiconductor structure is also provided.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
2.
Semiconductor Structure and Manufacturing Method Thereof
A semiconductor structure includes an epitaxial layer on a substrate, a first lightly doped layer on the epitaxial layer, a second lightly doped layer on the first lightly doped layer, a heavily doped layer on the first lightly doped layer, a metal silicide layer on the second lightly doped layer and the heavily doped layer, and a gate structure, which extends from a top surface of the metal silicide layer toward the substrate, through the second lightly doped layer, the heavily doped layer and the first lightly doped layer, and into the epitaxial layer. A doping concentration of the second lightly doped layer at an interface between the second lightly doped layer and the metal silicide layer is less than a doping concentration of the heavily doped layer and greater than a doping concentration of the first lightly doped layer. A method of manufacturing the semiconductor structure is also provided.
BCD SHANGHAI MICRO-ELECTRONICS COMPANY LIMITED (China)
Inventor
Zou, Cong
Dou, Sen
Peng, Shaohua
Abstract
A switching power supply includes a secondary control circuit coupled to a secondary side of a transformer of the switching power supply, and a primary control circuit coupled to a primary side of the transformer. The secondary control circuit is configured to receive a power request signal of a load device, and encode the power request signal to generate encoded information. The primary control circuit is configured to receive, by use of the transformer, a feedback signal reflecting an output voltage of the switching power supply, decode the encoded information based on a change of the feedback signal, and based thereon, control the switching power supply to supply power to the load device.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 1/36 - Means for starting or stopping converters
4.
Power Semiconductor Apparatus and Bonding Method Thereof
A semiconductor device includes a backside supporting layer having a first thickness, an adhesive layer over the backside supporting layer, a metal layer over the adhesive layer, wherein the metal layer functions as a backside connector and comprises a plurality of openings extending through the metal layer, a semiconductor substrate layer over the metal layer, wherein the semiconductor substrate layer has a second thickness, and wherein the adhesive layer is in direct contact with the semiconductor substrate layer through the plurality of openings, and a plurality of front side connectors, wherein active circuits in the semiconductor substrate layer are electrically coupled between the plurality of front side connectors and the metal layer.
A method includes providing a device wafer including a semiconductor substrate and a metal layer disposed over the semiconductor substrate; patterning the metal layer to form a plurality of openings extending through the metal layer; forming a first adhesive layer over the metal layer, wherein the first adhesive layer is in direct contact with the semiconductor substrate through the plurality of openings; providing a backside support wafer; bonding the device wafer to the backside support wafer through the first adhesive layer; curing the first adhesive layer to secure the backside support wafer to the device wafer; and forming recessed regions in the semiconductor substrate corresponding to saw dicing lanes of the device wafer.
An apparatus includes a reference current generation circuit configured to generate a predetermined reference current, a reference current path comprising a first switch, wherein the predetermined reference current is mirrored to generate a reference current in the reference current path, a load current path comprising a power switch, and a pulse width modulation (PWM) deglitch circuit configured to control the first switch to reduce an overshoot of a load current flowing through the power switch.
A semiconductor device includes a device wafer comprising a central portion having a first thickness and an edge portion having a second thickness greater than the first thickness, wherein a front side of the central portion is coplanar with a front side of the edge portion, and a backside of the edge portion protrudes beyond a backside of the central portion, and a backside support wafer bonded to the backside of the central portion through an adhesive layer, wherein at least a portion of the backside support wafer is laterally recessed relative to the edge portion of the device wafer such that the portion of the backside support wafer is surrounded by the edge portion of the device wafer.
An apparatus includes a reference current generation circuit coupled between a first voltage bus and a second voltage bus, wherein the reference current generation circuit is configured to generate a predetermined reference current, a first reference current path comprising a first switch, wherein the predetermined reference current is configured to be mirrored to generate a first reference current in the first reference current path, a load current path comprising a power switch, and an overshoot reduction circuit configured to reduce an overshoot occurring at a leading-edge of a load current flowing through the power switch.
H05B 45/54 - Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDsCircuit arrangements for operating light-emitting diodes [LED] responsive to LED lifeProtective circuits in a series array of LEDs
A metal-oxide-semiconductor (MOS) transistor includes a substrate including a well region, an insulator layer coupled to the substrate, and a source including a source region, a source contact passing through the insulator layer and the source region, and an ohmic contact disposed in the well region. The MOS transistor also includes a gate region including a gate insulator layer and a gate contact and a drain including a drain region and a drain contact passing through the insulator layer to the drain region. The MOS transistor can be an LDMOS transistor, for example, an LNDMOS or LPDMOS transistor.
An apparatus includes a bootstrap capacitor refresh pulse generation circuit configured to generate a refresh pulse to turn on a low-side switch of a power converter once an off-time of the low-side switch exceeds a predetermined threshold, and a logic gate configured to receive the refresh pulse and a low-side pulse width modulation (PWM) signal, and generate a drive signal applied to a gate of the low-side switch of the power converter.
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
11.
BOOTSTRAP CAPACITOR REFRESH CONTROL APPARATUS AND METHOD
An apparatus includes a bootstrap capacitor refresh pulse generation circuit configured to generate a refresh pulse to turn on a low-side switch of a power converter once an off-time of the low-side switch exceeds a predetermined threshold, and a logic gate configured to receive the refresh pulse and a low-side pulse width modulation (PWM) signal, and generate a drive signal applied to a gate of the low-side switch of the power converter.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
12.
Power Semiconductor Packaging and Manufacturing Method Thereof
The power semiconductor device comprises a substrate with a first epitaxial layer disposed above the substrate. The first epitaxial layer comprises a first doped channel located in a peripheral area surrounding a unit area, and the first doped channel extends vertically across the first epitaxial layer. A second epitaxial layer, disposed on the first epitaxial layer, comprises a second doped channel located in the peripheral area and above the first doped channel. The second doped channel extends vertically across the second epitaxial layer. A junction layer is disposed above the second doped channel, with a first electrode located on the junction layer. Current flows from the substrate through the first and second doped channels, the junction layer, and to the first electrode.
A semiconductor structure manufacturing method includes forming, on a protective layer that is on an epitaxial layer, a first patterned hard mask including an opening surrounded by side surfaces of the first patterned hard mask. The first patterned hard mask includes a first dielectric layer, a semiconductor layer and a second dielectric layer sequentially formed on the protective layer. A first doped region is formed in the epitaxial layer below the opening through the first patterned hard mask. A second patterned hard mask is formed on the side surfaces of the first patterned hard mask, through which a second doped region is formed in the epitaxial layer. The first doped region is located along a sidewall of the second doped region. A third patterned hard mask surrounding the second patterned hard mask is formed, through which a third doped region is formed in the second doped region.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
14.
Apparatus and Method for Reducing Stand-by Power Consumption in Isolated Power Conversion System
An apparatus includes a primary controller coupled to a primary circuit, a secondary controller coupled to a secondary circuit and configured to detect a load condition, wherein the secondary controller is configured to in response to detecting a load disconnection, pull down a secondary feedback node for a first predetermined time to signal the primary controller to reduce bias power, and then configure the secondary feedback node as a high impedance node, and in response to detecting a load reconnection, pull down the secondary feedback node for a second predetermined time to wake the primary controller, and wherein the primary controller is configured to detect whether a voltage on the primary feedback node falls below a threshold for at least a third predetermined time, and in response thereto, disable a feedback control loop of the isolated power converter to enter a sleep state.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
15.
Power Semiconductor Apparatus and Bonding Method Thereof
An apparatus includes a backside supporting layer having a first thickness, an adhesive layer over the backside supporting layer, a metal layer over the adhesive layer, wherein the metal layer functions as a backside connector, a semiconductor substrate layer over the metal layer, wherein the semiconductor substrate active layer has a second thickness, and a plurality of front side connectors, wherein active circuits in the semiconductor substrate layer over are electrically coupled between the plurality of front side connectors and the metal layer.
DIODES TECHNOLOGY (CHENGDU) COMPANY LIMITED (China)
DIODES SHANGHAI CO., LTD. (China)
SHANGHAI KAIHONG ELECTRONIC COMPANY LIMITED (China)
Inventor
Nan, Jiang
Abstract
A material container calibration apparatus, comprising: an outer inspection fixture (1) and an inner inspection fixture (2), wherein the outer inspection fixture (1) is formed with an inspection hole (11); at least one side of the inner inspection fixture (2) is provided with a comb-shaped plate (21), and each remaining side is provided with an inspection surface (22); and the comb-shaped plate (21) is formed with a plurality of inspection teeth (211). When a material container (01) passes through the inspection hole (11), the outer inspection fixture (1) is configured for verifying whether an outer side surface of the material container (01) matches an inner side surface of the inspection hole (11). If so, the outer side surface of the material container (01) is acceptable; if not, the outer side surface of the material container (01) is not acceptable. When the inner inspection fixture (2) passes through the material container (01), the inner inspection fixture (2) is configured for verifying whether all inspection teeth (211) pass through all material-retaining grooves (011) of the material container (01) in a one-to-one correspondence, and for verifying whether each of the inspection surfaces (22) matches an inner side surface of the material container (01). If so, the inner side surface of the material container (01) is acceptable; if not, the inner side surface of the material container (01) is not acceptable. The material container calibration apparatus only needs the material container (01) to pass through the outer inspection fixture (1) and the inner inspection fixture (2) respectively. The high inspection accuracy and high inspection efficiency of the material container calibration apparatus allow for the efficient and accurate inspection of material containers (01). Also provided is a material container calibration method.
G01B 5/20 - Measuring arrangements characterised by the use of mechanical techniques for measuring contours or curvatures
G01B 5/30 - Measuring arrangements characterised by the use of mechanical techniques for measuring the deformation in a solid, e.g. mechanical strain gauge
G01B 5/00 - Measuring arrangements characterised by the use of mechanical techniques
An apparatus includes a clock generator configured to generate a set signal fed into a set input of a latch, an error amplifier configured to generate a COMP signal, an offset generator configured to generate different offset voltages, and a comparator configured to generate a reset signal fed into a reset input of the latch, wherein a non-inverting input of the comparator is configured to receive a signal equal to a sum of a current sense signal and a slope compensation signal, and wherein the current sense signal is equal to a current flowing through a power converter times an adjustable gain, and an inverting input of the comparator is configured to receive an error signal, and wherein the error signal is equal to the COMP signal minus an offset voltage generated by the offset generator.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
An apparatus includes a clock generator configured to generate a set signal fed into a set input of a latch, an error amplifier configured to generate a COMP signal, an offset generator configured to generate different offset voltages, and a comparator configured to generate a reset signal fed into a reset input of the latch, wherein a non-inverting input of the comparator is configured to receive a signal equal to a sum of a current sense signal and a slope compensation signal, and wherein the current sense signal is equal to a current flowing through a power converter times an adjustable gain, and an inverting input of the comparator is configured to receive an error signal, and wherein the error signal is equal to the COMP signal minus an offset voltage generated by the offset generator.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
An apparatus includes a backside supporting layer having a first thickness, an adhesive layer over the backside supporting layer, a metal layer over the adhesive layer, wherein the metal layer functions as a backside connector, a semiconductor substrate layer over the metal layer, wherein the semiconductor substrate active layer has a second thickness, and a plurality of front side connectors, wherein active circuits in the semiconductor substrate layer over are electrically coupled between the plurality of front side connectors and the metal layer.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
20.
Vertical Power Semiconductor Device and Manufacturing Method Thereof
A semiconductor device includes a substrate comprising a first surface and a second surface positioned on an opposite side of the substrate. A first gate structure is located above the first surface of the substrate and a second gate structure is located above the first surface of the substrate, adjacent to the first gate structure. A first dielectric layer covers the first gate structure, the second gate structure, and the first surface of the substrate. The first dielectric layer has a first opening between the first gate structure and the second gate structure. A current spreading layer is located at a bottom of the first opening. The current spreading layer has a first width approximately equal to a width of the bottom of the first opening. A conductive plug is located between the first gate structure and the second gate structure and in contact with the current spreading layer.
H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
An apparatus includes a first inverter, a first capacitor connected between the input terminal and the output terminal of the first inverter, a second inverter, a third inverter, a second capacitor connected between the input terminal and the output terminal of the third inverter, a fourth inverter, a plurality of resistors coupled in series between an output of a logic gate and a first input of the logic gate, and a third capacitor connected between the first input of the logic gate and ground, wherein the logic gate has a second input configured to receive an enable signal, and wherein each of the first inverter and the third inverter is configured as a negative amplifier such that an effective capacitance between its input and output terminals is greater than a physical capacitance of the corresponding capacitor.
H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
A method of making a semiconductor device is provided. A monolithic die having at least two semiconductor dies is provided. Each of the at least two semiconductor dies includes a substrate and an epitaxial layer formed on the substrate. An isolation structure is formed electrically isolating two semiconductor dies of the at least two semiconductor dies. The isolation structure traverses the thickness of the substrate and the epitaxial layer and includes a first isolation trench.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
23.
Vertical Semiconductor Device and Manufacturing Method Therefor
A vertical semiconductor structure includes a semiconductor material layer having first and second opposite surface, a first shield structure and a first gate structure in the semiconductor material layer and extending from the first surface toward the second surface, and a first doped region in the semiconductor material layer and adjacent to the first surface. The first shield structure comprises a first shield dielectric layer and a first shield electrode surrounded by the first shield dielectric layer. The first gate structure has a depth less than that of the first shield structure and greater than that of the first doped region. The first gate structure is adjacent to the upper portion of the first shield dielectric layer. A thickness of an upper portion of the first shield dielectric layer at the first surface is less than a thickness of a lower portion of the first shield dielectric layer.
An apparatus includes a logic gate, a first inverter, a second inverter, a first resistor connected between the output of the logic gate and the input terminal of the first inverter, a first capacitor connected between the input terminal and the output terminal of the first inverter, a second resistor connected between the output terminal of the first inverter and the input terminal of the second inverter, a second capacitor connected between the input terminal of the second inverter and ground, and a third resistor connected between the output terminal of the second inverter and the logic gate, wherein the second input of the logic gate is configured to receive an enable signal, and wherein the first inverter is configured as a negative amplifier such that an effective capacitance provided by the first inverter and the first capacitor is greater than a physical capacitance of the first capacitor.
H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
An apparatus includes a reference current generation circuit coupled between a first voltage bus and a second voltage bus, wherein the reference current generation circuit is configured to generate a predetermined reference current, a first reference current path comprising a first switch, wherein the predetermined reference current is configured to be mirrored to generate a first reference current in the first reference current path, a load current path comprising a power switch, and a pulse width modulation (PWM) deglitch circuit configured to control the first switch so as to reduce an overshoot occurring at a leading-edge of a load current flowing through the power switch.
An apparatus includes a reference current generation circuit coupled between a first voltage bus and a second voltage bus, wherein the reference current generation circuit is configured to generate a predetermined reference current, a first reference current path comprising a first switch, wherein the predetermined reference current is configured to be mirrored to generate a first reference current in the first reference current path, a load current path comprising a power switch, and a pulse width modulation (PWM) deglitch circuit configured to control the first switch so as to reduce an overshoot occurring at a leading-edge of a load current flowing through the power switch.
A calibration method for a line scan imaging device includes: obtaining a maximum pixel brightness value from first images, wherein the first images are generated by line scan camera modules with a light source turned on, and stitched along a scan line extension direction, and the line scan camera modules are arranged along the scan line extension direction; obtaining second images generated by the line scan camera modules with the light source operating at a predetermined light intensity, wherein a light intensity provided by the light source when the maximum pixel brightness value is less than or equal to a predetermined brightness value serves as the predetermined light intensity; obtaining third images generated by the line scan camera modules with the light source turned off; and generating calibration information based on the second images and the third images.
A bipolar junction transistor (BJT) comprising a semiconductor region and a plurality of metal contacts, located on a top surface of the semiconductor region, where the plurality of metal contacts comprise one or more first metal contacts that are in contact with one or more emitter regions and one or more second metal contacts that are in contact with an upper surface of a body region of the semiconductor region. One or more insulating structures are located on the top surface of the semiconductor region, where the insulating structures isolate the one or more first metal contacts from the one or more second metal contacts. A metal layer is located over the insulating structures, where the metal layer is in contact with one or more first metal contacts and is isolated from the one or more second metal contacts by the insulating structures.
An apparatus includes a plurality of high-side switching elements and a plurality of low-side switching elements arranged to form a reconfigurable power stage, and a controller configured to execute a multi-variable optimization routine to improve an efficiency of the apparatus, wherein the multi-variable optimization routine comprises adjusting a plurality of distinct parameters including a number of active switching elements, a switching frequency, and a turn-on gate voltage, and wherein an adjustment to one of the plurality of distinct parameters is based on a change in a monitored operational parameter indicative of efficiency resulting from a prior adjustment to a different parameter.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
30.
METHOD AND APPARATUS FOR SAR ANALOG-TO-DIGITAL CONVERSION
A successive approximation register (SAR) analog-to-digital converter (ADC) may be used to generate a first digital data of N-bit and a second digital data of N-bit for an analog data. When the second digital data and the first digital data include a first sequence of most significant bits (MSBs) having same values, a third digital data of N-bit may be generated for the analog data using the SAR ADC in a partial mode. In the partial mode, the SAR ADC is configured to skip determining a second sequence of MSBs of the third digital data, and only determine remaining bits of the third digital data. When the second digital data and the first digital data do not include the first sequence of MSBs having same values, the SAR ADC operates in a full mode to determine every bit of the N-bit third digital data.
H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
31.
Method and apparatus for SAR analog-to-digital conversion
A successive approximation register (SAR) analog-to-digital converter (ADC) may be used to generate a first digital data of N-bit and a second digital data of N-bit for an analog data. When the second digital data and the first digital data include a first sequence of most significant bits (MSBs) having same values, a third digital data of N-bit may be generated for the analog data using the SAR ADC in a partial mode. In the partial mode, the SAR ADC is configured to skip determining a second sequence of MSBs of the third digital data, and only determine remaining bits of the third digital data. When the second digital data and the first digital data do not include the first sequence of MSBs having same values, the SAR ADC operates in a full mode to determine every bit of the N-bit third digital data.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
A quartz crystal resonator including a quartz crystal obtained from a quartz bar is provided. The quartz crystal is cut from the quartz bar along a cutting plane in a coordinate system having an optic axis, an electrical axis and a mechanical axis perpendicular to each other. The cutting plane has a first angle of about 35° to about 36° from the optic axis and a second angle of about 14° to about 16° from the electrical axis. The quartz crystal has a vibration frequency deviation within a range from −30 parts per million (ppm) to about +30 ppm over a temperature range from about −50° C. to about 150° C. Methods for making the quartz crystal resonator are also provided.
A trench semiconductor structure includes a semiconductor material layer having a first surface and a second surface. A first trench structure extends from the first surface towards the second surface, and includes an electrode and a gate. The electrode includes a first portion and a second portion below the first portion and the gate. An interlayer dielectric layer is disposed on the first surface covering the first trench structure and a doped region in the semiconductor material layer. A shielding metal layer covers the interlayer dielectric layer and the fist doped region and contacts the electrode. A metal layer is disposed on the shielding metal layer. The first portion of the first electrode is located between the doped region and the gate. The electrode and the doped region contact the shielding metal layer and are electrically connected to the metal layer.
The present application relates to a trenched semiconductor structure and a manufacturing method therefor. The trenched semiconductor structure comprises: a semiconductor material layer, which has a first surface and a second surface and is of a first conductivity type; a first trench structure, extending from the first surface to the second surface and comprising a first electrode and a first gate, the first electrode comprising a first portion adjacent to the first gate and a second portion located below the first portion and the first gate and connected to the first portion; a first doped region, which is located on the semiconductor material layer, is adjacent to the first surface and the first portion, and is of a second conductivity type; an interlayer dielectric layer, which is located on the first surface and covers the first trench structure; a shielding metal layer, which covers the interlayer dielectric layer and the first doped region, and is in contact with the first electrode; and a metal layer, located on the interlayer dielectric layer and the first doped region. The first portion of the first electrode is located between the first doped region and the first gate, and the first electrode and the first doped region are both in contact with the shielding metal layer and are both electrically connected to the metal layer.
Provided in the present invention are a power semiconductor structure and a manufacturing method therefor. The power semiconductor structure comprises: a substrate; an epitaxial layer, which is arranged on the substrate; a recess, which extends into the epitaxial layer; a doped region, which is arranged below the recess; a contact member, which is arranged on the doped region or is partially surrounded by the doped region; and a barrier layer, which is arranged on the epitaxial layer and in the recess, wherein the transverse spacing between the side wall of the recess and the outer side wall of the contact member is uniform around the contact member.
H01L 21/329 - Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors the devices comprising one or two electrodes, e.g. diodes
36.
Linear redriver with tunable low frequency and high frequency zero at equalizer stage
An equalizer stage circuit includes a first transistor and a second transistor disposed in a differential configuration. The equalizer stage circuit also includes a first selectable path. The first selectable path includes: a first terminal coupled to an emitter or a source of the first transistor; a second terminal coupled to an emitter or a source of the second transistor; a high-frequency portion comprising a first plurality of high-frequency RC time constant members connected in parallel between the first terminal and the second terminal; a first capacitor coupled to the first terminal; a second capacitor coupled to the second terminal; and a low-frequency portion comprising a second plurality of low-frequency RC time constant members connected between the first capacitor and the second capacitor.
An equalizer stage circuit includes a first transistor and a second transistor disposed in a differential configuration. The equalizer stage circuit also includes a first selectable path. The first selectable path includes: a first terminal coupled to an emitter or a source of the first transistor; a second terminal coupled to an emitter or a source of the second transistor; a high-frequency portion comprising a first plurality of high-frequency RC time constant members connected in parallel between the first terminal and the second terminal; a first capacitor coupled to the first terminal; a second capacitor coupled to the second terminal; and a low-frequency portion comprising a second plurality of low-frequency RC time constant members connected between the first capacitor and the second capacitor.
An apparatus includes a first inverter having an input terminal and an output terminal, a first capacitive device connected between the input terminal and the output terminal of the first inverter, and a resistor network coupled to the first capacitive device, wherein the first inverter is configured as a negative amplifier, and the first capacitive device and the resistor network are configured to determine a frequency of an oscillator.
H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
A method of manufacturing a power semiconductor structure includes forming a groove extending from a surface of an epitaxial layer into the epitaxial layer. A doped region is formed in the epitaxial layer under the groove. A first dielectric layer is disposed on the epitaxial layer exposing the doped region from the groove. A second dielectric layer is disposed on the first dielectric layer, the doped region and a sidewall of the groove. A portion of the second dielectric layer disposed on the doped region is removed to expose a portion of the doped region, on which a contact material is disposed to form a contact member. The contact member may be formed on the portion of the doped region or partially surrounded by the doped region. A remaining portion of the first dielectric layer and the second dielectric layer is then removed. The groove is optional.
A trench semiconductor structure includes a semiconductor material layer having a first surface and a second surface opposite to the first surface. A first trench structure extends from the first surface toward the second surface, and includes a first electrode, a second electrode above the first electrode, and a first oxide layer surrounding and separating the first electrode and the second electrode. A second trench structure extends from the first surface toward the second surface, and includes a first gate, a third electrode below the first gate, and a second oxide layer surrounding and separating the third electrode and the first gate. A first doped region is provided in the semiconductor material layer, away from the first surface, and between the first trench structure and the second trench structure. A second doped region is provided between the first surface and the first doped region.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
An apparatus includes a first inverter (302) having an input terminal and an output terminal, a first capacitive device (C1) connected between the input terminal and the output terminal of the first inverter, and a resistor network (320) coupled to the first capacitive device, wherein the first inverter is configured as a negative amplifier, and the first capacitive device (C1) and the resistor network are configured to determine a frequency of an oscillator.
A trench semiconductor structure includes a semiconductor material layer of a first conductivity type and having a first surface and a second surface. A first trench structure extends from the first surface toward the second surface, and includes a first electrode, a first gate and a second electrode below the first electrode and the first gate. A first doped region of a second conductivity type is disposed in the semiconductor material layer. A second doped region of the first conductivity type is disposed between the first surface and the first doped region. An interlayer dielectric layer on the first surface covers the first trench structure and the second doped region. The first electrode is located between the first gate and the first doped region. The first electrode and the first doped region are electrically connected to a metal layer on the interlayer dielectric layer. A manufacturing method is also provided.
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
43.
METHOD FOR OPERATING POWER CONVERTER, SEMICONDUCTOR CHIP AND POWER CONVERTER
A power converter includes a transformer, a clamp capacitor, a main switch, a clamp switch, and a control circuit. The transformer has a first primary coil and a secondary coil. The clamp capacitor has a first terminal coupled to a first terminal of the first primary coil. The main switch is coupled to a second terminal of the first primary coil. The clamp switch is coupled between a second terminal of the clamp capacitor and the main switch. The main switch, the clamp switch, and the first primary coil intersect at a node. The control circuit is configured to: periodically turn on the main switch; turn on the clamp switch before the main switch to generate a reverse current; turn off the clamp switch before the main switch to discharge an equivalent capacitor; and adjust an operation of the clamp switch based on a monitored voltage at the node.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A method for forming a semiconductor package includes providing a leadframe including a peripheral frame, a plurality of lead pads, and a die attach pad configured for mounting a semiconductor integrated circuit (IC) chip. The die attach pad comprises a first protruding portion on a first side of the die attach pad and a second protruding portion on a second side of the die attach pad. The method also includes attaching a first semiconductor IC die to the die attach pad, bonding IC die bonding pads to lead pads on the first side of the die attach pad, bonding IC die bonding pads to lead pads on the second side of the die attach pad, applying a molding that covers portions of the leadframe, a die attach material, and the first semiconductor IC die, and separating the plurality of lead pads from the peripheral frame.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
45.
Electrostatic Discharge Protection Structure, Semiconductor Power Device and Manufacturing Method Thereof
An electrostatic discharge protection structure in a semiconductor device includes a first trench structure including a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure. A second trench structure includes a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure. A first diode string is disposed between the first trench structure and the second trench structure and adjoins the first polysilicon structure and the second polysilicon structure. A first spacing oxide layer is disposed on the first diode string. A second diode string is disposed on the first spacing oxide layer and connected in parallel with the first diode string. Each of the first and the second diode strings includes first doped regions and second doped regions disposed alternately. A PN junction is formed at an interface between each first doped region and an adjacent second doped region.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
46.
Electrostatic Discharge Protection Structure, Semiconductor Power Device and Manufacturing Method Thereof
A manufacturing method includes: forming a lightly doped layer on a substrate; forming a first, a second and a third openings extending toward the substrate; forming a first diode string on the lightly doped layer; forming a first spacing oxide layer on the first diode string; forming a second diode string on the first spacing oxide layer; forming a first trench structure in the first opening; forming a source doped region in the lightly doped layer, wherein the source doped region is disposed between the first trench structure and the second opening; and forming a source electrode coupled to the source doped region and forming a gate electrode coupled to the first trench structure. The first diode string and the second diode string are arranged in parallel between the source electrode and the gate electrode.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
50.
Manufacturing Method for a Power MOSFET with a p-n-p-n-p Gate-Source ESD Diode Structure Formed Over A Breakdown Voltage Enhancement and Leakage Prevention Structure Comprising a Reduced Surface Field (RESURF) Structure and a Body Ring Structure
A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure in the epitaxial layer, comprising a reduced surface field (RESURF) structure, forming a source in the epitaxial layer and a gate-source Electrostatic Discharge (ESD) diode structure over the epitaxial layer, forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, and forming a drain contact on the opposing side of the epitaxial layer from the source contact.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a drain contact on opposing sides of the epitaxial layer of the source contact, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, and wherein the breakdown voltage enhancement and leakage prevention structure comprises a reduced surface field (RESURF) structure.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
54.
Electronic Device and Manufacturing Method Thereof
An electronic device includes a first semiconductor chip on a first substrate and a second semiconductor chip on a second substrate separated from the first substrate, with both semiconductor chips arranged between the first substrate and the second substrate. The first semiconductor chip includes a drain coupled to the first substrate and located on a side of the first semiconductor chip, with a gate and a source located on an opposite side of the first semiconductor chip. The second semiconductor chip has a drain coupled to the second substrate and located on a side of the second semiconductor chip, with a gate and a source located on an opposite side of the second semiconductor chip. A first connection structure couples the source of the first semiconductor chip to the second substrate. A second connection structure couples the source of the second semiconductor chip to the first substrate.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
55.
Semiconductor Structures and Manufacturing Methods Thereof
Various methods for manufacturing semiconductor structures are provided. An embodiment method includes forming a first patterned hard mask on a protective layer that is on an epitaxial layer, which includes an opening exposing a portion of the protective layer and surrounded by side surfaces of the first patterned hard mask. A first doped region and a second doped region are formed in a portion of the epitaxial layer below the opening via a first implantation and a second implantation, respectively, through the first patterned hard mask. A second patterned hard mask is formed on the side surfaces of the first patterned hard mask, through which a third doped region is formed in the portion of the epitaxial layer by performing a third implantation. The second doped region at least partially overlaps with the first doped region. The third doped region is surrounded by the second doped region.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
56.
Semiconductor Structures and Manufacturing Methods Thereof
Various methods for manufacturing semiconductor structures are provided. An embodiment method includes forming a first patterned hard mask on a protective layer that is disposed on an epitaxial layer. The first patterned hard mask includes an opening exposing a portion of the protective layer and surrounded by side surfaces of the first patterned hard mask. A second patterned hard mask is formed on the side surfaces of the first patterned hard mask. A first doped region is formed in the portion of the epitaxial layer below the opening using a first implantation through the second patterned hard mask. With the second patterned hard mask removed, a second doped region surrounding the first doped region, and a third doped region are formed in the portion of the epitaxial layer using respective second implantation and third implantation through the first patterned hard mask.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
57.
Semiconductor Structures and Manufacturing Methods Thereof
Various methods for manufacturing semiconductor structures are provided. A first patterned hard mask is formed on a protective layer, which includes an opening exposing a portion of the protective layer and surrounded by side surfaces of the first patterned hard mask. A second patterned hard mask is formed on the side surfaces of the first patterned hard mask. A first doped region is formed in a portion of an epitaxial layer below the opening by implantation through the second patterned hard mask. The second patterned hard mask is removed. A second doped region surrounding the first doped region is then formed in the portion of the epitaxial layer by implantation through the first patterned hard mask. The first patterned hard mask is trimmed to form a third patterned hard mask, through which a third doped region is formed along a sidewall of the second doped region by implantation.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
58.
Semiconductor Structures and Manufacturing Methods Thereof
Various methods for manufacturing semiconductor structures are provided. An embodiment method includes forming a first patterned hard mask on a protective layer that is on an epitaxial layer, which includes an opening exposing a portion of the protective layer and surrounded by side surfaces of the first patterned hard mask. A first doped region is formed in a portion of the epitaxial layer below the opening through the first patterned hard mask. A second patterned hard mask is formed on the side surfaces of the first patterned hard mask, through which a second doped region is formed in the portion of the epitaxial layer with the first doped region located along a sidewall of the second doped region. A third patterned hard mask is formed surrounding the second patterned hard mask, through which a third doped region is formed in the second doped region.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
59.
Semiconductor Structures and Manufacturing Methods Thereof
A semiconductor structure manufacturing method includes forming, on a protective layer that is disposed on an epitaxial layer, a first patterned hard mask including an opening surrounded by side surfaces of the first patterned hard mask and exposing a first portion of the protective layer. A first doped region is formed in a portion of the epitaxial layer below the opening through the first patterned hard mask. A second patterned hard mask is formed on the side surfaces of the first patterned hard mask, through which a second doped region is formed in the first doped region. The second patterned hard mask and a portion of the first patterned hard mask are removed, and a remaining portion of the first patterned hard mask forms a third patterned hard mask, through which a second portion of the protective layer is removed.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
60.
Vertical power semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate comprising a first surface and a second surface positioned on an opposite side of the substrate. A first gate structure is located above the first surface of the substrate and a second gate structure is located above the first surface of the substrate, adjacent to the first gate structure. A first dielectric layer covers the first gate structure, the second gate structure, and the first surface of the substrate. The first dielectric layer has a first opening between the first gate structure and the second gate structure. A current spreading layer is located at a bottom of the first opening. The current spreading layer has a first width approximately equal to a width of the bottom of the first opening. A conductive plug is located between the first gate structure and the second gate structure and in contact with the current spreading layer.
H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
An electrostatic discharge protection structure in a semiconductor device includes a first trench structure including a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure. A second trench structure includes a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure. A first diode string is disposed between the first trench structure and the second trench structure and adjoins the first polysilicon structure and the second polysilicon structure. A first spacing oxide layer is disposed on the first diode string. A second diode string is disposed on the first spacing oxide layer and connected in parallel with the first diode string. Each of the first and the second diode strings includes first doped regions and second doped regions disposed alternately. A PN junction is formed at an interface between each first doped region and an adjacent second doped region.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
62.
SWTICHING MODE POWER CONVERTER WITH PULSE SKIPPING AND CONTROL METHOD THEREOF
INOUTININOUTOUTINOUTOUT) when the PWM signal is low. α is a pre-configured constant. The control circuit is configured to trigger the PWM controller to skip pulses when a voltage across the capacitor decreases to be less than a threshold before a present switching cycle of the power converter ends.
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
63.
Switching mode power converter with pulse skipping and control method thereof
OUT) when the PWM signal is low. α is a pre-configured constant. The control circuit is configured to trigger the PWM controller to skip pulses when a voltage across the capacitor decreases to be less than a threshold before a present switching cycle of the power converter ends.
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
64.
VERTICAL SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
The present application relates to a vertical semiconductor device and a manufacturing method therefor. The vertical semiconductor device comprises: a semiconductor material layer; a first shielding structure, located on the semiconductor material layer and comprising a first shielding dielectric layer and a first shielding electrode surrounded by the first shielding dielectric layer; a first doped region, located on the semiconductor material layer, the first doped region having a first conductivity type; and a first gate structure, adjacent to the first doped region. The depth of the first gate structure is smaller than the depth of the first shielding structure and greater than the depth of the first doped region. The first shielding dielectric layer region is divided into an upper part and a lower part by taking the bottom of the first gate structure as a boundary line, and the first gate structure is adjacent to the upper part. The upper part has a first thickness at a first surface of the semiconductor material layer, the first thickness is smaller than a second thickness of the lower part, and the sum of the first thickness of the upper part and a third thickness of the first gate structure at the first surface is greater than the second thickness of the lower part.
A semiconductor structure includes a substrate comprising a first surface and a second surface positioned on an opposite side of the substrate. A first trench structure extends from the first surface toward the second surface, wherein the first trench structure comprises a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure. A shielding metal layer is located on the first surface of the substrate and covers the first trench structure. A first conductive layer is disposed on the shielding metal layer, and a second conductive layer is disposed on the second surface of the substrate. The substrate comprises a first doped region located between the first surface and the second surface, adjacent to the first oxide layer and separated from the first polysilicon structure.
A trench-type semiconductor power device includes: a substrate; an epitaxial layer; a body doped region located in the epitaxial layer; a source doped region located in the body doped region; and a trench structure comprises a first semiconductor layer extending in a second direction. The first semiconductor layer includes: a first part that abuts against the body doped region and the source doped region, and serves as a gate electrode having a first conductivity type; and a second part that extends in the second direction and away from the source doped region, and comprises a plurality of first doped regions having the first conductivity type and a plurality of second doped regions having a second conductivity type. The plurality of first doped regions and the plurality of second doped regions are staggered to form a diode string having back-to-back diodes.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
67.
Power semiconductor apparatus and bonding method thereof
An apparatus includes a backside supporting layer having a first thickness, an adhesive layer over the backside supporting layer, a metal layer over the adhesive layer, wherein the metal layer functions as a backside connector, a semiconductor substrate layer over the metal layer, wherein the semiconductor substrate active layer has a second thickness, and a plurality of front side connectors, wherein active circuits in the semiconductor substrate layer over are electrically coupled between the plurality of front side connectors and the metal layer.
An apparatus includes a secondary controller coupled to a secondary circuit of a power conversion system, and a primary controller coupled to a primary circuit of the power conversion system, the primary controller being coupled to the secondary controller through an isolation interface, wherein the secondary controller is configured to detect whether a load is coupled to the power conversion system, in response to the load being disconnected from the power conversion system, communicate with the primary controller through pulling down a secondary feedback node in the secondary circuit and a primary feedback node in the primary circuit for a first predetermined time, provide a high impedance at the secondary feedback node to reduce power consumption, and in response to the load being reconnected to the power conversion system, communicate with the primary controller through pulling down the secondary feedback node in the secondary circuit for a second predetermined time.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A method of manufacturing a semiconductor structure includes forming on a substrate, at intervals in a first direction, a first trench, a second trench, and a third trench, forming a first oxide layer in the first trench, forming a second oxide layer in the second trench, and forming a third oxide layer in the third trench. The method also includes forming a first semiconductor material layer in the first trench, forming a second semiconductor material layer in the second trench, and forming a third semiconductor material layer in the third trench. The method further includes forming a mask layer, performing a first etching process on the mask layer to form a first opening and a second opening, performing a second etching process at the second opening to form a third surface on the substrate, and forming a first doped region adjacent to the third surface exposed by the second opening.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
70.
Clock Signal Skew Calibration Apparatus and Control Method
An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit of the clock skew calibration circuit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal, a frequency divider configured to receive the clock signal and generate a reduced frequency signal indicative of a skew of a first multi-phase clock signal, and a delay line control circuit configured to adjust the skew of the first multi-phase clock signal by comparing the reduced frequency signal with a predetermined duty cycle, and generating a control signal to modify a delay applied to the first multi-phase clock signal.
An apparatus includes a secondary controller coupled to a secondary circuit of a power conversion system, and a primary controller coupled to a primary circuit of the power conversion system, the primary controller being coupled to the secondary controller through an isolation interface, wherein the secondary controller is configured to detect whether a load is coupled to the power conversion system, in response to the load being disconnected from the power conversion system, communicate with the primary controller through pulling down a secondary feedback node in the secondary circuit and a primary feedback node in the primary circuit for a first predetermined time, provide a high impedance at the secondary feedback node to reduce power consumption, and in response to the load being reconnected to the power conversion system, communicate with the primary controller through pulling down the secondary feedback node in the secondary circuit for a second predetermined time.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
09 - Scientific and electric apparatus and instruments
16 - Paper, cardboard and goods made from these materials
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Semiconductor devices; Integrated circuits Printed instructional and teaching materials in the field of semiconductor devices; Printed manuals in the field of electronic components; Printed brochures about electronic components Custom manufacture of semiconductor devices; Custom manufacturing of integrated circuits for others Design of semiconductor chips; Design of integrated circuits; Engineering services in the field of electronic components; Software development consulting in the field of electronic design
73.
DYNAMIC CONTROL OF OUTPUT DRIVER IN A SWITCHING AMPLIFIER
A switching amplifier circuit includes an output transistor, a current direction detection circuit, and a slew control circuit. The output transistor includes a control terminal coupled to a switching input signal; a drain node coupled to an output node coupled to a first end of a load device having the first end and a second end; and a source node coupled to a reference voltage. The current direction detection circuit is coupled to the output node and configured to detect a direction signal corresponding to an output current at the output node. The slew control circuit is configured to adjust a slew rate of the output transistor at the output node. The slew control circuit is coupled to the control terminal of the output transistor and is activated only during turnoff of the output transistor and operates in response to the direction signal.
An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
An alignment device (100) for use in a wafer processing system is described. The device (100) comprises a subustrate (105) configured to be handled by the wafer processing system, a sensor (160) mounted on the substrate, and a transmitter. Further a method of aligning a wafer handling robot in a semiconductor processing tool is described. The method comprises inserting the alignment device into the wafer handling robot, using the sensor to capture information relating to a position of the alignment device relative to the semiconductor processing tool, and wirelessly transmitting the captured information to a receiver.
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
76.
LED color and brightness control apparatus and method
A system includes a plurality of lighting modules, and a plurality of MOSFET devices connected in parallel and coupled between one of the plurality of lighting modules and ground, wherein the plurality of MOSFET devices comprises a first MOSFET device group configured to provide a bleed current flowing through the one of the plurality of lighting modules, a second MOSFET device group configured to provide a delay compensation current flowing through the one of the plurality of lighting modules, a third MOSFET device group configured to provide a PWM current flowing through the one of the plurality of lighting modules, and a fourth MOSFET device group configured to adjust a current flowing through the one of the plurality of lighting modules.
A method of manufacturing a semiconductor structure is provided. A substrate including a first silicon carbide layer and a second silicon carbide layer under the first silicon carbide layer is formed. The substrate includes a unit region and a termination region surrounding the unit region. A first guard ring structure is formed in the termination region and the first silicon carbide layer, adjoining a top surface of the first silicon carbide layer. A second guard ring structure is formed in the termination region and the second silicon carbide layer. Second guard ring well regions of the second guard ring structure correspond one-on-one to first guard ring well regions of the first guard ring structure. Each of the second guard ring well regions overlaps with a corresponding one of the first guard ring well regions in a vertical direction perpendicular to the top surface of the substrate.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
78.
Semiconductor structures and manufacturing methods thereof
Various methods for manufacturing semiconductor structures are provided. An embodiment method includes forming a first patterned hard mask and epitaxial layer on a semiconductor substrate, and forming a first doped region in the epitaxial layer by performing a first implantation through the first patterned hard mask. A second doped region is formed in the epitaxial layer by performing a second implantation through the first patterned hard mask, with the first doped region at least partially overlapping the second doped region. A second patterned hard mask is formed, which surrounds the first patterned hard mask and covers at least a portion of the first doped region. A third doped region is formed in the epitaxial layer by performing a third implantation through the first patterned hard mask and the second patterned hard mask.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
79.
Semiconductor Manufacturing Tool Alignment Device And Method
An alignment device for aligning a wafer handling robot in a wafer processing system includes a substrate having a through-hole. A sensor is mounted on a first surface of the substrate, and configured to capture, via the through-hole, information relating to a position of the alignment device in the wafer processing system. A transmitter is mounted on the first surface of the substrate and coupled to the sensor. The transmitter is configured to wirelessly transmit the information captured by the sensor. The transmitted information enables to determine whether the alignment device is within a threshold distance from a target position in the wafer processing system and to adjust the position of the alignment device. A method of aligning the wafer handling robot utilizing the alignment wafer, and a frame and method for calibrating the alignment wafer are also provided.
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
G01B 11/27 - Measuring arrangements characterised by the use of optical techniques for measuring angles or tapersMeasuring arrangements characterised by the use of optical techniques for testing the alignment of axes for testing the alignment of axes
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
80.
Manufacturing method for a power MOSFET with gate-source ESD diode structure
A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a source in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure comprising a body ring structure in the epitaxial layer, forming a gate-source Electrostatic Discharge (ESD) diode structure over the epitaxial layer, forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
81.
DATA CORRECTION AND PHASE OPTIMIZATION IN HIGH-SPEED RECEIVERS
Methods and systems for performing data correction and phase optimization are disclosed herein. In some implementations, a system for performing data correction comprises: an analog to digital converter (ADC) configured to receive differential data from a continuous time linear equalizer (CTLE) and generate a bitstream comprising a plurality of data bits and a corresponding plurality of data sign bits; a decision feedback equalization (DFE) block configured to receive the bitstream from the ADC and provide data to a clock and data recovery (CDR) block; and data correction circuitry. In some implementations, the data correction circuitry is configured to: receive the bitstream from the ADC; determine whether to correct a data sign bit; responsive to determining the data sign bit is to be corrected, flip the data sign bit; and provide the plurality of data sign bits, including the flipped data sign bits, to the DFE.
Diodes Technology (Chengdu) Company Limited (China)
Shanghai Kaihong Electronic Company Limited (China)
Inventor
Zhang, Huaigang
Wang, Chris
Abstract
A connector for connecting a gas pipe and a heating component of a wire bonder includes a first connection end for connecting the connector to the heating component, and a second connection end for connecting the connector to the gas pipe. A heat-insulation tube is connected between the first connection end and the second connection end. The heat-insulation tube is made of a heat-insulation material and configured to insulate or reduce heat transfer between the first connection end and the second connection end. The connector may further include a first fastening sleeve for fastening the connection between the first connection end and the heat-insulation tube, and a second fastening sleeve for fastening the connection between the second connection end and the heat-insulation tube.
An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path comprises a controllable switch and a first resistive device coupled in parallel between the capacitive device and the gate of the high-side switch, and a control switch connected between the gate of the high-side switch and ground.
H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
84.
SEMICONDUCTOR RECTIFIER DEVICE AND MANUFACTURING METHOD THEREFOR
The present application relates to a semiconductor rectifier device and a manufacturing method therefor. The semiconductor rectifier device comprises: an epitaxial layer having a top surface and a bottom surface opposite to each other; a first doped region located in the epitaxial layer and having a first conductivity type; a first trench structure located in the first doped region and extending from the top surface to the bottom surface; a second trench structure located in the first doped region, extending from the top surface to the bottom surface, and adjacent to the first trench structure; a second doped region located in the epitaxial layer between the first trench structure and the second trench structure, extending from the top surface to the bottom surface, and having a second conductivity type, the depth of the second doped region being less than the depth of the first trench structure; and a metal layer located on the top surface of the epitaxial layer, covering the first trench structure, the second trench structure and the second doped region, and in contact with the top surface of the epitaxial layer to form a Schottky junction surface.
An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a drain contact on opposing sides of the epitaxial layer of the source contact, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
86.
Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a silicon carbide layer, which has a unit region and a termination region surrounding the unit region. A first guard ring structure is located in the termination region of the silicon carbide layer, and adjoins a top surface of the silicon carbide layer. The first guard ring structure may include at least one first guard ring well region. A second guard ring structure is located in the silicon carbide layer and below the first guard ring structure. The second guard ring structure may include at least one second guard ring well region, which corresponds to the at least one first guard ring well region in a vertical direction. A method for manufacturing the semiconductor structure is also provided.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A semiconductor structure includes: a substrate, having a cell region and a terminal region, and having a first surface, a second located in the terminal region, and a third surface located in the cell region, the second surface and the third surface being located at different levels; a first trench structure, located in the cell region, traversing the third surface to extend towards the first surface, including a first semiconductor material layer and a first oxide layer partially protruding from the third surface, and extending in a first direction parallel to the third surface; and a second trench structure, located in the cell region, including a second semiconductor material layer and a second oxide layer partially protruding from the third surface, and extending parallel to the first direction, wherein the third surface is provided with a doped region between the first trench structure and the second trench structure.
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 27/102 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A device is provided for unpackaging components encased between a first tape body and a second tape body of a sealed tape. The device includes a component collection device including a cavity for receiving components falling out of the sealed tape being de-taped. A de-taping device is attached to the component collection device. The de-taping device includes a support base held over the cavity, and a shaft on one side of the support base. The support base with the shaft is configured to enable one of the first tape body and the second tape body to be extendable around the shaft and the support base and to be pullable, such that the first tape body and the second tape body are separated and the components fall out of the sealed tape. The support base may include a through-hole configured for sealed tapes to pass through and to be held.
B23P 19/02 - Machines for simply fitting together or separating metal parts or objects, or metal and non-metal parts, whether or not involving some deformationTools or devices therefor so far as not provided for in other classes for connecting objects by press fit or for detaching same
B29B 17/02 - Separating plastics from other materials
H05K 13/00 - Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
The present invention relates to a semiconductor chip package and a manufacturing method therefor. The semiconductor chip package comprises: a lead frame, having a first side and a second side opposite to each other, wherein the lead frame has a first recess recessed from the first side of the lead frame; an adhesive, filling the first recess; and a semiconductor chip, provided on the first side of the lead frame and the adhesive, wherein the width of the first recess is not greater than the width of the semiconductor chip.
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
90.
CLOCK SIGNAL SKEW CALIBRATION APPARATUS AND CONTROL METHOD
An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals, a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.
H03K 5/156 - Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
91.
Clock signal skew calibration apparatus and control method
An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals, a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.
A semiconductor chip package may include a lead frame having a first surface and a second surface opposite to each other. A groove may be provided on the first surface of the lead frame and filled with an adhesive. A width of the groove is not greater than a width of the semiconductor chip. A semiconductor chip may be disposed over the groove and affixed to the lead frame through the adhesive in the groove. A carrier may be disposed on the second surface of the lead frame. A method for manufacturing the semiconductor chip package is also provided.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
BCD Shanghai Micro-Electronics Company Limited (China)
Inventor
Zou, Cong
Dou, Sen
Peng, Shaohua
Abstract
A switching power supply includes a secondary control circuit coupled to a secondary side of a transformer of the switching power supply, and a primary control circuit coupled to a primary side of the transformer. The secondary control circuit is configured to receive a power request signal of a load device, and encode the power request signal to generate encoded information. The primary control circuit is configured to receive, by use of the transformer, a feedback signal reflecting an output voltage of the switching power supply, decode the encoded information based on a change of the feedback signal, and based thereon, control the switching power supply to supply power to the load device.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 1/36 - Means for starting or stopping converters
94.
Semiconductor molding system and foreign object detection method
Diodes Technology (Chengdu) Company Limited (China)
Shanghai Kaihong Electronic Company Limited (China)
Inventor
Wang, Desen
Feng, Zhigang
Abstract
A semiconductor molding system is provided that includes a molding device, an image collection device, and a controller connected to the molding device and the image collection device. The image collection device is configured to obtain a target image of a to-be-molded lead frame before the to-be-molded lead frame is molded by the molding device. The controller is configured to determine whether foreign object(s) exist in a non-molding area of the to-be-molded lead frame based on the target image of the to-be-molded lead frame and a reference image. A method for detecting foreign objects of a to-be-molded lead frame is also provided.
A semiconductor rectifier device includes: an epitaxial layer, having a top surface and a bottom surface; a first doped region having a first conductivity type, located in the epitaxial layer; a first trench structure, located in the first doped region; a second trench structure adjacent to the first trench structure, located in the first doped region; a second doped region having a second conductivity type, located in the epitaxial layer between the first trench structure and the second trench structure, wherein a depth of the second doped region is less than a depth of the first trench structure; and a metal layer, located on the top surface of the epitaxial layer, covering the first trench structure, the second trench structure, and the second doped region, wherein the metal layer is in contact with the top surface, forming a Schottky interface.
A semiconductor rectifier device comprises: an epitaxial layer having a top surface and a bottom surface; a first trench comprising a first side wall, a second side wall, and a first bottom surface; a second trench adjacent to the first trench, the second trench comprising a third side wall, a fourth side wall, and a second bottom surface; a first doped region abutting against the first side wall and at least a part of the first bottom surface of the first trench; a second doped region adjacent to and separated from the first doped region, wherein the second doped region abuts against the third side wall, the fourth side wall and the second bottom surface of the second trench; a gate structure disposed on the top surface between the first trench and the second trench; and a contact metal layer disposed on the top surface of the epitaxial layer.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
The present application relates to a semiconductor rectifying device and a method for manufacturing same. The semiconductor rectifying device comprises: an epitaxial layer, having a top surface and a bottom surface; a first groove, extending from the top surface to the bottom surface and comprising a first side wall and a second side wall opposite to each other, and a first bottom surface connected to the two side walls; a second groove, being adjacent to the first groove and comprising a third side wall and a fourth side wall opposite to each other, and a second bottom surface connected to the two side walls; a first doped region, extending from the top surface to the bottom surface and being adjacent to the first side wall and at least part of the first bottom surface of the first groove; a second doped region, being adjacent to the first doped region and separated from the first doped region, extending from the top surface to the bottom surface, and being adjacent to the third side wall, the fourth side wall, and the second bottom surface of the second groove; a gate structure, being disposed on the portion of the top surface between the first groove and the second groove, wherein the bottom surface of the gate structure is adjacent to the first doped region and the second doped region; and a contact metal layer.
An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path comprises a controllable switch and a first resistive device connected in series between the capacitive device and the gate of the high-side switch, and a control switch connected between the gate of the high-side switch and ground.
H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
99.
Power semiconductor packaging and manufacturing method thereof
The power semiconductor device comprises a base that includes a substrate and an epitaxial layer located above the substrate, with the base comprising a unit area and a peripheral area surrounding the unit area. A junction layer is located within the peripheral area and above the epitaxial layer. A barrier layer is located within the unit area and above the epitaxial layer. A first electrode is located on the junction layer and a second electrode is located on the barrier layer. The epitaxial layer includes a doped channel located within the peripheral area, extending between the junction layer and the base substrate. Current flows from the substrate through the doped channel and the junction layer to the first electrode.
H01L 31/0336 - Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups in different semiconductor regions, e.g. Cu2X/CdX hetero-junctions, X being an element of Group VI of the Periodic System
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure in the epitaxial layer comprising a body ring structure, forming a source and a body region in the epitaxial layer, forming an interlayer dielectric layer over the epitaxial layer, forming a gate-source Electrostatic Discharge (ESD) diode structure in the interlayer dielectric layer, forming a source contact connected to the source, and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, and forming a drain contact underneath the substrate.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
