Abstract

A method facilitating a memory system operable in advance during power-up is introduced, including the following. A power-up verification circuit is provided, internally coupled to a memory control circuit of the memory system. During a period of the power-up in which a power voltage signal is ramping but not yet reaching a power voltage threshold, a power-up verification state machine of the power-up verification circuit is activated responsive to a power-on reset signal and the power voltage signal. The activated power-up verification state machine communicates with circuit units of the memory system to enable execution of corresponding detections on the circuit units in accordance with a sequence of states of the power-up verification state machine. After completion of the sequence of states, a verification completion signal is sent to enable the memory control circuit to be powered by the power voltage signal and operable to control the memory system.

IPC Classes  ?

• G11C 16/30 - Power supply circuits
• G06F 3/06 - Digital input from, or digital output to, record carriers
• G11C 5/14 - Power supply arrangements
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

A control circuit is introduced for facilitating inrush current reduction for a voltage regulator providing an output voltage variable in response to an output voltage selection. The control circuit includes a soft-start circuit, a soft-start tracking circuit, and a controller. The soft-start circuit is utilized for providing a soft-start signal. The soft-start tracking circuit includes a first input terminal for receiving a feedback signal from the voltage regulator, a second input terminal coupled to the soft-start circuit, and an output terminal coupled to the soft-start circuit. The controller, coupled to the soft-start tracking circuit, is configured to output an enabling signal to the soft-start tracking circuit selectively in accordance with the output voltage selection. The soft-start tracking circuit is operable in response to the enabling signal so that the soft-start signal provided by the soft-start circuit substantially follows the feedback signal from the voltage regulator.

IPC Classes  ?

• H02M 1/32 - Means for protecting converters other than by automatic disconnection
• H02M 1/36 - Means for starting or stopping converters
• H02M 1/00 - Details of apparatus for conversion

Abstract

A termination voltage regulation apparatus with transient response enhancement includes a termination voltage regulator and a transient response enhancer. The termination voltage regulator provides a termination voltage at a termination voltage terminal, including first and second switching units. The transient response enhancer, coupled to the termination voltage regulator, is utilized for enhancing transient response of the termination voltage regulator, including a first enhancement circuit for sensing a first signal associated with the first switching unit and enabling a first control terminal of the first switching unit to be at a first voltage in response to the first signal in a sinking mode; and a second enhancement circuit for sensing a second signal associated with the second switching unit and enabling a second control terminal of the second switching unit to be at a second voltage in response to the second signal in a sourcing mode.

IPC Classes  ?

• G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
• G05F 1/59 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
• H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

Abstract

A method of controlling verification operations for error correction of a non-volatile memory device includes the following. A tolerated error bit (TEB) number for error correction of the non-volatile memory device is set to a first value to control verification operations in accordance with the TEB number. After at least one portion of the non-volatile memory device is programmed for a specific number of times, the TEB number is changed from the first value to a second value to control the verification operations in accordance with the TEB number, wherein the second value is greater than the first value and is less than or equal to the TEB threshold. The method may be performed while the at least one portion of the non-volatile memory device is programmed and verified.

IPC Classes  ?

• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A class D power amplifier with novel design is provided. The amplifier includes an input stage, a periodic signal generator, a comparator, a power output stage, and a boost circuit. The input stage is coupled to a first supply voltage. The periodic signal generator generates a periodic signal and a reference signal. The power output stage is coupled to a second supply voltage. The boost circuit compares an output of the input stage with the reference signal, and thereby adjusts a value of the second supply voltage. The value of the second supply voltage is larger than a value of the first supply voltage. The reference signal is proportional to an amplitude of the periodic signal, and the amplitude of the periodic signal is determined by the value of the second supply voltage.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages

Abstract

An electrostatic discharge (ESD) protection device for a semiconductor device that includes a gate, a source including a silicide portion having a plurality of source contacts, and a drain including a silicide portion having a plurality of drain contacts, wherein the source and drain are extended away from the gate along a device axis. The ESD device includes a resist protective oxide (RPO) portion located on the semiconductor device in between the plurality of drain contacts and in between the plurality of source contacts, respectively.

IPC Classes  ?

• H01L 29/45 - Ohmic electrodes
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Abstract

The present application proposes a memory chip includes a plurality of memory banks, a plurality of address pins, and a pseudo-address determining circuit. The plurality of address pins is arranged for receiving a plurality of address signals corresponding to the plurality of memory banks, respectively. The pseudo-address determining circuit has a plurality of input terminals coupled to the plurality of address pins, respectively, and a plurality of output terminals coupled to the plurality of memory banks. The pseudo-address determining circuit generates a pseudo-address table for the plurality of memory banks when the memory chip is powered-up. The pseudo-address table has a plurality of pseudo-addresses corresponding to the plurality of memory banks, respectively. The present application also provides a memory module that incorporates the memory chip and a method for pseudo-accessing memory banks of the memory chip.

IPC Classes  ?

• G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
• G06F 12/10 - Address translation

Abstract

The present application proposes a transient enhancing circuit for a constant-on-time converter. The constant-on-time converter includes an error amplifier and a comparator. The transient enhancing circuit includes a first sample-and-hold circuit and a zero-current detection circuit. The first sample-and-hold circuit has an input terminal and an output terminal. The input terminal of the first sample-and-hold circuit is coupled to an output terminal of the error amplifier, and the output terminal of the first sample-and-hold circuit is coupled to a first input terminal of the comparator. The zero-current detection circuit is coupled to the first sample-and-hold circuit and arranged for outputting a control signal when current flowing through a load of the constant-on-time converter is detected to be zero. The present application also proposes a constant-on-time converter using the transient enhancing circuit.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H02M 1/00 - Details of apparatus for conversion

Abstract

A constant on-time controller has a voltage divider, a current ripple extractor, a one-shot on-timer, a comparator and a flip flop. The voltage divider generates a feedback voltage according to a regulator output voltage. The current ripple extractor senses a current in an energy storage inductor of a buck regulator flowing through flowing through an output capacitor's ESR, and generates an extracted ripple current having no DC component accordingly. The one-shot on-timer outputs a constant-on time control signal according to a buck regulator input voltage and the regulator output voltage. The modulation circuit outputs a modulation signal according to a reference voltage signal, the feedback voltage and the extracted ripple current. The flip flop generates a control signal to the buck regulator according to the modulation signal and the constant-on time control signal. An off-time of the buck regulator is determined according to the modulation signal.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
• H02M 1/00 - Details of apparatus for conversion

Abstract

An erasing method used in a flash memory having memory blocks is illustrated, each of the memory blocks is divided into a plurality of memory sectors, and steps of the erasing method is illustrated as follows. An erasing and verifying process is performed sequentially on the memory blocks or the memory sectors of the memory block according to a memory sector enable signal. An over-erased correcting and verifying process is performed sequentially on the memory blocks or the memory sectors of the memory block according to the memory sector enable signal, wherein the memory sector enable signal is set to be asserted if an over-erased correction is performed on at least one of the memory blocks or at least one of the memory sectors of the memory block.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Abstract

A virtual bass generating circuit used in a speaker is used to filter out a high frequency part of an audio signal to generate a low passed audio signal, generates an even and odd audio signals respectively having even and odd harmonics of the low passed audio signal according to the low passed audio signal, subtracts an amplified low passed audio signal from an addition of an amplified even audio signal and an amplified odd audio signal to generate a first calculated audio signal, filters out a low frequency part and a high frequency part of the first calculated audio signal to generate a band passed audio signal, and adds the band passed audio signal and the audio signal to generate a second calculated audio signal with enhanced even and odd harmonics of the audio signal.

IPC Classes  ?

• H04R 3/04 - Circuits for transducers for correcting frequency response
• H04R 1/22 - Arrangements for obtaining desired frequency or directional characteristics for obtaining desired frequency characteristic only

Abstract

A controller for a switching regulator of a LED lighting system has a current monitor, a voltage divider, an integration circuit, and a comparator circuit. The current monitor is used to sense a LED current passing through a current sensing resistor of the switching regulator, and to generate a sensing current. The voltage divider is used to receive the sensing current to generate a first through third divided voltages, wherein the first divided voltage is larger than the second divided voltage, and the second divided voltage is larger than the third divided voltage. The integration circuit is used to compare the second divided voltage with a reference voltage, and to generate an integration voltage across a RC circuit thereof accordingly. The comparator circuit is used to compare the integration voltage with the first divided voltage and the third divided voltage, and to generate a driving signal.

IPC Classes  ?

• H05B 33/08 - Circuit arrangements for operating electroluminescent light sources

Abstract

A compensation circuit for compensating an input voltage offset of an error amplifier has a level shifter, a first trimming circuit, a second trimming circuit, and a compensation current sinking device. The level shifter shifts levels of a feedback voltage and a predetermined reference voltage and outputs a level shifted feedback voltage and a level shifted reference voltage. The first trimming circuit adjusts the level shifted reference voltage by trimming a first resistance thereof according to a trimming code, wherein the trimming code has the ratio relation of the input voltage offset and a resistance to be trimmed. The second trimming circuit adjusts the level shifted feedback voltage by trimming a second resistance thereof according to a trimming code. The compensation current sinking device sinks currents passing through the first and second trimming circuits.

IPC Classes  ?

• H03K 5/003 - Changing the DC level
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only

Abstract

A non-volatile memory having discrete isolation structures and SONOS (Silicon Oxide Nitride Oxide Silicon) memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.

IPC Classes  ?

• H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
• H01L 21/762 - Dielectric regions
• H01L 27/11568 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
• H01L 21/8234 - MIS technology

Abstract

A semiconductor memory device includes memory cells, a sensing amplifier, a precharge circuit, and a control signal generator. The precharge circuit has a NMOS transistor and two PMOS transistors, and is used to precharge bit lines of a bit line pair, wherein the NMOS transistor is controlled by a first control signal, and the two PMOS transistors are controlled by a second control signal. The control signal generator is used to generate the first and second control signals, wherein the first control signal is at a logic high level only when the second control signal is at a first logic low level, the first control signal is at a logic low level when the second control signal is at a second logic low or a first logic high level, and the second logic low level is higher than the first logic low level.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store

Abstract

The present invention discloses a circuit for generating a dual-mode proportional to absolute temperature (PTAT) current. The circuit includes a voltage stabilizing circuit to provide a voltage reference, and a load current control circuit comprising a first transistor to provide a first load current based on the voltage reference, a second transistor to provide a second load current based on the voltage reference, a first switch to control whether to allow the first load current to flow therethrough in response to different predetermined temperatures, and a second switch to control whether to allow the second load current to flow therethrough in response to the different predetermined temperatures. A resultant current resulting from at least one of the first load current or the second load current has different current magnitudes at the different predetermined temperatures.

IPC Classes  ?

• G05F 3/16 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices

Abstract

A voltage regulator circuit for providing power management for a memory device is disclosed. The voltage regulator circuit comprises a voltage regulator and a switch circuit. The switch circuit includes a first oscillator to generate an oscillating signal, and a pulse generator to generate a pulse signal in response to the oscillating signal. The voltage regulator provides a current during standby mode of the memory device in response to the pulse signal. The current is smaller than one provided by the voltage regulator during normal mode of the memory device.

IPC Classes  ?

• G11C 5/14 - Power supply arrangements

Abstract

A semiconductor memory device with a self-refresh timing circuit is provided. The semiconductor memory device comprises a plurality of memory banks, a command decoder, a bank address generator, a self-refresh counter, and the self-refresh timing circuit. The self-refresh timing circuit comprises a temperature sensor, a reference voltage source, a comparison circuit, an enable circuit, and an oscillation circuit. The comparison circuit compares a voltage from the temperature sensor with a constant voltage from the reference voltage source and generates a comparison signal. The enable circuit activates the comparison circuit when self-refresh operations for at least one refresh row are completed in all memory cell banks. The oscillation circuit generates a self-refresh clock signal which controls the operating frequency of the bank address generator and the self-refresh counter.

IPC Classes  ?

• G11C 7/06 - Sense amplifiersAssociated circuits

Abstract

The invention provides a delay lock loop circuit (DLL) for generating a locked signal, the DLL circuit includes: a phase detector, a first and a second voltage controlled delay chains, a charge pump and a duty cycle detection pump. The phase detector generates a phase detecting result by detecting a phase difference between the clock signal and the locked signal. The first and the second voltage controlled delay chains generate a first and a second delayed signals by delaying the clock signal according to the first and the second control signals, respectively. The charge pump is used for generating the first and the second control signal according to the phase detecting result. The duty cycle detection pump is used for controlling a voltage level of the second control signal according to the first and the second delayed signals.

IPC Classes  ?

• H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop

Abstract

A method for controlling operations of a delay locked loop (DLL) of a dynamic random access memory (DRAM) is provided herein. A phase detector of the DLL compares an external clock signal with a feedback clock signal to generate a first control signal. A delay line circuit of the DLL delays the external clock signal according to the first control signal. A detector of the DRAM detects variations of the first control signal to determine a length of an enable period of an enable signal. The delay line circuit and the output buffer are active only during the enable period when the DRAM is in a standby mode.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
• G11C 8/00 - Arrangements for selecting an address in a digital store

Abstract

A dynamic random-access memory (DRAM) and a method for testing the DRAM are provided. The DRAM includes a memory cell, a bit line associated with the memory cell, a local buffer, and a bit line sense amplifier (BLSA). The local buffer receives a first power voltage as power supply. The local buffer provides a ground voltage to the bit line when a data signal is de-asserted and provides the first power voltage to the bit line when the data signal is asserted. The BLSA receives a second power voltage as power supply. The BLSA provides the second power voltage to the bit line when the data signal and a wafer level burn-in test signal are both asserted. The second power voltage may be higher than the first power voltage. The wafer level burn-in test signal is asserted when the DRAM is in a wafer level burn-in test mode.

IPC Classes  ?

• G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation

Abstract

An anti-fuse circuit including a programmable module, a read module, and a control module is provided. The programmable module has a plurality of data cells. The read module is coupled to the programmable module. During a normal operation, the read module distinguishes which one or more of the data cells are stressed. The control module is coupled to the programmable module. During a stress operation, the control module controls each stressed data cell to be coupled to a high voltage, a low voltage, and a control voltage. The first end of each stressed data cells is coupled to the low voltage, the second end of each stressed data cells is coupled to the high voltage, and the control end of each stressed data cells is coupled to the control voltage during the stress operation.

IPC Classes  ?

• G11C 7/06 - Sense amplifiersAssociated circuits

Abstract

An anti-fuse circuit including a plurality of programmable units and a test module is provided. The programmable units receive a stress voltage, a program data, and a write enable signal. During a programming period, the programmable units sequentially transmit the program data. When the write enable signal is enabled, the stress voltage stresses the programmable units according to the program data, and the programmable units output programming results for test. The test module is coupled to the programmable units and receives the program data and the programming results. During a test period, the test module compares the programming results with the program data and outputs different logic levels according to a result of the comparison of the first programming results and the program data. A method for anti-fuse programming and test adapted to the foregoing anti-fuse circuit is also provided.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store

Abstract

The present invention provides a semiconductor memory device, the voltage divider circuit comprises a data line sense amplifier and an input output data sensing circuit. The data line sense amplifier receives a data line signal pair and senses the data line signal pair in a first timing period to generate a first output data and a second output data, wherein, the first output data and the second output data are complementary. The input output data sensing circuit receives at least one reference output data and one of the first and the second output data. The input output data sensing circuit generates a sensed data by comparing voltage levels of the reference output data and the one of the first and the second output data in a second timing period, wherein the voltage level of the reference output data is a pre-determined voltage level.

IPC Classes  ?

• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

A circuit for providing a reference voltage includes a bandgap reference circuit, a first unity gain buffer coupled to the bandgap reference circuit, a first switch for coupling a second reference voltage node to a third reference voltage node, a first capacitor coupled to the third reference voltage node, a second switch for coupling the third reference voltage node to a fourth reference voltage node, and a second capacitor coupled to the fourth reference voltage node, wherein during operation a fourth reference voltage at the fourth reference voltage node decays when the second capacitor discharges. A control circuit provides control signals for intermittently operating the bandgap reference circuit and for controlling the switches to recharge the second capacitor after the fourth reference voltage decays a predetermined amount.

IPC Classes  ?

• G05F 3/16 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices

Abstract

A phase interpolation module comprising a first, second, and third phase interpolation units is proposed. Each of the first, second, and third phase interpolation units comprises a first through third inverters, a first and second resistors, wherein the first resistor is coupled between an output end of the first inverter and an input end of the third inverter, and the second resistor is coupled between an output end of the second inverter and the input end of the third inverter. The first and second inverters of the first phase interpolation unit receive a first signal, the first and second inverters of the third phase interpolation unit receive a second signal, and the first and second inverters of the second phase interpolation unit respectively receive the first and second signals.

IPC Classes  ?

• H03H 11/16 - Networks for phase shifting

Abstract

A novelty repairing method and circuit are provided by the embodiments of the present invention, wherein the input/output (IO) compression manner can be used therein to reduce the access time during the chip probing 1 (CP1) test, and each redundant column selected line (RCSL) can be divided into several partial redundant column selected lines (P-RCSLs) which are respectively responsible for repairing the defects of the corresponding regions. Based upon the repairing method, the memory circuit can reduce the number of the RCSLs. Furthermore, a variable region dividing manner is applied therein, so as to increase the probability for repairing the defect of the memory circuit.

IPC Classes  ?

• G11C 7/06 - Sense amplifiersAssociated circuits
• G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
• G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
• G11C 8/00 - Arrangements for selecting an address in a digital store

Abstract

A method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprises the steps of: sequentially performing a plurality of divide-by-2 operations on the plurality of memory cells; generating a plurality of reduced groups from the memory cells after each of the divide-by-2 operations is performed; sequentially programming the memory cells of each reduced group; generating a final group after a final divide-by-2 operation is performed; programming the memory cells of the final group; and verifying whether the memory cells of the final group are completely programmed. The memory cells of the final group are composed of all the memory cells of the nonvolatile semiconductor memory device and the verifying step is only performed after the step of programming the memory cells of the final group.

IPC Classes  ?

• G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

A data input device for use in a memory device to avoid false data being written due to a postamble ringing phenomenon in a write operation is provided. The data input device comprises a buffer, a combinational logic circuit and a flip-flop unit. The buffer receives the data and outputs internal data to the flip-flop unit. The combinational logic circuit receives an external data strobe signal to generate a first data strobe signal and a second data strobe signal. The flip-flop unit stores the data in synchronization with the first data strobe signal and outputs the stored data in synchronization with the second data strobe signal. A last rising edge of the second data strobe signal is generated prior to onset of the postamble ringing on the external data strobe signal, so that a data transferred path in the flip-flop unit is closed prior to onset of the postamble ringing.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A circuit for generating multiphase clock signals and corresponding indication signals is provided. The circuit includes a multiphase clock generation circuit, a DLL circuit, a timing circuit, and a phase comparison circuit. The multiphase clock generation circuit receives an external clock to provide a plurality of first clock signals, phases of which differ from one another. The DLL circuit receives the external clock signal to provide a second clock signal. The timing circuit receives the second clock signal and a comparison signal to provide a plurality of indication signals. Each of the plurality of indication signals has rising edges which lead the rising edges of a corresponding one of the first clock signals. The phase comparison provides the comparison signal if a delayed phase of the corresponding one of the indication signals is within a phase of one of the first clock signals.

IPC Classes  ?

• H03K 3/00 - Circuits for generating electric pulsesMonostable, bistable or multistable circuits

Abstract

A semiconductor memory device and a method of testing the same are provided. In the method, the semiconductor memory device enters a test mode after receiving a mode selection signal. After the semiconductor memory device enters the test mode, a first word line is activated. Test data are then sequentially written into a plurality of memory cells coupled to the first word line. The first word line is deactivated, and data between each pair of bit lines are latched. A second word line is activated. After the second word line is activated, the data latched between each pair of bit lines are directly written into the memory cells coupled to the second word line.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store

Abstract

A delay-locked loop (DLL) and a method of using the DLL are provided. The DLL receives an external clock signal and outputs an internal clock signal. The DLL includes a variable delay line and a phase detector. The variable delay line delays the external clock signal and outputs a delayed external clock signal. The phase detector compares the phase of the external clock signal and the phase of the internal clock signal. The method includes the following steps: providing the delayed external clock signal directly to the phase detector of the DLL as the internal clock signal in a high frequency mode; and inverting the delayed external clock signal and providing an inverted delayed external clock signal to the phase detector as the internal clock signal in a low frequency mode.

IPC Classes  ?

• H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop

Abstract

The invention provides a voltage regulator including a voltage divider and a power supply. The voltage divider circuit includes a first, second, third PMOS transistors, a first NMOS transistor, a pull down circuit, and a switching capacitor circuit. The pull down circuit includes a plurality of switches controlled by a pull down control signal. The switching capacitor circuit controlled by a first control pulse includes a capacitor and provides the capacitor connected to the dividing voltage for a short period while the power supply starts up to provide the input voltage. The power supply includes a comparator and a power voltage switch. The comparator compares the dividing voltage and a reference voltage and outputs a comparison result correspondingly. The power voltage switch is controlled by the comparison result to provide the input voltage from a power voltage.

IPC Classes  ?

• G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems

Abstract

A comparator comprises a current mirror, a differential input pair, and a auxiliary circuit. The current mirror has a biasing end coupled to a power voltage, a first end, and a current outputting end coupled to an output node of the comparator. The differential input pair has a first and second input ends for respectively receiving a first voltage and a second voltage, a second and third ends, and a ground end, wherein the third end is coupled to the first end. The auxiliary circuit is coupled between the output node and the second end, and provides a minimum voltage of a comparison result output at the output node. The comparison result is the power voltage when the first voltage is larger than the second voltage, and the comparison result is the minimum voltage when the first voltage is less than the second voltage.

IPC Classes  ?

• H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
• H03F 3/45 - Differential amplifiers

Abstract

A fuse circuit comprises a fuse set and an enable circuit. The enable circuit is configured to receive a test mode enable signal and a power up signal to generate an enable signal and a voltage level to the fuse set for indicating whether an external supply voltage reaches a predetermined value and whether a test mode is enabled. In particular, an output signal of the fuse set is constant in the test mode, regardless of whether a fuse in the fuse set is blown or not.

IPC Classes  ?

• H01H 37/76 - Contact member actuated by melting of fusible material, actuated due to burning of combustible material or due to explosion of explosive material

Abstract

A data outputting method of a memory circuit is illustrated. The memory circuit having at least 16 data buffers DQ[0]˜DQ[15] for storing at least 16 batches of data is provided. If a quadruple data outputting mode is selected for the memory circuit, when the clock signal triggers the 16 data buffers DQ[0]˜DQ[15], the 4 batches of the data stored in the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9] via 4 input/output pins connected to the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9], the batch of data stored in the data buffer DQ[2n+2] is transferred to be stored in the data buffer DQ[2n], and the batch of the data stored in the data buffer DQ[2n+3] is transferred to be stored in the data buffer DQ[2n+1], for n is an integer from 0 through 2, and from 4 through 6.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A voltage regulator circuit comprises active and standby amplifiers, first and second transistors, and a capacitor. The active amplifier has a negative input connected to a first reference voltage, and the standby amplifier has a negative input connected to a second reference voltage. The first reference voltage is greater than the second reference voltage. The first transistor has a gate connected to an output of the active amplifier and a drain connected to a voltage regulated output, and the second transistor has a gate connected to an output of the standby amplifier and a drain connected to the voltage regulated output. The capacitor is connected between a chip enable signal and the voltage regulated output.

IPC Classes  ?

• G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
• G05F 1/44 - Regulating voltage or current wherein the variable is actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices semiconductor devices only

Abstract

A method for eliminating bit line leakage current of a memory cell in random access memory devices comprises the steps of: periodically activating a pre-charge equalization circuit, which provides a pre-charge voltage to a pair of complementary bit lines of a memory cell, if the memory cell is in a self-refresh mode or a standby mode; and temporarily activating the pre-charge equalization circuit after the memory cell is refreshed if the memory cell is in the self-refresh mode or the standby mode.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store

Abstract

A method for controlling standby current coming from bit line leakage in random access memory devices comprises the steps of: continuously deactivating a pre-charge equalization circuit providing a pre-charge voltage to a pair of complementary bit lines of a memory cell if the memory cell is in a self-refresh mode, a standby mode or an active mode; temporarily activating the pre-charge equalization circuit before the memory cell is refreshed if the memory cell is in a self-refresh mode or a standby mode; and temporarily activating the pre-charge equalization circuit before the memory cell is refreshed or accessed if the memory cell is in an active mode.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store

Abstract

A slew rate control circuit is provided. The slew rate control circuit includes at least one switch and an inverter. A first end of the switch is coupled to a power terminal. A toggle end of the switch is coupled to a first control terminal. A second end of the switch is coupled to an output terminal. An output end of the inverter is coupled to the output terminal. An input end of the inverter is coupled to an input terminal. A voltage at the first control terminal conducts the switch to reduce the slew rate when a large voltage variation occurs at the output terminal. A method of controlling a slew rate and a slew rate control device are provided.

IPC Classes  ?

• H03K 5/12 - Shaping pulses by steepening leading or trailing edges

Abstract

A duty cycle correction circuit comprises a duty cycle detector, a filter, an amplifier, a charge pump, a control circuit, and a duty cycle corrector. The duty cycle detector is configured to generate a first pair of control signals according to a pair of internal clock signals. The filter is configured to obtain average voltages of the first pair of control signals. The amplifier is configured to compare output voltages of the filter for generating an enable signal, and the control circuit is configured to generate a selection signal according to the enable signal. The charge pump is configured to generate a second pair of control signals according to the enable signal and the selection signal, and the duty cycle corrector is configured to receive a pair of external clock signals, the first pair of control signals, and the second pair of control signals for generating the pair of internal clock signals with a corrected duty cycle.

IPC Classes  ?

• H03K 3/017 - Adjustment of width or dutycycle of pulses

Abstract

A dynamic RAM which includes a first inverter, a second inverter, a sense amplifier, a first pair of switches, a pair of bit lines, and a dynamic RAM cell. The first inverter receives a first driving signal. A power end of the first inverter is coupled to a first voltage source. The second inverter receives a second driving signal output from the first inverter. A power end of the second inverter is coupled to a second voltage source. The sense amplifier senses and amplifies a voltage difference between a first sensing signal and a second sensing signal. A power end of the sense amplifier is coupled to a third voltage source, wherein a voltage value of the second voltage source is between a voltage value of the first voltage source and a voltage value of the third voltage source.

IPC Classes  ?

• G11C 11/4063 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
• G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• G11C 11/409 - Read-write [R-W] circuits
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Abstract

th comparing result correspondingly, and 1≦j≦M. The invention also provides a method of testing n input/output arrays. The invention also provides a storage device.

IPC Classes  ?

• G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
• H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes

Abstract

A power-up circuit comprises an external supply voltage potential detector, a first internal supply voltage potential detector, a second internal supply voltage potential detector, and a logic circuit. The external supply voltage potential detector is configured to detect a supply voltage that is external to the memory device and to generate a first detection signal indicating whether a voltage potential of the external supply voltage reaches a first predetermined value. The first internal supply voltage potential detector is configured to detect a first internal supply voltage that is internal to the memory device and to generate a second detection signal indicating whether a voltage potential of the first internal supply voltage reaches a second predetermined value. The second internal supply voltage potential detector is configured to detect a second internal supply voltage that is internal to the memory device and to receive the first detection signal and an output voltage of the first internal supply voltage potential detector for generating a third detection signal indicating whether the voltage potentials of the external supply voltage and the first and second internal supply voltages reach the first, second, and third predetermined values respectively. The logic circuit is configured to receive the third detection signal and to generate a power-up signal.

IPC Classes  ?

• G11C 5/14 - Power supply arrangements

Abstract

A double data rate memory device comprises first and second sense amplifiers, a data selection circuit, and a data processing circuit. The first sense amplifier is configured to provide even data loaded on a first input and output data line, and the second sense amplifier is configured to provide odd data loaded on a second input and output data line. The data selection circuit is connected to the first and second sense amplifiers and is configured to provide output data loaded on a single data line, and the data processing circuit connected to the data selection circuit and configured to transfer the even data and the odd data in first and second data paths. The even data and the odd data are combined into the output data of the data selection circuit, and the data selection circuit selects the output data in response to a least significant bit of a column address and transfers the selected data on the single data line in response to a clock signal.

IPC Classes  ?

• G11C 8/00 - Arrangements for selecting an address in a digital store

Abstract

A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit.

IPC Classes  ?

• H03K 3/017 - Adjustment of width or dutycycle of pulses
• H03K 5/04 - Shaping pulses by increasing durationShaping pulses by decreasing duration
• H03K 7/08 - Duration or width modulation

Abstract

A method for tracking a delay locked loop (DLL) clock is described. An external clock signal is allowed to pass through delay cells of a DLL during a first period of the external clock signal when a transition edge of a track signal applied on the DLL occurs. Then, when a transition edge of a sensing signal applied on the DLL occurs at a start of a second period of the external clock signal, the external clock signal is inhibited to pass through the delay cells and the number of the delay cells through which the external signal pass during the first period of the external clock signal is counted. When a reset signal is asserted, a delay time of each delay cell is reset such that a ratio of the delay time to the period of the external clock signal is kept from 10% to 15%.

IPC Classes  ?

• H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop

Abstract

A method for operating a memory device with pseudo double clock signals comprises the steps of: generating an even clock signal and an odd clock signal, wherein the clock rates of both the even clock signal and the odd clock signal are half that of the input clock signal, and the even clock signal is the inverse signal of the odd clock signal; if the logic level of the even clock signal is 1 when receiving a trigger of a control signal, applying the even clock signal to a memory device; and if the logic level of the odd clock signal is 1 when receiving another trigger of the control signal, applying the odd clock signal to the memory device.

IPC Classes  ?

• G11C 8/00 - Arrangements for selecting an address in a digital store

Abstract

A main word line driving circuit for driving word lines in a memory device comprises first and second level shifting units and an inverting unit. The first level shifting unit is configured to convert a decode signal into a first operative signal, and the second level shifting unit is configured to convert the decode signal into a second operative signal. The inverting unit is configured to receive the first and second operative signals. A supply voltage of the first level shifting unit is selectively switched to a first bias voltage when the plurality of word lines are selected or partially selected and switched the output voltage to a second bias voltage when the plurality of word lines are deselected.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store

Abstract

A semiconductor memory device comprises a plurality of memory cells, a bit line sense amplifier, a local sense amplifier, and a sense amplifier. The memory cells are connected between a word line and a bit line pair, and the bit line sense amplifier is configured to amplify voltages of data from the bit line pair and then transmits the data to a local data line pair. The local sense amplifier is configured to amplify voltages of the data from the local data line pair and transmit the data to a global data line pair in response to first and second control signals, and the sense amplifier is configured to amplify the voltages of the data from the global data line pair and transmit the data to an input/output line pair during a read operation. The local sense amplifier comprises a first read circuit, a second read circuit, and a write circuit, and when the memory device performs the read operation, the data is transmitted from the first read circuit to the write circuit via the second read circuit.

IPC Classes  ?

• G11C 7/02 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals

Abstract

An over erase correction method of a flash memory apparatus is provided. The flash memory apparatus includes at least a microprocessor, a memory array, a bit line exchange unit and a column decoder. By controlling the column decoder of the flash memory during a period of the over-erase correction, the column decoder outputs control signals to the bit line exchange unit for selecting at least one of the bit lines according to a magnitude of the bit line leakage current. The drop in the charge pump voltage due to the bit line leakage current is reduced, and thus, the over-erase correction is executed effectively during the period of the over-erase correction.

IPC Classes  ?

• G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

A memory device is provided. The memory device includes a plurality of memory array banks, a bus, a data buffer, and four data paths. The data buffer provides data from the memory array banks to an external node. The first data path includes a first compression module for compressing the data from the memory array banks to the bus. The second data path transmits the data from the memory array banks to the bus. The third data path includes a second compression module for compressing data from the bus to the data buffer. The fourth data path transmits the data from the bus to the data buffer.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store

Abstract

A suitable erase verification (ERSV) method of a flash memory apparatus is provided, which is different from the conventional ERSV method. That is, by managing the ERSV operation on the flash memory after at least once of erase operation, a flash memory controller in the flash memory apparatus selectively assigns at least one of de-selected sectors instead of all of the de-selected sectors to perform the ERSV. Therefore, by managing the ERSV operation on the flash memory, the time for the ERSV operation thereon is reduced.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Abstract

A temperature-compensated ring oscillator includes a control signal generator and a voltage controlled oscillator. The control signal generator is configured to generate at least one control signal, and includes at least one first resistor and second resistor. A first temperature coefficient of the first resistor is negative, and a second temperature coefficient of the second resistor is positive. The voltage controlled oscillator receives the control signal, outputs an oscillation signal, and has (2k+1) cascaded inverter units, where k≧1. Each of the inverter units includes a first transistor, a second transistor and an inverter. The first transistor has a drain coupled to a first supply voltage and a gate to receive the control signal. The second transistor has a source to receive a second supply voltage and a gate to receive the control signal. The inverter is coupled between the first and the second transistors.

IPC Classes  ?

• H03K 3/03 - Astable circuits
• H03B 5/04 - Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature

Abstract

A circuit for reducing popping sound comprises a waveform generator, a voltage accumulator, and a comparator. The waveform generator is configured for generating a periodic waveform, and the voltage accumulator is configured for generating an increased voltage. The comparator is configured for comparing the periodic waveform with the increased voltage for generating a successive pulse signal. A percentage of a duty cycle in the successive pulse signal is increased gradually.

IPC Classes  ?

• H03K 3/017 - Adjustment of width or dutycycle of pulses

Abstract

A voltage level shifter comprises a voltage adjustment circuit, an inverter, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second NMOS transistor. The voltage adjustment circuit is configured for receiving a first voltage and a second voltage and for generating an adjustment voltage. When the first voltage is higher than the second voltage, the adjustment voltage is substantially equal to the first voltage, and when the first voltage is lower than the second voltage, the adjustment voltage is substantially equal to the second voltage.

IPC Classes  ?

• H03K 19/0175 - Coupling arrangementsInterface arrangements

Abstract

A method for conducting an over-erase correction describes the steps of: conducting a first erase and verification operation; using an FN soft program to correct over-erased cells if bit line leakage is found after the first erase and verification operation; conducting a second erase and verification operation; and using a hot carrier HC soft program to correct over-erased cells if bit line leakage is found after the second erase and verification operation.

IPC Classes  ?

• G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices

Abstract

A word line decoder circuit is provided in the present invention. The word line decoder circuit comprises at least one local pre-decoder, at least one 3-transistors row driver, a controllable power supply, and a controllable pull-down circuit. The controllable power supply is controlled by an inversed sector select signal to provide a first voltage to the row driver and local pre-decoder. The local pre-decoder uses 5-transistors architecture, in which there are 2 PMOS transistors and 3 NOS transistors. The controllable pull-down circuit pulls down the local pre-decoder and is controlled by a sector select signal and pre-decoding signal. The local pre-decoder receives a local pre-decoding signal to select the row driver. When the row driver is selected, the row driver determines a word line according to a row driver pull-down signal and a row driver pull-up signal.

IPC Classes  ?

• G11C 8/00 - Arrangements for selecting an address in a digital store

Abstract

A page buffer used in a NAND flash memory comprises a first latch circuit, a second latch circuit, a bit line voltage supply circuit and a verification circuit comprising a first verification path, a second verification path and a third verification path. The first latch circuit and the second latch circuit latch the data programmed into and read from the NAND flash memory. The bit line voltage supply circuit supplies bit line voltages to the corresponding bit line of the NAND flash memory. The verification circuit verifies the programming operations of the NAND flash memory. The first verification path is for the verification of a first LSB programming operation. The second verification path is for the verification of a second LSB programming operation before the first LSB programming operation is verified. The third verification path is for the verification of the second LSB programming operation after the first LSB programming operation is verified.

IPC Classes  ?

• G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

A sector of a word line driver circuit is provided, comprising a local reset signal generator module and m word line clusters. The m word line clusters are coupled to the local reset signal generator module. The local reset signal generator module is used to generate j reset signals. The x-th reset signal is determined according to an x-th pre-decoding signal, a bank selectable signal and a sector selectable signal, wherein j is a nature number, and x is an integer from 1 to j. Each of the m word line clusters comprises j row drivers. The x-th row driver of the y-th word line cluster determines a [x+j*(y−1)]-th word line signal according to the x-th reset signal, the x-th pre-decoding signal, the sector selectable signal, and a y-th cluster select signal, wherein m is a nature number, and y is an integer from 1 to m.

IPC Classes  ?

• G11C 8/00 - Arrangements for selecting an address in a digital store

Abstract

A triangular wave generating circuit includes: an integrating unit including a capacitor, the integrating unit having an output for providing a triangular wave signal; first and second constant current sources for charging and discharging the capacitor; a switch unit for coupling the first and second current sources to the integrating unit to charge and discharge the capacitor in response to an internal clock signal; a high/low level limiter including first and second comparing units for comparing the output of the integrating unit with upper and lower triangular wave peak limit reference voltages, respectively, and providing output signals indicating when the output of the integrating unit coincides with the peak limit reference voltages; a clock generator for providing the internal clock signal in response to the comparing unit output signals; and means for varying a peak-to-peak swing of the triangular wave signal over time to synchronize the internal clock signal with an externally supplied clock pulse.

IPC Classes  ?

• H03K 4/06 - Generating pulses having essentially a finite slope or stepped portions having triangular shape

Abstract

A method for erasing flash memory comprises the steps of: setting a critical ending condition; simultaneously erasing selected multiple sectors of the flash memory; stopping simultaneous erasing if one of the selected multiple sectors meets the critical ending condition; and erasing the remainder of each of the selected multiple sectors sequentially.

IPC Classes  ?

• G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices

Abstract

A voltage regulator circuit for a memory circuit comprises a voltage divider, a capacitor, an active-mode voltage regulator and a standby-mode voltage regulator. The active-mode voltage regulator is always on while in active mode, and turned on whenever a refresh is requested. The standby-mode voltage regulator is periodically turned on while in standby mode, and turned on whenever a refresh is requested. In addition, the active voltage regulator uses stronger transistors than those used by the standby-mode voltage regulator, and both the active-mode voltage regulator and the standby-mode voltage regulator are coupled to the voltage divider and the capacitor.

IPC Classes  ?

• G11C 5/14 - Power supply arrangements

Abstract

A voltage generating circuit is provided, including a voltage output terminal, a ground terminal, a capacitor, a selector, a first switch, and a second switch. The capacitor is connected between a pump signal and the output of the selector. The selector is controlled by a first control signal and used to select the voltage source or the voltage output terminal to connect the capacitor. The first switch is controlled by a second control signal, and the second switch is controlled by a third control signal. When the first switch is turn-on, the voltage output terminal is connected to the ground terminal. When the second switch is turn-on, the voltage output terminal is connected to the voltage source.

IPC Classes  ?

• H02M 3/18 - Conversion of DC power input into DC power output without intermediate conversion into AC by dynamic converters using capacitors or batteries which are alternately charged and discharged, e.g. charged in parallel and discharged in series

Abstract

A level shifter comprises a voltage converting circuit, a voltage pull-up circuit, and a control signal generating circuit. The voltage converting circuit is configured to receive an input signal of a first voltage level and to output an output signal of a second voltage level. The voltage pull-up circuit is coupled to the voltage converting circuit and configured to expeditiously pull up a voltage of an output node of the level shifter to the second voltage level in response to a control signal. The control signal generating circuit is configured to receive the input signal and to provide the control signal to the voltage pull-up circuit. The control signal generating circuit includes three transistors.

IPC Classes  ?

• H03K 19/0175 - Coupling arrangementsInterface arrangements

Abstract

A triangle wave generator with function of spreading frequency spectrum is provided. The triangle wave generator includes a switch control circuit, a current generator, an integrator, and a spread spectrum control circuit. The switch control circuit provides an internal clock and a switch control signal. The current generator is coupled to the switch control circuit and provides charge current according to the switch control signal. The integrator is coupled to the current generator and provides a triangle wave signal. The spread spectrum control circuit is coupled to the switch control circuit and the current generator for providing a current control signal according to the internal clock.

IPC Classes  ?

• H03K 4/06 - Generating pulses having essentially a finite slope or stepped portions having triangular shape

Abstract

A delay circuit has: an inverting receiver with a resistive element, the inverting receiver having an input node for receiving an input signal and an output node coupled to the resistive element; a capacitive element, coupled to the output node of the inverting receiver and the resistive element; a first transistor, having lower turned ON voltage at higher temperature; a second transistor, used for generating a rail to rail signals on a terminal of the first transistor; and an output inverter, having an input node coupled to the first transistor and an output node for outputting an output signal of the delay circuit. Further, a third transistor is used for enhancing pulling low of the output signal of the delay circuit.

IPC Classes  ?

• H03H 11/26 - Time-delay networks

Abstract

A voltage regulator in a semiconductor memory has: a comparing unit including first and second bias current sources, for comparing an output voltage with first and second reference voltages under control of a first signal, the second bias current source being ON under control of a second signal; and a driver active element, coupled to the comparing unit, for outputting the output voltage. Before sensing operations, the output voltage is reset to the second reference voltage. During the sensing operations, the output voltage is maintained at the first reference voltage and the second signal is asserted for turning ON the second bias current source for raising speed of the comparing unit. After the sensing operations, the output voltage is reset to the second reference voltage.

IPC Classes  ?

• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

A charge pump comprises a ring oscillator and a pumping circuit. The ring oscillator provides a plurality of oscillating clocks. The pumping circuit includes a plurality of pumping blocks coupled to each other for outputting a boosted voltage, and each pumping block is connected to a corresponding oscillating clock.

IPC Classes  ?

• G05F 1/10 - Regulating voltage or current

Abstract

A bit line precharge circuit is provided by the present invention. The bit line precharge circuit groups the precharge sub-circuits to share one drain bias controller. The drain bias controller has an inverter and a NMOS clamping transistor to form a negative feedback loop, to quickly precharge bit lines. When operating in read operation, only one drain bias controller is needed. Therefore, it can greatly save the layout area and operating power consumption without any extra dummy bit line or layout expansion.

IPC Classes  ?

• G11C 16/06 - Auxiliary circuits, e.g. for writing into memory

Abstract

A charge pump cell with an input and output nodes includes a first, second, and third equalization units, and a first, second, and third capacitors. The input node is coupled to the inputs of the first, second and third equalization units, and the output node is coupled to the second equalization unit. One end of the second capacitor is coupled to the control end of the first equalization unit for enabling or disabling the first equalization unit, and also coupled to the output of the third equalization unit. One end of the third capacitor is coupled to the output of the second equalization unit. One end of the first capacitor is coupled to the control ends of the second and third equalization units, and also coupled to the output of the first equalization unit.

IPC Classes  ?

• G05F 1/10 - Regulating voltage or current

Abstract

A fuse-fetching circuit comprises a plurality of fuses, a plurality of first switches and a shift register. Each of the first switches includes a first data end, a second data end and a control end. The first data end is connected to the fuse, and the control end is controlled by a fuse-fetching signal. The shift register includes a plurality of registers, each of which includes a first latch, a first transmission gate, a second latch and a second transmission gate. The first latch is connected to the second data end of the first switch.

IPC Classes  ?

• H01H 37/76 - Contact member actuated by melting of fusible material, actuated due to burning of combustible material or due to explosion of explosive material

Abstract

A high efficiency control circuit for operating a switching regulator is provided. The switching regulator can regulate an output voltage no matter the input voltage is higher, lower, or close to the output voltage. The switching regulator has first, second, third and fourth switches. The control circuit can operate the switching regulator in buck mode, boost mode, or buck-boost mode. In a buck-boost mode, the control logic drives the four switches in an efficiency sequence for reducing energy consumption during the switch transition, on the other side, resistive loss owing to the energy transfer phase is also minimized. Furthermore, the invention is capable of control duty cycle limitation to fit the consideration of the linearity of the converter.

IPC Classes  ?

• G05F 1/652 - Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is AC or DC using variable impedances in parallel with the load as final control devices

Abstract

In a voltage reference circuit, a bandgap reference circuit, for generating a bandgap reference voltage and a reference current, includes an operation amplifier, and a first transistor for providing the reference current. Another transistor mirrors the reference current to provide a first current. A compensation controller converts a node voltage from the bandgap reference circuit into a second current and performs current subtraction on the first current and the second current to provide a compensation feedback current to another node of the bandgap reference circuit. So that, second order temperature compensation is performed on the bandgap reference voltage.

IPC Classes  ?

• G05F 1/10 - Regulating voltage or current

Abstract

Provided is a current supply for providing a charge current to a load. The current supply includes: a driving transistor, providing the charge current to the load; a sensing transistor, limiting the charge current; a pulling low transistor, pulling low a controlling node which controls the driving transistor and the sensing transistor; a constant voltage controller, pulling up the controlling node, controlling the conduction state of the driving transistor and accordingly maintaining the voltage across the load at the first reference voltage, when a voltage across the load rises up and comes close to a first reference voltage; and a constant current controller, controlling the controlling node and the pulling low transistor to limit the charge current to be constantly provided to the load, when the voltage across the load drops much lower than the first reference voltage.

IPC Classes  ?

• H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

Abstract

A selection method of bit line redundancy repair includes the steps of providing a plurality of logical addresses of memory blocks in the normal cell array, generating a plurality of extra fuse signals, generating a code based on states of the extra fuse signals, the code matching a defective type of the memory blocks, and selecting a plurality of redundancy blocks in the redundancy cell array to replace the memory blocks according to the code. The apparatus includes a redundancy repair enable circuit for generating a redundancy enable signal based on logical addresses of the memory blocks, a controlling fuse circuit for sending a code matching a defective type of the memory blocks, and a redundancy decoder circuit for receiving the redundancy enable signal and the code to replace a plurality of memory blocks in the normal cell array with redundancy blocks.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store

Abstract

A method of programming a group of memory cells in a semiconductor memory device selecting a group of memory cells for programming, and enabling a first subgroup of memory cells from the group of memory cells for programming. After enabling the first subgroup, the programming method waits a first predetermined time period and after the first predetermined time period, enables a second subgroup of memory cells from the group of memory cells for programming while continuing to enable the first subgroup for programming.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A program method for a flash memory semiconductor device includes the steps of providing a bit line voltage for programming a group of memory cells and detecting if the bit line voltage meets a selected target voltage. When the bit line voltage meets the selected target voltage, a program operation is performed on the group of memory cells. When the bit line voltage does not meet the selected target voltage, the programming operation is individually performed on at least a first subgroup of memory cells from the group and a second subgroup of memory cells from the group.

IPC Classes  ?

• G11C 16/00 - Erasable programmable read-only memories

Abstract

A voltage regulator as a stable power supply to internal circuits in a semiconductor memory device is provided. This regulator includes a comparing unit, a first driver transistor, a feedback unit, an auxiliary control unit, a first switch, a second switch, and a second driver transistor. The comparing unit compares a reference voltage with a feedback signal to control the first driver transistor and maintain the internal power supply at a stable level. The second driver transistor, controlled by the first and second switches responsive to a trigger signal corresponding abrupt current consumptions and the auxiliary control unit responsive to the comparing result, supplies sufficient and appropriate current to the internal circuits and prevents the internal power supply from excessive overshoot and drop-out.

IPC Classes  ?

• G05F 3/02 - Regulating voltage or current

Abstract

A transmission method for a serial periphery interface (SPI) serial flash includes the steps of providing a first system clock signal and transmitting a plurality of data strings with each two bits of the data strings transmitted in a period of the first system clock signal. A second system clock signal is generated by the first system clock signal to provide a double frequency to enhance the transmission rate of all the data inputted into or outputted from the SPI serial flash.

IPC Classes  ?

• G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
• G06F 1/00 - Details not covered by groups and
• G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom

Abstract

A DRAM bit line precharge voltage generator comprises a first amplifier having a first current source and comparing a first voltage with a precharge voltage to control a first PMOS transistor, a second amplifier having a second current source and comparing a second voltage with the precharge voltage to control a second PMOS transistor, a third amplifier having a third current source and comparing a third voltage with the precharge voltage to control a first NMOS transistor, and a fourth amplifier having a fourth current source and comparing the first voltage with the precharge voltage to control a second NMOS transistor. The precharge voltage feedbacks from an output node connected between the second PMOS transistor and the first NMOS transistor. The DRAM bit line precharge voltage generator with a low-frequency pole provided by the first amplifier, the first PMOS transistor, the fourth amplifier, and the second NMOS transistor exhibits the characteristics of robustness, low standby current and low-output impedance.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store

Abstract

A circuit for providing a reference voltage includes a bandgap reference circuit, the bandgap reference circuit providing a first reference voltage and a data storage. The data storage stores a digital value corresponding to the first reference voltage. A digital to analog converter is coupled to the data storage for providing a second reference voltage corresponding to the digital value. The circuit also includes an output switch circuit responsive to at least one control signal, the output switch circuit providing either the first reference voltage or the second reference voltage to an output node responsive to the control signal.

IPC Classes  ?

• G05F 1/10 - Regulating voltage or current

Abstract

A charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, and an output unit is provided. Each controlled CP determines whether to provide charges to a node by a control signal, and each uncontrolled CP constantly provides charges to the node. The higher the node voltage at the node is, the more the controlled CPs not providing charge to the node are, so as to suppress the voltage of the node. In addition, the output unit regulates and outputs an output voltage according to the node voltage by the negative feedback.

IPC Classes  ?

• G05F 1/10 - Regulating voltage or current

Abstract

An amplifier includes a first comparator, a second comparator, and an output switch. The first and second comparators respectively compare a pair of differential signals with a half-swing modulation signal to generate first and second pulse-width-modulation (PWM) control signals, wherein a voltage swing of the half-swing modulation signal is smaller than voltage swing of the differential signals. The output switch includes a pair of inputs coupled to receive the PWM control signals to provide a ternary encoded output signal in response to the PWM control signals.

IPC Classes  ?

• H03F 3/38 - DC amplifiers with modulator at input and demodulator at outputModulators or demodulators specially adapted for use in such amplifiers

Abstract

A method for programming a multi-level-cell NAND flash memory device having plural memory cells is disclosed to reduce the programming time. The method comprises: programming each memory cell to a zero state, programming from the zero state to a first state by activating a first program signal and programming from the zero state to a quasi-second state and a semi-third state by activating a second program signal, programming from the quasi-second state to a second state and programming from the semi-third state to a quasi-third state by activating the second program signal, and programming from the quasi-third state to a third state by activating the first program signal. The present invention also discloses a page buffer to perform the method for programming a multi-level-cell NAND flash memory device, which comprises a bit line selection circuit, a first register, a second register, a first verify circuit, a second verify circuit and an exclusion circuit.

IPC Classes  ?

• G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

A method for reading a NAND flash memory device having plural normal cells, which utilizes plural reference bit lines associated with plural reference cells to read the normal cells in one phase to reduce the read time, is disclosed. The method comprises ramping up a selected word line voltage in a predetermined period and reading the normal cells with a zero state, a first state, a second state and a third state in the predetermined period. The present invention also discloses a memory cell array concerning the method for reading a NAND flash memory device. The memory cell array, which utilizes a voltage generator and plural reference cells to read the normal cells in one phase to reduce the amount of precharging and discharging of the normal bit lines, comprises plural normal cell blocks arranged in parallel, plural reference cell blocks interleaved between the normal cell blocks, plural normal bit lines coupled to the normal cell blocks, plural reference bit lines coupled to the reference cell blocks and a voltage generator.

IPC Classes  ?

• G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

A NAND non-volatile two-bit memory cell comprises a cell stack and two select stacks disposed on an active area of a substrate. Each select stack is respectively disposed on a side of the cell stack with a sidewall between the cell stack and a respective select stack. The cell stack has four components: a first dielectric layer disposed over the substrate; a charge accumulation layer capable of holding charge in a portion thereof to store information and disposed over the first dielectric layer; a second dielectric layer disposed over the charge accumulation layer; and a control gate disposed over the second dielectric layer. The select stack has two components: a third dielectric layer disposed over the substrate and a select gate, capable of inverting an underneath channel region to function as a source or a drain of the memory cell, disposed over the third dielectric layer.

IPC Classes  ?

• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
• H01L 29/76 - Unipolar devices

Abstract

A method for erasing a flash memory group is provided, which comprises the following steps. (a) Apply a erase (ERS) pulse to a first subset of the group. (b) Perform one of a soft program verification (SPGMV) and a tight soft program verification (TSPGMV) on the first subset of the group. (c) Repeat steps (a) and (b) until a first predetermined condition is true. (d) Perform an erase verification (ERSV) on a second subset of the group. (e) Repeat steps (a) to (d) until a second predetermined condition is true. And (f) fix bit line leakage in a third subset of the group with a slow program (SLPGM) and apply an ERS pulse to the third subset.

IPC Classes  ?

• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

A method of automatically determining a sensing timing in a page buffer of a NAND flash memory device is disclosed, which includes the steps of discharging a first reference bit line, discharging a second reference bit line, determining a first control signal and determining a second control signal. To perform the method, an apparatus of automatically determining a sensing timing in a page buffer of a NAND flash memory device is also disclosed. The apparatus includes a first reference bit line, a first current sink, a first reference page buffer, the second reference bit line, a second current sink and a second reference page buffer. The first reference bit line is coupled to the first current sink and the first reference page buffer at both ends thereof. The second reference bit line is coupled to the second current sink and the second reference page buffer at both ends thereof.

IPC Classes  ?

• G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices

Abstract

In a method of erasing flash memory cells, the flash memory cells organized in selectable memory blocks, the erasing step comprising applying an erase pulse voltage to a commonly biased cell well of at least one selected and at least one unselected memory blocks, the method comprising the steps of: raising the erase pulse voltage to a first intermediate voltage less than a target erase pulse voltage; maintaining the erase pulse voltage at the first intermediate voltage for a first period of time; after the first time period, raising the erase pulse voltage to the target erase pulse voltage; and maintaining the erase pulse voltage at the target erase pulse voltage during an erase operation.

IPC Classes  ?

• G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices

Abstract

A method of biasing word lines in a flash memory array wherein a selected word line is selected for a reading operation during data access includes the steps of biasing deselected word lines with a deselected word line voltage, delaying for a delay period and after the delay period, biasing the selected word line with a selected word line voltage for performing the reading operation.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store

Abstract

A FLASH memory device is provided including a plurality of first floating gates formed over a gate oxide layer formed over a substrate, the first group of floating gates being formed using a selected photolithography process associated with a minimum line width; a second group of floating gates including a plurality of second floating gates, wherein the first and second floating gates are disposed in series, with individual ones of the second floating gates disposed between respective ones of the first floating gates; a plurality of spacers, individual ones of the spacers disposed between adjacent ones of the first and second floating gates; a plurality of control gates associated with the floating gates, wherein the spacers and/or the second floating gates have widths less than the minimum line width.

IPC Classes  ?

• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
• H01L 29/76 - Unipolar devices
• H01L 21/792 -

Abstract

A clock circuit for generating a spread spectrum clock signal with reduced amplitude electromagnetic interference (EMI) spectral components is provided where the clock circuit includes a delay line circuit, the delay line circuit providing a spread spectrum clock signal from a reference clock signal in response to a modulation signal, a delay of said delay line circuit being controlled by said modulation signal.

IPC Classes  ?

• H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission

Abstract

A clock circuit for generating a spread spectrum clock signal with reduced amplitude electromagnetic interference (EMI) spectral components is provided where the clock circuit includes a delay line circuit, the delay line circuit providing a spread spectrum clock signal from a reference clock signal in response to a modulation signal, a delay of said delay line circuit being controlled by said modulation signal.

IPC Classes  ?

• H03D 3/24 - Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits