The neuron Logic Gate Metal-Oxide-Semiconductor (νLGMOS) circuits to mimic neurons' “integrate-and-fire” behaviors in biological neural network system can be fabricated with industry Complementary Metal-Oxide Semiconductor (CMOS) logic process technology, with which digital computational circuits are fabricated. A processing system having analog νLGMOS circuits, conversion circuitry and digital circuits optimized for power and cost for varieties of applications can be then fabricated with the same CMOS logic process technology for IC chips. Meanwhile analog νLGMOS circuits inspired from biological neural network systems can be simulated, designed, and fabricated for IC chips for the applications of biomedical fields.
A memory device is disclosed, comprising a 4T-SRAM cell and a read circuit. The 4T-SRAM cell comprising two P-type MOSFET devices for a data bit storage and two N-type MOSFET for accessing switches has benefits of less numbers of MOSFET devices for smaller cell size and low leakage current than the conventional 6T-SRAM cell. The read circuit comprises a latch and a discharge device. The latch with two output nodes is coupled between a supply voltage rail and a ground voltage rail. The discharge device is coupled to the two output nodes, a bit line pair and the ground voltage rail. Since one of two storage nodes for the 4T-SRAM cell is floating, the stored data in the 4T-SRAM cell is vulnerable for conventional read operations. The read circuit of the invention resolves the vulnerability issue of the 4T-SRAM cell.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H10B 41/60 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
The multi-digit binary in-memory multiplication devices are disclosed. The multi-digit binary in-memory multiplication devices of the invention can dramatically reduce the operational steps in comparison with the conventional binary multiplier device. In one embodiment with the expense of more hardware, the in-memory multiplication device can achieve one single step operation. Consequently, the multi-digit binary in-memory multiplication device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.
G06F 7/40 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using contact-making devices, e.g. electromagnetic relay
n in-memory adder device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.
G06F 7/507 - AddingSubtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
An in-memory digital processor, Perpetual Digital Perceptron (PDP), is disclosed. The digital in-memory processor of the invention processes the input digital information according to a database of the digital content data stored/hardwired in the Content Read Only Memory (CROM) array and outputs the correspondent digital response data stored/hardwired in the Response Read Only Memory (RROM) array. The PDP is the hardwired digital in-memory processor without re-configuration capability and similar to the instinct functions of biological hardwired brains without re-shaping their neuromorphic structures from training and learning.
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using elements simulating biological cells, e.g. neuron
A dynamic digital perceptron device is disclosed. The dynamic digital perceptron device of the invention comprises a volatile content memory array, a detection and driver circuit and a volatile response memory array. The dynamic digital perceptron device processes input digital information according to a database of the digital content data stored in the volatile content memory array and outputs the correspondent digital data stored in the volatile response memory array by the detection and driver circuit. Moreover, the volatile content memory array and the volatile response memory array in the dynamic digital perceptron device are constructed by the latch-types of memory cells to handle the rapid and frequent changing digital processing environments.
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using elements simulating biological cells, e.g. neuron
In-memory arithmetic processors for the “n-bit” by “n-bit” multiplication, the “n-bit” by “n-bit” addition, and the “n-bit” by “n-bit” subtraction operations are disclosed. The in-memory arithmetic processors of the invention can obtain the operational resultant integer in the binary format for two inputted integers represented by two “n-bit” binary codes in one-step processing with no sequential multiple-step operations as for the conventional arithmetic binary processors. The in-memory arithmetic processors are implemented by a 2-dimensional memory array with X and Y decoding for the two inputted operational integers in the arithmetic binary operations.
For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.
H01L 27/00 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
H01L 27/11558 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate the control gate being a doped region, e.g. single-poly memory cells
H01L 27/11526 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
Inspired by the processing methods of biologic brains, we construct a network of multiple configurable non-volatile memory arrays connected with bus-lines as a neuromorphic code processor for code processing. In contrast to the Von-Neumann computing architectures applying the multiple computations for code vector manipulations, the neuromorphic code processor of the invention processes codes according to their configured codes stored in the non-volatile memory arrays. Similar to the brain processor, the neuromorphic code processor applies the one-step feed-forward processing in parallel resulting in a dramatic power reduction compared with the computational methods in the conventional computer processors.
2 for the LGNVM NOR flash arrays can be achieved by this method, where F is the minimal feature size for a specific CMOS logic process technology node.
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 27/11558 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate the control gate being a doped region, e.g. single-poly memory cells
A non-differential sense amplifier circuit for reading out information in Non-Volatile Memories (NVMs) is disclosed. The circuit comprises a half latch, a PMOSFET device, a switch device and a reset transistor. The PMOSFET device has a source electrode connected to a digital voltage rail, a drain electrode connected to an output node of the half latch and a gate electrode connected to a bitline path coupled with a selected NVM cell. After the bitline path is pre-charged and the reset transistor is turned off, applying a read voltage to a word line related to the selected NVM cell causes a voltage at the gate electrode of the PMOSFET device to drop differently according to an electrical conductance state of the selected NVM cell. The disclosed circuitries can achieve extra low power consumption and high sensing speed compared to those in the conventional sensing scheme.
G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
The standby leakage current reduction schemes for digital data storing components are disclosed. By floating the low digital voltage node of the digital data storing components in standby mode, the major standby leakage current paths to the ground voltage caused by the channel diffusion leakage current of MOSFET devices can be terminated. The standby leakage currents will be reduced to the small reverse junction leakage currents to the grounded substrate. For retaining the stored data in the digital data storing components in standby mode, the low digital voltage node is connected to the ground voltage periodically according to a plurality of rectangular voltage pulses outputted from a pulse generator trigged by a low frequency clock oscillator. Due to no external voltage bias to the low digital voltage node other than floating the digital low voltage node, the data recovering process is instant.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
In view of the neural network information parallel processing, a digital perceptron device analogous to the build-in neural network hardware systems for parallel processing digital signals directly by the processor's memory content and memory perception in one feed-forward step is disclosed. The digital perceptron device of the invention applies the configurable content and perceptive non-volatile memory arrays as the memory processor hardware. The input digital signals are then broadcasted into the non-volatile content memory array for a match to output the digital signals from the perceptive non-volatile memory array as the content-perceptive digital perceptron device.
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G11C 15/00 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
G06F 12/1036 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
A Configurable Non-Volatile Content Addressable Memory (CNVCAM) cell consisting of a pair of complementary non-volatile memory devices and a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) is disclosed. The CNVCAM cells can be constructed to form the NOR-type match line memory array and the NAND-type match line memory array. In contrast to the Random Access Memory (RAM) accessed by the address codes with the prior knowledge of memory locations, CNVCAM can be pre-configured into non-volatile memory content data and searched by an input content data to trigger the further computing process. The unique property of CNVCAM can provide a key component for neural computing.
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
A Configurable Non-Volatile Content Addressable Memory (CNVCAM) cell consisting of a pair of complementary non-volatile memory devices and a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) is disclosed. The CNVCAM cells can be constructed to form the NOR-type match line memory array and the NAND-type match line memory array. In contrast to the Random Access Memory (RAM) accessed by the address codes with the prior knowledge of memory locations, CNVCAM can be pre-configured into non-volatile memory content data and searched by an input content data to trigger the further computing process. The unique property of CNVCAM can provide a key component for neural computing.
G11C 15/00 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
17.
Ultra-low power programming method for N-channel semiconductor non-volatile memory
DB relative to the substrate to facilitate the valence band electrons in the P-type substrate to tunnel to the conducting band of the N-type drain electrode. A positive high gate voltage pulse is then applied to the gate electrode of the N-channel semiconductor NVM to collect the surface energetic electrons toward the charge storage material.
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
SS) to the input nodes of the pair of complementary SGLNVM devices, the output node of the pair of complementary SGLNVM devices outputs digital signals according to its configuration. The NV-LUT outputs digital signals from a plurality of pairs of complementary SGLNVM devices through a digital switching multiplexer. The NV-LUT is a good substitution for SRAM based LUT commonly used in Field Programmable Gate Array (FPGA).
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
19.
Interconnection matrix using semiconductor non-volatile memory
An interconnection matrix consists of a plurality of semiconductor Non-Volatile Memory (NVM) forming an M×N array. Semiconductor NVM devices in the array are either programmed to a high threshold voltage state or erased to a low threshold voltage state according to a specific interconnection configuration. Applied with a gate voltage bias higher than the low threshold voltage and lower than the high threshold voltage to the control gates of the entire semiconductor NVM devices in the array, the configured interconnection network is formed. The disclosed interconnection matrix can be applied to configuring circuit routing in Integrated Circuit (IC).
A 3-D Single Floating Gate Non-Volatile Memory (SFGNVM) device based on the 3-D fin Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The disclosed Non-Volatile Memory (NVM) device consists of a pair of semiconductor fins and one floating metal gate. The floating metal gate for storing electrical charges to alter the threshold voltage of the fin MOSFET crosses over the pair of semiconductor fins on top of coupling and tunneling dielectrics above the surfaces of the two semiconductor fins. One semiconductor fin with the same type impurity forms the control gate of the non-volatile memory device. The other semiconductor fin is doped with opposite type of impurity in the channel regions under the metal floating gate and with the same type of impurity in the source and drain regions on the sides of the crossed metal floating gate.
SS passed through the high conductance non-volatile memory element in the pair is directly accessed by the access transistor without applying a sense amplifier as the conventional EEPROM would require. Without sense amplifiers, the digital data in CEEPROM can be fast accessed. The power consumption and the silicon areas required for sense amplifiers can be saved as well.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
22.
Scalable gate logic non-volatile memory cells and arrays
Scalable Gate Logic Non-Volatile Memory (SGLNVM) devices fabricated with the conventional CMOS process is disclosed. Floating gates of SGLNVM with the minimal length and width of the logic gate devices form floating gate Metal-Oxide-Semiconductor Field Effect Transistor. The floating gates with the minimal gate length extend over silicon active areas to capacitively couple control gates embedded in silicon substrate (well) through an insulation dielectric. The embedded control gate is formed by a shallow semiconductor type opposite to the type of the silicon substrate or well. Plurality of SGLNVM devices are configured into a NOR-type flash array where a pair of SGLNVM devices share a common source electrode connected to a common ground line with two drain electrodes connected to two separate bitlines. The pairs of the NOR-type SGLNVM cells are physically separated and electrically isolated by dummy floating gates to minimize cell sizes.
Scalable Gate Logic Non-Volatile Memory (SGLNVM) devices fabricated with the conventional CMOS process is disclosed. Floating gates of SGLNVM cell with the minimal length and width of the logic gate devices form floating gate Metal-Oxide-Semiconductor Field Effect Transistor. The floating gates with the minimal gate length extend over silicon active areas to capacitively couple control gates embedded in silicon substrate (well) through an insulation dielectric. The embedded control gate is formed by a shallow semiconductor type opposite to the type of the silicon substrate or well. Plurality of SGLNVM devices are configured into a NOR-type flash array where a pair of SGLNVM devices share a common source electrode connected to a common ground line with two drain electrodes connected to two separate bitlines. The pairs of the NOR-type SGLNVM cells are physically separated and electrically isolated by dummy floating gates to minimize cell sizes.
A rechargeable battery is disclosed. The rechargeable battery of the invention includes a high density capacitor and an integrated circuit. The high density capacitor is connected between a ground terminal and a first node carrying a first voltage. The integrated circuit includes a band gap circuit, a first detecting unit, a voltage divider, a second detecting unit and at least one low dropout voltage regulator. The first detecting unit measures the first voltage and determines whether to apply an input charging voltage to the high density capacitor. The second detecting unit measures the second voltage according to the band gap voltage and determines whether to connect a third node to the first node. Each low dropout voltage regulator is connected to the third node and generates a specified voltage output and a specified current output according to the band gap voltage and the first voltage.
Dual Conducting Floating Spacer Metal Oxide Semiconductor Field Effect Transistors (DCFS MOSFETs) and methods for fabricate them using a process that is compatible with forming conventional MOSFETs are disclosed. A DCFS MOSFET can provide multi-bit storage in a single Non-Volatile Memory (NVM) memory cell. Like a typical MOSFET, a DCFS MOSFET includes a control gate electrode on top of a gate dielectric-silicon substrate, thereby forming a main channel of the device. Two electrically isolated conductor spacers are provided on both sides of the control gate and partially overlap two source/drain diffusion areas, which are doped to an opposite type to the conductivity type of the substrate semiconductor. The DCFS MOSFET becomes conducting when a voltage that exceeds a threshold is applied at the control gate and is coupled through the corresponding conducting floating spacer to generate an electrical field strong enough to invert the carriers near the source junction. By storing charge in the two independent conducting floating spacers, DCFS MOSFET can have two independent sets of threshold voltages associated with the source junctions.
patents
