A semiconductor device includes a first circuit configured to receive a first signal, which is a differential parallel signal, and output a second signal, which is a differential serial signal, based on the first signal. The first circuit includes a second circuit configured to convert the first signal to a third signal, which is a differential serial signal, a third circuit configured to receive the third signal and output the second signal, which corresponds to the third signal, a fourth circuit configured to receive the third signal and output a fourth signal corresponding to the third signal selectively during a predetermined operation mode, and a fifth circuit configured to receive the fourth signal and output a fifth signal obtained by buffering the fourth signal.
According to some embodiments, a semiconductor device includes a signal input terminal configured to input a signal. The semiconductor device includes a first transistor of a first conductivity type, a second transistor of a second conductivity type, a third transistor of the second conductivity type, a fourth transistor of the second conductivity type. The current capacity of the second transistor and a current capacity of the third transistor are higher than a current capacity of the first transistor.
A semiconductor memory device comprises: first semiconductor layers stacked in a first direction; a via wiring electrically connected to the first semiconductor layers; memory portions electrically connected to the first semiconductor layers; first gate electrodes facing the first semiconductor layers; a first wiring and a second wiring provided on one side and the other side in the first direction with respect to the first semiconductor layers; a second semiconductor layer provided between the first semiconductor layers and the first wiring, and electrically connected to the via wiring; a first connecting electrode electrically connected to the first wiring and the second semiconductor layer; a third semiconductor layer provided between the first semiconductor layers and the second wiring, and electrically connected to the via wiring; and a second connecting electrode electrically connected to the second wiring and the third semiconductor layer.
A semiconductor memory device includes a semiconductor substrate; a memory cell array layer disposed apart from the semiconductor substrate in a first direction intersecting with the semiconductor substrate. The memory cell array layer includes: a first stacked structure and a second stacked structure arranged in a second direction; and a third stacked structure provided between the first and second stacked structures. The first to third stacked structures include a plurality of first layers and a plurality of first insulating layers alternately stacked in the first direction and extending in a third direction. The first and second stacked structures include a plurality of blocks arranged in the second direction. A plurality of blocks excluding the first block closest to the third stacked structure includes a first conductive layer in the first layer. The third stacked structure and the first block include a second insulating layer as the first layer.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
A semiconductor device manufacturing method of embodiments includes: performing a first supply of a chemical solution from an application nozzle onto a surface of a wafer; storing the application nozzle in a container; performing a second supply of a solvent into the container; measuring first defects in the solvent discharged from the container; performing the first supply of the chemical solution from the application nozzle onto the surface of the wafer when the number of first defects is less than a first threshold value; and continuing the second supply of the solvent into the container when the number of first defects is equal to or greater than the first threshold value.
A semiconductor memory device comprises a first wiring layer and a second wiring layer. The second wiring layer comprises a plurality of word line voltage supply line groups and a plurality of block select line groups that are arranged alternately in a second direction. The plurality of block select line groups each include a first block select line and a second block select line. The first block select line, which is a first block select line counting from one side in the second direction, of a plurality of block select lines, comprises a first bent portion where the first block select line is bent in a direction of getting further away from a word line voltage supply line adjacent in the second direction. The second block select line comprises a first connecting portion which is electrically connected at its end portion in the first direction to the first wiring layer.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/08 - Address circuitsDecodersWord-line control circuits
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
A storage device includes a memory cell that includes: first, second, third conductive layers; a switching layer between the first and third conductive layers; and a resistive layer between the third and second conductive layers. The switching layer includes first, second, and third portions. The switching layer contains a first element and an oxide, a nitride, or an oxynitride of a second element, or the first element and a third element. The first element is at least one selected from a group consisting of Te, Se, S, Sb, and As. The second element is at least one selected from a group consisting of Zr, Al, Hf, Y, Ta, La, Ce, Mg, Si, and Ti. The third element is at least one selected from a group consisting of Zn, Sn, Ga, In, Bi, and Mg. The lengths of the first, second, and third portions are different from each other.
A semiconductor device of embodiments includes: a first electrode; a second electrode; a first oxide semiconductor layer between the first electrode and the second electrode; a second oxide semiconductor layer separated from the first oxide semiconductor layer in a second direction perpendicular to a first direction connecting the first electrode and the second electrode; and a gate electrode surrounding the first oxide semiconductor layer and the second oxide semiconductor layer and extending in the second direction. The gate electrode includes a first portion and a second portion. The first portion faces the first oxide semiconductor layer and is in contact with the gate insulating layer in the second direction, and has a first length in the first direction. The second portion is away from the first oxide semiconductor layer in the second direction and has a second length in the first direction smaller than the first length.
A manufacturing method for a semiconductor device according to an embodiment includes a first step deforming a bump of a semiconductor element by applying a first load to the semiconductor element to press the bump onto a circuit board and applying either no ultrasonic vibration or ultrasonic vibration with a first strength to the bump and a second step, after the first step, bonding the bump to a pad of the circuit board by applying a second load to the semiconductor element to press the bump and applying ultrasonic vibration with a second strength stronger than the first strength to the bump.
A memory system includes a non-volatile memory and a controller. The controller includes an instruction information processing unit configured to generate internal instruction information for causing the non-volatile memory to execute an instruction that causes the non-volatile memory to read and write the data based on external instruction information including the instruction and configured to transmit the internal instruction information to the non-volatile memory through the memory interface circuit, and a delay circuit control unit configured to control a delay circuit based on a magnitude relationship between a data amount read and written by the non-volatile memory during unit time and a first threshold value. The delay circuit is configured to delay execution of the instruction.
A semiconductor device includes a substrate, an oxide semiconductor layer that is spaced from the substrate and contains a first metal element and oxygen (O), a first wiring opposed to the oxide semiconductor layer, a gate insulating film disposed between the oxide semiconductor layer and the first wiring, a first conductive layer that is in contact with the oxide semiconductor layer and contains a second metal element and oxygen (O), a second wiring connected to the first conductive layer, and a first insulating portion in contact with the second wiring. The first insulating portion includes a first region and a second region between the first region and the second wiring. A concentration of the first metal element or the second metal element in the second region is higher than a concentration of the first metal element or the second metal element in the first region.
A semiconductor memory device of embodiments includes: a semiconductor layer; a gate electrode layer; a first insulating layer between the semiconductor layer and the gate electrode layer; a second insulating layer between the first insulating layer and the gate electrode layer; and a charge storage layer between the first insulating layer and the second insulating layer, containing at least one first crystal including a first region having one space group selected from a group consisting of a space group Pca21 (space group number 29), a space group R3 (space group number 146), a space group R3m (space group number 160), and a space group Pmn21 (space group number 31), and containing at least one first element selected from a group consisting of Hf and Zr, at least one second element selected from a group consisting of Ti, Ce, Ta, W, Nb, Mo, Mn, Ru, and Sn, and oxygen.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
13.
SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD
A substrate processing apparatus includes a substrate holder to hold a substrate, a treatment liquid supplier to supply a treatment liquid onto a surface of the substrate to be cleaned, a cooler to supply a cooling medium for cooling the substrate, an impactor to apply an impact to a treatment liquid layer, and a controller. The controller controls the cooler to cool the treatment liquid layer to a temperature lower than a freezing point, and controls the impactor to apply an impact to a starting point of forced freezing located away from a starting point of spontaneous freezing in the treatment liquid layer formed on the surface of the substrate to be cleaned, when a temperature of the treatment liquid layer formed reaches a set temperature that is lower than a freezing point and higher than a temperature at which spontaneous freezing occurs.
B08B 7/00 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass
B08B 3/10 - Cleaning involving contact with liquid with additional treatment of the liquid or of the object being cleaned, e.g. by heat, by electricity or by vibration
B08B 7/02 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass by distortion, beating, or vibration of the surface to be cleaned
B08B 13/00 - Accessories or details of general applicability for machines or apparatus for cleaning
In general, according to one embodiment, a semiconductor memory device includes: first, second, and third interconnect layers sequentially arranged while being apart from one another in a first direction; a memory pillar extending in the first direction and including a portion intersecting the first interconnect layer and functioning as a first memory cell; and a control circuit controlling a read operation of the first memory cell, wherein, during the read operation, the control circuit performs a first operation of rising a voltage of the third interconnect layer from a first to a second voltage at a first rate; a second operation of rising a voltage of the second interconnect layer from the first to a third voltage at a second rate higher than the first rate; and, a third operation of changing a voltage of the first interconnect layer to a read level voltage.
A semiconductor device includes a first electrode; a second electrode; an oxide semiconductor layer extending between the first electrode and the second electrode; and a gate electrode provided next to the oxide semiconductor layer. The first electrode includes a first region, a second region, and a third region. The first region is provided between the second region and the oxide semiconductor layer, and includes at least one of In, Sn, Zn, Ta, or W. The second region includes a second metal element and includes or does not include N, and the second metal element includes one of Ti, W, Mo or Ta. The third region includes a first part and a second part, the third region includes a first element and O, and the first element includes at least one of Ti, Al, Zr, Hf, or Si.
A memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller is configured to: after transmitting a write command and an address to the nonvolatile memory via a first signal line, transmit dummy data to the nonvolatile memory via the first signal line during at least a portion of a period that is between when the address is transmitted via the first signal line and when write data of the write command is transmitted via the first signal line, and after transmitting the dummy data via the first signal line, transmit a data strobe signal to the nonvolatile memory via a second signal line and transmit the write data of the write command to the nonvolatile memory via the first signal line in synchronization with the data strobe signal.
This semiconductor storage device comprises: a plurality of memory blocks each including a memory cell and a word line; a voltage supply line commonly electrically connected to the plurality of word lines corresponding to the plurality of memory blocks; a plurality of transistors electrically connecting the plurality of word lines and a voltage supply line; a plurality of signal supply lines connected to gate electrodes of the plurality of transistors; a plurality of block decoder units capable of outputting a signal to any one from among the plurality of signal supply lines in accordance with the input of a signal corresponding to a block address; and a control circuit. Each among the plurality of block decoder units comprises a latch circuit. The control circuit rewrites data of the plurality of latch circuits corresponding to plurality of selected memory blocks in a multiple memory block erasure operation.
According to an embodiment, a semiconductor memory device includes first and second array chips and a circuit chip. A first memory cell array includes a first memory cell and first and second selection transistors. A second memory cell array includes a second memory cell and third and fourth selection transistors. A third memory cell array includes a third memory cell and fifth and sixth selection transistors. A fourth memory cell array includes a fourth memory cell and seventh and eighth selection transistors. A first word line is connected to the first and third memory cells. A second word line is connected to the second and fourth memory cells. A first bit line is connected to the first and seventh selection transistors. A second bit line is connected to the third and fifth selection transistors. In a write operation, different voltage application conditions are set for the first array chip and the second array chip.
A semiconductor device includes an upper electrode, a lower electrode, an oxide semiconductor including a first portion connected to the upper electrode, a connection portion, a second portion that is connected to a lower end portion of the first portion through the connection portion, has a diameter larger than that of the lower end portion of the first portion, and connected to the lower electrode, a gate insulating film surrounding a side surface of the first portion and has an outer diameter smaller than that of the second portion, a first insulating layer through which the first portion penetrates, a gate electrode which is provided below the first insulating layer and faces the first portion via the gate insulating film, the first portion penetrating through the gate electrode, and a second insulating layer provided below the gate electrode, wherein the connection portion is surrounded by the second insulating layer.
A first conductor extends in a first direction. A first semiconductor surrounds the first conductor along a first plane intersecting the first direction. A first insulator surrounds the first semiconductor along the first plane. A second conductor surrounds the first insulator along the first plane. A third conductor is located farther in the first direction than the first semiconductor and surrounds the first conductor along the first plane. A second insulator is between the first semiconductor and the third conductor.
A semiconductor memory device of an embodiment includes a memory cell including a semiconductor layer, a gate electrode layer containing a ferroelectric, and a first wiring and a second wiring connected to the semiconductor layer, and a control circuit. The control circuit executes a first write operation of applying a first voltage with a first polarity to the memory cell, and executes a second write operation of applying a second voltage having a smaller absolute value than the first voltage with the first polarity to the memory cell. The control circuit executes a first operation to the memory cell before the second write operation to the memory cell. The first operation applies a voltage having a larger absolute value than the second voltage with the first polarity and applies a voltage having a larger absolute value than the second voltage with a polarity opposite to the first polarity.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
A semiconductor memory device includes a memory block including first and second sub memory blocks, a bit line and a source line, and a control circuit. The first and the second sub memory blocks include first and second memory cells and first and second word lines, respectively. The control circuit performs, in an erase operation on the memory block, a first determination operation to determine a write state of the second memory cell, a first erase operation performed when the second memory cell is in the write state, and a second erase operation performed when the second memory cell is in an erase state.
A memory device of embodiments includes a memory cell including a first conductive layer, a switching layer, a third conductive layer, a variable resistance layer, and a second conductive layer in this order. The switching layer contains a first oxide of a first element selected from Al, Si, Ge, Zr, Y, Ta, La, Ce, Ti, Hf, and Mg, a second element selected from Al, Zn, Sn, Ga, In, and Bi, and a third element selected from Te, S, Se, and Sb. The switching layer includes a first region, a second region, and a third region, and the first region is between the second region and the third region. The first region contains the first oxide, and the second region and the third region contain a second oxide of the second element or a third oxide of the third element.
A semiconductor memory device includes first and second stacked films, each of which includes a plurality of conductive layers and a plurality of insulating layers alternately stacked one on top of another, a first core insulating film penetrating the stacked film and containing an oxide, a channel semiconductor film around the first core insulating film and penetrating the first stacked film, a tunnel insulating film around the channel semiconductor film and penetrating the first stacked film, and a charge storage film around the tunnel insulating film and penetrating the first stacked film. The first stacked film additionally includes a second core insulating film around the first core insulating film, penetrating the first stacked film and containing a nitride, and a third core insulating film between the channel semiconductor film and the second core insulating film, penetrating the first stacked film, and including an oxide.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
25.
SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device according to an embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer between the first electrode and the second electrode; and a gate electrode facing the oxide semiconductor layer. The gate electrode includes a first portion and a second portion sandwiching the oxide semiconductor layer between them. The distance between an inner side of the first portion and an inner side of the second portion decreases from the first electrode side towards the second electrode side. The distance between an outer side of the first portion and an outer side of the second portion decreases from the first electrode side towards the second electrode side.
A memory device of embodiments includes a memory cell including a first conductive layer, a switching layer, a third conductive layer, a variable resistance layer, and a second conductive layer provided in this order. The switching layer contains an oxide of a first element, and a compound of a second element and a third element. The first element is Si, B, Ge, P, or As. The second element is Zn, Sn, Ga, In, or Bi. The third element is Te, S, or Se. A ratio of a sum of atomic concentrations of the first element and oxygen to a sum of atomic concentrations of the first element, the second element, the third element, and oxygen in the switching layer is equal to or more than 10%.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
A conductor device includes a first power line to which a first voltage is supplied, a second power line to which a second voltage lower than the first voltage is supplied, a first logic circuit including a first electrode, and electrically connected to the first power line, a second logic circuit including a second electrode provided separately from the first electrode, and electrically connected to the first power line and the first logic circuit, a voltage supplying circuit that controls, based on a first control signal, whether or not to supply a third voltage to the first electrode, the third voltage being lower than the first voltage and higher than the second voltage, and a first transistor including a gate electrode to which a second control signal is input, and electrically connected between the second electrode and the second power line.
A semiconductor memory device includes: semiconductor layers stacked in a first direction and arranged in a second direction and a third direction; via-wirings each electrically connected to the semiconductor layers stacked in the first direction; memory portions electrically connected to the semiconductor layers; gate electrodes opposed to the semiconductor layers; and wiring members each disposed between two gate electrodes adjacent in the third direction among the gate electrodes. The plurality of gate electrodes include first gate electrodes disposed at a first position in the first direction and arranged in the third direction. The wiring members include first wiring members disposed at the first position in the first direction and arranged in the third direction. The first wiring members are mutually electrically connected via the first gate electrodes.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the top-view layout
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
Reliable high-speed serial transmission is performed. A semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, which is a differential parallel signal, and output a second signal, which is a differential serial signal, based on the first signal. The second circuit is configured to adjust an output impedance of an output node of the first circuit. The third circuit is configured to vary a power supply voltage that is supplied to at least a part of the first circuit in accordance with an adjustment of the output impedance by the second circuit.
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
According to one embodiment, a semiconductor memory device including multiple first memory cells and a first selection mechanism is provided. The multiple first memory cells are stacked above a substrate. The multiple first memory cells are connected in parallel between a first vertical bit line and a first vertical source line. The first vertical bit line extends in a stacking direction. The first vertical source line extends in the stacking direction. The first selection mechanism is disposed between the substrate and the multiple first memory cells in the stacking direction. The first selection mechanism selectively connects the first vertical bit line to a first local bit line. The first selection mechanism selectively connects the first vertical source line to a first local source line.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
31.
STORAGE SYSTEM HAVING A HOST DIRECTLY MANAGE PHYSICAL DATA LOCATIONS OF STORAGE DEVICE
A storage system includes a host including a processor and a memory unit, and a storage device including a controller and a non-volatile memory unit. The processor is configured to output a write command, write data, and size information of the write data, to the storage device, the write command that is output not including a write address. The controller is configured to determine a physical write location of the non-volatile memory unit in which the write data are to be written, based on the write command and the size information, write the write data in the physical write location of the non-volatile memory unit, and output the physical write location to the host. The processor is further configured to generate, in the memory unit, mapping information between an identifier of the write data and the physical write location.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
A semiconductor storage device according to the present invention comprises a first memory cell transistor, a second memory cell transistor, a sense amplifier, and a control unit. In a first operation mode, the control unit, via the sense amplifier, senses data stored at the first memory cell transistor. In the first operation mode, the control unit adjusts a first prescribed number of first read voltages to the first prescribed number of third read voltages that include a second prescribed number that is smaller than the first prescribed number of second read voltages that correspond to a plurality of second threshold voltage distributions, applies the first prescribed number of third read voltages to a gate of the second memory cell transistor via a word line, and, via the sense amplifier, senses data stored at the second memory cell transistor.
According to one embodiment, a memory system includes a first semiconductor device and a controller. The first semiconductor device includes a first chip having a first temperature sensor. The controller includes a comparison circuit makes a comparison between a first measurement temperature of the first temperature sensor and first temperature data and outputs a first comparison result, and makes a comparison between the first measurement temperature and second temperature data and outputs a second comparison result, and a detection circuit performs detection of a defect in the first temperature sensor based on the first and second comparison results, and outputs a first detection result. The first chip switches a first use temperature based on the first detection result.
In one embodiment, a semiconductor device includes a stacked film alternately including first insulators and electrode layers in a first direction, and including a non-staircase portion, and a staircase portion provided in a second direction relative to the non-staircase portion. The device further includes a first pillar portion including a second insulator provided in the staircase portion. The stacked film includes partial stacked films stacked in the first direction, and the first pillar portion includes partial pillar portions respectively provided in the partial stacked films. The partial pillar portions include a first partial pillar portion having a first major radius and a first minor radius, and a second partial pillar portion having a second major radius and a second minor radius, an angle of the first/second major radius relative to the second direction being smaller/larger than an angle of the first/second minor radius relative to the second direction.
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
In general, according to one embodiment, an operation method using a first latch circuit including: first and second inverters each includes an input terminal coupled to first and second nodes respectively, and an output terminal coupled to the second and first nodes, respectively, the operation method comprising: storing first and second data in the first and second node by setting the first and second inverters to a driven state, wherein the second data is inverted data of the first data; reading the first data from the first node to a bus coupled to the first latch circuit by setting the first and second inverters to an undriven state; writing the first data based on the second data to the first node from which the first data is read by setting the first inverter to the driven state; and driving the second inverter after the first data is written.
A first semiconductor extends in a first direction. A first pillar extends in a second direction crossing the first direction and is in contact with the first semiconductor. A first conductor is coupled to an end of the first pillar on a side in the second direction and extends in a third direction crossing the first direction and the second direction. A first transistor is provided farther in the second direction than the first conductor and coupled to the first conductor. A second conductor is provided farther in the second direction than the first conductor, extends in the third direction, and is coupled to the first transistor.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
37.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes a wiring board, a first semiconductor module that includes one or more first semiconductor chips staked together, a wire that connects one of the one or more first semiconductor chips to the wiring board, and a second semiconductor module that is arranged adjacent to the first semiconductor module and includes second semiconductor chips stacked together. At least part of the wire is in contact with an adhesive layer between an N-th second semiconductor chip and an (N+1)th second semiconductor chip from a lowermost layer among the second semiconductor chips.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
38.
MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a memory system includes a controller configured to write data and history information to one of a plurality of blocks. In copying first data that is valid data stored in a copy source block, to a copy destination block, the controller reads the first data and first history information from the copy source block, the first history information being history information corresponding to the first data, and writes the read first data and second history information to the copy destination block. The second history information is based on a value of the read first history information.
A semiconductor storage device includes a first plane and a second plane, a signal line, a determination circuit, and a control unit. The signal line applies voltages to a first word line connected to a first memory cell transistor in a first block of the first plane and a second word line connected to a second memory cell transistor in a second block of the second plane. The determination circuit determines based on a voltage of the signal line whether there is any leakage in the first word line or the second word line. Based on determination results of the determination circuit, the control unit registers the first block as a bad block and registers the second block as a victim block able to be used as a good block.
According to one embodiment, a semiconductor memory device includes an input and output pad group, a memory cell array including a plurality of memory cells, and an input and output circuit provided between the input and output pad group and the memory cell array. The input and output circuit includes a plurality of transistors, and a substrate bias voltage supply circuit that is controllable to supply one of a first voltage having the same value as a power supply voltage of the input and output circuit and a second voltage having a value different from the first voltage as a substrate bias voltage to the plurality of transistors.
The semiconductor testing apparatus according to an embodiment includes a plurality of signal generators that apply a test signal to each of a plurality of IF of a device under test, and a signal generation controller that compiles a signal including basic timing information and pattern information for a test item to be measured into a data signal, and performs timing adjustment of the test signal by setting timing information based on the data signal.
According to some embodiments, provided is a separation system configured to separate a bonded substrate, in which a first substrate and a second substrate are bonded together, into the first substrate and the second substrate. The separation system includes a first chuck configured to hold the first substrate of the bonded substrate. The separation system includes a second chuck configured to hold the second substrate of the bonded substrate and move the second substrate in a first direction away from a plate surface of the first substrate. The separation system includes an adjuster configured to adjust a tilt of the second chuck with respect to a direction perpendicular to a set line set on a holding surface of the second substrate of the second chuck. The separation system includes a controller configured to operate the adjuster to maintain symmetrical progression of the separation relative to the set line.
B32B 43/00 - Operations specially adapted for layered products and not otherwise provided for, e.g. repairingApparatus therefor
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
43.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device includes forming an insulating film on a substrate; forming a recess portion extending toward the substrate from an upper surface of the insulating film; forming a first film on the upper surface of the insulating film and along an inner surface of the recess portion, wherein the first film has hydrophobicity; treating an upper surface of the first film to be hydrophilic; and polishing the first film until the upper surface of the insulating film is exposed.
A memory system is configured to access a host in conformity with a CXL™ (Compute Express Link) interface protocol. The memory system includes: a non-volatile memory; a volatile memory; and a memory controller configured to manage a number of accesses to the non-volatile memory by address and store numbers of accesses in the volatile memory as a histogram. The memory controller includes an update unit configured to, in reception of a command from the host: in a case where a condition is satisfied, skip reading of a number of accesses for a command address designated by the command, and in a case where the predetermined condition is not satisfied, read the number of accesses for the command address, and change the number of accesses for the command address stored in the volatile memory.
According to some embodiments, a memory system includes a nonvolatile memory including a plurality of memory cells. The memory system includes a temperature sensor configured to acquire temperature data through temperature measurement. The memory system includes a buffer configured to store the temperature data; and a memory controller. When the nonvolatile memory executes a first operation in response to a first instruction transmitted from the memory controller, the temperature sensor acquires the temperature data representing a temperature of the nonvolatile memory in the first operation and the buffer stores the temperature data acquired by the temperature sensor as updated data. The nonvolatile memory transmits the temperature data stored in the buffer to the memory controller in response to a second instruction transmitted from the memory controller.
A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first diffusion layer region and a second diffusion layer region; a first gate insulating film and including a portion between the first diffusion layer region and the second diffusion layer region; and a first gate electrode positioned over the first gate insulating film. The second transistor includes: a third diffusion layer region and a fourth diffusion layer region; a second gate insulating film and including a portion between the third diffusion layer region and the fourth diffusion layer region; and a second gate electrode positioned over the second gate insulating film. At least one of the first transistor or the second transistor is formed in a recess portion that has a bottom surface at a position lower than an upper surface of the device isolation portion.
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
A memory system comprises a nonvolatile memory including a plurality of blocks, and a memory controller. The memory controller is configured to track a wear-out degree of each block, and perform a write operation on a certain block in a first write mode of writing a first number of bit per memory cell. The memory controller is configured to, determine, when the wear-out degree of the certain block exceeds a first threshold, whether the nonvolatile memory has a first predetermined size of free space corresponding to the first write mode, and when determining so, invalidate address mapping for a first part of a logical address range and switch a write mode for the certain block from the first write mode to a second write mode of writing a second number of bit per memory cell. The second number is less than the first number.
A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of physical full blocks. Each of the plurality of physical full blocks includes a plurality of physical sub-blocks. The memory controller executes a data erase operation independently for each of the plurality of physical sub-blocks in each of the plurality of physical full blocks, and in each of the plurality of physical full blocks, sets all of the plurality of physical sub-blocks therein to a same storage mode. The storage mode set for a physical sub-block indicates the number of bits of data stored in a memory cell thereof.
A memory system includes an input data acquiring unit, a quantization range determining unit, a parameter setting unit, an estimating unit, and a voltage setting unit. The input data acquiring unit acquires input data indicating a relationship between the number of on-cells and a plurality of read voltages. The quantization range determining unit determines a quantization range of a shift value of the read voltages. The parameter setting unit sets a parameter of a quantized neural network. The estimating unit estimates a shift value of the read voltages from the input data with the quantized neural network using the parameter set by the parameter setting unit. The voltage setting unit sets a read voltage that is used during a read operation of a semiconductor storage device based on the shift value of the read voltages.
According to one embodiment, a semiconductor memory device includes a stacked body in which a plurality of electrode films and a plurality of first insulating films are alternately stacked in a first direction, a columnar body that penetrates the stacked body in the first direction, an aluminum oxide film provided between the columnar body and each of the electrode films, and a first tetravalent metal oxide provided at an interface between the columnar body and the aluminum oxide film.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
A semiconductor memory device includes a plurality of conductive layers arranged in a first direction and extending along a second direction crossing the first direction, a semiconductor column penetrating the conductive layers, a charge storage film between the semiconductor column and the conductive layers, a conductive line extending above the conductive layers in the first direction and electrically connected to the semiconductor column, and a contact electrode penetrating one or more of the conductive layers to contact an upper surface of one of the conductive layers other than said one or more of the conductive layers. The semiconductor column includes a plurality of first portions arranged in the first direction, and a width in the second direction of an upper part of each of the first portions is greater than a width in the second direction of a lower part of said each of the first portions.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
According to the embodiment, two or more memory chips each include first storage areas. First memory chips among the two or more memory chips are connected to two or more channels. The memory controller executes a storage operation of storing first data on a group of second storage areas. Each of the second storage area is one of the first storage areas of each of the first memory chips. In the storage operation, the memory controller generates parity data corresponding to first data. The memory controller stores partial parity data that is part of the parity data in the second storage areas of each of the first memory chips. The memory controller stores both the partial parity data and partial first data that is part of the first data, in a second storage area of each of one or more second memory chips.
According to one embodiment, a method of managing a manufacturing line is provided. The method of managing a manufacturing line includes determining a variation characteristic of a load factor of the manufacturing line that includes multiple resources. The method of managing a manufacturing line includes determining a variation characteristic of a load factor of each of the multiple resources. The method of managing a manufacturing line includes identifying the resource that is to be improved out of the multiple resources in response to the variation characteristic of the load factor of the manufacturing line and the variation characteristic of the load factor of each of the resources.
According to one embodiment, a semiconductor integrated circuit having a first inductive element and a second inductive element is provided. The first inductive element is provided in a first signal line. The second inductive element is provided in a loop arranged apart from the first signal line. The second inductive element is magnetically coupled to the first inductive element. The first signal line has signal terminals arranged at both ends. The loop is configured to be devoid of a signal terminal.
According to one embodiment, a semiconductor circuit includes: a detection unit that detects a first signal waveform of a first input signal on a first communication path and a second signal waveform of a second input signal on a second communication path, which is different from the first communication path; a signal generation unit that generates a control signal based on the detected first and second signal waveforms; and a first driver unit that outputs an output signal corresponding to the first input signal at a driver strength based on the control signal.
According to one embodiment, in a first write operation, a controller transfers first data to be written to a memory device and causes the memory device to store first data into a memory cell array. In a second write operation, the controller transfers second data to be written to the memory device and acquires the second data from a buffer circuit. The controller determines the number of error bits included in the acquired second data. When the number of error bits is larger than a first threshold value, the controller executes a training operation of adjusting delay time of a delay circuit. When the number of error bits is smaller than the first threshold value, the controller causes the memory device to store, into the memory cell array, the second data having been stored in the buffer circuit, without executing the training operation.
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
According to one embodiment, a semiconductor device includes: a first electrode; a second electrode which is in contact with an upper surface of the first electrode; a third electrode provided above the second electrode; an oxide semiconductor which extends in a first direction from the second electrode toward the third electrode; a first conductor provided next to the oxide semiconductor; and a first insulating film provided between the first conductor and the oxide semiconductor, wherein: the first insulating film includes a first region and a second region, the second region being sandwiched between the first region and the oxide semiconductor; and a concentration of nitrogen in the first region is higher than a concentration of nitrogen in the second region.
According to one embodiment, a data compression device includes N data compression circuits each including a dictionary buffer, and a dictionary buffer concatenation control circuit. The dictionary buffer concatenation control circuit controls switching between a first mode in which the N data compression circuits operate independently and a second mode in which the N data compression circuits cooperate. The dictionary buffer concatenation control circuit inputs, in the first mode, mutually different uncompressed data to the N data compression circuits, concatenates, in the second mode, N dictionary buffers by storing oldest dictionary data of an i-th dictionary buffer in an (i+1)-th dictionary buffer, and inputs the same uncompressed data to N data compression circuits.
According to one embodiment, a data decompression device decompresses a compressed data string obtained by dictionary-based compression, the compressed data string including first compressed data having a first offset. A dictionary circuit includes at least one first dictionary storing first decompressed data corresponding to the first compressed data, and at least one second dictionary storing the first decompressed data. An assignment circuit assigns the first compressed data to at least one dictionary of the at least one first dictionary or the at least one second dictionary.
According to one embodiment, a magnetic memory device includes: a first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction and provided above the first wiring; a first memory cell provided between the first wiring and the second wiring; a third wiring extending in the first direction and provided above the second wiring; and a second memory cell provided between the second wiring and the third wiring. The first memory cell includes a first selector body, a first conductor, and a first MTJ body provided on an upper surface of the first conductor. The second memory cell includes a second selector body, a second conductor, and a second MTJ body provided on an upper surface of the second conductor. The upper surface of the first conductor is flattened.
According to one embodiment, a semiconductor memory device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, and a pillar extending in the stacked body in a stacking direction of the stacked body, in which the pillar includes a first semiconductor layer extending in the stacked body in the stacking direction, and a second semiconductor layer that extends in the stacked body in the stacking direction and includes more grain boundaries than grain boundaries of the first semiconductor layer, and an additive having a peak concentration at an interface between the first semiconductor layer and the second semiconductor layer is included.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A memory device according to an embodiment includes a substrate and first and second circuit layers. The first circuit layer includes a CMOS circuit. The second circuit layer includes a memory cell array including a layer stack and pillars. The layer stack includes insulating layers and first conductive layers alternately stacked. The pillars penetrate the layer stack and is connected to a source line. The second circuit layer includes a contact electrically connected to the CMOS circuit. The source line includes a second conductive layer. The second conductive layer has a portion provided to cover an upper portion of the first pillars and has a portion provided to cover an upper portion of the contact. The second conductive layer electrically connects the pillars and the contact. A surface of the second conductive layer is provided in a non-planar shape above at least one of the pillars and the contact.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
According to one embodiment, a memory system includes: a memory device including memory cells for storing data; and a memory controller configured to control an operation of the memory device, wherein the memory device is configured to: acquire, in response to a first read command set, a first determination result of threshold voltages of the memory cells based on a first read level related to a first threshold voltage distribution and a second determination result of threshold voltages of the memory cells based on a first lower-voltage side offset read level, the first lower-voltage side offset read level is obtained by offsetting the first read level to a lower-voltage side, acquire a first number of mismatches between the first determination result and the second determination result, and calculate a first correction amount of the first read level based on the first number of mismatches.
According to one embodiment, a communication method is provided. The communication method includes transmitting a first packet including identification information on a first chip and designation of a first size from a controller to a first bus. The communication method includes enabling first data of the first size to be transferred from the first chip to a second bus in response to the first packet being received by the first chip. The communication method includes releasing the second bus after the transfer of the first data is completed.
An information processing apparatus comprising processing circuitry configured to select analysis target data, select hint data related to a feature to be noted, construct a machine learning model that extracts a first feature included in the analysis target data and a second feature included in the hint data based on the selected analysis target data and the selected hint data, calculate a first index for evaluating the first feature, calculate a second index for evaluating the second feature, and update a weight of the machine learning model based on the first index and the second index.
According to one embodiment, in a semiconductor integrated circuit, a switch is connected between a first power supply and a second power supply. The switch turns off when receiving a first level at a control terminal. A first control circuit includes an input node and an output node. The output node is connected to the control terminal of the switch. A second control circuit includes an output node and an input node. The input node is connected to the control terminal of the switch. The semiconductor integrated circuit satisfies at least one of a condition that drive strength to the first level is greater than drive strength to the second level in the first control circuit and another condition that the drive strength to the second level is greater than the drive strength to the first level in the second control circuit.
According to one embodiment, in a semiconductor memory device, a third conductive film extends in a third direction intersecting a first direction and a second direction within a first semiconductor film. A fourth conductive film is separated from a third conductive film in the first direction. The fourth conductive film extends in the third direction within the first semiconductor film. A fifth conductive film extends in the third direction within the first semiconductor film between the third conductive film and the fourth conductive film. A reference potential is applied to the fifth conductive film. A first memory cell is provided at a position in which a first conductive film faces the first semiconductor film with a first insulating film interposed therebetween. A second memory cell is provided at a position in which a second conductive film faces the first semiconductor film with a second insulating film interposed therebetween.
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
A semiconductor storage device of one embodiment includes a stacked body, a first insulating film, and a second insulating film. In the stacked body, conductive layers are stacked with insulating layers in between. The stacked body has a staircase structure. The first insulating film extends through the stacked body in a terrace region in the staircase structure. The second insulating film is in a step part region of the staircase structure. The second insulating film extends through the stacked body in the stacking direction. The second insulating film has a plane width greater than that of the first insulating film. In some examples, a plurality of first and second insulating films may be provided. In such a case, a disposition density of the second insulating films can be greater than that of the first insulating films.
A magnetic storage device includes a first magnetic layer; a first predetermined element containing layer containing O and containing at least one first predetermined element selected from Sc, Y, Ti, Zr, Hf, Al, Si, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Ho, Dy, Er, Yb, and Lu; a second magnetic layer provided between the first magnetic layer and the first predetermined element containing layer; a second predetermined element containing layer provided between the first predetermined element containing layer and the second magnetic layer, wherein the second predetermined element containing layer substantially contains only at least one second predetermined element selected from P, As, Sb, Bi, S, Se, and Te; and a non-magnetic layer provided between the first magnetic layer and the second magnetic layer.
H01F 10/16 - Thin magnetic films, e.g. of one-domain structure characterised by magnetic layers characterised by the composition being metals or alloys containing cobalt
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
According to one embodiment, an information processing system includes a plurality of memory systems and a storage controller. The storage controller assigns a first identifier and a second identifier to a first write request requesting writing of original data and a second write request requesting writing of mirror data, respectively. A controller of each of the memory systems writes first data to a first write destination block in response to determining that an identifier contained in a write request received from the storage controller is the first identifier, and writes the first data to a second write destination block in response to determining that the identifier contained in the write request is the second identifier.
According to some embodiments, a micro-Raman spectrometer includes a stage configured to hold a sample on a surface of which a fluorescent material is applied. The micro-Raman spectrometer includes a laser optical system configured to irradiate the sample with laser light. The micro-Raman spectrometer includes a Raman scattered light detector configured to detect Raman scattered light emitted from the sample. The micro-Raman spectrometer includes a fluorescence detector configured to detect fluorescence emitted from the fluorescent material. The micro-Raman spectrometer includes an analyzer configured to analyze a Raman signal of the Raman scattered light detector and a fluorescence signal of the fluorescence detector. The micro-Raman spectrometer includes a controller connected to the analyzer and configured to control the stage and the laser optical system.
According to one embodiment, there is provided a semiconductor manufacturing tool that is capable of further facilitating an electrochemical process. The semiconductor manufacturing tool according to the embodiment includes a plurality of process baths, an anode and a cathode, and an electrical circuit. Each of the plurality of process baths is capable of containing a substrate processing liquid and a first substrate. The anode and the cathode are provided for each of the process baths. The electrical circuit electrically connects a plurality of first substrates held in the substrate processing liquid via the anode and the cathode and supplies electrical power via the anode and the cathode for subjecting the plurality of first substrates to an electrochemical process.
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
A semiconductor memory device comprises: conductive layers stacked in a stacking direction; memory cells connected to the conductive layers; a first contact electrode extending in the stacking direction and connected to one of the conductive layers; and a second contact electrode connected to an end portion in the stacking direction of the first contact electrode. The first contact electrode comprises: a first conductive member extending in the stacking direction; an insulating column which extends in the stacking direction and has an outer peripheral surface covered by the first conductive member; and a second conductive member provided in the end portion on a second contact electrode side in the stacking direction of the first contact electrode, has an outer peripheral surface contacting the first conductive member, and has a surface on the second contact electrode side in the stacking direction contacting the second contact electrode.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
There are provided a memory system and an information processing system in which measures against transient errors are implemented. In one example, a memory system includes: a nonvolatile memory chip; and a controller that controls the nonvolatile memory chip. The nonvolatile memory chip has a first storage unit that stores address translation information for translating a logical address into a physical address and management information for the controller managing the nonvolatile memory chip, and a second storage unit that stores, for every first cycle, duplicate information of the address translation information and the management information stored in the first storage unit, and the controller controls whether or not to cause the duplicate information stored in the second storage unit to be exhibited in the first storage unit.
In one embodiment, a dresser includes a substrate. The dresser further includes a first layer provided on the substrate. The dresser further includes at least one convex portion provided on the substrate or the first layer, having an upper end that is higher than an upper face of the first layer, and having a composition that is different from a composition of the first layer. The dresser further includes a second layer provided on the at least one convex portion.
According to one embodiment, a magnetic memory device includes a lower structure, a stacked structure provided on the lower structure, a boron containing layer provided along a side surface of the stacked structure, a metal oxide layer provided between the stacked structure and the boron containing layer. The stacked structure includes a structure in which a basic portion, a lower portion and an upper portion are stacked in a first direction. The basic portion includes a structure in which a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction and a nonmagnetic layer between the first and second magnetic layers are stacked in the first direction.
According to one embodiment, a magnetic memory device includes a magnetoresistance effect element including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a non-magnetic layer provided between the first magnetic layer and the second magnetic layer, and having a structure in which the first magnetic layer, the second magnetic layer, and the non-magnetic layer are stacked, an electrode having an upper surface connected to a lower surface of the magnetoresistance effect element, and a first insulating layer formed of an amphoteric oxide, which surrounds a side surface of the electrode and has an upper surface at a position lower than that of the upper surface of the electrode.
According to one embodiment, a memory device includes first and second wiring lines and a memory cell between the first and second wiring lines. The memory cell includes a main memory portion including a variable resistance memory element and a switching element, a first electrode between the first wiring line and the main memory portion, and a second electrode between the second wiring line and the main memory portion. At least one of the first and second electrodes includes a structure in which first and second main electrode layers and a sub-electrode layer between the first and second main electrode layers are stacked, and a material of the sub-electrode layer has a higher resistivity than those of materials of the first and second main electrode layers.
According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of insulating layers, the electrode layers and the insulating layers being alternately stacked, and a memory film extending in a stacking direction in the stacked body. The memory film includes an oxide film facing the insulating layers, a block insulating film facing the electrode layers and the oxide film, and a charge storage film facing the block insulating film. The block insulating film has a larger thickness at a portion facing each of the insulating layers than at a portion facing each of the electrode layers, and the charge storage film has a smaller thickness at a portion facing each of the insulating layers than at a portion facing each of the electrode layers.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/528 - Layout of the interconnection structure
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
80.
SYSTEM AND METHOD FOR CONFIGURABLE HARDWARE ARCHITECTURE FOR READ OPERATIONS OF A FLASH MEMORY
In some embodiments, a flash memory system may include a non-volatile memory, a controller, a first processor, and a second processor. The first processor may generate a first configuration including a pointer to a first set of predefined configurations among a plurality of predefined configurations. In response to generating the first configuration, the circuit may generate, in a memory, the first set of predefined configurations. The controller may execute a first operation according to the first set of predefined configurations generated in the memory. The second processor may generate a second configuration comprising a pointer to a second set of predefined configurations among the plurality of predefined configurations. In response to generating the second configuration, the controller may generate, in the memory, the second set of predefined configurations. The controller may execute a second operation according to the second set of predefined configurations generated in the memory.
The present disclosure relates to a flash memory system may include a non-volatile memory and a circuit. The non-volatile memory may include one or more blocks, each block including a plurality of rows of cells. The circuit for performing operations on the non-volatile memory, may obtain a row identifier identifying a row of a target page, among the plurality of rows. The circuit may generate, by a machine learning model, one or more voltage thresholds for a read operation, based on the row identifier. The circuit may perform the read operation on the target page of the non-volatile memory with the one or more voltage thresholds.
A plasma processing device comprises: a plasma generating chamber which is connected to a raw material supplier and generates a plasma of a raw material supplied from the raw material supplier; a plasma processing chamber which is adjacent to the plasma generating chamber and has a substrate placed therein; and a filter which is disposed between the plasma generating chamber and the plasma processing chamber, and allows a part of particles included in the generated plasma to pass therethrough, the filter is formed with holes ranging over the plasma generating chamber and the plasma processing chamber, and the filter comprises a heater that heats the holes.
A first insulator is located in a first direction from the first substrate. A first conductor is in the first insulator. A second substrate is located more in the first direction than the first insulator. A first well region has a first conductivity type, is provided in the second substrate, and has a first impurity concentration. A first impurity region has the first conductivity type, is in contact with the first well region in the second substrate at a position located more in the second direction than the first well region, and has a second impurity concentration that is 4 times to 1×108 times the first impurity concentration. A second well region has a second conductivity type and is in contact with the first impurity region in the second substrate at a position located more in the second direction than the first impurity region.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
84.
MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM
According to one embodiment, a system includes: a memory device including word lines and memory cells connected to word lines; and a memory controller, the memory controller acquires first data related to threshold voltages of selected cells connected to a selected word line among the word lines, acquires second data from first adjacent cells connected to a first adjacent word line adjacent to one end of the selected word line, acquires first correction data by correcting the first data based on the second data, acquires third data from second adjacent cells connected to a second adjacent word line adjacent to another end of the selected word line, acquires second correction data by correcting the first correction data based on the third data, and executes soft bit decoding processing on the second correction data to generate read data from the selected cells.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
According to some embodiments, a grinding head configured to grind a grinding target, the head includes a wheel including a rotating front surface and a plurality of grindstones arranged in an annular shape on the rotating front surface with a rotation axis of the rotating front surface as a center. Each of the plurality of grindstones includes a first surface configured to be in contact with the grinding target and a second surface inclined at an acute angle with respect to a traveling direction of the grindstone from the rotating front surface to the first surface.
B24B 7/22 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfacesAccessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
B24D 7/06 - Bonded abrasive wheels, or wheels with inserted abrasive blocks, designed for acting otherwise than only by their periphery, e.g. by the front faceBushings or mountings therefor with inserted abrasive blocks, e.g. segmental
A memory system according to one embodiment includes a memory system includes a memory device, a memory controller, a power supply circuit, and a power storage device. The memory controller controls the memory device. The power supply circuit generates power for driving the memory device and the memory controller based on power supplied from an external power supply, and supplies the generated power to the memory device and the memory controller. The power storage device stores electric energy and to supply the electric energy to the memory device and the memory controller through the power supply circuit in a case where power supply from the external power supply is stopped. The memory controller applies one of first and second write modes having different power consumption to a write operation for the memory device according to a power storage capacity of the power storage device.
A semiconductor device includes gate electrodes that extend in a first direction and are separated from each other in a second direction intersecting the first direction, bit electrodes that extend in the second direction above the gate electrodes and are separated from each other in the first direction, oxide semiconductors that extend along a third direction intersecting the first and second directions, penetrate the gate electrodes, and are electrically connected to the gate electrodes and the bit electrodes, and gate insulating films each surrounding a corresponding one of the oxide semiconductors. Within an intersection region in which one of the gate electrodes overlaps one of the bit electrodes in the third direction, said one of the gate electrodes opposes one of the oxide semiconductors across the gate insulating film. A cross-section of each of the oxide semiconductors taken along the first and second directions has an oval shape.
According to a modulo arithmetic device of one embodiment, a first intermediate value is acquired by shifting right a dividend by a shift amount w correlated with a bit length of a divisor. The shift amount w takes a value not more than the bit length of the divisor. A second intermediate value is acquired by multiplying the first intermediate value by a value m. A third intermediate value is acquired by shifting right the second intermediate value by a shift amount (2k−w). The parameter k takes a value equal to or larger than the bit length of the divisor. A fourth intermediate value is acquired by multiplying the third intermediate value by the divisor. A fifth intermediate value is acquired by subtracting the fourth intermediate value from the dividend. A remainder is acquired by subtracting a value n-times the divisor from the fifth intermediate value.
G06F 7/72 - Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radixComputing devices using combinations of denominational and non-denominational quantity representations using residue arithmetic
A storage device includes a memory cell array and a peripheral circuit, wherein a first circuit of the peripheral circuit includes a first transistor, a second transistor, a trench, a first insulating layer, and a second insulating layer. The first transistor is connected to a first word line via first and fourth connecting electrodes, and the second transistor is connected to a second word line via second and fifth connecting electrodes. The trench is arranged in a first semiconductor layer between the first and second transistors, the first insulating layer is formed in the trench, the second circuit is connected to a bit line via third and sixth connecting electrodes, and the second insulating layer is in contact with the first insulating layer at an end portion on a side further from a memory cell array.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
G11C 16/26 - Sensing or reading circuitsData output circuits
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
90.
DATABASE MANAGEMENT SYSTEM AND METHOD FOR EXECUTING QUERY PROCESSING TO DATABASE
A database management system includes a processor and a memory, wherein the processor is configured to calculate features of each of a first node and a second node of a directed graph, calculate the feature of the first node by inputting the feature of the second node to be input to the first node to a first neural network that is dependent on an input order of the first node, and calculate the feature of the second node by inputting the feature of the first node to be input to the second node to a second neural network that is not dependent on an input order of the second node.
A memory system includes a non-volatile memory having a plurality of blocks, and a memory controller. The memory controller is configured to set one of writing modes including a first mode of writing a single bit of data per memory cell and a second mode of writing multi bits of data per memory cell as a data writing mode for each of one or more blocks, upon receiving information indicating a size of write data to be written into the non-volatile memory from a host device, determine whether the size exceeds a size of a first free space of the non-volatile memory usable for data writing in the first writing mode, and upon determining that the size of the write data exceeds the size of the first free space, write at least a part of the write data into the non-volatile memory in the second writing mode.
According to embodiments, a memory system includes a data management circuit, a memory, a write control circuit, and a data determination circuit. The data management circuit manages data, which is received from a host on a first data size basis, on a second data size basis. The second data size is greater than the first data size. The data determination circuit determines whether or not data of the second data size received by the write control circuit matches a data pattern set in advance. In a case where first data received by the write control circuit matches the data pattern, the data management circuit sets a flag indicating that the first data matches the data pattern in an entry of a management table corresponding to the first data, and the write control circuit discards the first data without writing the first data to the memory.
A memory system includes a plurality of memory cells and a controller. The controller is configured to acquire a data set corresponding to a distribution of threshold voltages of the plurality of memory cells by reading the plurality of memory cells using a reference read voltage; select one from a plurality of acquisition operations of acquiring an actual read voltage for reading data stored in the plurality of memory cells based on the data set, wherein the plurality of acquisition operations include a first acquisition operation of acquiring the actual read voltage from the data set using a first trained machine learning model and a second acquisition operation different from the first acquisition operation; and acquire the actual read voltage using the selected acquisition operation and read the plurality of memory cells using the acquired actual read voltage.
A semiconductor storage device includes an oxide semiconductor that extends in a first direction, an insulating film on a side surface of the oxide semiconductor, a gate electrode that faces the insulating film, a first electrode that includes a first conductor which contains a first oxide conductive material and is connected to an upper end of the oxide semiconductor, a second electrode that extends in the first direction and includes a second conductor containing a second oxide conductive material and connected to a lower end of the oxide semiconductor, a dielectric layer on an outer peripheral surface of the second electrode, and a third electrode on an outer peripheral surface of the dielectric layer. The second conductor has a first surface that faces an inner peripheral surface of the third electrode with the dielectric layer interposed therebetween.
A semiconductor device includes a first electrode, a first insulating layer on the electrode, a gate electrode on the first layer, a second insulating layer on the gate electrode, a second electrode on the second layer, a channel layer extending in a first direction between the first and second electrodes and penetrating the first layer, the gate electrode, and the second layer, one end of the channel layer connected to the first electrode, and the other end of the channel layer connected to the second electrode, and a gate insulating layer between the channel layer and the gate electrode. In the first insulating layer, a width of the channel layer in a second direction intersecting the first direction varies discontinuously in the first direction and the width of the channel layer surrounded by the gate electrode is less than the width of the channel layer contacting the first electrode.
A semiconductor memory device includes: a plurality of first conductive layers arranged in a first direction and extending in a second direction intersecting with the first direction and a third direction intersecting with the first direction and the second direction; and a memory structure extending in the first direction, the memory structure including a first semiconductor layer opposed to the plurality of first conductive layers and a gate insulating layer disposed between the first semiconductor layer and the plurality of first conductive layers. The first semiconductor layer contains single-crystallized silicon and an impurity. The impurity contain: a first metallic element that is able to form silicide; and a second metallic element constituting a metal material having a linear expansion coefficient larger than a linear expansion coefficient of a silicon material.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/00 - Details of semiconductor or other solid state devices
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10D 62/60 - Impurity distributions or concentrations
97.
SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor storage device according to one embodiment has a first multi-layered body, a second multi-layered body, a source line, a first columnar part, a second columnar part, a first bit line, and a second bit line. The source line is between the first multi-layered body and the second multi-layered body in a first direction. The first columnar part extends in the first direction within the first multi-layered body. The second columnar part extends in the first direction within the second multi-layered body. The first bit line is on a side of the first multi-layered body opposite to the source line.
A semiconductor storage device according to one embodiment has a first multi-layered body, a second multi-layered body, a source line, a first columnar part, a second columnar part, a first bit line, and a second bit line. The source line is between the first multi-layered body and the second multi-layered body in a first direction. The first columnar part extends in the first direction within the first multi-layered body. The second columnar part extends in the first direction within the second multi-layered body. The first bit line is on a side of the first multi-layered body opposite to the source line.
The second bit line is on a side of the second multi-layered body opposite to the source line.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
First and second inverters between first and second nodes respectively includes a third transistor coupled to a third node and a fifth transistor coupled to a fourth node. A sixth transistor is coupled between the fifth transistor and the third node. A seventh transistor is coupled between the third transistor and the fourth node. An eighth transistor is coupled to the third transistor and the third node. A ninth transistor is coupled to the fifth transistor and the fourth node. A voltage at gates of the sixth and seventh transistors is lowered at a first time. A voltage at gates of the eighth and ninth transistors is lowered. The voltage at the gates of the sixth and seventh transistors is raised after the first time and before a state of first and second voltages applied to the first and second nodes is formed.
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
99.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate, a first transistor on the semiconductor substrate, an insulating layer above the semiconductor substrate in a first direction, a semiconductor layer provided on the insulating layer and partially overlapping the semiconductor substrate and the insulating layer in the first direction, a second transistor on the semiconductor layer, a first contact penetrating the insulating layer in the first direction such that the first contact is not in contact with the semiconductor layer, a second contact extending parallel to the first contact, and a memory cell array provided above the insulating layer and electrically connected to the second transistor through the second contact.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
An imprint device includes a template having a pattern to be transferred to a resin material disposed on a processing substrate or a dummy substrate, and a control unit that performs first imprint processing in which the template is pressed against an uncured first resin material disposed on one shot region of the processing substrate to transfer the pattern to the first resin material, and second imprint processing in which the template is pressed against an uncured second resin material disposed on the dummy substrate. The control unit performs the second imprint processing after the first imprint processing performed on a first shot region and before the first imprint processing performed on a second shot region, wherein the first imprint processing is to be performed on the first shot region and the second shot region in successive order.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
B29C 43/14 - Compression moulding, i.e. applying external pressure to flow the moulding materialApparatus therefor of articles of definite length, i.e. discrete articles in several steps
B29L 31/34 - Electrical apparatus, e.g. sparking plugs or parts thereof
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
