The application relates to DL workload sharding on heterogeneous devices and provides a method for heterogeneous sharding of a DL workload. The method may include: converting, based on device information about a plurality of heterogeneous devices, a SD graph representing the DL workload into a MD graph including a plurality of sub-graphs that respectively represent a plurality of DL sub-workloads to be assigned to DL stages on the plurality of heterogeneous devices for completing the DL workload; and assigning the plurality of sub-graphs to respective DL stages on the plurality of heterogeneous devices.
This disclosure describes systems, methods, and devices related to enhanced quality of service signaling in wireless communications. A device may generate a capabilities element indicating support for end-to-end (E2E) quality of service (QoS) provisioning; transmit a management frame including the capabilities element; identify a stream classification service (SCS) request from a first station (STA) to establish an E2E QoS flow between the first STA and a second STA; identify traffic for the E2E QoS flow using a traffic classification (TCLAS) element of classifier type 0 included within the SCS request; identify QoS parameters in the SCS request as applying to an entire path between the first STA and the second STA rather than applying to a single medium access control (MAC) hop; and initiate an SCS setup with the second STA to complete the E2E QoS provisioning.
Systems and methods are provided for a hybrid image processing system that integrates latent diffusion model outputs into a hardware ISP pipeline through floating latent space projection operators. The system includes a latent projector that maps ISP image data into the latent space of a diffusion model, a latent merge block that combines the projected image representation with the diffusion model's output in the latent space, and a latent deprojector that converts the merged representation back to the image domain. The latent projector and deprojector are compact convolutional neural networks trained to approximate the variational autoencoder encoder and decoder of the diffusion model. Real-time operation is enabled through latent-domain computation, temporal subsampling of the diffusion model with latent-space interpolation, and static background masking. The system enables incorporation of AI-generated content into live video with high fidelity and temporal coherence.
An apparatus and method for shader thread optimizations. For example, a graphics processing apparatus comprises: one or more graphics processing cores to execute hull shaders to configure tessellation operations to be performed on one or more input meshes; tessellation circuitry to tessellate the one or more input meshes to generate a plurality of minimally tessellated patches and a plurality of non-minimally tessellated patches according to a tessellation function; and domain shader circuitry to buffer domain points corresponding one or more of the minimally tessellated patches until a sufficient number of domain points are buffered to maximize or improve utilization on the one or more graphics cores.
Integrated circuit structures having deep via bars and flyover structures are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires over a second vertical stack of horizontal nanowires. A gate structure is over the first vertical stack of horizontal nanowires and the second vertical stack of horizontal nanowires. A conductive via bar is laterally adjacent to the first vertical stack of horizontal nanowires and the second vertical stack of horizontal nanowires. A conductive link is laterally adjacent to and in contact with the gate structure, the conductive link extending over and isolated from the conductive via bar.
The application relates to a memory access adaptive self-attention mechanism for a Transformer model. A method may include: estimating first execution time of selecting a number k of dominant data elements from an initial self-attention input matrix for a Transformer model to generate a sparse self-attention input matrix; estimating second execution time of performing a self-attention operation for the Transformer model based on the sparse self-attention input matrix; estimating third execution time of performing the self-attention operation based on the initial self-attention input matrix; and performing the self-attention operation based on the first execution time, the second execution time and the third execution time.
This disclosure describes systems, methods, and devices related to resource unit tone allocations. A device may identify null tones and first direct current tones of a bandwidth, the bandwidth including resource units of tones; generate, using the null tones and the first direct current tones, data tones for a 26-tone resource unit, pilot tones for the 26-tone resource unit, and second direct current tones for the 26-tone resource unit; cause transmission, to a second wireless device, of a first frame including an indication that the 26-tone resource unit is allocated to the second wireless device; and identify a second frame received from the second wireless device using the 26-tone resource unit.
The disclosure is directed to systems and methods for multicast and broadcast services (MBS) for a wireless network including transmitting to a user equipment (UE) a signaling configuration for reception by the UE of multicast and broadcast services (MBS) in a low quality of service (QoS) multicast or broadcast delivery using an multicast control channel (MCCH) carried over a physical downlink shared channel (PDSCH) scheduled by a downlink control information (DCI) holding a cyclic redundancy check (CRC) scrambled with a dedicated radio network temporary identifier (RNTI) identifying the low QoS or broadcast reception capability of the UE. The method includes monitoring by the UE a physical downlink control channel (PDCCH) cell specific search space (CSS) configured for MBS for the DCI scheduling, the PDSCH carrying the MCCH in the DCI. The PDCCH CSS is configured for a CORESET #0 for the UE in RRC_CONNECTED/IDLE mode, the monitoring in Type0 PDCCH CSS or Type0A PDCCH CSS configured as part of a PDCCH-ConfigCommon configuration.
H04W 72/1273 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows of downlink data flows
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04W 72/231 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the layers above the physical layer, e.g. RRC or MAC-CE signalling
H04W 76/20 - Manipulation of established connections
H04W 76/40 - Connection management for selective distribution or broadcast
9.
AFFIXED CABLE GUIDANCE STRUCTURE FOR EGRESS OF CO-PACKAGED SILICON PHOTONICS OPTICAL FIBER
Embodiments disclosed herein include an apparatus that includes a substrate with an optoelectrical module coupled to the substrate, and an optical interface coupled to the optoelectrical module. In an embodiment, a frame is provided around the substrate, where the frame is coupled to the substrate, and where the frame comprises a first guide ramp. In an embodiment, a clip coupled to the frame, where the clip comprises a second guide ramp. In an embodiment, an optical fiber is coupled to the optical interface, where the optical fiber passes within a gap between the first guide ramp and the second guide ramp.
Techniques are provided herein to form an integrated circuit having backside conductive contacts beneath gate structures. Backside cavities beneath the gate structures are formed using backside lithography and anisotropic etching. The backside cavities are subsequently filled with a conductive material to form the backside contacts. A semiconductor device includes a gate structure around or otherwise on a semiconductor region that extends from a first source or drain region to a second source or drain region. The substrate beneath the semiconductor device is removed from the backside to expose a subfin region that is also removed using a backside etch and replaced with a dielectric material. Suitable lithographic operations may be performed on the backside dielectric material along with an anisotropic etch to form any number of cavities through the dielectric material. The backside conductive contacts are then formed within the backside cavities.
H01L 23/528 - Layout of the interconnection structure
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
11.
INTEGRATED CIRCUITS WITH THERMAL MANAGEMENT LAYER ADJACENT TO BOND LAYER FOR IMPROVED HEAT DISSIPATION
Techniques are provided herein to form semiconductor dies (or integrated circuits) with a thermally conductive layer adjacent to a bond interface to enhance the thermal dissipation from the semiconductor devices. A semiconductor die or integrated circuit includes any number of semiconductor devices within a device layer. A frontside interconnect region is provided above the device layer to, for example, route signals between the various semiconductor devices in the device layer. A thermally conductive layer may be provided above the frontside interconnect region, such as on a top-most layer of the frontside interconnect region. The thermally conductive layer includes a material having a thermal conductivity of, for example, at least 1.5 W/m·K. A bond layer may be provided adjacent (e.g., directly above or directly below) the thermally conductive layer and may be any suitable dielectric material, such as silicon dioxide.
Structures having memory with backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. One of the metal layers includes an array of uninterrupted signal lines. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a ground metal line.
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
A computer-readable storage medium stores instructions for execution by one or more processors of a UE to configure the UE for carrier phase positioning and to cause the UE to decode a first DE PRS from a first transmission point (TP). A first DE RSCP is determined based on the first DE PRS. A second DE PRS from a second TP is decoded. A second DE RSCP is deter mined based on the second DE PRS. A DE RSCPD is determined based on the first DE PRS and the second DE PRS. The DE RSCPD is encoded for transmission in a measurement report together with a first legacy measurement based on the first DE PRS and the second DE PRS.
An apparatus and system are described for a new synchronization raster for 5th generation (5G) channel bandwidths less than 5 MHz. The raster is used to scan frequencies to acquire a Synchronization System Block (SSB). A guard band (GB) of 142.5 kHz is based on a 15 resource block (RB) channel bandwidth. A small and large step size of the raster is 50 kHz and at most 600 kHz, respectively, and a Synchronization System (SS) block reference frequency position is given by: N*600 kHz+M*50 kHz, N is an integer, Mϵ{1, 3, 5}. The SSB is at most 2 RBs less than the channel bandwidth in RB. A Global Synchronization Channel Number (GSCN) is given by 3N+(M−3)/2+26638.
The application relates to session-based recommendation. A method for session-based recommendation may include: generating a similarity graph comprising a plurality of nodes and one or more edges, each node corresponding to an individual session and an edge being generated to connect two nodes in the similarity graph, wherein a similarity score of a pair of sessions corresponding to the two nodes exceeds a preset similarity threshold; and loading the similarity graph into a Graph Neural Network (GNN) for the session-based recommendation.
Examples described herein relate to a network interface device. In some examples, packet processing circuitry in the network interface device is to receive a first packet and based on the first packet being associated with an identifier for which an entry is not present in a look-up table accessible to the packet processing circuitry, the packet processing circuitry is to provide the identifier for the first packet and an action for the identifier of the first packet and cause the first packet to configure a second look-up-table accessible to the packet processing circuitry with the action for the identifier.
Examples described herein relate to a network interface device comprising circuitry to receive an access request with a target logical block address (LBA) and based on a target media of the access request storing at least one object, translate the target LBA to an address and access content in the target media based on the address. In some examples, translate the target LBA to an address includes access a translation entry that maps the LBA to one or more of: a physical address or a virtual address. In some examples, translate the target LBA to an address comprises: request a software defined storage (SDS) stack to provide a translation of the LBA to one or more of: a physical address or a virtual address and store the translation into a mapping table for access by the circuitry. In some examples, at least one entry that maps the LBA to one or more of: a physical address or a virtual address is received before receipt of an access request.
This disclosure describes systems, methods, and devices related to optimized bandwidth operation. A device may determine supported bandwidth modes for operation in a first frequency band, the supported bandwidth modes including a plurality of bandwidths of at least 160 MHz. The device may indicate the supported bandwidth modes by transmitting a capability signaling structure during an association procedure. The device may negotiate a multi-link association with a second device by exchanging bandwidth mode capabilities for at least one link in the first frequency band. The device may manage an operating bandwidth mode for communications with the second device based on a second frequency band.
Integrated cells may perform matrix multiplication (MatMul) operations. An integrated cell may include a random-access memory (RAM) cell, dot product unit(s), multiplexer(s), adder, route-in unit, control unit, and vector machine. The RAM cell may store weights and activations. The dot product unit(s) may compute dot products from the weights and activations. The adder may accumulate the dot products. The route-in unit may facilitate data transfer from the RAM cell to the dot product unit(s) or data transfer from another integrated cell to the integrated cell. The control unit may manage memory operations and detect and repair errors in memory operations. The vector machine may provide instructions to the dot product unit(s) and multiplexers to direct the flow of multiply-accumulate operations. Counters may be used to control weight fetching from RAM cells. A MatMul operation may be decomposed, and the integrated cells may perform the MatMul operation through multiple clock cycles.
G06F 5/10 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
20.
III-N TRANSISTORS WITH FEATURES FOR IMPROVED PERFORMANCE
Disclosed herein are IC structures with III-N transistors and features designed to enhance their performance, as well as packages, assemblies, and devices incorporating such IC structures. One such feature includes providing an oxide-nitride-oxide-nitride stack over the channel region of a III-N transistor. Another such feature is providing field plates extending from source and drain regions of a III-N transistor. Yet another feature is fabricating a III-N transistor with a curved gate. Still another feature is providing III-N transistors separated from one another by isolation structures with nitride liners.
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/86 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of Schottky-barrier gate FETs
21.
SWITCHED CAPACITOR VOLTAGE REGULATORS EMPLOYING III-N TRANSISTORS
Disclosed herein are IC structures with SCVRs employing III-N transistors, as well as associated packages, assemblies, and devices. In one aspect, an IC structure may include a plurality of pairs of III-N transistors, the plurality of pairs including a first pair including a first III-N transistor and a second III-N transistor, and a second pair including a first III-N transistor and a second III-N transistor; a first isolation structure between the first and second III-N transistors of the first pair; and a second isolation structure between the first and second III-N transistors of the second pair in which: the first III-N transistor of the first pair and the first III-N transistor of the second pair are in-phase transistors of an SCVR, and the second III-N transistor of the first pair and the second III-N transistor of the second pair are out-of-phase transistors of the SCVR.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
22.
INTEGRATED CIRCUIT STRUCTURES WITH III-N TRANSISTORS AND BACKSIDE VIAS
Disclosed herein are IC structures with III-N transistors and backside vias and associated packages, assemblies, and devices. In one example, an IC structure may include a substrate having a first side and a second side; a semiconductor material over the first side of the substrate, the semiconductor material including gallium and nitrogen; a first conductive backside via; and a second conductive backside via, in which: the first and the second conductive backside vias extend from the second side of the substrate to the first side of the substrate and into the semiconductor material, and a distance between the second side of the substrate and an end of the first conductive backside via in the semiconductor material is different from a distance between the second side of the substrate and an end of the second conductive backside via in the semiconductor material.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
23.
ENERGY SUPPLY- AND DEMAND-BASED CONFIGURATION AND OPERATION OF ELECTRIC VEHICLES
Disclosed herein are devices, methods, and systems for configuring a vehicle according to energy requirements of a supply of energy (e.g., an electric grid). An energy configuration system may determine an energy plan for a vehicle based on energy requirements about a supply of electricity to which the vehicle is capable of dispensing electrical charge, wherein the energy plan includes plans for dispensing electrical charge from the vehicle to the supply and/or for withdrawing electrical charge from the supply. The energy configuration system may then generate movement instructions for the vehicle based on the energy plan.
Systems, apparatus, articles of manufacture, and methods to enable attachment of surface mounting technology (SMT) components of different sizes to an underlying substrate are disclosed. An example apparatus includes a circuit board; a first pad on the circuit board, the first pad to be electrically coupled to a first terminal of a surface mounting technology (SMT) component, the first pad having a first edge and a second edge opposite the first edge, the first edge shorter than the second edge; and a second pad on the circuit board, the second pad to be electrically coupled to a second terminal of the SMT component, the second pad having a third edge and a fourth edge opposite the third edge, the third edge shorter than the fourth edge.
Systems, methods, and apparatuses to detect reordering issues are described. In some examples, a system comprises a first Peripheral Component Interconnect Express (PCIe) device to transmit transaction layer packets (TLPs) and integrity and data encryption sync (IDE_SYNC) messages to a second PCIe device; and the second PCIe device to receive the TLPs and IDE_SYNC messages, wherein the second PCIe device is to perform at least one of a detection of a TLP reordering by a PCIe fabric based at least in part on when an IDE_SYNC message is received and/or a detection of an TLP ordering error when a TLP is received before a IDE_SYNC message that preceded it.
This disclosure describes systems, methods, and devices related to internet of things (IoT) onboarding. A device may initiate the device with an internet of things (IoT) IoT provisioning profile. The device may identify an advertisement of openroaming framework received from an IoT deployment site access network. The device may initiate association and authentication with the IoT deployment site access network using information included in the IoT provisioning profile. The device may perform extensive authentication protocol (EAP) using the IoT provisioning profile. The device may identify a network access granted message from the IoT deployment site access network.
H04L 41/0806 - Configuration setting for initial configuration or provisioning, e.g. plug-and-play
H04L 61/4511 - Network directoriesName-to-address mapping using standardised directoriesNetwork directoriesName-to-address mapping using standardised directory access protocols using domain name system [DNS]
27.
TIME-DOMAIN RESOURCE ALLOCATION FOR TRANSPORT BLOCK OVER MULTIPLE SLOT (TBOMS) TRANSMISSIONS
Various embodiments are directed to time-domain resource allocation for transport block over multiple slot (TBoMS) transmissions. An apparatus may comprise: memory to store configuration information that includes a shared time domain resource allocation (TDRA) list associated with transport block over multiple slot (TBoMS) processing; and processing circuitry, coupled with the memory, to: retrieve the configuration information from the memory, wherein the TDRA list includes an entry having an indication of a scheduling delay (k2) and number of slots (N) for a TBoMS transmission; and encode a message for transmission to a user equipment (UE) that includes the configuration information. Other embodiments may be disclosed or claimed.
State space model (SSM) neural network operations can be executed efficiently on neural network accelerators by mapping sequential aggregation operations to data-parallel hardware. For cumulative sum operations, the neural network accelerator can perform matrix-to-matrix multiplication with a lower-triangular mask to achieve the same result. For reduce sum operations, the neural network accelerator can perform matrix-to-vector multiplication with a vector mask to achieve the same result. These mappings exploit the parallelism in the neural network accelerators, reduce memory traffic, and leverage sparsity compression and compute skipping for efficiency. Additionally, activation functions can be accelerated using programmable look-up tables during the drain phase. The approach achieves significant latency and energy improvements without hardware changes, enabling high performance deployment of SSM-based models on resource-constrained neural network accelerators.
An integrated circuit (IC) device may implement a deep neural network (DNN). The IC device may be a three-dimensional (3D) integrated system that includes a memory die and logic die. The memory die may include memory blocks, such as sequential random-access memory blocks or a sequential read-only memory blocks. The logic die may include an interface unit, a vector operation unit, compute units (e.g., multiply-accumulate units), and an interconnect fabric with adders. The interface unit may receive the input of the DNN and transfer the input to the vector operation unit. The vector operation unit may perform one or more vector operations of the DNN based on the input. The compute units and adders may perform matrix multiplication operations of the DNN based on the vector operation unit's output. Each memory block may be coupled with a compute unit through a via.
Techniques and mechanisms for optically coupling photonic wire bond (PWB) structures each to a respective optical fiber core of a plurality of multi-core fibers. In one embodiment, multiple PWBs are fabricated by a three-dimensional (3D) printing process which facilitates efficient alignment of the multiple PWBs with a fiber array unit or other device which comprises, or accommodates coupling to, the plurality of multi-core fibers. Such efficient alignment enables the multi-core fibers to be arranged in a two-dimensional (2D) array. In other embodiments, the 3D printing process comprises a two-photon polymerization process.
Methods and apparatus for package level hybrid electromagnetic interference (EMI) shields are disclosed. A disclosed example shield for a die package includes a first shield portion defining a first section of a perimeter of the EMI shield, the first shield portion including a first EMI absorbing material with a first characteristic, and a second shield portion defining a second section of the perimeter, the second shield portion including a second EMI absorbing material with a second characteristic different from the first characteristic, the first and second shield portions to be electrically coupled to a ground plane of the die package when the EMI shield is coupled to the die package.
H01L 23/552 - Protection against radiation, e.g. light
H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups or
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H01L 23/367 - Cooling facilitated by shape of device
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
32.
INTEGRATED PACKET DELAY/PACKET LOSS PERFORMANCE MEASUREMENTS
An apparatus and system for generating performance measurements related to integrated user plane packet delay for a next generation radio access network (NG-RAN) and downlink (DE) packet loss on a Uu interface between the NG-RAN and a user equipment (UE). Measurements include individual distributions of uplink (UL) packet delays that include the DI UL Packet Data Convergence Protocol (PDCP) delay in the UE and that exclude the DI UL PDCP delay. Additional measurements include the average DL delay and the average UL delay between the NG-RAN and the UE that includes and that excludes the DI UL PDCP delay.
Embodiments attempt to solve challenges in a wireless communications system, such as a cellular system. Embodiments describe various techniques, systems, and devices to support multi-path relay operations for user equipment (UE), such as remote UE and relay UE, as well as base stations such as gNodeB (gNB), in a Third Generation Partnership Project (3GPP) Fifth Generation (5G) New Radio (NR) or Sixth Generation (6G) systems, among other wireless communications systems. Other embodiments are described and claimed.
Systems, apparatuses, methods, and computer-readable media are provided for a user equipment (UE) to know whether a network supports UE route selection policy (URSP) provisioning in an evolved packet system (EPS). For example, a UE may receive an indication of a capability of a session management function (SMF) and/or a packet data network (PDN) gateway-control plane function (PGW-C) to support UE route selection policy (URSP) provisioning in an EPS extended Protocol Configuration Options (ePCO). The UE may send a request for a bearer resource modification based on the indication. The request may include a UE policy container. Other embodiments may be described and claimed.
H04W 40/22 - Communication route or path selection, e.g. power-based or shortest path routing using selective relaying for reaching a BTS [Base Transceiver Station] or an access point
H04W 8/22 - Processing or transfer of terminal data, e.g. status or physical capabilities
H04W 76/20 - Manipulation of established connections
35.
MULTI-CONNECTIVITY GRAPH SEGMENTATION METHOD FOR COMPILERS
To improve execution performance of neural network models on hardware accelerators, one or more changes to the compiler can be made to generating fully static schedules for neural network models. By partitioning the processing graph into subgraphs, where adjacent subgraphs use disjoint subsets of hardware barriers and multiple boundary task nodes are allowed for a boundary separating adjacent subgraphs, the compiler can correct execution order and conflict-free reuse of hardware barriers with little impact to the original schedule layout. Moreover, the compiler can insert management operations, such as barrier reprogramming and direct task submission, within the schedule itself. Doing so can eliminate the need for runtime software or firmware to manage execution, reducing latency and enabling better performance.
Various embodiments herein provide techniques for multiple physical random access channel (PRACH) transmissions for coverage enhancement. For example, embodiments may relate to PRACH window determination for multiple PRACH transmissions. In one example, the PRACH repetition window is determined in accordance with a number of consecutive valid PRACH occasions associated with a synchronization signal block (SSB). Other embodiments may be described and claimed.
Examples described herein relate to a network interface device that includes circuitry to decide packet format of a packet including data to be transmitted based on network utilized to transmit the packet and circuitry to form the packet based on the decided packet format. In some examples, the network utilized to transmit the packet is based on an egress port of the packet. In some examples, the network utilized to transmit the packet comprises one or more of: direct interconnect, small scale-up network, or large scale-out network. In some examples, to decide packet format, the circuitry is to form the packet byte by byte to reduce overhead caused by preamble and number of header fields.
H04L 67/02 - Protocols based on web technology, e.g. hypertext transfer protocol [HTTP]
H04L 69/321 - Interlayer communication protocols or service data unit [SDU] definitionsInterfaces between layers
H04L 69/324 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
H04L 69/325 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the network layer [OSI layer 3], e.g. X.25
38.
HIGH PERFORMANCE MICROELECTRONIC ASSEMBLIES INCLUDING THROUGH-SILICON VIA BRIDGES WITH TOP DIE LAST APPROACH
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer including first dies in a first insulating material; a second layer on the first layer, the second layer including second dies and third dies in a second insulating material, the second dies having a first thickness, the third dies having a second thickness different than the first thickness, and the second dies and the third dies having a surface, wherein the surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways through the RDL, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways through the RDL and by interconnects.
Techniques for vector database lookups and/or inference are described. An example of a system includes memory of a first type to store one or more of a machine learning model including at least a proper subset of a key-value (KV) cache and weights, a machine learning model memory manager, and/or a vector database search module; and memory of a second type to store one or more of at least a proper subset of the KV cache and weights of the machine learning model and/or the vector database, wherein the machine learning model memory manager is to determine and implement a memory split between the memory of the first type and the memory of the second type for the KV cache and weights of the machine learning model and the vector database search module is to perform an opportunistic, out-of-order vector database lookup upon receiving a vector database request.
Various embodiments herein are directed to the request of Msg3 physical uplink shared channel (PUSCH) repetitions. In order to improve coverage, repetition is supported for Msg3 PUSCH during the 4-step RACH procedure. In this case, either separate PRACH occasions or shared PRACH occasions with separate PRACH preambles may be configured to differentiate the enhanced UE that requests the Msg3 PUSCH repetition and legacy UEs that do not.
Wafer level electron beam prober systems, devices, and techniques, are described herein related to providing wafer level testing for fabricated device structures. Such wafer level testing contacts a first side of a die of a wafer with a probe to provide test signals to the die under test and performs e-beam imaging of the first side of the die while the test signals are provided to the die under test.
Methods, apparatuses, and computer readable media for critical update overhead reduction, where an access point (AP) is configured to: determine that first updated parameters for the first AP and second updated parameters for a second AP are same updated parameters, and encode, a frame for transmission, the frame comprising an element, the element comprising the first updated parameters for the first AP, and the frame comprising an indication that the first updated parameters are also for the second AP.
Described herein are capacitor devices formed using perovskite insulators. In one example, a perovskite templating material is formed over an electrode, and a perovskite insulator layer is grown over the templating material. The templating material improves the crystal structure and electrical properties in the perovskite insulator layer. One or both electrodes may be ruthenium. In another example, a perovskite insulator layer is formed between two layers of indium tin oxide (ITO), with the ITO layers forming the capacitor electrodes.
Methods, apparatus, systems and articles of manufacture are disclosed to monitor and manage usage of resources on a computing platform. An example apparatus includes a processor and a subsystem. The example processor includes a modified operating system, the operating system modified to monitor application execution via the processor to determine a usage scenario for the apparatus. The example processor includes an index generator to generate a system usage scenario index quantifying a snapshot of the usage scenario for the processor and the subsystem of the apparatus. The example processor includes a rebalancer to reallocate resources of at least one of the processor or the subsystem based on the system usage scenario index.
An apparatus can include universal serial bus type C (USB-C) connection circuitry. The apparatus can also include input/output (I/O) circuitry coupled to the USB-C connection circuitry. The I/O circuitry can receive a power signal over the USB-C connection circuitry. The apparatus can include baseband circuitry to initiate wireless wide area network (WWAN) communication responsive to receiving a wake signal from the I/O circuitry. The WWAN communication can include messages received from the USB-C connection circuitry. Other apparatuses, systems, and methods are described.
Disclosed herein are IC structures with nanoribbon transistors and backside capacitors, and related methods and devices. In one aspect, an IC structure includes a nanoribbon including a semiconductor material and a transistor including a channel portion and first and second source/drain (S/D) regions, wherein the channel portion includes a portion of the semiconductor material of the nanoribbon and has a front side and a back side, and the first and second S/D regions are at the opposite ends of the channel portion. The IC structure further includes a contact structure in conductive contact with the first S/D region and a capacitor in conductive contact with the second S/D region, wherein the contact structure is at the front side of the channel portion and the capacitor is at the back side of the channel portion.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A user equipment (UE) is configured for operation in a New Radio (NR) network. The UE comprises front-end circuitry coupled to one or more antennas and processing circuitry coupled to the front-end circuitry. The processing circuitry is to decode network signaling that configures measurement operations for one or more serving cells, including at least one deactivated secondary cell, and that indicates synchronization signal block parameters. The processing circuitry is to monitor for synchronization signal occasions associated with a serving cell during a measurement interval determined based on the network signaling. The processing circuitry performs radio resource management measurements for the serving cell based on monitored synchronization signal occasions and allocates measurement resources according to a carrier-specific scaling factor that biases measurement processing among serving cells. The processing circuitry encodes a measurement report for transmission to a base station, based on radio resource management measurements.
An IC device comprises a composite die structure that includes a base layer of comprising bulk silicon and a first chiplet integral with the base layer. The first chiplet includes first interconnects in first interconnect layers. A second chiplet is bonded to the base layer and horizontally adjacent to the first chiplet. The second chiplet includes second interconnects in second interconnect layers. A first dielectric material is between the first and second chiplets. Third interconnect layers extend over both the first and second interconnect layers. The third interconnect layers include third interconnects and a surface comprising conductive contacts opposite the base layer of the composite die structure. The third interconnects are coupled with the first interconnects, the second interconnects, and the conductive contacts. The third interconnect layers comprise a second dielectric material different from the first dielectric material.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
49.
METHODS OF FORMING DISAGGREGATED SILICON PACKAGES WITH DIRECT RDL-LESS BLOCK ASSEMBLY
Microelectronic integrated circuit package structures include a package structure comprising two or more first integrated circuit (IC) dies directly on and electrically coupled to a substrate. A bridge die is adjacent to the two or more first IC dies and directly on the substrate. A second IC die is directly on the bridge die and on at least one of the two or more first IC dies, and a third IC die is directly on the bridge die, adjacent to the second IC die. A mold material at least partially surrounds the two or more first IC dies and the second and third IC dies.
This disclosure describes systems, methods, and devices related to network efficiency optimization. For example, a device may receive a first cell discontinuous transmission (DTX)/discontinuous reception (DRX) configuration and a second cell DTX/DRX configuration while in a radio resource control (RRC) connected mode. The device may perform a transmission and reception based on the first cell DTX/DRX configuration. The device may receive a downlink control information (DCI) indication to switch to the second cell DTX/DRX configuration/rules associated with a base station cell DTX/DRX mode transition. The device may perform a transmission and reception based on the second cell DTX/DRX configuration. The device may postpone operations based on the first cell DTX/DRX configuration.
H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling
51.
METHODS AND ARRANGEMENTS FOR LOW-POWER WAKE-UP SIGNALING
Logic may generate or decode a low-power wake-up signal (LP-WUS) received via the interface, the LP-WUS comprising wake-up signal (WUS) symbols, the WUS symbols modulated with an on-off keying (OOK) modulation or a frequency shift keying (FSK) modulation, the LP-WUS comprising information to perform at least one low-power wake-up radio (LP-WUR) function via a LP-WUR of the UE while a main radio of the UE is powered off, wherein the LP-WUR function comprises measurement of at least part of the LP-WUS. And logic may determine at least one metric based on the measurement or cause transmission of the LP-WUS.
Various approaches for the deployment and coordination of network operation processing, compute processing, and inter-satellite communication coordination, within one or multiple satellite non-terrestrial networks, are discussed. Among other examples, a data center located at one or more satellites operating in a middle Earth orbit (MEO) plane, geosynchronous orbit (GEO) plane, or high-Earth elliptical orbit (HEO) plane, may be used to provide network and data processing operations for a low-Earth orbit (LEO) constellation.
An apparatus including: a USB Type-C interface comprising a plurality of signal pins; and an audio bus controller coupled to the USB Type-C interface, wherein the audio bus controller is configured to: transmit and receive signals according to an audio bus protocol on at least one signal pair of the plurality of signal pins to communicate with an audio bus device coupled to the USB Type-C interface.
A memory device includes: a memory array configured to store data, and a control circuit coupled to the memory array and configured to, in response to a read operation targeting data for which a read-once indicator associated with the data stored in the memory array is set: output the data, and render the data unavailable for a subsequent read operation.
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
55.
SOURCE-SIDE SYNCHRONIZATION OF FRAME UPDATES FOR DISPLAYS
Systems and methods for source-side variable refresh rate (VRR) synchronization for organic light-emitting diode (OLED) displays are described. A processor may determine a number of emission cycles since a previous frame update based on emission cycle information of a display. The processor may determine a time delay based on the number of emission cycles and may provide a next frame to the display based on the time delay to align the next frame with an emission cycle boundary of the display. The time delay may be determined based on whether the number of emission cycles is an integer and whether the number of emission cycles is less than a number of emission cycles per frame. Source-side synchronization may enable VRR operation on OLED displays without requiring frame buffer hardware in the display timing controller.
G09G 3/3283 - Details of drivers for data electrodes in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
56.
METHODS AND APPARATUS TO CONNECT INTERCONNECT BRIDGES TO PACKAGE SUBSTRATES
Methods and apparatus to connect interconnect bridges to package substrates are disclosed. An example package substrate includes a dielectric layer including a cavity, a first contact pad positioned in the cavity, a first semiconductor die including a second contact pad and a third contact pad, the second contact pad positioned on a first surface of the first semiconductor die, the third contact pad positioned on a second surface of the first semiconductor die, the second surface opposite the first surface, the second contact pad coupled to the first contact pad, the third contact pad to be coupled to a second semiconductor die, and a non-conductive material surrounding the first contact pad and the second contact pad.
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways and by interconnects.
A port is used to couple to another device over an interconnect, where the port generates a request to change a link width of a bidirectional link and includes a first link direction to send data to the other device and a second link direction to receive data from the other device. The port sends the request to the other device over the interconnect and sends a signal on a subset of lanes of the link in the first link direction in association with the request to change the link width of the link, where the subset of lanes are to be added to or subtracted from the link width of the link based on the request.
Embodiments herein may relate to a die for use in a multi-die package. The die may include clock circuitry that is able to identify a phase of a data signal to be transmitted and a phase of a clock signal to be transmitted on a die-to-die (D2D) link. The clock circuitry may further be configured adjust the phase of the clock signal such that the phase of the clock signal is approximately 90 degrees from the phase of the data signal such that the clock signal and the data signal are received by a receiver die of the D2D link with a 90 degree phase difference. Other embodiments may be described and claimed.
Techniques for decompression and sparsity decoding are described. Examples detailed herein utilize a matrix data micro-engine invoked by an instruction and configured using a descriptor. The matrix data micro-engine pulls in data from memory (e.g., in a stream of blocks) and processes this data to make it ready for computational hardware. This effectively decouples the memory access patterns from the compute cadence. The use of the descriptor allows for complex, multi-stage data transformations (e.g., INT4 to FP16 conversion, 2:4 sparsity expansion, and layout transposition) to occur strictly within the hardware data path (stream decompressor and sparsity mask decoder) without polluting the instruction cache with decompression code or burdening the main CPU pipeline.
This disclosure describes systems, methods, and devices related to multiplexing uplink transmissions. A user equipment (UE) device may detect a first set of beta offset indices associated with multiplexing high priority uplink control information (UCI) into a physical uplink shared control channel (PUSCH); detect a second set of beta offset indices associated multiplexing low priority UCI into the PUSCH; detect downlink control information (DCI) using a physical downlink control channel (PDCCH) which schedules the PUSCH; determine, based on the first set of beta offset indices and the second set of beta offset indices, that UE device is to multiplex the high priority UCI with the low priority UCI into the PUSCH; and encode, based on the second set of beta offset indices, a multiplexed uplink transmission for transmission to the 5G network device using the PUSCH, the multiplexed uplink transmission comprising the high priority UCI and the low priority UCI.
A Universal Serial Bus 4 (USB4) host system for tunneling USB2 data includes a USB controller and a first routing circuit communicatively coupled to the USB controller. The first routing circuit is to configure a downstream tunneled path between the USB controller and a second routing circuit. The first routing circuit is further to packetize outgoing USB2 data received from the USB controller into a first plurality of USB4 tunneled packets. The first routing circuit is further to encode the first plurality of USB4 tunneled packets for transmission to the second routing circuit via the downstream tunneled path, to initiate processing of the outgoing USB2 data by a USB2 device associated with the second routing circuit.
A low-temperature solder (LTS) cap on solder bumps on a substrate and/or solder bumps on a die may improve head-and-pillow open defects. In some examples, the LTS cap melts earlier than the substrate-side or die-side solder during a TCB process, creating a capillary bridge of molten LTS between the die-side solder and substrate-side solder. In one such example, the molten LTS capillary bridge connecting the die-side and substrate-side bumps may improve the heat transfer to the substrate-side solder and significantly reduce or eliminate head-and-pillow open defects.
Techniques and mechanisms for facilitating secure communications in a trusted execution environment (TEE). In an embodiment, one of a root complex or an input-output device provides functionality to register a message tag as being at least temporarily unavailable for use in any communication via a protected channel. In an embodiment, tag registry is based on a timeout of a completion message which was expected to include, or otherwise correspond to, the tag in question. A registered tag is unavailable for use at least until the completion timeout has been determined to have a cause other than a malicious agent. In another embodiment, a TEE security manager (TSM) or a device security manager (DSM) provides functionality to generate an explicit request that an integrity and data encryption (IDE) protected channel be flushed.
G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
65.
USER EQUIPMENT CONFIGURED FOR PERFORMING SIDELINK POSITIONING MEASUREMENTS IN 5G NR NETWORKS
The present disclosure is related to user equipment (UE) behaviors and requirements for sidelink positioning. A target UE receives a sidelink positioning protocol (SLPP) request to measure and report sidelink (SL) positioning measurements. The target UE measures a set of SL positioning reference signals (PRSs) based on the received request, and transmits a measurement report. The measurement report includes positioning results based on the measurement of the set of SL PRSs. Other embodiments may be described and/or claimed.
A system and method for managing Non-Primary Channel Access (NPCA) misalignment and Network Allocation Vector (NAV) in wireless local area networks (WLANs) are disclosed. A wireless device detects overlapping basic service set (OBSS) activity on a primary channel, switch to a non-primary channel, and maintain a backoff counter without reset. NPCA operations include PPDU-based and TxOP-based mechanisms, where the device receives frames with duration fields, encodes synchronization data, and transmits control frames initiating transmission opportunities with NPCA maximum TxOP duration in designated fields. NAV management is performed by processing preamble information from received physical layer protocol data units (PPDUs) to determine network parameter configurations and adjust device operation.
Methods, apparatuses, and computer readable media for dynamic unavailability operation in wireless local area networks (WLANS), where a non-access point (AP) station (STA) (non-AP STA) is configured to: encode, in accordance with a first communications standard, a first frame to an access point (AP), the first frame indicating an unavailability time of the non-AP STA for communications with the AP, decode, in accordance with the first communications standard, a second frame from an access point (AP), the second frame comprising a channel usage element, the channel usage element comprising a usage mode and channel entry, the usage mode indicating a second communications standard, and the channel entry indicating a channel in accordance with the first communications standard, and encode, in accordance with the second communications standard, a third frame for transmission within the channel and during the unavailability time.
Integrated circuit structures having uniform grid metal gate and trench contact cut with pyramidal channel structures are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires having a pyramidal profile with a pyramid angle. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The dielectric cut plug structure has a re-entrant profile with a cut angle laterally spaced apart from the pyramid angle of the pyramidal profile of the vertical stack of horizontal nanowires.
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
Block-level quantization parameter (QP) adaptation involves assigning different QPs to different regions within a frame. A block-level QP adaptation technique computes a spatial correlation metric using the minimum sum-square difference (SSD) between the current block and candidate neighbor blocks. Blocks highly similar to their spatial neighbors are preserved at high quality by assigning a lower QP, while blocks with little correlation to their neighbors can be encoded more aggressively by assigning a higher QP. Another limitation arises where a lower QP may produce both higher distortion and a higher bit rate simultaneously. To detect this phenomenon, the number of transform coefficients whose magnitude exceeds the current quantizer step size is counted. When the count exceeds a threshold, the block is classified as a qualified block. For qualified blocks, an adaptive QP search is conducted within a bounded range to refine the block's QP.
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
70.
ARTIFICIAL INTELLIGENCE (AI) CPU PROCESSING WITH SELF-DIRECTED APPLICATION CLUSTER DEPLOYMENTS
Various aspects of configuring and executing artificial intelligence (AI) computing operations on a central processing unit (CPU) with self-directed application deployment at an edge device are described. In an example, an edge computing system improves AI model inferencing within mixed-generation or mixed-capability CPU clusters (e.g., server nodes) by dynamically reassigning tasks based on real-time instruction-usage patterns. High-performance AI nodes can be tagged to ensure deterministic and high-quality inferencing, improving performance on nodes with native AI acceleration capabilities. By binding inference tasks to nodes with AI extensions and distributing other service pods across available nodes, the disclosed approach enhances AI processing throughput while supporting diverse hardware configurations, including CPUs with varying AI inference capabilities (e.g., CPUs that include Advanced Matrix Extensions (AMX) tiles or similar hardware blocks).
Embodiments disclosed herein include die modules and methods of making die modules. In an embodiment, a die module comprises a first die with a set of first pads with surfaces that are substantially coplanar with a surface of a first dielectric layer. In an embodiment, the die module further comprises a second die with a set of second pads with surfaces that are substantially coplanar with a surface of a second dielectric layer. In an embodiment the first pads are bonded to the second pads and the first dielectric layer is bonded to the second dielectric layer.
Example method and apparatus, systems, and articles of manufacture for immersion cooling systems are disclosed herein. An example apparatus disclosed herein includes an inlet to receive coolant from an immersion cooling tank; an outlet to be coupled to the immersion cooling tank; a first flow path extending between the inlet and the outlet; and a second flow path extending between the inlet and the outlet, the first flow path and the second flow path disposed in parallel.
Multi-die bridge assemblies and methods for three-dimensional packaging. The architectures assemble a bridge component with two or more integrated circuit die to thereby create a multi-die (MD) bridge assembly. The means for attaching the bridge component to the dies can be hybrid bonding, solder bumps, thermal compression bonding, or a combination thereof. The created MD bridge assembly can be subjected to performance testing prior to attachment to a substrate. Attaching the MD bridge assembly to the substrate can include fitting the bridge component portion into a cavity in the substrate and attaching the bridge component to a cavity floor with another plurality of attachment options.
A system and method for LLM reinforcement learning with heterogeneous processors. An example system comprises: a first one or more processors to perform large language model (LLM) inference operations based on a current model version and to generate corresponding training data samples; a second one or more processors having a heterogeneous architecture relative to the first one or more processors, the second one or more processors configurable to perform reinforcement learning operations using the corresponding training data samples to update model weights for the current model version; and a weight transfer engine to provide point-to-point communication channels between the first one or more processors and the second one or more processors, the second one or more processors to transmit the model weights over the point-to-point communication channels to the first one or more processors.
A die-to-die (D2D) adapter couples to a protocol layer block using a first interface to couple to a protocol layer block and couples to a physical layer (PHY) block using a second interface. The D2D adapter is to determine parameters of a D2D link to couple a first die to a second die and select, based on the parameters, a particular one of a plurality of different data formats for use on the D2D link. Protocol layer data is received at the D2D adapter over the first interface from the protocol layer block. The D2D adapter passes the protocol layer data over the second interface to the PHY block based on the particular data format.
Apparatus and method for scaled integer 5-bit based FP 4 processing. For example, a method comprises: loading a plurality of source 4-bit floating-point (FP4) data elements in one or more registers; determining pairs of INT5 scalar values, INT5 bases, and INT5 signs corresponding to pairs of the source FP4 data elements; performing decoding of each pair of INT5 scalar values in accordance with a map comprising a reduced set of logic gates configured to map each INT5 scalar value directly to generate a corresponding INT5 scalar result; multiplying each corresponding pair of INT5 bases circuitry to generate a base product; generating a two's complement representation of the base product, the two's complement representation comprising a plurality of result bits; and selecting, by a multiplexor network, a set of the result bits based on the corresponding INT5 scalar result, the set of the result bits comprising a dot-product result.
Described herein are stacked memory devices that include some peripheral devices for controlling the memory in a separate layer from one or more memory arrays. The layers of the memory device are connected together using vias, which transfer power and data between the layers. In some examples, a portion of the peripheral devices are included in a memory layer, and another portion are included in a peripheral device layer. Multiple layers of memory arrays and/or peripheral devices may be included, e.g., one peripheral device layer may control multiple layers of memory arrays, or different layers of memory arrays may have dedicated peripheral device layers. Different types of memory arrays, such as DRAM or SRAM, may be included.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Various embodiments herein provide techniques related to a user equipment (UE). The UE may be configured to identify an indication related to transmission or reception activity of a cell of a cellular network during a non-active duration of the cell that is related to cell discontinuous transmission (DTX) or cell discontinuous reception (DRX). The UE may further be configured to monitor, based on the indication, for receipt of a signal. Other embodiments may be described and/or claimed.
H04L 5/00 - Arrangements affording multiple use of the transmission path
H04W 72/231 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the layers above the physical layer, e.g. RRC or MAC-CE signalling
80.
MODEL OPTIMIZATION IN INFRASTRUCTURE PROCESSING UNIT (IPU)
An Infrastructure Processing Unit (IPU), including: a model optimization processor configured to optimize an artificial intelligence (AI) model for an accelerator managed by the IPU, and deploy the optimized AI model to the accelerator for execution of an inference; and a local memory configured to store data related to the AI model optimization.
Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a P-type conductive layer on a first gate dielectric including a high-k dielectric layer on a first dipole material layer. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the P-type conductive layer on a second gate dielectric including the high-k dielectric layer on a second dipole material layer.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Techniques are provided herein to form semiconductor devices that include a gate cut formed after the formation of source/drain contacts. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region that extends from a source region to a drain region. Conductive contacts formed over the source and drain regions along a source/drain trench. The gate structure may be interrupted with a dielectric gate cut that further extends past the gate trench and into the source/drain trench where it can cut into one or more of the contacts. The contacts are formed before the gate cut to ensure complete fill of conductive material when forming the contacts. Accordingly, a liner structure on the conductive contacts is also broken by the intrusion of the gate cut and does not extend further up or down the sidewalls of the gate cut.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
83.
GATE AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
Gate and fin trim isolation for advanced integrated circuit structure fabrication is described. For example, a method of fabricating an integrated circuit structure includes forming a plurality of fins along a first direction, removing a portion of one of the plurality of fins to form a trench, forming an isolation structure in the trench, the isolation structure extending above the one of the plurality of fins, forming a gate structure over the plurality of fins, the gate structure along a second direction orthogonal to the first direction, forming a dielectric spacer along sidewalls of the gate structure and the isolation structure, and, subsequent to forming the dielectric spacer, forming epitaxial source or drain structures in or on the plurality of fins.
The cross-component sample offset (CCSO) filter is a significant in-loop filtering tool introduced in the AV2 video coding standard. The complexity of deriving frame-level CCSO filtering parameters involving a cascaded, pseudo-brute-force search across many combinations of the CCSO parameters is prohibitive for real-world encoder deployments and hardware implementations. This issue is addressed by introducing a hierarchical decision framework to selectively skip or drastically narrow the parameter search based on lightweight, content-adaptive analysis performed before the search begins. In some examples, frame type and encoded size determine whether to search, reuse reference parameters, or disable CCSO. When searching, sharp edge analysis adaptively restricts the candidate parameter space, thereby reducing search complexity significantly.
H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 19/82 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation involving filtering within a prediction loop
85.
FREQUENCY-DEPENDENT DATA WIDTH NEGOTIATION FOR BACKWARDS-COMPATIBLE LINKS LIKE PCI-EXPRESS AND COMPUTE EXPRESS LINK
This disclosure describes systems, methods, and devices related to optimized link negotiation. A device may negotiate a data rate with an upstream port during a configuration state of a link training and status state machine. The device may receive a capability bit from the upstream port indicating a requirement for bifurcation at the negotiated data rate. The device may activate a first logic stack and a second logic stack to serve the upstream port based on the capability bit. The device may determine a subset of physical lanes to establish a secondary link managed by the second logic stack.
Embodiments herein relate to systems, apparatuses, or processes creating a package that includes a die embedded in a molding, where a surface of the die is coplanar with a surface of the molding. During a stage of package manufacture, the die may have a finished side that may be coupled with a component of the package, and an unfinished side. During a subsequent stage of package manufacture, molding may be placed around the die, and then the molding and at least a portion of the die may be planarized, which may involve grinding and polishing. The planarization may reveal one or more TSV at the side of the die which is now finished and ready for electrical coupling with other components. As a result, a side of the molding at a side of the die to be coplanar. Other embodiments may be described and/or claimed.
Embodiments disclosed herein include package substrates with bridge dies. In an embodiment, an apparatus comprises a first layer that is a glass layer. A via is provided through the first layer, where the via is electrically conductive. In an embodiment, a second layer is over the first layer, and the second layer comprises an organic dielectric material. In an embodiment, a cavity is provided in the second layer, where the via is within a footprint of the cavity. In an embodiment, a die is in the cavity. In an embodiment, the die is electrically coupled to the via.
Methods and apparatus to ensure the security of server partitioning. The method is performed on a multi-socket platform including first and second sockets interconnected by a socket-to-socket interconnect, the multi-socket platform being capable of being configured in a first partition mode with a single partition using both the first and second sockets and a second partition mode under which the first and second sockets are partitioned as respective first and second partitions. Following the platform being operated in the single partition mode, the first socket is rebooted to be operated as local socket in a separate partition under the second partition mode and under which communication over the socket-to-socket interconnect is disabled without using any communication between the first and second sockets. Softstrap and hardware strap partition mode configuration schemes are provided to implement the method on various multi-socket platform architectures.
A device, method, and non-transitory computer-readable medium are provided for communicating using an integrated millimeter wave (IMMW) physical layer convergence protocol data unit (PPDU). Access point circuitry may generate a preamble for IMMW PPDU, including at least a Short Training Field (STF), a Long Training Field (LTF), and a SIG field, wherein the payload content of the SIG field is duplicated at least three times in the frequency domain to occupy a 320 MHz channel, and wherein the SIG field includes pilot signals and modulated signals of encoded SIG payload content; generate a data field for the IMMW PPDU including at least data orthogonal frequency division multiplex (OFDM) symbols, wherein each OFDM symbol includes data subcarriers and pilot subcarriers; and send the IMMW PPDU to one or more station devices (STAs).
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04L 5/00 - Arrangements affording multiple use of the transmission path
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METHODS AND APPARATUS FOR MIPI SOUNDWIRE INTEGRATION
A device including: an upstream-facing port configured to communicate with a host controller via USB signaling; at least one downstream-facing port configured to communicate with one or more audio bus peripheral devices; and processing circuitry configured to: process first audio bus data received via USB transactions through the upstream-facing port; cause the first audio bus data to be forwarded to the one or more audio bus peripheral devices via the audio bus protocol through the at least one downstream-facing port, process second audio bus data received from the one or more audio bus peripheral devices via the audio bus protocol through the at least one downstream-facing port; and cause the second audio bus data to be forwarded to the host controller via USB transactions through the upstream-facing port.
An electronic device, including: a display panel configured to display image frame data received from a source device directly; a remote frame buffer configured to store the image frame data received from the source device; and a display panel controller configured to refresh the image frame data displayed on the display panel with the image frame data stored in the remote frame buffer when changing a display property.
Systems, apparatus, articles of manufacture, and methods are disclosed for document parsing for retrieval-augmented generation. A non-transitory machine readable storage medium comprises instructions to cause programmable circuitry to at least: extract a characteristic of a document to be parsed; generate a prompt for a natural language processing machine learning model engine based on the characteristic, the prompt to provide an instruction for the natural language processing machine learning model engine to parse the document into a plurality of segments based on document context; determine an output of the natural language processing machine learning model engine based on the prompt, the output indicating a segmentation of the document into the plurality of segments; and cause a plurality of embedding vectors for the plurality of segments to be stored in a vector database.
An apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to obtain a first output from a natural language processing machine learning model engine, the first output generated with retrieval augmented generation (RAG) to respond to a user query, obtain a first feedback answer input associated with the user query, generate an embedding of the first feedback answer input and the user query, cause the embedding to be stored in a vector database to provide feedback for the RAG, and obtain a second output from the natural language processing machine learning model engine, the second output generated in response to the user query, the second output to include the first feedback answer input.
Rotary positional embedding (RoPE) execution on some DNN accelerators can be a bottleneck of performance. To address this issue, inefficient operations in RoPE are identified by a compiler and replaced by convolution operators. Executing RoPE can involve performing a reshaping operation, a concatenating operation, and a convolution operation. These operations can be executed efficiently on DNN accelerators optimized to perform convolutions.
For matrix multiplication (MatMul) in large language models, group-wise quantization is used for weight compression, resulting in data quantization on both the output and input channels when converted to convolution on a deep neural network (DNN) accelerator. Unrolling the MatMul into smaller operations with the same input channel scale value (referred to as channel-wise quantization) can lead to significant increase in workload count, while the compute overhead for each workload is small. To address this issue, the MatMul operation is instead performed on a reshaped input matrix and a reshaped weight matrix and unnecessary outputs are discarded. The result still obtains the correct result for MatMul but trade off calculation complexity for workload overhead.
Various examples of the present disclosure relate to a firmware apparatus, firmware device, firmware method and corresponding computer program, to a processor, method for a processor and corresponding computer program, and to a computer program. Some aspects of the present disclosure relate to various examples of the present disclosure relate to a firmware apparatus, firmware device, firmware method and corresponding computer program, to a processor, method for a processor and corresponding computer program, and to a computer program. A firmware apparatus comprises interface circuitry, machine-readable instructions and processing circuitry to execute the machine-readable instructions to provide a first entry point for handling global system interrupts, and to provide a plurality of second entry points for handling hardware partition-specific system interrupts, the plurality of second entry points being based on a plurality of hardware partitions of the computer system.
Various embodiments herein provide techniques related to a sidelink positioning reference signal (SL PRS). In some embodiments, the SL PRS may be multiplexed with information related to one or more other SL channel on resources of a resource pool that is related to SL transmission. The multiplexed SL PRS and information related to the one or more other SL channel may then be transmitted. Other embodiments may be described and/or claimed.
Various embodiments herein provide techniques for a user equipment (UE), that may correspond to an uncrewed aerial vehicle (UAV)) to notify a wireless cellular network of a change in a flight path of the UE. For example, embodiments may relate to triggering conditions that trigger an update in the flight path, and/or how the updated flight path is reported to the network. Other embodiments may be described and claimed.
This disclosure describes systems, methods, and devices for configuring uplink and downlink transmissions in a full duplex system. A Next Generation Node B (gNB) device may configure an uplink frequency resource and a downlink frequency resource within a serving cell or bandwidth part for different symbols; provide a frequency resource configuration, indicative of the uplink frequency resource and the downlink frequency resource, to a user equipment (UE); provide, to the UE, a signal configuration or downlink control information (DCI) scheduling a signal transmission; and identify an uplink transmission from the UE based on the signal configuration and the frequency resource configuration, or provide a downlink transmission to the UE based on the signal configuration and the frequency resource configuration.
The present disclosure is related to wireless communications, cellular networks, and communication system implementations, and in particular, to technologies and techniques for performing low power wake-up signal (LP-WUS) measurements. In particular, the present disclosure describes LP-WUS and wake-up channel structures and designs for LP-WUS based radio resource management (RRM) measurement, radio link monitoring (RLM) measurement, and beam failure detection (BFD) measurement, as well as mechanisms for activation and deactivation of LP-WUS monitoring, and other LP-WUS aspects.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04B 17/309 - Measuring or estimating channel quality parameters
