An apparatus to facilitate a fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising execution circuitry to receive a fused SHA instruction identifying a length corresponding to a data size of the fused SHA instruction and a functional control identifying an operation type of the fused SHA instruction; based on decoding the fused SHA instruction, cause a sub-function identified by the length and the function control to be scheduled to an integer pipeline of the execution resource; and execute the sub-function of the fused SHA instruction in an integer pipeline of the execution circuitry, the sub-function to perform merged operations on a source operand of the fused SHA instruction, the merged operations comprising a rotate operation, a shift operation, and an xor operation.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
Techniques to form semiconductor devices that include subfins that are at least partially amorphized are described. A backside dopant implantation process using dopants (e.g., germanium) may be used to create amorphous semiconductor material in the subfins. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region formed from a fin of semiconductor material. The fin includes a subfin laterally adjacent to a dielectric fill. A backside ion implantation process may be used to implant dopants such as Ge into the subfin and consequently form an amorphized portion of the subfin. In some examples, the amorphized portion is under the gate structure and laterally between a source region and a drain region. The amorphized portion may extend from a bottom surface of the subfin to just under the gate structure, and in some cases, leave a crystalline portion of subfin below the gate structure.
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
Examples described herein relate to a device that includes: a plurality of nodes, wherein a node of the plurality of nodes comprises at least one processor and a structure comprising multiple physical layers, wherein different physical layers of the multiple physical layers are to provide communication entry points to at least some of the same nodes at different node spans by a stack of overlapping two dimensional (2D) meshes. In some examples, a first layer of the multiple layers comprises a first trace that comprises a link that connects a first span of nodes. In some examples, a second layer of the multiple layers comprises a second trace that comprises a link that connects a second span of nodes, where the first span of nodes is greater than the second span of nodes.
Methods, systems and apparatuses may provide for hardware sampler technology that determines mip region dimensions of a feedback map based on a description of the feedback map, identifies accessed texels in a texture based on a view of a resource that is paired with the feedback map, and records the accessed texels in the feedback map based on the mip region dimensions.
Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.
Methods, apparatus, systems, and articles of manufacture are disclosed to partition neural network models for executing at distributed Edge nodes. An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions. One or more of the at least one processor circuit is to partition a neural network model into a first portion to be executed at an edge of a network and a second portion to be executed at a cloud based on a transmission metric.
H04L 41/5054 - Déploiement automatique des services déclenchés par le gestionnaire de service, p. ex. la mise en œuvre du service par configuration automatique des composants réseau
G06N 3/04 - Architecture, p. ex. topologie d'interconnexion
H04L 41/5019 - Pratiques de respect de l’accord du niveau de service
H04L 43/08 - Surveillance ou test en fonction de métriques spécifiques, p. ex. la qualité du service [QoS], la consommation d’énergie ou les paramètres environnementaux
H04L 67/00 - Dispositions ou protocoles de réseau pour la prise en charge de services ou d'applications réseau
H04L 67/10 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau
7.
PROCESS AND AN APPARATUS FOR THE PASSIVATION OF THE BLACK BORDER SIDEWALL ON THE EXTREME ULTRAVIOLET PHOTOMASKS
The present disclosure generally relates to a method that includes providing a photomask, wherein the photomask includes a trench defined by two sidewalls which are exposed, introducing the photomask into a controlled environment, and directing (i) one or more reactive gases, (ii) a laser, (iii) one or more reactive gases and a laser, or (iv) one or more reactive gases and an electron beam, to the two sidewalls to render a passivation layer adjacent to and in contact with each sidewall. An apparatus and the photomask are also described.
B23K 26/08 - Dispositifs comportant un mouvement relatif entre le faisceau laser et la pièce
B23K 26/352 - Travail par rayon laser, p. ex. soudage, découpage ou perçage pour le traitement de surface
G03F 1/22 - Masques ou masques vierges d'imagerie par rayonnement d'une longueur d'onde de 100 nm ou moins, p. ex. masques pour rayons X, masques en extrême ultra violet [EUV]Leur préparation
Integrated cells may perform matrix multiplication (MatMul) operations. An integrated cell may include a random-access memory (RAM) cell, dot product unit(s), multiplexer(s), adder, route-in unit, control unit, and vector machine. The RAM cell may store weights and activations. The dot product unit(s) may compute dot products from the weights and activations. The adder may accumulate the dot products. The route-in unit may facilitate data transfer from the RAM cell to the dot product unit(s) or data transfer from another integrated cell to the integrated cell. The control unit may manage memory operations and detect and repair errors in memory operations. The vector machine may provide instructions to the dot product unit(s) and multiplexers to direct the flow of multiply-accumulate operations. Counters may be used to control weight fetching from RAM cells. A MatMul operation may be decomposed, and the integrated cells may perform the MatMul operation through multiple clock cycles.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06N 3/10 - Interfaces, langages de programmation ou boîtes à outils de développement logiciel, p. ex. pour la simulation de réseaux neuronaux
9.
COMMUNICATION PROTOCOL USING FREE-SPACE CONNECTIVITY
A device may include a first die, including: a data transmission interface configured to inductively transmit and receive signals; a processor configured to generate a transmission asynchronous pattern; receive a response pattern via the data transmission interface indicating whether the transmission asynchronous pattern was received by a second die; control a data transfer between the first die and the second die via the data transmission interface based on the response pattern; and a second die, including: a data transmission interface configured to inductively transmit and receive signals; a processor configured to receive the transmission asynchronous pattern; check whether the received transmission asynchronous pattern is correct; generate a response pattern indicating whether the received transmission asynchronous pattern is correct; control a data transfer between the first die and the second die via the data transmission interface based on the check whether the received transmission asynchronous pattern is correct.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
Three-dimensional gaussian splatting (3DGS) is a powerful technique for three-dimensional reconstruction using multiple input images. Using 3DGS to reconstruct large-scale scenes can utilize large amounts of graphical processing unit (GPU) memory and take a long time to complete. Splitting the large-scale scene into multiple regions and applying 3DGS on multiple GPUs in parallel can reduce memory usage and improve computational time. However, it is not trivial to obtain an integrated model based on the training models produced by the parallel GPUs. To address this technical challenge, the training models are aligned, conflicting gaussian pairs are identified, and properties of the conflicting gaussian pairs are merged during the rendering process. The result is a solution that can execute 3DGS on parallel GPUs and can produce a usable and high fidelity integrated model for three-dimensional reconstruction of a large-scale scene.
Techniques are provided herein to form semiconductor devices that have their semiconductor subfins removed and replaced with one or more dielectric materials. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the semiconductor material includes a subfin adjacent to a dielectric layer that acts as shallow trench isolation (STI) between semiconductor devices. A backside process may be performed to remove the bulk substrate and expose a bottom surface of the subfin. The subfin may then be removed from the backside to form backside recesses. A dielectric liner may be formed within the backside recesses and a dielectric fill may be formed within a remaining volume of the backside recesses. Replacing the subfins with dielectric materials may lower parasitic capacitance between the subfins and the gate electrodes as well as reduce parasitic current between adjacent source or drain regions.
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
12.
LOW POWER 4:1 MULTIPLEXED RANK DUAL INLINE MEMORY MODULES
Disclosed herein is memory device that includes a printed circuit board (PCB) and a plurality of dynamic random-access memory (DRAM) devices arranged on the PCB and logically divided into four pseudo-channels. A shared command/address (C/A) bus of the device is configured to transmit command signals to all four pseudo-channels and a set of multiplexers on the device are controllable to selectively couple data signals between the four pseudo-channels and a memory controller. A control interface of the device is configured to interleave data burst transactions of the data signals across the four pseudo-channels, wherein a burst of the data burst transactions is distributed across two groups, each group comprising two of the four pseudo-channels operating in parallel.
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
Examples described herein relate to adjusting a queue size based on utilization of a device and an artificial intelligence (AI) model trained on at least one or more of: data size, request priority, device congestion, device latency, device interface throughput, network throughput, queue length, queue priority, request receipt rate, number of queues allocated to receive the requests, device memory usage, and/or whether address translation prefetch mode is enabled or not enabled. In some examples, the device includes an accelerator to perform cryptographic and/or compression operations in response to the requests.
Microelectronic assembly architectures including a die stack in which each die includes a redistribution layer, and the die stack is positioned such that the face of each die is perpendicular to a face of a base, are provided. Each die has a first face and a second face opposite the first face, and an edge extending between the first and second faces. A redistribution layer is deposited on the first face of each die. The faces of each die in the die stack are parallel to the faces of the other dies. The die stack is positioned on the base such that the faces of each die are orthogonal to the face of the base. Each die can have a conductive contact on a bottom edge, and the conductive contact can be coupled to the respective redistribution layer on the die and to a conductive contact on the base.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
15.
ADAPTIVE PREDICTION COST ESTIMATION FOR VIDEO ENCODING
Systems and methods for adaptive prediction cost estimation in video encoding are provided. The techniques improve early cost estimation and reduce the number of candidates for the later decision stages and final RDO stage. In particular, an adaptive sum of absolute transformed differences (SATD) is determined for each candidate, and, based on the adaptive SATD values, a subset of candidates is selected for mode decision search to determine block partitioning, motion vectors, and encoding modes, The adaptive SATD combines a weighted DC component of the SATD and the AC component of the SATD. The weighting factor is selected from a DC adjustment ratio table based on the spatial variation and the QP for a respective coding tree unit. The techniques improve cost estimation accuracy, reduce encoding complexity, and are hardware-friendly for integration into video codecs such as HEVC, AV1, VVC, and AV2.
H04N 19/156 - Disponibilité de ressources en matériel ou en calcul, p. ex. codage basé sur des critères d’économie d’énergie
H04N 19/14 - Complexité de l’unité de codage, p. ex. activité ou estimation de présence de contours
H04N 19/169 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif
16.
SYSTEMS AND METHODS FOR PERFORMING INSTRUCTIONS TO CONVERT TO 16-BIT FLOATING-POINT FORMAT
Disclosed embodiments relate to systems and methods for performing instructions to convert to 16-bit floating-point format. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a first source vector comprising N single-precision elements, and a destination vector comprising at least N 16-bit floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the specified source vector to 16-bit floating-point, the conversion to include truncation and rounding, as necessary, and to store each converted element into a corresponding location of the specified destination vector, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode.
Microelectronic assemblies with glass cores with tapered insulator edges, as well as related devices and fabrication techniques, are disclosed. In one aspect, a microelectronic assembly according to an embodiment of the present disclosure may include a glass core (e.g., a layer of glass or a glass structure) having a first face, and an insulator material having a bottom face, a top face opposite the bottom face, and an outer edge extending between the bottom face and the top face. The top bottom face of the insulator material is on the glass core, and the outer edge of the insulator material tapers from a first perimeter at the bottom face to a second perimeter at the top face. The taper of the outer edge results in the first perimeter being larger than the second perimeter.
H01L 23/14 - Supports, p. ex. substrats isolants non amovibles caractérisés par le matériau ou par ses propriétés électriques
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
18.
LID OR STIFFENER ATTACHMENT STRUCTURE WITH A HYBRID ADHESIVE
An embodiment may include an apparatus, that comprises a first substrate and an adhesive layer on the first substrate. In an embodiment, the adhesive layer comprises a first adhesive, where the first adhesive is a polymer that comprises silicon and oxygen, and a second adhesive, where the second adhesive is an epoxy. In an embodiment, the first adhesive is adjacent to the second adhesive. In an embodiment, the apparatus further comprises a second substrate coupled to the first substrate by the adhesive layer.
Techniques are provided herein to form semiconductor devices that include one or more self-aligned gate cuts having a hybrid architecture between adjacent devices. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (also referred to as a channel region). The gate structure may be interrupted between two transistors with a gate cut that extends through at least an entire thickness of the gate structure and includes dielectric material. The gate cut includes a hybrid design that is formed in two parts. A first part of the gate cut is formed prior to any gate patterning and is self-aligned between adjacent fins of semiconductor material. A second part of the gate cut is formed over the first part of the gate cut and is integrated with spacer structures formed on the sidewalls of a sacrificial gate that extends over the adjacent fins.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Conductive vias for 3D integration may be formed during or after assembly to couple dies or die stacks. In one example, such conductive vias may extend through the dies or die stacks and through an interface with conductive bumps, without terminating on the bumps. Bypassing conductive bumps with a conductive via may enable improved performance, power delivery, and thermal management. In one example, an assembly includes a first IC structure (such as a substrate, interposer, or other IC structure) and a second IC structure (such as a die or die stack) over the first IC structure. The assembly includes an interface layer between the first IC structure and the second IC structure, where the interface layer includes a plurality of conductive bumps. A conductive via extends through the interface layer with the bumps and is coupled with a conductive element of the first IC structure.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
In some embodiments, a voltage regulator with circuitry to facilitate DCM to CCM transitions are provided to mitigate against excessive voltage droops.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H02M 1/00 - Détails d'appareils pour transformation
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation avec commande numérique
22.
OVERHANG ARCHITECTURES FOR HIGH BANDWIDTH MEMORY (HBM) MULTI-DIE ASSEMBLIES AND METHODS FOR MAKING SAME
Overhang architectures for high bandwidth memory (HBM) multi-die assemblies and methods for making same. The overhang architecture places the DRAM (HBM) underneath the top IC die. The signal interconnects between the top IC die and the DRAM die are direct signal interconnects without lateral routing on a package substrate or on a motherboard.
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
23.
SEQUENTIALLY CLEARING SUBSETS OF PREDICTION STATE OF PROCESSORS WHILE CONTINUING TO PROCESS INSTRUCTIONS
A method of an aspect includes processing instructions with a processor, making predictions associated with some of the instructions based on prediction state, clearing a plurality of subsets of the prediction state sequentially, and continuing the processing of the instructions while the plurality of the subsets of the prediction state are being cleared. Other methods, processors, and systems are also disclosed.
Examples include techniques associated with mapping system memory physical addresses to isolation domains for uniform memory access (UMA) by a system. Examples include mapping separate system memory physical addresses ranges associated with memory devices communicatively coupled with at least one compute die of the system through an input/output (I/O) die of the system. The separate system memory physical addresses to be mapped to isolation domains and address decoder information is generated to indicate the mapping of the separate system memory physical address ranges to the isolation domains.
G06F 21/54 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
25.
PORT SELECTION FOR HARDWARE QUEUING MANAGEMENT DEVICE
In an embodiment, a processor may include multiple processing engines and multiple hardware queue manager (HQM) devices. Each HQM device is to queue data requests for a different subset of the plurality of processing engines. At least one processing engine is to execute a first set of instructions to: detect a first enqueue instruction to enqueue data in a first HQM device of the plurality of HQM devices; in response to a detection of the first enqueue instruction, perform a look-up of the first HQM device in a data structure to determine a recommended port for the first HQM device; and transmit the first enqueue instruction using the recommended port for the first HQM device.
An apparatus to facilitate hardware support for n-dimensional matrix load and store instructions is disclosed. The apparatus includes a graphics processor comprising a general-purpose graphics execution resources, the general-purpose graphics execution resources including a matrix accelerator, the matrix accelerator configured to perform a matrix operation on a plurality of tensors stored in a memory; and circuitry configured to facilitate access to the memory by the general-purpose graphics execution resources, wherein the circuitry is configured to: receive a request to access a tensor of the plurality of tensors; and generate a n-dimensional block access message along a dimension of n>2 of the tensor, the n-dimensional block access message to enable access to the tensor by the matrix accelerator, wherein the n-dimensional block access message comprises an application programming interface (API) descriptor defining a tensor width, tensor pitch, tensor block offset, and a tensor block size of the tensor.
A host device comprising first circuitry to receive one or more packets sent by a communication device over a serial communication interface between the communication device and the host device, wherein the one or more packets comprise media configuration information stored in a memory of the communication device and an indication of a mapping of the memory of the communication device; and second circuitry to transmit data packets over the serial communication interface after the host device has been configured based on the media configuration information.
A mechanism is described for facilitating training and deploying of pose regression in neural networks in autonomous machines. A method, as described herein, includes facilitating capturing, by an image capturing device of a computing device, one or more images of one or more objects, where the one or more images include one or more training images associated with a neural network. The method may further include continuously estimating, in real-time, a present orientation of the computing device, where estimating includes continuously detecting a real-time view field as viewed by the image capturing device and based on one or more images. The method may further include applying pose regression relating to the image capturing device using the real-time view field.
A deep neural network (DNN) accelerator may execute in-place deep learning operations. The DNN accelerator may write an input tensor of a DNN layer into a memory that includes a plurality of memory entries storing input elements in the input tensor. The DNN accelerator may compute an output tensor of the layer using the input tensor and another tensor, e.g., by performing multiply-accumulate operations on the input tensor and the other tensor. The DNN accelerator may use a scatter map to write the output tensor into the memory and generate a gather map to be used for reading the output tensor in the next layer. The DNN accelerator may remove an input element from a memory entry and store an output element in the memory entry. The position of the input element in the input tensor may be different from the position of the output element in the output tensor.
An apparatus of a communication device, the apparatus may include: an interface configured to transmit a sensing signal and receive a reflected sensing signal; and a processor configured to: determine a sensing signal configuration of a further communication device;
estimate a sensing interference of the further communication device based on the sensing signal configuration; and perform an interference cancellation on the reflected sensing signal using the sensing interference.
H04W 72/541 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de qualité en utilisant le niveau d’interférence
An apparatus including an interface configured to receive first sensor data representative of a monitoring of an environment according to a first modality and second sensor data representative of a monitoring of the environment according to a second modality; and a processor configured to provide the first sensor data to an input of a first trained generative model configured to generate first output data comprising a first extracted feature of the first sensor data in a latent space; provide the second sensor data to an input of a second trained generative model configured to generate second output data comprising a second extracted feature of the second sensor data in the latent space; and combine the first output data and the second output data to generate a combined feature.
A microelectronic assembly with a bridge die and through-assembly conductive vias may enable higher performance connectivity of dies or die stacks. In one example, an assembly includes a first IC structure (e.g., a bridge die) over and coupled with a circuit board, a second IC structure (e.g., a substrate) over the first IC structure, and a plurality of coplanar dies or die stacks between and bonded with the first IC structure and the second IC structure. Conductive vias may be formed through the dies or die stacks after attaching the dies or die stacks to the first or second IC structures, where a conductive via through a die or die stack may extend through the die or die stack so that a first portion of the conductive via is coplanar with the side or face of the die or die stack that is bonded with the first IC structure.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
Microelectronic assemblies may include through-assembly conductive vias of varying depth to couple dies or die stacks with one another via a bridge die and/or substrate. In one example, an assembly includes an interconnect structure (e.g., a bridge die) including conductive contacts on a first side and one or more integrated circuit (IC) structures bonded with a second side, where an IC structure includes one or more dies. The assembly may include a first conductive via with a first bottom end in the interconnect structure and a first top end opposite the first bottom end, and a second conductive via with a second bottom end in the interconnect structure and a second top end opposite the second bottom end, where the first top end is in a first plane and the second top end is in a second plane that is different from the first plane.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Back-end-of-line (BEOL) interconnect fuses are described. In an example, an integrated circuit structure includes a first dielectric layer having first conductive lines therein. A second dielectric layer is over the first dielectric layer and has first conductive vias and second conductive lines therein. One of the second conductive lines is a fuse element. A third dielectric layer is over the second dielectric layer and has second conductive vias and third conductive lines therein. The second dielectric layer has a lower dielectric constant than the first dielectric layer and than the third dielectric layer, or the second dielectric layer has a lower thermal conductivity than the first dielectric layer and than the third dielectric layer, or both.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
35.
STACKED SEMICONDUCTOR DIE ARCHITECTURE WITH DIES STACKED ORTHOGONAL TO A BASE DIE OR SUBSTRATE
Microelectronic assemblies with a die stack positioned such that a face of each die in the stack is orthogonal to a face of a base are disclosed. Each die has a first face and a second face opposite the first face. The die stack includes multiple dies, with the faces of each die parallel to the faces of the other dies in the die stack. The die stack is positioned on the base such that the faces of each die are substantially orthogonal to the face of the base. Each die in the die stack can have a corresponding conductive contact, and the conductive contact on each die in the die stack can be coupled to a conductive contact on the base via an interconnect. The interconnect can be a solder joint, such as a solder bump or solder ball.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
36.
PROVIDING BYTECODE-LEVEL PARALLELISM IN A PROCESSOR USING CONCURRENT INTERVAL EXECUTION
In one embodiment, an apparatus comprises: a first plurality of registers to store information of at least a main sequence; a second plurality of registers to store information of at least one concurrent interval, the at least one concurrent interval independent of the main sequence, where the second plurality of registers are accessible only by instructions of the at least one concurrent interval and the first plurality of registers are accessible by instructions of the main sequence and the at least one concurrent interval; and an execution circuit coupled to the first register file and the second register file, the execution circuit to execute the instructions of the main sequence and the at least one concurrent interval. Other embodiments are described and claimed.
An apparatus and method are described for performing an early depth test on graphics data. For example, one embodiment of a graphics processing apparatus comprises: early depth test circuitry to perform an early depth test on blocks of pixels to determine whether all pixels in the block of pixels can be resolved by the early depth test; a plurality of execution circuits to execute pixel shading operations on the blocks of pixels; and a scheduler circuit to schedule the blocks of pixels for the pixel shading operations, the scheduler circuit to prioritize the blocks of pixels in accordance with the determination as to whether all pixels in the block of pixels can be resolved by the early depth test.
H04N 13/279 - Générateurs de signaux d’images à partir de modèles 3D d’objets, p. ex. des signaux d’images stéréoscopiques générés par ordinateur les positions des points de vue virtuels étant choisies par les spectateurs ou déterminées par suivi
H04N 13/344 - Affichage pour le visionnement à l’aide de lunettes spéciales ou de visiocasques avec des visiocasques portant des affichages gauche et droit
H04N 13/383 - Suivi des spectateurs pour le suivi du regard, c.-à-d. avec détection de l’axe de vision des yeux du spectateur
Methods, apparatus, systems and articles of manufacture to identify a video decoding error are disclosed. An example apparatus includes an atlas generator to generate atlas data for one or more atlases generated from input views of video; a hash generator to: perform a hash operation on the atlas data to generate a hash value; and include the hash value in a message; and a multiplexer to combine the one or more atlases, coded atlas data corresponding to the atlas data, and the message to generate a video bitstream.
H04N 19/65 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant la tolérance aux erreurs
H04N 19/597 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage prédictif spécialement adapté pour l’encodage de séquences vidéo multi-vues
Examples described herein relate to a network interface device comprising a host interface; a direct memory access (DMA) circuitry; a network interface; and circuitry to: based on at least partial processing of packets by a transmit packet processing pipeline, perform reordering of the packets based on associated egress time stamps, wherein the partial processing of the packets by the transmit packet processing pipeline comprises at least packet parsing and provide the packets for egress from a port based on the associated egress time stamps.
Examples described herein relate to: an interface and circuitry to: monitor a bus for a particular message and based on detection of the particular message, replace the particular message with an invalid portion and provide the invalid portion to a receiver, wherein the particular message comprises a command and wherein the receiver comprises an Embedded Multi-Media Card (eMMC). In some examples, the circuitry comprises a platform root of trust (PRoT), a management controller, a multiplexer, or a host system.
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p. ex. les dispositifs connectés à un bus ou les dispositifs en ligne
G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
41.
INTEGRATED MEMORY AND COMPUTE SYSTEM FOR OPTIMIZED NEURAL NETWORK COMPUTATION
An integrated circuit (IC) device may implement a deep neural network (DNN). The IC device may be a three-dimensional (3D) integrated system that includes a memory die and logic die. The memory die may include memory blocks, such as sequential random-access memory blocks or a sequential read-only memory blocks. The logic die may include an interface unit, a vector operation unit, compute units (e.g., multiply-accumulate units), and an interconnect fabric with adders. The interface unit may receive the input of the DNN and transfer the input to the vector operation unit. The vector operation unit may perform one or more vector operations of the DNN based on the input. The compute units and adders may perform matrix multiplication operations of the DNN based on the vector operation unit's output. Each memory block may be coupled with a compute unit through a via.
A deep neural network (DNN) accelerator may include one or more multi-precision converters for precision conversion during DNN execution. A multi-precision converter may include an input extractor for extracting an exponent and mantissa from an input value, an input generator for generating an intermediate exponent and an intermediate mantissa from the extracted exponent and the extracted mantissa, a group of exponent converts for converting the intermediate exponent to exponents of different input or output precisions, an exponent selector for selecting one of the exponent converters for a particular input or output precision, a group of mantissa converters for converting the intermediate mantissa to mantissas of different input or output precisions, a mantissa selector for selecting one of the mantissa converter for a particular input or output precision. An output value is generated from the exponent generated in the selected exponent converter and the mantissa generated in the selected mantissa converter.
G06F 7/556 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul de fonctions logarithmiques ou exponentielles
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06F 7/552 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul de puissances ou racines
G06F 7/48 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
43.
EMBEDDING A STATE SPACE MODEL ON MODELS-ON-SILICON HARDWARE ARCHITECTURE
A state space model with selective updates, also referred to as a Mamba-based block, in a Mamba-based model can be embedded onto a silicon chip. Specialized hardware modules in a models-on-silicon chip, such as an optimized selective scan unit and an optimized 1D convolution unit, can perform the operations of the selective state space model of the Mamba-based model. These modules individually and collectively enhance processing speed, power efficiency, and overall performance. The parameters such as weights of the Mamba-based model are arranged in a sequential order in one or more sequential read memories according to a predetermined timing sequence. By embedding the selective state space model onto the models-on-silicon architecture, which excels in managing larger input context sizes, this solution transforms the Mamba-based model into a highly viable and efficient option for AI tasks being performed on resource-constrained devices.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
Apparatus and method for a low-power quantum controller. For example, one embodiment of an apparatus comprises: a low-power quantum control chip to process a first portion of quantum program code associated with a quantum computing application, the low-power quantum control chip configurable within a dilution refrigeration unit, the low-power quantum control chip comprising: an interface to couple the quantum control chip to a computer which is to execute a second portion of the quantum program code associated with the quantum computing application; a Static Random Access Memory (SRAM) to store the first portion of quantum program code; a compute unit to execute the first portion of quantum program code during execution of the quantum computing application and responsively generate control signals; routing hardware logic to route the control signals; a plurality of digital signal processor (DSP) units coupled to the routing hardware logic, at least one DSP of the plurality of DSPs to receive one or more of the control signals and responsively generate analog qubit control signals to control qubits of a quantum processor.
G06N 10/80 - Programmation quantique, p. ex. interfaces, langages ou boîtes à outils de développement logiciel pour la création ou la manipulation de programmes capables de fonctionner sur des ordinateurs quantiquesPlate-formes pour la simulation ou l’accès aux ordinateurs quantiques, p. ex. informatique quantique en nuage
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
45.
EPITAXIAL SOURCE AND DRAIN REGIONS WITH LOW-K INNER SPACERS
Techniques are provided herein to form an integrated circuit having semiconductor devices with low-k inner dielectric spacers between semiconductor bodies (e.g., nanoribbons, nanowires, or nanosheets). The dielectric spacers may include any suitable low-k dielectric material. Additionally, the inner dielectric spacers may be formed after the formation of source or drain regions, which improves the stress profile of the source or drain regions against the semiconductor bodies. In one such example, semiconductor bodies extend in a first direction between source or drain regions and a gate structure extends in a second direction over the semiconductor bodies between the source or drain regions. Inner spacers separate the gate structure from the source or drain regions along the first direction. The inner spacers may include a low-k dielectric material, such as silicon dioxide. In some examples, the inner spacers extend outwards beyond the ends of the semiconductor bodies along the first direction.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Methods, apparatus, systems, and articles of manufacture are disclosed to synchronize tasks. An example apparatus to synchronize tasks includes at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to identify a first task frequency associated with a first task, the first task executed by the computing device, the first task outputting first data at first times, identify a second task frequency associated with a second task, the second task executed by the computing device, the second task outputting second data at second times, when the second task frequency is different from the first task frequency, calculate a first difference between the second task frequency and the first task frequency, and adjust at least one of the first task frequency or the second task frequency based on the first difference such that the second times match the first times.
Techniques are provided for dynamic noise suppression. A methodology implementing the techniques according to an embodiment includes generating a magnitude spectrum and a phase spectrum of an input audio signal comprising speech and dynamic noise. The method also includes employing a temporal convolution network (TCN) to generate a separation mask based on the magnitude spectrum. The TCN comprises depth-wise (DW) convolution layers, each DW convolution layer including a state buffer to store a number of previous states of the associated DW convolution layer. The number of stored previous states is based on a dilation factor of the associated DW convolution layer. The method further includes multiplying the separation mask with the magnitude spectrum to separate the speech from the dynamic noise to obtain a denoised magnitude spectrum. The method further includes reconstructing the input audio signal with reduced dynamic noise based on the denoised magnitude spectrum and the phase spectrum.
G10L 21/0232 - Traitement dans le domaine fréquentiel
G10L 25/30 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par la technique d’analyse utilisant des réseaux neuronaux
G10L 25/78 - Détection de la présence ou de l’absence de signaux de voix
H04R 3/04 - Circuits pour transducteurs pour corriger la fréquence de réponse
48.
METHOD AND APPARATUS FOR HIGH-PERFORMANCE PAGE-FAULT HANDLING FOR MULTI-TENANT SCALABLE ACCELERATORS
Apparatus and method for high-performance page fault handling. For example, one embodiment of an apparatus comprises: one or more accelerator engines to process work descriptors submitted by clients to a plurality of work queues; fault processing hardware logic associated with the one or more accelerator engines, the fault processing hardware logic to implement a specified page fault handling mode for each work queue of the plurality of work queues, the page fault handling modes including a first page fault handling mode and a second page fault handling mode.
A mechanism is described for image frame rendering. An apparatus of embodiments, as described herein, includes one or more processors to receive a plurality of past image frames including a plurality of pixels, receive a predicted optical flow, generate a predicted frame and a confidence map associated with the predicted frame based on the plurality of past image frames and the predicted optical flow, render a first set of the plurality of pixels in the predicted frame based on the confidence map and adding the rendered pixels to the predicted frame to generate a final frame.
Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.
G06F 9/448 - Paradigmes d’exécution, p. ex. implémentation de paradigmes de programmation
G06F 16/215 - Amélioration de la qualité des donnéesNettoyage des données, p. ex. déduplication, suppression des entrées non valides ou correction des erreurs typographiques
G06T 1/20 - Architectures de processeursConfiguration de processeurs p. ex. configuration en pipeline
Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
The disclosure described herein generally relates to a foldable input/output (I/O) port of a computing device, including: a connector board electrically connected to a circuit board of the computing device; one or more I/O connectors arranged on the connector board, wherein the one or more I/O connectors are electrically connected to the connector board and capable of receiving one or more external connectors when the foldable I/O port is in an open configuration; and a housing portion, pivotably connected to the computing device, wherein the housing portion is capable of housing the connector board and the one or more I/O connectors.
Provided is a non-transitory machine-readable medium comprising machine-readable instructions which, when the carried out on an apparatus, cause the apparatus to receive first data indicating a security policy for an application to be carried out on the apparatus. The instructions further cause the apparatus to instruct, based on the security policy, a security advisor to determine a security appraiser to enforce the security policy. The instructions further cause the apparatus to instruct, upon reception of second data indicating the determined security appraiser, the determined security appraiser to determine whether third data provided for enforcing the security policy is suitable to enforce the security policy.
Systems, methods, and apparatuses relating sparsity based FMA. In some examples, an instance of a single FMA instruction has one or more fields for an opcode, one or more fields to identify a source/destination matrix operand, one or more fields to identify a first plurality of source matrix operands, one or more fields to identify a second plurality of matrix operands, wherein the opcode is to indicate that execution circuitry is to select a proper subset of FP8 data elements from the first plurality of source matrix operands based on sparsity controls from a first matrix operand of the second plurality of matrix operands and perform a FMA.
A system to support time sensitive networking (TSN) in a 5G system is described. The TSN application function (AF) sends to a device-side translator a Port Management Information Container (PMIC) and port number that has a Stream Identification type value and Stream Identification controlling parameters that depend on the Stream Identification type value for per-stream policing and filtering in a distributed bridge. During establishment of the bridge, the network-side translator port numbers are provided to the TSN AF in a Bridge Management Information Container (BMIC). Any PDU session of the bridge is able to be selected for Ethernet port and Bridge management procedures between the network-side translator and the TSN AF.
Various embodiments are generally directed to convolutional neural networks (CNN). A calibration dataset and a pretrained CNN comprising 32-bit floating point weight values may be sampled to generate an input activation tensor and a weight tensor. A transformed input activation tensor may be generated by multiplying the input activation tensor and an input matrix to generate a transformed input activation tensor. A transformed weight tensor may be generated by multiplying the weight tensor and a weight matrix. A scale factor may be computed for each transformed tensor. An 8-bit CNN model including the scale factors may be generated.
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p. ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
The present disclosure provides an apparatus and method of guided neural network model for image processing. An apparatus may comprise a guidance map generator, a synthesis network and an accelerator. The guidance map generator may receive a first image as a content image and a second image as a style image, and generate a first plurality of guidance maps and a second plurality of guidance maps, respectively from the first image and the second image. The synthesis network may synthesize the first plurality of guidance maps and the second plurality of guidance maps to determine guidance information. The accelerator may generate an output image by applying the style of the second image to the first image based on the guidance information.
A user may register with a fleet system responsible for remote management of a fleet of endpoint devices. The fleet system can determine a level of trust for the user based on information associated with an email address of the user and other information and register the user if the determined level of trust is sufficient. The registered user can request an activation token to be used for provisioning an endpoint device for consent-free out-of-band management. An endpoint device can be provisioned by the user submitting the activation token to the fleet service, the fleet service sending the activation token to the endpoint device, the endpoint device generating an ownership voucher request that includes the activation token, the fleet service verifying and validating the ownership voucher request, the fleet service returning a signed ownership voucher to the endpoint device, and the endpoint device verifying the signed ownership voucher.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
59.
SEMICONDUCTOR DEVICE HAVING A NECKED SEMICONDUCTOR BODY AND METHOD OF FORMING SEMICONDUCTOR BODIES OF VARYING WIDTH
Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.
H10D 62/00 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 62/822 - Hétérojonctions comprenant uniquement des hétérojonctions de matériaux du groupe IV, p. ex. des hétérojonctions Si/Ge
H10D 62/83 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
H10D 86/00 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre
60.
CONTENT SUMMARIZATION AND/OR RECOMMENDATION APPARATUS AND METHOD
Embodiments are provided for summarization and recommendation of content. In disclosed embodiments, a summarization engine scores constituent parts of content, and generates a plurality of summaries from a plurality of points of view for the content based at least in part on the scores of constituent parts. The summaries may be formed with constituent parts extracted from the contents. A recommendation engine provides recommendations to a user based on rankings of the summaries generated by the summarization engine. Other embodiments may be described and/or claimed.
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p. ex. condensation
H01L 21/308 - Traitement chimique ou électrique, p. ex. gravure électrolytique en utilisant des masques
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
H10D 1/47 - Résistances n’ayant pas de barrières de potentiel
H10D 30/62 - Transistors à effet de champ à ailettes [FinFET]
H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
H10D 62/00 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 62/822 - Hétérojonctions comprenant uniquement des hétérojonctions de matériaux du groupe IV, p. ex. des hétérojonctions Si/Ge
H10D 62/834 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé caractérisés en outre par les dopants
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
Circuitry and methods for implementing conditional fence instructions are described. In certain examples, a hardware processor (e.g., core) includes a branch predictor to predict one of a taken path and a not taken path for a conditional branch instruction; decoder circuitry to decode an instruction into a decoded instruction, the instruction comprising a field that indicates a condition to be set by execution of another instruction, and an opcode that indicates execution circuitry is to, in response to the condition being satisfied, implement an execution fence to delay execution of the instruction until prior instructions in program order execute and delay execution of instructions after the instruction in program order until the instruction executes; and the execution circuitry to execute the decoded instruction according to the opcode.
Integrated circuit structures having deep via structures, and methods of fabricating integrated circuit structures having deep via structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. A conductive via is vertically beneath and extends into the conductive trench contact structure. The conductive via has a first width beneath the epitaxial source or drain structure less than a second width laterally adjacent to the epitaxial source or drain structure.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10D 30/62 - Transistors à effet de champ à ailettes [FinFET]
Techniques are provided herein to form an integrated circuit having source and/or drain regions with shaped bottom surfaces to reduce parasitic capacitance. In an example, the bottom portions of the source and/or drain regions may be etched from the backside to form inwardly tapered ends. An array of semiconductor devices each include a semiconductor region extending (e.g., in a first direction) from a source region to a drain region, with a gate structure extending (e.g., in a second direction perpendicular to the first direction) over the semiconductor region. A lower portion of the source and/or drain regions (e.g., a portion at least extending below the semiconductor region) has an inwardly tapered shape. The inward taper may be provided using a backside etching process. The tapered ends of the source and/or drain regions have an increased distance to the adjacent gate structures, thus reducing the parasitic capacitance.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H10D 30/43 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à une dimension, p. ex. transistors FET à fil quantique ou transistors ayant des canaux à confinement quantique à une dimension
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
09 - Appareils et instruments scientifiques et électriques
Produits et services
computer hardware; semi-conductors; integrated circuits; integrated circuits designed for ruggedized applications; integrated circuits designed for higher levels of quality, assurance, and reliability in harsh environments
66.
DEVICE AND METHOD FOR DETERMINING INCIDENT POWER DENSITY REFERENCE LEVEL EXPOSURES FROM SPECIFIC ABSORPTION RATE MEASUREMENTS
An incident power density determination device includes a human tissue phantom, configured to approximate dielectric properties of human tissue; one or more radiofrequency probes, positioned within the human tissue phantom, configured to generate measurements of radiofrequency emissions absorbed within the human tissue phantom; and a processor, configured to determine an incident power density at an outer surface of the human tissue phantom based on the generated measurements of the radiofrequency emissions.
Logic may determine user equipment (UE) context information associated with a UE, the UE context information comprising new information related to establishment of a new connection with the UE or related to an update of the UE context information for an existing connection with the UE. Logic may identify an event trigger associated with new information. And logic may respond to a query from the near-RT RIC for UE context information associated with the UE, wherein the UE supports a non-grid of beams mode for beamforming.
This disclosure describes systems, methods, and devices for estimating dimple etch recess depth in a gate-all-around transistor. A method may include receiving, by a device, first measurements of the gate-all-around transistor, the first measurements based on first optical data from a spacer etch stage of fabricating the gate-all-around transistor; inputting, by the at least one processor, using a feed forward network, the first measurements to a machine learning model trained to estimate dimple etch recess in the gate-all-around transistor; inputting, by the at least one processor, to the machine learning model, second optical data from a dimple etch stage of fabricating the gate-all-around transistor; and generating, by the at least one processor, using the machine learning model, based on the second optical data and the first measurements, second measurements comprising the first measurements and dimple etch recess estimates for the gate-all-around transistor.
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
G06F 18/214 - Génération de motifs d'entraînementProcédés de Bootstrapping, p. ex. ”bagging” ou ”boosting”
Systems, apparatus, articles of manufacture, and methods are disclosed control on-off switching in wireless networks. An example computer readable medium comprises instructions that, when executed, cause at least one programmable circuitry to at least generate a mathematical graph that includes measurement information about a first communication cell and a second communication cell; process a first embedding of the mathematical graph with a graph convolutional network layer to generate an updated embedding; concatenate the first embedding and the updated embedding to generate a concatenated embedding; and process the concatenated embedding via a neural network; and cause the first communication cell to be deactivated based on the result of the neural network.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06N 3/04 - Architecture, p. ex. topologie d'interconnexion
In an embodiment, an apparatus includes a receiver circuit to: in response to a determination that the receiver circuit is in a high latency processing mode, transmit a hint signal to a transmitter circuit; receive a response message from the transmitter circuit; process the response message to reduce a current workload of the receiver circuit; and switch the receiver circuit from the high latency processing mode to a low latency processing mode. Other embodiments are described and claimed.
The present disclosure is related to machine learning model swap (MLMS) framework for that selects and interchanges machine learning (ML) models in an energy and communication efficient way while adapting the ML models to real time changes in system constraints. The MLMS framework includes an ML model search strategy that can flexibly adapt ML models for a wide variety of compute system and/or environmental changes. Energy and communication efficiency is achieved by using a similarity-based ML model selection process, which selects a replacement ML model that has the most overlap in pre-trained parameters from a currently deployed ML model to minimize memory write operation overhead. Other embodiments may be described and/or claimed.
G06F 18/21 - Conception ou mise en place de systèmes ou de techniquesExtraction de caractéristiques dans l'espace des caractéristiquesSéparation aveugle de sources
G06V 10/75 - Organisation de procédés de l’appariement, p. ex. comparaisons simultanées ou séquentielles des caractéristiques d’images ou de vidéosApproches-approximative-fine, p. ex. approches multi-échellesAppariement de motifs d’image ou de vidéoMesures de proximité dans les espaces de caractéristiques utilisant l’analyse de contexteSélection des dictionnaires
An apparatus to facilitate encoding video data is disclosed. The apparatus includes rendering logic to render graphics video data as frame data, fade extractor logic to extract fade effects data to be applied to the frame data to generate frame auxiliary metadata comprising the fade effects data, weighted prediction logic to receive the frame data and the auxiliary metadata and compute one or more weighted predictions on the frame data at one or more frame sequences indicated in the fade effects data and encoding logic to encode the frame data based on the one or more weighted predictions.
H04N 19/105 - Sélection de l’unité de référence pour la prédiction dans un mode de codage ou de prédiction choisi, p. ex. choix adaptatif de la position et du nombre de pixels utilisés pour la prédiction
H04N 19/132 - Échantillonnage, masquage ou troncature d’unités de codage, p. ex. ré-échantillonnage adaptatif, saut de trames, interpolation de trames ou masquage de coefficients haute fréquence de transformée
H04N 19/167 - Position dans une image vidéo, p. ex. région d'intérêt [ROI]
H04N 19/172 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant une image, une trame ou un champ
H04N 19/70 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques caractérisés par des aspects de syntaxe liés au codage vidéo, p. ex. liés aux standards de compression
73.
GATE ALIGNED FIN CUT FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
Gate aligned fin cut for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a first fin segment having a fin end, and a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment. A first gate structure is over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment. A second gate structure is over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment. An isolation structure is laterally between the fin end of the first fin segment and the fin end of the second fin segment.
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H10D 30/43 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à une dimension, p. ex. transistors FET à fil quantique ou transistors ayant des canaux à confinement quantique à une dimension
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
74.
METHODS AND APPARATUS TO ANALYZE SOFTWARE APPLICATIONS
This disclosure is related to software application analysis and, more particularly to, methods and apparatus to analyze software applications. An example non-transitory machine readable storage medium includes instructions to cause programmable circuitry to at least determine a first partition of a first processing resource, reallocate applications executing on the first partition, allocate an application under test to execute on the first partition, monitor execution of the application under test, and output a report associated with the execution.
Various aspects relate to three-dimensional integrated circuits including a plurality of conformal integrated circuit slices stacked one upon the other. The plurality of conformal integrated circuit slices includes various components. A communication face defines a communication surface configured to conform to a portion of a topography of a non-planar host substrate. A plurality of input-output devices is configured to communicate to a corresponding plurality of host-side input-output devices associated with the non-planar host substrate.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/304 - Traitement mécanique, p. ex. meulage, polissage, coupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
76.
SPATIAL ELEMENT ADAPTATION FOR NETWORK ENERGY SAVING
The present disclosure describes mechanisms to configure user equipment (UEs) with a set of channel state information (CSI) and/or measurement configurations, and mechanisms to indicate codepoints that activate or trigger selected ones of the configured CSI/measurement configures that individual UEs are to use to report CSI and/or other measurements. The set of configurations can indicate how individual UEs are to compute CSI and/or measurement feedback reports. The set of configurations can include information about which subset of antenna ports from a set of antenna port configurations, and potential transmission power offsets between CSI reference signal (CSI-RS) and physical downlink shared channel (PDSCH). The signaling mechanisms can include radio resource control (RRC) for the CSI/measurement configurations and/or downlink control information (DCI) signaling for activation/triggering of the selected CSI/measurement configurations. The activation/triggering signaling can include a limited number of bits to indicate the codepoints.
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04W 72/23 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal
Disclosed herein are devices, systems, and methods related to edge couplers for providing wireless channel interconnects between edges of chiplets, components, modules, devices, packages, SoCs, etc. Such edge couplers may be formed from a stack of multiple layers and a core arranged between layers of the stack. A driven via extends from at least one feed layer of the stack of multiple layers into the core, wherein the driven via is isolated from ground. A plurality of grounded through-hole vias are grounded, extend from at least one ground layer of the stack, and traverse through the core, wherein the plurality of grounded through-hole vias partially surround the driven via.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/34 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a one-bit weight associated with a neural network, as well as an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a fused operation including an exclusive not OR (XNOR) operation and a population count operation. The adder is configured to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06N 3/084 - Rétropropagation, p. ex. suivant l’algorithme du gradient
G06T 1/20 - Architectures de processeursConfiguration de processeurs p. ex. configuration en pipeline
79.
WIRELESS COMMUNICATION, MAINTAINING WIRELESS THROUGHPUT, AND DETECTION AND MANAGEMENT OF HUMAN BODY PROXIMITY TO TRANSMITTING ANTENNAS
Various principles and methods are described herein to improve wireless communication in a user computing device. Certain aspects of the disclosure describe management of wireless transmissions relative to various regulations related to a specific absorption rate. Other aspects of the disclosure relate to detection of user proximity to a transmitting antenna. Other aspects relate to alternative strategies to improve wireless communication, such as selection of alternate antennas or baseband modems, or changes in device orientation.
H04W 52/36 - Commande de puissance d'émission [TPC Transmission power control] utilisant les limitations de la quantité totale de puissance d'émission disponible avec une plage ou un ensemble discrets de valeurs, p. ex. incrément, variation graduelle ou décalages
A port is to couple to another die over a die-to-die (D2D) link and includes a die-to-die (D2D) adapter to determine, from a set of registers, a set of capabilities of the D2D adapter to advertise in a negotiation with a link partner D2D adapter, where the D2D adapter is on a die and the link partner D2D adapter is located on a remote link partner die. A first capabilities advertisement message is sent to the link partner D2D adapter to advertise the set of capabilities to the link partner D2D adapter. A second capabilities advertisement message is received from the link partner D2D adapter, wherein the second capabilities advertisement message identifies a set of capabilities of the link partner D2D adapter. A final configuration of a D2D link is determined to couple the die to the link partner die.
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
81.
SYSTEMS AND METHODS FOR CROSS-DOMAIN TRAINING OF SENSING-SYSTEM-MODEL INSTANCES
Disclosed herein are systems and methods for cross-domain training of sensing-system-model instances. In an embodiment, a system receives, via a first application programming interface (API), an input-dataset selection identifying an input dataset, which includes a plurality of dataframes that are in a first dataframe format and that have annotations corresponding to one or more sensing tasks performed with respect to the dataframes. The system executes a plurality of dataframe-transformation functions to convert the plurality of dataframes of the input dataset into a predetermined dataframe format. The system trains an instance of a first machine-learning model using the converted dataframes of the input dataset to perform at least a subset of the one or more sensing tasks. The system outputs, via the first API, one or more model-validation metrics pertaining to the training of the instance of the first machine-learning model.
Examples described herein relate to a network interface device comprising: a direct memory access (DMA) circuitry; a device interface; a network interface; and a circuitry to: transmit a clock reference frame to multiple talker devices at a predefined rate to cause the multiple talker devices to synchronize clock signals with a time stamp value in the clock reference frame. In some examples, the circuitry is to synchronize a leading edge of a media clock signal based on the time stamp value and provide the media clock signal to an media processing system.
An agent chip in a multi-chip architecture orchestrates multiple specialized AI models embedded and/or etched on different chips. Implementing the agent chip effectively solves the problem of deploying multiple specialized AI models in a cost-effective and scalable manner by training and utilizing the agent chip to orchestrate multiple specialized AI models embedded on different models-on-silicon chips. Each models-on-silicon chip is optimized for a specific task or goal, and the agent chip coordinates and/or routes their activities to perform complex, multi-faceted tasks efficiently. Accordingly, the multi-chip architecture allows for efficient, scalable, and cost-effective machine learning inference, significantly reducing power consumption and latency.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
This disclosure describes systems, methods, and devices related to enhanced network performance. A device may receive from higher layers configuration information that designates a set of physical resource blocks (PRBs) as unavailable for transmission within a wideband carrier. The device may determine, based on the configuration information, whether a scheduled physical downlink or uplink channel or signal at least partially overlaps with unavailable PRBs. The device may cancel transmission of the scheduled physical downlink or uplink channel or signal on the overlapped unavailable PRBs. The device may receive or transmit physical downlink shared channel (PDSCH) or physical uplink shared channel (PUSCH), respectively, on PRBs within an allocated resource block group (RBG) that are not designated as unavailable.
This disclosure describes systems, methods, and devices related to optimized network management. A device may receive a downlink control information (DCI) message to trigger channel state information (CSI) reporting, wherein the CSI reporting comprises aperiodic Layer 1 Sounding Reference Signal-Reference Signal Received Power (L1 SRS-RSRP) or Layer 1 Cross Link Interference-Received Signal Strength Indicator (L1 CLI-RSSI) based on SRS or CLI measurement resources, respectively. The device may determine a measurement reference resource for aperiodic L1-SRS-RSRP or L1-CLI-RSSI measurement based on timing of the received DCI and an explicit or implicit indication of the corresponding measurement reference resource. The device may perform a measurement operation corresponding to the measurement reference resource. The device may transmit a Layer 1 SRS-RSRP or CLI-RSSI measurement report on an uplink shared channel (PUSCH) based on the received DCI.
H04W 72/232 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal les données de commande provenant de la couche physique, p. ex. signalisation DCI
H04W 72/21 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens ascendant de la liaison sans fil, c.-à-d. en direction du réseau
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
According to various examples, a radio access network controller is described comprising a processor configured to determine whether a mobile terminal is located at a center region of a radio cell of a communication network or an edge region of the radio cell, and control the communication network to serve the mobile terminal by a plurality of radio units of a plurality of radio cells using coherent joint transmission by allocating the same time, frequency, code and spatial resources, if the processor determines that the mobile terminal is in the edge region of the radio cell and control the communication network to serve the mobile terminal by one radio unit of the radio cell using single-cell processing if the processor determines that the mobile terminal is in the center region of the radio cell.
H04W 28/08 - Équilibrage ou répartition des charges
H04W 72/541 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de qualité en utilisant le niveau d’interférence
87.
OPTIMIZATION OF EXECUTABLE GRAPH FOR ARTIFICIAL INTELLIGENCE MODEL INFERENCE
The application relates to optimization of an executable graph for AI model inference. An optimization method may include: duplicating the executable graph to generate a number M of same executable graphs; determining one or more nodes eligible for optimization from the executable graph, based on an inference throughput related parameter associated with an inference device to perform the AI model inference; and generating an optimized executable graph for the AI model inference by optimizing the one or more nodes from each of the number M of same executable graphs. Here, M is an integer in a range of 2 to a maximum number N of allowed executable graphs, and N is an integer manually configured or estimated based on a memory size of the inference device and a size of the executable graph.
The application provides an apparatus, method, and storage medium for evaluation and mitigation of soft-errors in parallel and distributed training and inference of transformers. The apparatus includes two or more processing units capable to communicate with each other and operating collectively as a transformer for deep learning. Each processing unit is configured to perform a matrix multiplication on a first matrix with a first column summation vector added after a last row of the first matrix and a first parameter matrix with a first row summation vector added after a last column of the first parameter matrix, to obtain a second matrix; perform an all-reduce operation on second matrices obtained by the two or more processing units to obtain a third matrix; and determine whether a soft error has occurred by performing a checksum verification on the third matrix.
Immersion cooling systems, apparatus, and related methods for cooling electronic computing platforms and/or associated electronic components are disclosed herein. An immersion cooling chassis includes a first face, a second face opposite the first face, a third face disposed between the first face and the second face, the third face perpendicular to the first face, a fourth face disposed between the first face and the second face, the fourth face perpendicular to the first face and opposite the third face, and a first portion to be cooled via a first convection of a coolant fluid, the first portion including a coolant inlet defined in the third face, and a coolant outlet defined in the first face, and a second portion to be cooled via a second convection of air, the second portion including an air inlet defined in the first face between the fourth face and the coolant outlet.
A first device includes a first receiver, configured to receive a first signal from a second device over a first connection, corresponding to a first channel, and a second receiver, configured to receive a second signal from the second device over a second connection, corresponding to a second channel; the first receiver includes a first scrambler and a first block counter, and the second receiver includes a second scrambler and a second block counter; and wherein, in response to receiving an instruction to transition the second receiver from a low power state to an active state, the first device is configured to set the second scrambler based on a known relationship between the first scrambler and the second scrambler, and to resolve a skew based on a difference between the first block counter and the second block counter.
One embodiment provides a graphics processor device that includes circuitry configured to detect a connection of a second display device to a display subsystem of the graphics processor while a first display device of the graphics subsystem is active, write pre-determined pixel data to a reserved portion of memory associated with the display subsystem, configure timings for the second display device while resources allocated to the first display device remain available to the first display device, display the pre-determined pixel data from the reserved portion of the memory on the second display device during reallocation of the resources of the display subsystem to enable output the framebuffer data to the second display device, and transition the second display device from the display of the pixel data in the reserved portion of the memory to the display of the framebuffer data after resources of the display subsystem are reallocated.
G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation
G09G 5/02 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation caractérisés par la manière dont la couleur est visualisée
92.
OUT-OF-ORDER EXECUTION OF GRAPHICS PROCESSING UNIT TEXTURE SAMPLER OPERATIONS
Embodiments described herein are generally directed facilitating out-of-order execution of GPU texture sampler operations. An embodiment of a method includes a texture sampler of a GPU maintaining (i) a latency queue operable to store information regarding a set of transactions associated with each of multiple texture sampler operations and (ii) multiple virtual channel (VC) queues each operable to store information regarding transactions for a respective single texture sampler operation at a time. Out-of-order processing of the texture sampler operations is facilitated by making use of the latency queue and the VC queues. For example, during a transaction processing interval, the availability of data in a cache for the transactions associated with each of the VC queues may be determined. A VC queue may be selected based on the determined availability of data. A transaction associated with a head of the selected VC queue may then be processed.
Improved semiconductor chip package thermo-mechanical cooling assembly are disclosed. An example An apparatus includes: a bolster plate to be coupled to a back plate, the bolster plate and backplate to sandwich a circuit board therebetween; a loading plate including a first fixture, the first fixture to engage a load stud protruding from the bolster plate; and a heat sink base including a second fixture, the second fixture to engage a pin protruding from the loading plate.
A user may express their intent for a program using informal code representations, such as natural language and pseudocode, optionally combined with source code. An artificial intelligence runtime interprets the informal code representation to generate executable code. The user may be prompted by clarifying questions about the program if the artificial intelligence runtime infers that the program is a partial implementation or if ambiguity is present in the program. The informal code representation and the source code may be automatically revised based on the user's responses to the clarifying questions. Once the user has indicated that the program is performing as intended, the executable code associated with the program may be stored as validated executable code without the need to be represented in a higher-level language (e.g., Python, C#). The validated executable code can be used by the artificial intelligence runtime in subsequent executions of the program.
An apparatus for a user equipment (UE) operating in a New Radio (NR) network is disclosed. The apparatus includes processing circuitry configured to enable measurement reporting by detecting a trigger event for a Lower-layer Triggered Mobility (LTM) beam reporting event, where the trigger event is based on a signal characteristic change associated with a signal transmitted or received by the UE. Upon detection, the processing circuitry generates an LTM beam report and encodes the report for transmission to a base station via an uplink channel. The apparatus further comprises memory coupled to the processing circuitry, which is configured to store the LTM beam report. This enables efficient and responsive mobility management in NR networks through event-triggered measurement reporting.
H04W 72/21 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens ascendant de la liaison sans fil, c.-à-d. en direction du réseau
H04W 72/232 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal les données de commande provenant de la couche physique, p. ex. signalisation DCI
H04W 72/231 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal les données de commande provenant des couches au-dessus de la couche physique, p. ex. signalisation RRC ou MAC-CE
H04W 36/30 - La resélection étant déclenchée par des paramètres spécifiques par des données de mesure ou d’estimation de la qualité des liaisons
Software defined cooling structures are described. A method comprises decoding sensor data from a sensor of an electronic component of an electronic device, generating a control directive to move a software defined cooling (SDC) structure of a cooling system from a first position to a second position based on the sensor data, moving the SDC structure from the first position to the second position in response to the control directive, the second position to comprise a position within a defined distance to the electronic component of the electronic device, and performing thermal management of the electronic component using the SDC structure. Other embodiments are described and claimed.
Techniques are provided herein to form an integrated circuit having stacked semiconductor devices with their source or drain regions coupled together via matching backside connections. In an example, FET (field effect transistor) devices may be formed on two different substrates and bonded together at their backsides such that backside contacts beneath each device substantially align at or near the bonding interface. The substrate beneath both the first FET and the second FET is removed, and backside contacts are formed beneath the source or drain regions of the first and second FETs. A bonding layer may also be formed on the backside of either the first FET or the second FET. The second FET is then flipped upside down and bonded to the backside of the first FET, such that the backside contacts from the first and second FET's are substantially aligned and are conductively coupled through the bonding layer.
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Techniques are provided herein to form an integrated circuit with a double-height standard cell layout that can utilize both frontside and backside connections. The layout involves merging two of the transistors into a single wider transistor that extends along the midline of the double-height standard cell layout. Accordingly, the double-height standard cell layout may include three total transistors with one transistor being wider than the other two. The transistors may be configured as an inverter with enhanced driving capability in the double height standard cell layout. The wider transistor at the center of the double-height standard cell layout includes a source or drain region with both a topside contact and a backside contact to provide additional interconnect routing flexibility. The double-height standard cell may include an n-channel device having a first width aligned along a centerline of the double-height standard cell and two p-channel devices or vice versa.
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
