Techniques for using integrity check value tripwires for memory safety are described. In an embodiment, an apparatus includes an instruction decoder to decode one or more instructions to copy a memory region; and execution circuitry coupled to the instruction decoder, the execution circuitry to perform one or more operations corresponding to the one or more instructions, including detecting an integrity check value (ICV) mismatch; determining whether a granule in the memory region represents a tripwire; determining a suppression mode associated with the one or more instructions; and in response to determining that the suppression mode allows copying the tripwire, copying the tripwire.
G06F 21/54 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
2.
METHODS AND APPARATUS TO REDUCE AN ACTION SPACE FOR WORKLOAD EXECUTION
An example apparatus includes at least one programmable circuit to analyze workload runs for a plurality of combinations of enabled setting to determine a subset of the plurality of combinations that satisfy a target performance metric; run a workload for a second combination of enabled settings to generate a result, the second combination combining enabled settings from two or more of the subset of the plurality of combinations; analyze the result to determine the second combination satisfies the target performance metric; and deploy the second combination and the subset of the plurality of combinations to a device to process a second workload using at least one of the second combination of the subset of the plurality of combinations.
In one embodiment, an apparatus comprises a substrate with conductive contacts on a first side of the substrate and a housing coupled to the first side of the substrate. The housing defines a set of holes around the conductive contacts. The apparatus further includes Gallium-based liquid metal in each hole, with the liquid metal being in contact with the conductive contact of the hole. The apparatus further includes a passivation layer on a surface of the liquid metal in each hole, the passivation layer being on an opposite end of the hole from the conductive contact in the hole.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
An apparatus includes at least one memory, instructions, and processor circuitry to execute the instructions to track movement of a head of a user wearing earphones, the earphones to move with the movement of the head of the user, the earphones to be communicatively coupled to a computing device. The processor circuitry is to obtain media content, the media content including first audio data for a first channel and second audio data for a second channel. The processor circuitry is to adjust, based on the movement of the head of the user, the first audio data for the first channel and the second audio data for the second channel. The processor circuitry is to cause the adjusted first audio data and the adjusted second audio data to be played by the earphones.
Immersion cooling systems are disclosed. An example immersion cooling system includes an immersion tank including a cooling fluid and a reservoir to contain a recirculated portion of the cooling fluid. The reservoir is separated from the immersion tank by a height to generate a liquid surface height variance between the cooling fluid in the immersion tank and the cooling fluid in the reservoir. A supply conduit is to fluidly couple the immersion tank and the reservoir. The cooling fluid to be provided from the reservoir to the immersion tank via gravity.
Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
Embodiments are related to a fifth generation (5G) or sixth generation (6G) wireless communications system. A method for an access node of a wireless system comprises encoding a session start request message to start a data collection session (DCS) to collect data for a machine learning (ML) model from a user equipment (UE) by a base station of a wireless system, the session start request message including UE context information, decoding a session start response message to indicate the start of the DCS by the base station, the session start response message including DCS configuration information for the ML model, and encoding a data collection request message for the UE to collect measurements for the ML model based on the DCS configuration information for the ML model by the base station. Other embodiments are described and claimed.
Techniques for an attack-aware digital twin in a time sensitive network are described. A method includes receiving time information for a network by an attack-aware digital twin (AADT), the AADT to simulate operations of a clock manager for a node in the network based on models of the clock manager, generating model clock control information to adjust a clock to a network time for the network, the model clock control information to contain a malicious time sample introduced by a time desynchronization attack in the network, and removing the malicious time sample from the model clock control information to adjust the clock to the network time for the network. Other embodiments are described and claimed.
An apparatus and system of providing multi-path transmissions are described. A user equipment (UE) sends a Multi-path Policy Provisioning Request in a UE Policy Container to a policy control function (PCF). The PCF provisions a UE route selection policy (URSP) to the UE including a Multi-Path preference in an Access Type preference or multi-path parameter of a Route Selection Descriptor of a URSP rule. The Multi-Path preference indicates a preferred path over a Uu interface and Layer-2 or Layer-3 UE-to-Network Relay. The UE determines packet data unit (PDU) establishment additionally based on path availability, as well as ProSe Layer-3 UE-to-Network Relay Offload indication and ProSe Policy. The Multi-path Policy Provisioning Request is earned in a Registration Request message or UE Policy Provisioning Request message.
H04W 40/22 - Sélection d'itinéraire ou de voie de communication, p. ex. routage basé sur l'énergie disponible ou le chemin le plus court utilisant la retransmission sélective en vue d'atteindre une station émettrice-réceptrice de base [BTS Base Transceiver Station] ou un point d'accès
H04W 88/04 - Dispositifs terminaux adapté à la retransmission à destination ou en provenance d'un autre terminal ou utilisateur
Systems and methods are provided for an acoustic-based determination that a device is inside a bag, enabling a device to react early to a potential hot bag scenario before the device begins to overheat. Acoustic cues associated with the device being put in a bag can be detected, and an ultrasonic echo can be analyzed to identify characteristics of reflections from a bag material. Ambient acoustics are used as a cue for hot bag detection, and acoustic analysis can be implemented in an audio digital signal processor, consuming a minimum amount of energy and allowing the acoustic-based device context detection method to function when the device is in standby, sleep, and/or hibernate mode. When the acoustic-based device context detection method determines that the device is inside a bag, the method prevents the device from entering a high power state, providing users with worry-free battery life.
A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
12.
NETWORK OPTIMIZATION AND POSITIONING TECHNIQUES FOR 5G BACKHAUL
Various approaches for the deployment and coordination of network operation processing, communications, and mobile device positioning, in connection with backhaul of a radio access network (RAN), are disclosed. An example method of operation of backhaul communications used with a radio access network (RAN) includes: obtaining measurements corresponding to wireless communications of a radio access network (RAN) operating with a backhaul, the measurements based on in-phase and quadrature (IQ) data of the wireless communications; performing a comparison of the measurements to an expected operational state of the RAN, with the expected operational state being established from a baseline of the IQ data collected in the RAN; and modifying the wireless communications of the backhaul based on the comparison of the measurements to the expected operational state.
A driving assistance device comprises a processor which is configured to generate a risk map using road surface data and vehicle data; and to generate a driving instruction based on the risk map; wherein the risk map represents areas of risk related to a road surface within a vicinity of a vehicle; and wherein the road surface data represent irregularities of a road surface within the vicinity of the vehicle.
B60K 35/28 - Dispositions de sortie, c.-à-d. du véhicule à l'utilisateur, associées aux fonctions du véhicule ou spécialement adaptées à celles-ci caractérisées par le type d’informations de sortie, p. ex. divertissement vidéo ou informations sur la dynamique du véhiculeDispositions de sortie, c.-à-d. du véhicule à l'utilisateur, associées aux fonctions du véhicule ou spécialement adaptées à celles-ci caractérisées par la finalité des informations de sortie, p. ex. pour attirer l'attention du conducteur
A computing platform comprising a plurality of disaggregated data center resources and an infrastructure processing unit (IPU), communicatively coupled to the plurality of resources, to compose a platform of the plurality of disaggregated data center resources for allocation of microservices cluster.
The disclosure provides an apparatus, method, device and medium for label-balanced calibration in post-training quantization of DNNs. An apparatus includes interface circuitry configured to receive a training dataset and processor circuitry coupled to the interface circuitry. The processor circuitry is configured to generate a small ground truth dataset by selecting images with a ground truth number of 1 from the training dataset; generate a calibration dataset randomly from the training dataset; if any image in the calibration dataset has the ground truth number of 1, remove the image from the small ground truth dataset; generate a label balanced calibration dataset by replacing an image with a ground truth number greater than a preset threshold in the calibration dataset with a replacing image selected randomly from the small ground truth dataset; and perform calibration using the label balanced calibration dataset in post-training quantization. Other embodiments are disclosed and claimed.
G06V 10/774 - Génération d'ensembles de motifs de formationTraitement des caractéristiques d’images ou de vidéos dans les espaces de caractéristiquesDispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p. ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]Séparation aveugle de source méthodes de Bootstrap, p. ex. "bagging” ou “boosting”
16.
METHODS AND APPARATUS FOR MULTI-ZONE TEMPERATURE CONTROL OF JET IMPINGEMENT COOLING OF INTEGRATED CIRCUIT PACKAGES
Systems, apparatus, articles of manufacture, and methods for temperature control of jet impingement cooling of integrated circuit packages are disclosed. An example system includes: a first nozzle to direct a first portion of impingement fluid towards an integrated circuit package; a second nozzle to direct a second portion of the impingement fluid towards the integrated circuit package; a first flow restrictor to control a first pressure of the first portion of the impingement fluid provided to the first nozzle; and a second flow restrictor to control a second pressure of the second portion of the impingement fluid provided to the second nozzle.
An apparatus to facilitate tessellation redistribution for reducing latencies in processors is disclosed. The apparatus includes a processor to provide parallel interconnected geometry fixed-function units with separate front end and back ends, the front ends to perform patch culling and transmission and the back ends to perform patch reception from the front end and patch tessellation; provide a tessellation redistribution central engine to redistribute patches among the back ends using a redistribution bus; receive, by the tessellation redistribution central engine from the front ends in parallel, patch transmissions marked for distribution, the tessellation redistribution engine to process the patch transmissions in order; and in response to receiving a synchronization barrier packet from one of the front ends, broadcast, by the tessellation redistribution central engine, the synchronization barrier packet to the back ends to cause one of the back ends to process tessellation work locally.
Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.
A graphics processing device is provided that includes a set of compute units to execute a workload, a cache coupled with the set of compute units, and circuitry coupled with the cache and the set of compute units. The circuitry is configured to, in response to a cache miss for the read from a first cache, broadcast an event within the graphics processor device to identify data associated with the cache miss, receive the event at a second compute unit in the set of compute units, and prefetch the data identified by the event into a second cache that is local to the second compute unit before an attempt to read the instruction or data by the second thread.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06T 1/20 - Architectures de processeursConfiguration de processeurs p. ex. configuration en pipeline
Systems, apparatuses and methods may provide for technology that identifies a first keyword and a second keyword in a plurality of keywords, determines that a first relevance associated with the first keyword is greater than a second relevance associated with the second keyword, vectorizes the first keyword to a first level of precision, vectorizes the second keyword to a second level of precision, wherein the first level of precision is greater than the second level of precision, and stores the vectorized first keyword and the vectorized second keyword to a retrieval-augmented generation (RAG) vector database.
This disclosure describes systems, methods, and devices related to multi-link device (MLD) data continuity. An MLD device may set up one or more links with a station multi-link device (STA MLD), wherein the STA MLD comprises one or more logical entities defining separate station devices. The MLD device may transmit a data packet associated with a traffic identifier (TID) to the STA MLD. The MLD device may determine that the data packet was not received by the STA MLD. The MLD device may retransmit the data packet to the STA MLD. The MLD device may increment a retransmit counter every time the data packet is retransmitted. The MLD device may refrain from transmitting a second data packet until the data packet is dropped or successfully received by the STA MLD.
Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces that are parallel to the first and second surfaces and exposed at the third surface; a second IC die having a fourth surface and including voltage regulator circuitry; and a third IC die having a fifth surface, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die by first interconnects, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die by second interconnects, and the first IC die is electrically coupled to the second IC die by conductive pathways in the third IC die.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
Magnetic inductors for microelectronics packages are provided. Magnetic inductive structures include a magnetic region, a magnetic region base region, and a conductive region that forms a channel within the magnetic region. The magnetic region has a different chemical composition than the base region. Additional structures are provided in which the magnetic region is recessed into a package substrate core. Further inductor structures are provided in which the conductive region includes through-core vias and the conductive region at least partially encircles a portion of a package substrate core. Additionally, methods of manufacture are provided for semiconductor packages that include magnetic inductors.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01F 1/03 - Aimants ou corps magnétiques, caractérisés par les matériaux magnétiques appropriésEmploi de matériaux spécifiés pour leurs propriétés magnétiques en matériaux inorganiques caractérisés par leur coercivité
H01F 41/16 - Appareils ou procédés spécialement adaptés à la fabrication ou à l'assemblage des aimants, des inductances ou des transformateursAppareils ou procédés spécialement adaptés à la fabrication des matériaux caractérisés par leurs propriétés magnétiques pour appliquer des pellicules magnétiques sur des substrats le matériau magnétique étant appliqué sous forme de particules, p. ex. par sérigraphie
24.
INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORM GRID METAL GATE AND TRENCH CONTACT PLUG
Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A memory device may include one or more semiconductor structures having a frontside and a backside, one or more gate electrodes, and metal layers at both the frontside and backside. A frontside metal layer may include metal lines that are used as bit lines of the memory device. A backside metal layer may include metal lines that are used as write bit lines of the memory device. A write bit line at the backside may be parallel to a bit line at the frontside. Another backside metal layer may include metal lines that are used as word lines of the memory device. A word line at the backside may be parallel to a gate electrode. A switch may be between a bit line and a write bit line. The bit line is electrically coupled to the write bit line when the switch is closed.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
26.
BRIDGE PRINTED CIRCUIT BOARD EMBEDDED WITHIN ANOTHER PRINTED CIRCUIT BOARD
Embodiments herein relate to systems, apparatuses, techniques, or processes for forming a bridge PCB within one or more metal layers of a main PCB. The bridge PCB, which may be manufactured using mSAP techniques, may be formed between the first and the second metal layers of the main PCB and may be used for high speed signal routing between two dies, such as a system-on-chip die and a memory die, that are on the main PCB and coupled by the bridge PCB. Other embodiments may be described and/or claimed.
Embodiments of a microelectronic assembly comprise: a package substrate having a blind cavity between a first surface and a second opposing surface; a bridge die in the blind cavity, the blind cavity being open towards the first surface; and a plurality of integrated circuit (IC) dies coupled to the first surface and to the bridge die. The blind cavity has a floor and a plurality of sidewalls, at least one sidewall is at an obtuse angle to the floor, and the at least one sidewall is patterned with conductive traces.
H01L 23/482 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
28.
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH A COOLING MICROCHANNEL
Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a substrate with a microchannel, and a metallization stack with a conductive trace that is parallel to the first and second surfaces and exposed at the third surface; and a second IC die having a fourth surface, wherein the conductive trace exposed at the third surface of the first IC die is electrically coupled to the fourth surface of the second IC die by an interconnect.
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
29.
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AS A SOLID STATE BATTERY
Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including an active region including a capacitor; and a metallization stack including a first conductive trace electrically coupled to a first conductor of the capacitor and a second conductive trace electrically coupled to a second conductor of the capacitor, wherein the first conductive trace and the second conductive trace are parallel to the first and second surfaces and exposed at the third surface; and a second IC die including a fourth surface, where the first conductive trace and the second conductive trace at the third surface of the first IC die are electrically coupled to the fourth surface of the second IC die by interconnects.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
30.
DEVICE, METHOD AND SYSTEM TO SUPPORT A SYNCHRONOUS DATA FLOW WITH AN IDENTIFICATION OF AN EXECUTABLE TASK
Techniques and mechanisms for identifying a next task to be executed for an application which is modeled with a synchronous data flow (SDF) graph. In an embodiment, the SDF graph comprises nodes which each represent a different respective task, wherein the nodes variously exchange, via channels, tokens which represent data for operations of the application. A manager circuit manages and provides access to schedule registers which provide state information at a node-specific level of granularity. For a given node, a corresponding schedule register provides a status parameter which identifies whether the given node is currently qualified to be executed. The status parameter is based on one or more channel registers which each provide state information at a channel-specific level of granularity. In another embodiment, a processor comprises circuitry to send to the manager circuit a request to identify, based on the schedule registers, a next task to be executed.
Various embodiments herein provide techniques for configuring and/or using a measurement gap (MG) for a positioning reference signal (PRS) measurement. For example. a user equipment (UE) may receive a configuration of a pre-configured measurement gap; identify that a measurement gap is needed for a positioning reference signal (PRS) measurement and that the CE has not previously notified a network of the PRS measurement prior to receipt of the configuration; and encode, based on the identification, a location measurement indication for transmission to a network entity to indicate that the PRS measurement is to be performed. Other embodiments may be described and claimed.
Various embodiments herein provide techniques to enable communication between a user equipment (UE) microservice and a microservice of a wireless cellular network via service mesh. A first solution is described, in which the service mesh is in the network, and the network includes a service mesh proxy to communicate with the UE. A second solution is also described, in which the UE is part of the cellular network service mesh and includes a service mesh proxy in the UE. Other embodiments may be described and claimed.
H04L 67/61 - Ordonnancement ou organisation du service des demandes d'application, p. ex. demandes de transmission de données d'application en utilisant l'analyse et l'optimisation des ressources réseau requises en tenant compte de la qualité de service [QoS] ou des exigences de priorité
H04L 67/56 - Approvisionnement des services mandataires
34.
DYNAMIC TRIPLET CONVOLUTION FOR CONVOLUTIONAL NEURAL NETWORKS
Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement dynamic triplet convolution for convolutional neural networks are disclosed. An example apparatus disclosed herein for a convolutional neural network is to calculate one or more scalar kernels based on an input feature map applied to a layer of the convolutional neural network, ones of the one or more scalar kernels corresponding to respective dimensions of a static multidimensional convolutional filter associated with the layer of the convolutional neural network. The disclosed example apparatus is also to scale elements of the static multidimensional convolutional filter along a first one of the dimensions based on a first one of the one or more scalar kernels corresponding to the first one of the dimensions to determine a dynamic multidimensional convolutional filter associated with the layer of the convolutional neural network.
Methods, apparatus, systems, and articles of manufacture are disclosed for teacher-free self-feature distillation training of machine-learning (ML) models. An example apparatus includes at least one memory, instructions, and processor circuitry to at least one of execute or instantiate the instructions to perform a first comparison of (i) a first group of a first set of feature channels (FCs) of an ML model and (ii) a second group of the first set, perform a second comparison of (iii) a first group of a second set of FCs of the ML model and one of (iv) a third group of the first set or a first group of a third set of FCs of the ML model, adjust parameter(s) of the ML model based on the first and/or second comparisons, and, in response to an error value satisfying a threshold, deploy the ML model to execute a workload based on the parameter(s).
Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
Various embodiments herein provide techniques for multiple physical random access channel (PRACH) transmissions. For example, embodiments provide techniques to determine a random access response (RAR) window and/or a random access (RA)—radio network temporary identifier (RNTI) for multiple PRACH transmissions. Furthermore, embodiments relate to multiple PRACH transmissions triggered by physical downlink control channel (PDCCH) order. Other embodiments may be described and claimed.
H04W 74/0833 - Procédures d’accès aléatoire, p. ex. avec accès en 4 étapes
H04W 72/23 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
39.
MICROELECTRONIC COMPONENT HAVING MOLDED REGIONS WITH THROUGH-MOLD VIAS
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/367 - Refroidissement facilité par la forme du dispositif
40.
METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES
Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
G01R 31/27 - Test de dispositifs sans les extraire physiquement du circuit dont ils font partie, p. ex. compensation des effets dus aux éléments environnants
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/14 - Supports, p. ex. substrats isolants non amovibles caractérisés par le matériau ou par ses propriétés électriques
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p. ex. marques de repérage, schémas de test
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
41.
AUTONOMOUS GENERATION OF NETWORK AND DEVICE CONFIGURATIONS
Described herein are technique to enable the autonomous generation of configurations for a network environment, including but not limited to an edge network of a datacenter. Additional embodiments include prompt-based generation of network and device configurations and neural network based systems for adaptive network management.
Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
43.
TEST AND REPAIR ARCHITECTURE FOR INTER AND INTRA CLUSTER DEFECTS
Embodiments disclosed herein include apparatuses for improved testing between chips. In an embodiment, an apparatus comprises a plurality of transmit clusters on a first chip, where individual ones of the plurality of transmit clusters comprise a set of transmit lanes on the first chip. In an embodiment, a plurality of finite state machines (FSMs) are on the first chip, where individual ones of the plurality of transmit clusters comprise one of the plurality of FSMs. In an embodiment, a global transmit test generator is communicatively coupled to each of the set of transmit lanes on the first chip, and a global transmit expected response generator is communicatively coupled to each of the plurality of FSMs on the first chip.
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
44.
SOCKET CONTACT PIN DEPOPULATION AND HOUSING CUT-OUT IN LOW S-G REGION FOR POST-RESONANCE CROSSTALK SUPPRESSION IN HIGH FREQUENCY APPLICATIONS
Embodiments disclosed herein include sockets and socket modules. In an embodiment, a socket module comprises a housing and a first pin through the housing in a first row of pins. In an embodiment, a second pin is through the housing in a second row of pins. In an embodiment, at least three intervening rows of pins are between the first row of pins and the second row of pins. In an embodiment, one or more pin locations in the at least three intervening rows of pins are depopulated.
Described herein is a graphics processor comprising first circuitry configured to execute a decoded instruction and second circuitry configured to second circuitry configured to decode an instruction into the decoded instruction. The second circuitry is configured to determine a number of registers within a register file that are available to a thread of the processing resource and decode the instruction based on that number of registers.
Techniques to form semiconductor device conductive interconnections. In an example, an integrated circuit includes a recessed via and a conductive bridge between a top surface of the recessed via and an adjacent source or drain contact. A transistor device includes a semiconductor material extending from a source or drain region, a gate structure over the semiconductor material, and a contact on the source or drain region. Adjacent to the source or drain region, a deep via structure extends in a vertical direction through an entire thickness of the gate structure. The via structure includes a conductive via that is recessed below a top surface of the conductive contact. A conductive bridge extends between the contact and the conductive via such that the conductive bridge contacts a portion of the contact and at least a portion of a top surface of the conductive via.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
47.
METHOD AND APPARATUS FOR DATA/INSTRUCTION ACCESS BASED ON PERFORMANCE HINTS
Methods, apparatus, and computer programs are disclosed for data/instruction access based on performance hints. In some embodiments, a method comprises decoding an instruction to access data or code by a core of a computer processor, the instruction to provide one or more hints on how the data or code is to be processed through a cache hierarchy of the computer processor based on the instruction, the one or more hints indicating which level of the cache hierarchy or which cache in a level of the cache hierarchy to load or store the data or code, a priority of the data or code in a cache, or how the data or code is to be shared among multiple cores of the computer processor. The method further comprises processing the data or code based on the one or more hints responsive to the decoded instruction.
An apparatus and system of establishing a Transmission Configuration Indication (TCI) state switch delay are described. The TCI state switch delay for a reference signal (RS) on a component carrier (CC) in intra-band carrier aggregation (CA) is dependent on whether a TCI state indicated in the DCI is known based on a type of Quasi Co-Location (QCL) and whether a common TCI state ID is known on the CC. The delay is known for a delay of QCL-typeD RS on the CC or any other QCL-typeD RS in the CC set that contains the CC. The delay may be based on that of a single CC delay, with the slot where the new TCI state applies determined based on a carrier with a smallest subcarrier spacing (SCS) in the CC or the CC set.
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
For example, a wireless communication device may be configured to generate a wide bandwidth Long Training Field (LTF) configured for channel sounding over a wide channel bandwidth of at least 320 Megahertz (MHz). For example, the wide bandwidth LTF may include a plurality of Orthogonal Frequency Division Multiplexing (OFDM) symbols over the wide channel bandwidth. For example, the wireless communication device may be configured to transmit a Null Data Packet (NDP) over the wide channel bandwidth. For example, the NDP may include a non-High-Throughput (non-HT) Short Training Field (L-STF), a non-HIT LTF (L-LTF) after the L-STF, a non-HT Signal (L-SIG) field after the L-LTF, a Repeated L-SIG (RL-SIG) field after the L-SIG field, and the wide bandwidth LTF after the RL-SIG field.
A system includes memory circuitry to store a secure shared memory buffer (SSMB) and instructions; and a processor to create the SSMB in the memory circuitry and assign ownership of the SSMB to an SSMB owner, the SSMB owner being a trusted execution environment virtual machine running on the computing system; configure access permissions for the SSMB by the SSMB owner to allow one or more SSMB users to access the SSMB, the one or more SSMB users being trusted execution environment virtual machines running on the computing system; allocate memory by the SSMB owner from the SSMB owner's private memory space in the memory circuitry for the SSMB; and allowing secure access by the one or more SSMB users to the SSMB in response to successfully verifying authorization of the one or more SSMB users based at least in part on the access permissions.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 21/53 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p. ex. "boîte à sable" ou machine virtuelle sécurisée
In one embodiment, a display panel may have multiple regions that are controlled by independent driver circuitries to allow for independent refreshing of different regions. Circuitry, e.g., in a graphics source or in the display, can determine, based on a partial frame update, which panel regions to refresh and refresh those regions, e.g., while not refreshing other regions of the panel.
G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
52.
METHOD, APPARATUS, AND COMPUTER-READABLE MEDIUM FOR RECONFIGURING AN ACTIVE REGION OF A DISPLAY
A method, apparatus, and non-transitory computer-readable medium or reconfiguring an original active region of a first display is disclosed. The apparatus comprises interface circuitry for communication with both the first and second displays, memory circuitry, machine-readable instructions, and processor circuitry configured to execute the machine-readable instructions. The processor circuitry is operable to determine a subset active region within the original active region of the first display and to generate a hint for configuring the second display based on this subset active region.
G06F 3/14 - Sortie numérique vers un dispositif de visualisation
G06F 21/10 - Protection de programmes ou contenus distribués, p. ex. vente ou concession de licence de matériel soumis à droit de reproduction
G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.
Various approaches for the deployment and use of communication exclusion zones, defined for use with a satellite non-terrestrial network (including within a low-earth orbit satellite constellation), are discussed. In an example, defining and implementing a non-terrestrial communication exclusion zone includes: calculating based on a future orbital position of a low-earth orbit satellite vehicle, an exclusion condition for communications from the satellite vehicle; identifying, based on the exclusion condition and the future orbital position, a timing for implementing the exclusion condition for the communications from the satellite vehicle; and generating exclusion zone data for use by the satellite vehicle, the exclusion zone data indicating the timing for implementing the exclusion condition for the communications from the satellite vehicle.
Examples described herein relate to a cold plate. An example apparatus includes a first layer with one or more channels to receive fluid. The example apparatus further includes a second layer that is more rigid than the first layer. The second layer is to be mounted to the first layer and separated from the first layer by a gasket to reduce corrosion of the second layer.
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p. ex. condensation
H01L 21/308 - Traitement chimique ou électrique, p. ex. gravure électrolytique en utilisant des masques
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
H01L 29/167 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée caractérisés en outre par le matériau de dopage
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
Methods and apparatus relating to tall Dual Inline Memory Module (DIMM) structural retention are described. In one embodiment, a Dual In-Line Memory Module (DIMM) retention frame is coupled to a top portion of a tall (e.g., “two unit” or taller) DIMM. A plurality of fasteners physically attach the DIMM retention frame to a Printed Circuit Board (PCB). The DIMM retention frame reduces movement of the tall DIMM. Other embodiments are also claimed and disclosed.
Provided is a non-transitory machine-readable medium including machine-readable instructions. The machine-readable instructions cause, when executed on an apparatus, the apparatus to receive, by a trusted authority, a request for access to user data stored on a distributed network. The machine-readable instructions further cause the apparatus to search, by the trusted authority, an immutable ledger for an entry related to the user data. The machine-readable instructions further cause the apparatus to selectively decide, by the trusted authority and based on an access policy for the user data indicated by the entry, whether to grant access to the user data.
Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.
H01F 5/04 - Dispositions des connexions électriques aux bobines, p. ex. fils de connexion
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
An apparatus includes a host interface; a network interface; and a programmable circuitry communicably coupled to the host interface and the network interface, the programmable circuitry comprising one or more processors to implement network interface functionality and to: determine portions of a set of computer vision (CV) processes to be deployed on the programmable circuitry and a host device, wherein the host device to be communicably coupled to the programmable network interface device; access instructions to cause the portions of the set of the CV processes to be deployed on the host device and the programmable network interface device; and wherein a media processing portion of the set of the CV processes is to be deployed to the programmable circuitry, and wherein the programmable circuitry is to utilize media processing hardware circuitry hosted by the apparatus to perform the media processing portion.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, a method for forming an IC package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second dielectric material, having a surface, on the first dielectric material; and forming a second conductive via in the second dielectric material, wherein the second conductive via is electrically coupled to the first conductive via, has tapered sidewalls with an angle that is greater than 80 degrees relative to the surface of the second dielectric material, and a maximum diameter between 2 microns and 20 microns.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/498 - Connexions électriques sur des substrats isolants
Management of data transfer for network operation is described. An example of an apparatus includes one or more network interfaces and a circuitry for management of data transfer for a network, wherein the circuitry for management of data transfer includes at least circuitry to analyze a plurality of data elements transferred on the network to identify data elements that are delayed or missing in transmission on the network, circuitry to determine one or more responses to delayed or missing data on the network, and circuitry to implement one or more data modifications for delayed or missing data on the network, including circuitry to provide replacement data for the delayed or missing data on the network.
Methods and apparatus relating to techniques for region-based deterministic memory safety are described. In some embodiment, one or more instructions may be used to encrypt, decrypt, and/or check a pointer to a portion of the data stored in memory. The portion of the data is stored in a first region of the memory. The first region of the memory includes a plurality of identically sized allocation slots. Other embodiments are also disclosed and claimed.
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p. ex. les mémoires adressables directement
G06F 12/0871 - Affectation ou gestion d’espace de mémoire cache
Embodiments herein relate to systems, apparatuses, techniques or processes for packages that include a glass substrate, with one or more photonic integrated circuits embedded into cavities within the glass substrate. Dies may be on the glass substrate and electrically coupled with the embedded photonic integrated circuits. Photonic wire bonds may optically couple the embedded photonic integrated circuits with one or more optical waveguides that are within the glass substrate. Other embodiments may be described and/or claimed.
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/13 - Circuits optiques intégrés caractérisés par le procédé de fabrication
65.
METHODS, SYSTEM, ARTICLES OF MANUFACTURE, AND APPARATUS TO MANAGE TELEMETRY DATA IN AN EDGE ENVIRONMENT
Methods, apparatus, systems and articles of manufacture are disclosed to manage telemetry data in an edge environment. An example apparatus includes a publisher included in a first edge platform to publish a wish list obtained from a consumer, the wish list including tasks to execute, a commitment determiner to determine whether a commitment is viable to execute at least one of the tasks in the wish list, the commitment to be processed to identify the telemetry data, and a communication interface to establish a communication channel to facilitate transmission of the telemetry data from the first edge platform to a second edge platform.
Described herein is a graphics processor comprising a graphics processing cluster coupled with the memory interface, the graphics processing cluster including a plurality of processing resources, a processing resource of the plurality of processing resources including a register file including a first plurality of registers associated with a first hardware thread of a plurality of hardware threads of the processing resource and a second plurality of registers associated with a second hardware thread of the plurality of hardware threads of the processing resource and first circuitry configured to facilitate access to memory on behalf of the plurality of hardware threads and store metadata for memory access requests from the plurality of hardware threads.
Systems, apparatus, articles of manufacture, and methods are disclosed to manage and securely store platform service records. An apparatus for monitoring a compute device, the apparatus comprising interface circuitry, non-volatile flash memory, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to analyze telemetry data obtained via a sensor of the compute device, the analyzing of the telemetry data to detect an undesired event, and storing, in response to detection of the undesired event, the telemetry data in a ledger, wherein the ledger is digitally signed to prevent unauthorized modification and stored in the non-volatile flash memory.
It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to generate a first attestation measurement of a runtime image executed in a confidential computing environment at a first point in time. The machine-readable instructions further include instructions to store the first attestation measurement as baseline attestation measurement in a storage circuitry. The machine-readable instructions further include instructions to generate a second attestation measurement of the runtime image executed in confidential computing environment at a second point in time. The machine-readable instructions further include instructions to generate an attestation evidence report based on the baseline attestation measurement and the second attestation measurement.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
G06F 21/64 - Protection de l’intégrité des données, p. ex. par sommes de contrôle, certificats ou signatures
69.
APPARATUS, SYSTEM, AND METHOD OF FORWARD ERROR CORRECTION (FEC) CODING
For example, a STA may determine a pre-FEC padding factor value for a PPDU, the pre-FEC padding factor value in a range between 1 and 2Na, wherein Na is an integer greater than 2; set Na bits in a Signal (SIG) field of the PPDU to indicate the pre-FEC padding factor value; and encode a data field of the PPDU according to a FEC coding based on the pre-FEC padding factor value. For example, a STA may encode a data field of a PPDU according to a FEC coding based on a pre-FEC padding factor value and based on a condition that no post-FEC padding is to be applied for the PPDU; and set an LDPC extra symbol subfield in a SIG field of the PPDU to indicate whether or not an LDPC extra symbol is present based on encoding of the data field of the PPDU.
An apparatus and method are described for performance-optimal frequency selection. For example, one embodiment of a processor comprises: a plurality of different types of intellectual property (IP) circuit blocks including a first type of IP circuit blocks and at least a second type of IP circuit blocks; power management circuitry to perform operations to determine voltages and frequencies at which to operate the plurality of different types of IP circuit blocks, the operations including: determining a plurality of voltage/frequency combinations for the first type of IP circuit block based on stored voltage/frequency curve data; determining maximum frequency values for the second type of IP circuit blocks corresponding to one or more of the plurality of voltage/frequency combinations, the maximum frequency values based on the stored voltage/frequency curve data; adjusting one or more of the maximum frequency values based on one or more corresponding stored scalar values to determine final maximum frequency values for each of the second type of IP circuit blocks; and causing the first type of IP circuit blocks to operate at one of the plurality of voltage/frequency combinations and responsively causing one or more of the second type of IP circuit blocks to operate at a corresponding final maximum frequency value.
This disclosure describes systems, methods, and devices related to video encoding using macroblock mode prediction. A device may input features of a macroblock of pixels of a video frame to a logistic regression machine learning model trained to predict an encoding cost of a sub-block of the macroblock; generate, based on a logistic regression using the logistic regression machine learning model and the input features, a value indicating that the sub-block is to be used or not used as a partition for the macroblock; generate, using a decision tree machine learning model, a selection of an intra prediction mode for encoding the video frame, wherein a respective node of the decision tree machine learning model selects either to perform or skip a respective intra prediction mode; select an inter prediction mode or an intra prediction mode based on the value and the selection; and encode the video frame.
H04N 19/149 - Débit ou quantité de données codées à la sortie du codeur par estimation de la quantité de données codées au moyen d’un modèle, p. ex. un modèle mathématique ou un modèle statistique
72.
PHOTONICS INTEGRATED CIRCUIT EMBEDDED IN A GLASS SUBSTRATE AND OPTICALLY COUPLED WITH A PHOTONIC WIRE BOND
Embodiments herein relate to systems, apparatuses, techniques or processes for packages that include a glass substrate, with one or more photonic integrated circuits embedded into cavities within the glass substrate. Dies may be on the glass substrate and electrically coupled with the embedded photonic integrated circuits. Photonic wire bonds may optically couple the embedded photonic integrated circuits with one or more optical waveguides that are within the glass substrate. Other embodiments may be described and/or claimed.
Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second IC die including a fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die by an interconnect including solder.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
74.
APPARATUS, SYSTEM, AND METHOD OF CONFIGURING RATE-DEPENDENT PARAMETERS FOR TRANSMISSION OF A PHYSICAL LAYER (PHY) PROTOCOL DATA UNIT (PPDU)
For example, a wireless communication station (STA) may be configured to determine a selected setting of one or more rate-dependent parameters for transmission of a Physical layer (PHY) Protocol Data Unit (PPDU) based on a minimal Medium Access Control (MAC) Protocol Data Unit (MPDU) size requirement such that, for at least one MPDU of the PPDU, a first count of MAC padding bits to pad the MPDU according to the selected setting of the one or more rate-dependent parameters is less than a second count of MAC padding bits to pad the MPDU according to a channel-based setting of the one or more rate-dependent parameters, wherein, the channel-based setting of the one or more rate-dependent parameters is based on a condition of a wireless communication channel for transmission of the PPDU; and to transmit the PPDU according to a transmission data rate based on the selected setting.
One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.
Embodiments are generally directed to methods and apparatuses of spatially sparse convolution module for visual rendering and synthesis. An embodiment of a method for image processing, comprising: receiving an input image by a convolution layer of a neural network to generate a plurality of feature maps; performing spatially sparse convolution on the plurality of feature maps to generate spatially sparse feature maps; and upsampling the spatially sparse feature maps to generate an output image.
G06F 18/2136 - Extraction de caractéristiques, p. ex. en transformant l'espace des caractéristiquesSynthétisationsMappages, p. ex. procédés de sous-espace basée sur des critères de parcimonie, p. ex. avec une base trop complète
A method and apparatus for authentication of a user. A user profile is generated during an initial registration. The user profile may include a trusted location of the user. During a subsequent authentication process for the user, it is determined whether the user is located in the trusted location of the user, and an access to a service for the user may be controlled based on a result of the authentication process and the determination whether the user is located in the trusted location of the user. A location-based parameter of the trusted location of the user may be determined and stored in advance, and it is determined whether the user is located in the trusted location of the user by comparing the location-based parameter of the current location of the user and the location-based parameter of the trusted location of the user.
A data processing unit may include a memory, processing elements (PEs), and a control unit. The memory may store weight blocks within a weight tensor of a neural network operation. Each weight block has an input channel (IC) dimension and an output channel (OC) dimension and includes subblocks. A subblock includes one or more weights having a first data precision and one or more other weights having a second data precision. The second data precision is lower than the first data precision. The control unit may distribute different ones of the subblocks to different ones of the PEs. A PE may receive a subblock and perform a first MAC operation on a weight having a first data precision and a second MAC operation on a weight having a second data precision. The first MAC operation may consume more computation cycles or more multipliers than the second MAC operation.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p. ex. la justification, le changement d'échelle, la normalisation
80.
DYNAMIC QUANTIZATION AND MEMORY MANAGEMENT OF KEY-VALUE CACHE FOR SERVING LARGE LANGUAGE MODELS
Key-value (KV) cache paging schemes can improve memory management for KV caches by storing a KV cache page having key tensors and value tensors for a fixed number of tokens in a fixed-sized block in the KV cache of a worker. To further improve memory management, the schemes can be modified to implement dynamic variable quantization. Quantization level of a KV cache page can be set based on a runtime importance score of the KV cache page. In addition, the quantization level of the KV cache page can be set based on the system load. The end result is a scheme that can achieve a high compression ratio of KV cache pages in the KV cache. Fitting more KV cache pages in the KV cache can lead to higher inference throughput, higher system-level user capacity, and higher end-to-end service availability.
Various embodiments herein provide techniques related to registering a user equipment (UE) with a wireless network based on a blockchain identity (BI) of the UE. In embodiments, the BI, or a derived key thereof, may be used to sign a cryptographic challenge provided by the network, wherein the challenge is based on the BI. Other embodiments may be described and/or claimed.
An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to sparsify a base model of a foundation model to generate a sparse base model, apply a neural low-rank adapter search to the sparse base model, and output a fine-tuned base model based on application of the neural low-rank adapter search to the sparse base model.
This disclosure describes systems, methods, and devices related to optimized resource technologies. A device may create a Managed Object Instance (MOI) representing actions executed based on artificial intelligence or machine learning (AI/ML) inference function. The device may notify a management and network service (MnS) consumer about the creation of the MOI. The device may execute actions by a network or management function acting as the consumer of the inference output. The device may manage performance of the AI/ML inference function.
H04L 41/16 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p. ex. des réseaux de commutation de paquets en utilisant l'apprentissage automatique ou l'intelligence artificielle
H04L 41/5067 - Mesures de la qualité du service [QoS] centrées sur le client
84.
NON-TRANSITORY MACHINE-READABLE STORAGE MEDIUM, METHOD AND APPARATUS FOR CHAT MANAGEMENT
Provided is a computer-readable medium including computer-readable instructions. When the instructions are executed by a computer, the computer may implement a method. According to this method, contextual information of a plurality of users in a conversation is generated based on messages from the plurality of users over a period of time. Then the contextual information of the plurality of users is sent to a first artificial intelligence (AI) language model as input for training the AI language model and a request is sent to the first AI language model, wherein the request requires a response associated with the contextual information.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
A dual inline memory module (DIMM) connector has pins to connect to pad footprints and signal routing that reduces crosstalk and noise. The shape and placement of ground pads and signal pads can improve grounding of noise signals and improve the signal isolation on the signal pins. The ground pads can have additional ground vias to increase the ground path to the ground plane.
H01R 13/6471 - Moyens pour empêcher la diaphonie par agencement particulier des conducteurs de mise à la masse et de signaux, p. ex. GSGS [mise à la masse - signal - mise à la masse - signal]
G06F 1/18 - Installation ou distribution d'énergie
A dual inline memory module (DIMM) connector has pins to connect to pad footprints and signal routing that reduces crosstalk and noise. The signals pins are staggered with alternating signal pins being longer and shorter. Longer pins have corresponding signal pads on the system board farther away from the connector than corresponding signals pads for the shorter pins.
H05K 1/11 - Éléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
G06F 1/18 - Installation ou distribution d'énergie
G11C 5/04 - Supports pour éléments d'emmagasinageMontage ou fixation d'éléments d'emmagasinage sur de tels supports
H01R 12/72 - Dispositifs de couplage pour circuits imprimés rigides ou structures similaires se couplant avec la bordure des circuits imprimés rigides ou des structures similaires
H01R 12/73 - Dispositifs de couplage pour circuits imprimés rigides ou structures similaires se couplant avec la bordure des circuits imprimés rigides ou des structures similaires se raccordant à d'autres circuits imprimés rigides ou à des structures similaires
H01R 13/24 - Contacts pour coopération par aboutage élastiquesContacts pour coopération par aboutage montés élastiquement
H01R 13/6471 - Moyens pour empêcher la diaphonie par agencement particulier des conducteurs de mise à la masse et de signaux, p. ex. GSGS [mise à la masse - signal - mise à la masse - signal]
87.
ENHANCED CODE RATE REDUCTION FOR PROBABILISTIC CONSTELLATION SHAPING IN WIRELESS COMMUNICATIONS
This disclosure describes systems, methods, and devices for probabilistic constellation shaping in wireless transmissions may include a device configured to generate, using a first quadrature amplitude modulation (QAM) order shaping encoder associated with a first code rate, shaped amplitude bits; generate, using a forward error correcting (FEC) encoder and a second code rate smaller than the first code rate, parity bits for the shaped amplitude bits; cause to transmit, using a channel, a first portion of the parity bits as sign bits for the shaped amplitude bits; and cause to transmit, using the channel, a second portion of the parity bits.
Methods, apparatus, systems and articles of manufacture for distributed use of a machine learning model are disclosed. An example edge device includes a model partitioner to partition a machine learning model received from an aggregator into private layers and public layers. A public model data store is implemented outside of a trusted execution environment of the edge device. The model partitioner is to store the public layers in the public model data store. A private model data store is implemented within the trusted execution environment. The model partitioner is to store the private layers in the private model data store.
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès
G06F 16/951 - IndexationTechniques d’exploration du Web
G06F 18/21 - Conception ou mise en place de systèmes ou de techniquesExtraction de caractéristiques dans l'espace des caractéristiquesSéparation aveugle de sources
G06F 18/2411 - Techniques de classification relatives au modèle de classification, p. ex. approches paramétriques ou non paramétriques basées sur la proximité d’une surface de décision, p. ex. machines à vecteurs de support
G06F 21/74 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information opérant en mode dual ou compartimenté, c.-à-d. avec au moins un mode sécurisé
G06N 3/04 - Architecture, p. ex. topologie d'interconnexion
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
Various aspects of techniques, systems, and use cases for robot movement within human-robot collaboration (HRC) areas are disclosed. Convex free-space regions around points of interest in the HRC are detected and updated using one or more sensors. Collision-free motion plans for robots use a Hierarchical Convex Polytope (HCP) region in which the robot is removed from the occupied space in the scene using depth cameras.
G05B 19/4155 - Commande numérique [CN], c.-à-d. machines fonctionnant automatiquement, en particulier machines-outils, p. ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'un programme sous forme numérique caractérisée par le déroulement du programme, c.-à-d. le déroulement d'un programme de pièce ou le déroulement d'une fonction machine, p. ex. choix d'un programme
For example, a wireless communication station (STA) may be configured to determine a usage-based channel Bandwidth (BW) setting, for example, based on a link-usage parameter corresponding to a usage of a wireless communication link for communication of traffic between the STA and an Access Point (AP). For example, the STA may be configured to transmit a channel BW reduction request to the AP, for example, based on a determination that the usage-based channel BW setting is less than an operating channel BW setting for the STA. For example, the channel BW reduction request may be configured to request the AP to reduce the operating channel BW setting for the STA based on the usage-based channel BW setting.
Embodiments of a semiconductor die comprise: a first bond-pad on a first surface to couple to a package substrate, a second bond-pad on a second surface, the second surface being opposite to the first surface, a hole through the semiconductor die, a conductive pillar within the hole separated from sidewalls of the hole by an air gap, the conductive pillar coupled to the first bond-pad and the second bond-pad, and pathways conductively coupling at least two integrated circuit (IC) dies proximate to the second surface.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
Photonic devices, packages, and systems with sub-surface compound microlenses are disclosed. An example microlens structure includes a glass core and a microlens stack embedded in the glass core, the stack comprising a plurality of regions stacked a direction of propagation of light that is to be manipulated by the microlens structure, wherein each region is a region of a substantially uniform refractive index that is different from the refractive index of the glass core. Such a stack may be referred to as a “sub-surface compound microlens,” where the term “sub-surface” is indicative of the fact that the stack may be below all surfaces of the glass core (i.e., is embedded in the glass core) and the term “compound” is indicative of the fact that the stack is a compound arrangement of multiple regions (e.g., each region is an individual microlens).
Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second IC die including a fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die by an interconnect including solder.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
94.
APPARATUS, SYSTEM, AND METHOD OF CONFIGURING RATE-DEPENDENT PARAMETERS FOR TRANSMISSION OF A PHYSICAL LAYER (PHY) PROTOCOL DATA UNIT (PPDU)
For example, a wireless communication station (STA) may be configured to determine a selected setting of one or more rate-dependent parameters for transmission of a Physical layer (PHY) Protocol Data Unit (PPDU) based on a minimal Medium Access Control (MAC) Protocol Data Unit (MPDU) size requirement such that, for at least one MPDU of the PPDU, a first count of MAC padding bits to pad the MPDU according to the selected setting of the one or more rate-dependent parameters is less than a second count of MAC padding bits to pad the MPDU according to a channel-based setting of the one or more rate-dependent parameters, wherein, the channel-based setting of the one or more rate-dependent parameters is based on a condition of a wireless communication channel for transmission of the PPDU; and to transmit the PPDU according to a transmission data rate based on the selected setting.
H04W 72/23 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04W 80/02 - Protocoles de couche liaison de données
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
95.
APPARATUS, SYSTEM, AND METHOD OF CURRENT CONSUMPTION ADJUSTMENT
For example, a current consumption adjuster may be configured to adjust a current consumption from a power supply of an integrated circuit. For example, the current consumption adjuster may include a controllable load circuitry to controllably apply one or more loads to the power supply of the integrated circuit. For example, the current consumption adjuster may include a controller configured to identify a current consumption event including a transition of a current consumption of the integrated circuit from the power supply. For example, the controller may be configured to control activation of the controllable load circuitry to apply an event-based load to the power supply, for example, based on the current consumption event.
For example, a wireless communication station (STA) may be configured to determine a usage-based channel Bandwidth (BW) setting, for example, based on a link-usage parameter corresponding to a usage of a wireless communication link for communication of traffic between the STA and an Access Point (AP). For example, the STA may be configured to transmit a channel BW reduction request to the AP, for example, based on a determination that the usage-based channel BW setting is less than an operating channel BW setting for the STA. For example, the channel BW reduction request may be configured to request the AP to reduce the operating channel BW setting for the STA based on the usage-based channel BW setting.
H04W 72/0453 - Ressources du domaine fréquentiel, p. ex. porteuses dans des AMDF [FDMA]
H04W 72/0457 - Affectation de bande ou de débit variable
H04W 72/0446 - Ressources du domaine temporel, p. ex. créneaux ou trames
H04W 72/543 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de qualité sur la base de la qualité demandée, p. ex. QdS [QoS]
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
97.
FLOATING POINT ACCURACY CONTROL VIA DYNAMIC EXPONENT AND MANTISSA BIT CONFIGURATIONS
Systems, apparatuses and methods may provide for technology that determines a tensor distribution of a machine learning model on a per-layer basis, sets a floating point format of the machine learning model based on the tensor distribution, wherein the floating point format is variable on the per-layer basis, and generates an inference output from the machine learning model in accordance with the floating point format.
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p. ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
98.
RECEPTION OF NEW RADIO (NR) MULTICAST AND BROADCAST SERVICE (MBS) CONTROL AND DATA IN THE DOWNLINK
Various embodiments herein provide techniques related to downlink multicast and broadcast service (MBS) data and control. In embodiments, abase station may identify, based on an active bandwidth part (BWP) of a user equipment (UE), a transmission control indicator (TCI) state list configuration related to a unicast transmission to the UE; and transmit the multicast or broadcast transmission based on the TCI state list. Other embodiments may be described and/or claimed.
H04W 72/30 - Gestion des ressources des services de diffusion
H04W 72/0453 - Ressources du domaine fréquentiel, p. ex. porteuses dans des AMDF [FDMA]
H04W 72/23 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal
Systems, apparatuses, methods, and computer-readable media are provided for dynamic hybrid automatic repeat request (HARQ)-acknowledgement (ACK) feedback for multi-cell scheduling (e.g., a downlink control information (DCI) that schedules physical downlink shared channels (PDSCHs) and/or physical uplink shared channels (PUSCHs) on multiple cells). Embodiments may include techniques to determine a downlink assignment index (DAI) and/or a HARQ-ACK codebook, e.g., a Type-1. Type-2, and/or Type-3 codebook, for multi-cell scheduling. Other embodiments may be described and claimed.
H04L 1/1867 - Dispositions spécialement adaptées au point d’émission
H04W 72/1273 - Jumelage du trafic à la planification, p. ex. affectation planifiée ou multiplexage de flux de flux de données en liaison descendante
H04W 72/232 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal les données de commande provenant de la couche physique, p. ex. signalisation DCI
A method comprises establishing, in a trusted security manager of a trusted execution environment, a device update pre-authentication policy for a device communicatively coupled to the trusted execution manager, providing the device update pre-authentication policy to the device, receiving, from the device, a pre-authentication event signal, and providing, to the device, a pre-authentication event response comprising an update indicator to indicate to the device whether a runtime update may be performed.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/53 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p. ex. "boîte à sable" ou machine virtuelle sécurisée
G06F 21/54 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
