A 3D memory device includes a memory patch with memory cells organized in a 3D array. The memory cells are coupled to local digit lines which are coupled in sets to global digit lines. The global digit lines are coupled to sense amplifiers. The sense amplifiers are in a sense amplifier region which is positioned above the memory patch. The sense amplifiers may be arranged in a grid of multiple columns and at least two rows. The global digit lines may be coupled to their respective sense amplifiers by vertical conductive elements. The sense amplifiers may have two contact pads coupling them to two global digit lines, and the contact pads may be arranged on a same side of the sense amplifier.
Disclosed herein are methods, apparatuses and systems including thickness control mechanisms. The thickness control mechanisms may correspond to electrical insulators deposited into trenches that are formed on a semiconductor substrate. After forming circuits on the semiconductor substrate, the substrate may be thinned on an opposing side until the thickness control mechanisms are exposed. Prior to thinning, the substrate can be attached to a carrier with a layer of insulative material disposed between the substrate and carrier. The attached structure may correspond to a silicon on insulator (SOI) structure.
This disclosure is directed to a system for dynamically suspending erase operations on a memory device. The system determines a queue depth of pending host read commands while an erase operation is in progress on a memory device. The system determines whether the queue depth transgresses a threshold value. The system, in response to determining whether the queue depth transgresses the threshold value, selects an erase suspend operation from a plurality of erase suspend operation types and suspends the erase operation on the memory device using the selected erase suspend operation.
A 3D memory device includes a plurality of global digit line pairs. Each global digit line pair may generally be stacked with one global digit line of the pair above the other. Along the length of a global digit line pair there may be one or more twist regions. Within a twist region, the global digit line pair exchanges which global digit line is on top and which is on bottom. Within the twist region, at least one of the global digit lines couples to a transfer element which is offset from the twisting global digit line. To accommodate this, the adjacent global digit line pair may be shunted to have one of the global digit lines run in a shunt layer different than the layer with the transfer element.
A 3D memory device includes memory banks. During refresh operations, responsive to a refresh signal and refresh address directed to a given bank, one or more word lines in a first portion of the bank are refreshed at a first time and one or more word lines in a second portion of the bank are refreshed at a second time after the first time. For example, one or more row control circuits associated with the bank provide a first sense amplifier enable signal to the first portion and a second sense amplifier enable signal to the second portion. The second sense amplifier enable signal is provided through a delay circuit to stagger the two signals in time.
Methods, systems, and devices for virtual block structure for random read operations are described. A memory system may implement sub-virtual blocks within each virtual block of the memory system. To use an implemented sub-virtual block architecture, the memory system may write to a first sub-virtual block of a virtual block before writing to a second sub-virtual block of the virtual block. The memory system may perform various access operations at the non-volatile memory of the memory system by accessing the first sub-virtual block or the second sub-virtual block of the virtual block. In some examples, after writing to and reading from the sub-virtual blocks, the memory system may perform an erase operation on all sub-virtual blocks of the virtual block simultaneously.
Apparatuses and techniques for implementing usage-based-disturbance alert signaling are described. The technology allows usage-based-disturbance (UBD) alerts to be externally communicated from a memory device without a dedicated external interface. Rather, UBD alerts are combined with memory error/alert signals and communicated on a shared alert-related interface. UBD tracking occurs at the memory bank level, with corresponding independent UBD alert signals. These signals are efficiently combined to generate an overall UBD alert. A temporary backoff signal is generated when an overall UBD alert is sent. The backoff signal ensures requisite external timing parameters are met while allowing the individual memory banks to generate persistent UBD alerts.
Methods, systems, and devices for programming verification in a memory system are described. A memory system may increase, during a programming operation for a word line, the voltage applied to the word line from a first level to a second level higher than the first level, where a set of memory cells coupled with the word line is attempted to be written with a set of multi-bit values based on increasing the voltage to the second level. The memory system may decrease, during a verification operation for the programming operation, the voltage applied to the word line to a third level lower than the first level. The memory system may determine whether the set of memory cells has been written with the set of multi-bit values based on decreasing the voltage applied to the word line.
Methods, systems, and devices for bank-configurable power modes are described. Aspects include operating a memory device that has multiple memory banks in a first mode. While operating in the first mode, the memory device may receive a command to enter a second mode having a lower power consumption level than the first mode. The memory device may enter the second mode by switching a first subset of the memory banks to a first low power mode that operates at a first power consumption level and a second subset of the memory banks to a second low power mode that operates at a second power consumption level that may be lower than the first power consumption level. In some cases, the memory device may switch the first subset of memory banks from the first low power mode while maintaining the second subset of memory banks in the low power mode.
G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
G06F 1/28 - Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
G06F 1/3234 - Power saving characterised by the action undertaken
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
10.
RESET TECHNIQUES FOR PROTOCOL LAYERS OF A MEMORY SYSTEM
Methods, systems, and devices for reset techniques for protocol layers of a memory system are described. A communications link may be established between a host system and the memory system. In some examples, the communications link may be based on one or more first parameters associated with a first protocol layer and one or more second parameters associated with a second protocol layer. The system may support communication (e.g., from the host system to the memory system) of an indication to reset the communications link, and the host system, the memory system, or both may reset the one or more first parameters based on communicating the indication to reset the communications link. The host system and memory system may attempt to reestablish the communications link based on resetting the one or more first parameters and maintaining the one or more second parameters.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
11.
HIGH-SPEED SIGNAL STABILIZATION IN A COMMON SUBSTRATE
A device includes a circuit substrate comprising a plurality of signal traces that form a differential pair of signal lines, including a first differential signal line and a second differential signal line; a first die arranged on the circuit substrate, wherein the first die is coupled to the differential pair of signal lines; a second die arranged on the circuit substrate, wherein the second die is coupled to the differential pair of signal lines; a first surface-mounted resistor arranged on the circuit substrate, wherein the first surface-mounted resistor is configured to provide a first jumper connection, between the first die and the second die, along the first differential signal line; and a second surface-mounted resistor arranged on the circuit substrate, wherein the second surface-mounted resistor is configured to provide a second jumper connection, between the first die and the second die, along the second differential signal line.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
This disclosure is directed to a system for fast-cycling a memory device. The system receives a fast-cycling start command to initiate a fast-cycling mode for the set of memory devices, the fast-cycling mode accelerating program-erase counts (PECs) of memory blocks to an end-of-life (EOL) condition, the EOL condition comprising a threshold number of PECs. The system, in response to receiving the fast-cycling start command, enables a standalone mode for an individual memory device of the set of memory devices that prevents the individual memory device from servicing host input/output requests. The system executes fast-cycling operations on the individual memory device until the EOL condition is satisfied.
G06F 11/18 - Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits, e.g. by quadding or by majority decision circuits
A 3D memory device includes a memory patch with memory cells organized in a 3D array. The memory cells are coupled together by local digit lines, and sets of local digit lines are coupled to global digit lines through respective multiplexer circuits. Multiplexer drivers provide multiplexer control signals to sets of the multiplexer circuits. The multiplexer drivers may be positioned in a die above the array die. In some embodiments, multiplexer drivers provide their signals just to the multiplexers in the patch they are over. In some embodiments, the multiplexer drivers provide their signals to the multiplexers in multiple patches. For example, the multiplexer control signals may extend through a staircase region between memory patches.
Systems, methods, and apparatus are provided for substrate isolation in a three-dimensional (3D) memory array. A 3D memory device can include a substrate, an isolation layer on the substrate, a vertical stack on the isolation layer, and a vertical opening through the vertical stack to the isolation layer.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
15.
INTEGRATED INDUCTOR-CAPACITOR STRUCTURE FOR VOLTAGE CONVERTERS
Apparatuses and systems are provided for an inductor-capacitor (LC) structure that is part of or coupled to a voltage converter. The LC structure can include a capacitor and an inductor comprising a plurality of coils. At least a portion of the plurality of coils wraps around the capacitor so as for the inductor to form an integrated structure with the capacitor.
Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10N 70/20 - Multistable switching devices, e.g. memristors
17.
DATA CHARACTERISTIC-BASED ERROR CORRECTION SYSTEMS AND METHODS
Apparatuses and methods for error correction based on data characteristics are disclosed. Data characteristics can include importance of the data. Data is received at a memory controller from a host device, and a characteristic of the received data is determined. A level of error correction is selected from a plurality of error correction levels for the received data based on the determined characteristic. The received data and an error correction code are written to a memory. The error correction code is generated based on the selected level of error correction. In some implementations, the characteristic of the received data is determined using a neural network.
Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task. In response to determining that the performance capability is adequate, the controller changes a mode of operation of the memory system so that one or more resources of the second memory device are used to service the task.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
19.
MICROELECTRONIC DEVICES, AND RELATED METHODS, MEMORY DEVICES AND ELECTRONIC SYSTEMS
A microelectronic device includes a stack structure, a memory array region, and an extension region horizontally neighboring the memory array region. The stack structure comprises levels of conductive material vertically alternating with levels of insulative material. The extension region includes an array extension region abutting the array region, and a select gate drain (SGD) contact region at least partially horizontally overlapping the array extension region. The SGD contact region comprises SGD contact structures extending vertically to one of the levels of conductive material within an upper section of the stack structure. The device includes a word line (WL) contact region horizontally neighboring the SGD contact region of the extension region. The WL contact region comprises WL contact structures individually in contact with another one of the levels of conductive material within a lower section of the stack structure and extending vertically through the entire vertical height of the stack structure.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
A method includes determining that a power event involving a memory sub-system has occurred. The method further including in response to the determination that the power event has occurred, generating signaling indicative of performance of an operation to provide power to a plurality of memory components of the memory sub-system, where the signaling indicative of performance includes a power control signal is applied to a first memory component at a first time, and is applied to a second memory component at a second time that is subsequent to the first memory component entering a steady state.
A 3D memory device includes multiple memory patches each of which includes a 3D array of memory cells arranged at the intersection of word lines running in a first direction, local digit lines (LDLs) running in a second direction, and global digit lines (GDLs) running in a third direction. The memory device includes a number of ‘quilts’ each of which includes four memory patches arranged in a 2x2 grid. The sense amplifiers are positioned along the border between patches in the third direction. Adjacent sense amplifiers are couple to adjacent GDLs in the two associated patches. In some embodiments, the sense amplifiers are positioned above the memory patches in the second direction. In some embodiments, multiplexer drivers are also positioned above the array. The quilts may be relatively compact and don’t have sense amplifiers along their edges, allowing for easier tiling at the edge of the device.
Methods, systems, and devices for memory sparing using row remapping and application-specific integrated circuit resources are described. A memory system may perform memory repair and recovery using additional resources at a memory system controller, using additional spare resources within the memory according to data compression, or both. A memory system controller may include one or more buffers that include volatile resources allocated for memory sparing. During a write operation, if the data is to be written to a failed region of memory, the memory system controller may write the data to a buffer at the controller and may remap the target address to the buffer. Additionally, or alternatively, extra rows, columns, and chunks of memory that are available after data compression may be repurposed for memory sparing. The memory system may remap addresses of failed rows, chunks, or columns of memory to the extra rows, columns, and chunks of memory.
Apparatuses and methods per-row count based refresh target identification. A memory device stores count values associated with the word lines. An aggressor detector circuit stores a maximum of the count values and a row address associated with the maximum count value. Responsive to a targeted refresh signal, the stored count value is compared to a threshold. If the count value has crossed the threshold, then a targeted refresh operation may be performed on one or more refresh addresses based on the stored address, and the count value may be reset.
A system comprises a memory device and a processing device, operatively coupled with the memory device. The processing device detects an error during a read operation on a set of target cells of the memory device. The processing device selects, based on a state information bin with which the set of target cells is associated, a read error handling (REH) flow for the set of target cells, wherein the set of target cells is associated with the state information bin based on corresponding cell state information. The processing device executes the REH flow on the set of target cells of the memory device to correct the error.
Methods, systems, and devices for dynamic voltage selection for memory systems are described. A memory system may include an interface coupled with a corresponding interface of a host system, where the interface may include one or more pins operable to dynamically output a combination of signals indicating a set of voltage levels. During operation, the memory system may monitor a quantity of operating parameters, and may output the combination of signals via the one or more pins indicating a set of voltage levels selected in accordance with a change in one or more of the operating parameters. A host system may be operable to monitor one or more corresponding pins for an updated combination of signals, and may output an indication of the set of voltage levels to a power supply which may provide corresponding voltage levels for one or more power supply inputs to the memory system.
In some implementations, a controller may obtain, from respective host systems of a plurality of host systems, a plurality of request messages for data associated with a first group identifier of one or more group identifiers. The controller may store the data to a cache of the controller based on obtaining the data from the one or more memory devices. The controller may provide the data to the plurality of host systems based on storing the data to the cache. The controller may identify, based on providing the data, whether each host system of the plurality of host systems has received the data. The controller may provide a plurality of acknowledgment messages to the plurality of host systems based on identifying that each host system of the plurality of host systems has received the data.
G06F 16/27 - Replication, distribution or synchronisation of data between databases or within a distributed database systemDistributed database system architectures therefor
A method of forming a microelectronic device includes forming conductive interconnect structures vertically extending through isolation material to conductive contact structures coupled to pillar structures, forming a metal silicide material on the interconnect structures and the first isolation material, forming a conductive material on the metal silicide material, and forming a dielectric material over the conductive material. The method further includes forming openings vertically extending through the dielectric material, the conductive material, the metal silicide material, and the isolation material and forming additional isolation material to extend over remaining portions of the dielectric material and at least partially fill the openings. Related devices and systems are disclosed.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A microelectronic device includes a first die and a second die vertically overlying and attached to the first die. The first die includes an array region and a peripheral region horizontally neighboring the array region. The array region includes memory cells respectively including a first transistor structure, a second transistor structure horizontally neighboring the first transistor structure, and a storage device vertically underlying and coupled to the first transistor structure and the second transistor structure. The peripheral region includes sub word line driver circuitry. The second die includes sense amplifier regions and a CMOS region horizontally neighboring some of the sense amplifier regions. The sense amplifier regions are within a horizontal area of the array region of the first die and include sense amplifier circuitry. Related memory devices and electronic systems are provided.
A 3D memory device includes multiple memory patches each of which includes a 3D array of memory cells arranged at the intersection of word lines running in a first direction, local digit lines (LDLs) running in a second direction, and global digit lines (GDLs) running in a third direction. A memory section includes two memory patches with a staircase region in between. The word lines run continuously through the two patches and through the in-between staircase region. Sub-word line drivers (SWDs) are positioned above the staircase region and coupled to respective ones of the word lines by conductive elements running in the second direction. In this way the SWDs may be located in a middle of the memory section.
A 3D memory device includes multiple memory patches each of which includes a 3D array of memory cells arranged at the intersection of word lines running in a first direction, local digit lines (LDLs) running in a second direction, and global digit lines (GDLs) running in a third direction. The GDLs are coupled to sense amplifiers. For example, a first set of sense amplifiers are coupled to even ones of a first half of the GDLs, a second set are coupled to even ones of a second half of the GDLs, a third set are coupled to odd ones of the first half of the GDLs, and a fourth set are coupled to odd ones of the second half of GDLs. The first and the fourth set of sense amplifiers may be positioned above the array, while the second and third sets are not.
A system can include a memory device comprising multiple dies, and a processing device, operatively coupled with the memory device, to perform various operations including identifying multiple management units to be programmed, where one management unit contains memory cells from a die having one endurance metric and another management unit contains memory cells from a die having another endurance metric, and determining a value of a media endurance metric for each management unit. The operations further include determining, for each management unit, a respective endurance exhaustion parameter defined by a relationship media endurance metrics, and distributing operations to each management unit based on the endurance exhaustion parameter.
A value associated with a number of accesses of a word line and a length of said accesses may be stored on said word line. A timer may provide a periodic signal that increments a counter to update the value. The updated value may then be written back to the word line. In some examples, a memory device including the word lines may have a specification that prevents the word line from closing prior to writing the updated value to the word line.
A method includes forming a tier stack of an electronic circuit, the tier stack including a plurality of tiers. A tier includes a first layer of first dielectric material and a second layer of second dielectric material. The method further includes forming a selector gate within the tier stack at the second layer of at least one of the plurality of tiers. The selector gate includes a nitride-based dielectric barrier adjacent to a metalloid layer. The metalloid layer includes a first metalloid. The method further includes selectively etching the second layer of second dielectric material of each of the plurality of tiers to form a void within each of the plurality of tiers. The method further includes filling the void within each of the plurality of tiers with a conductive material to form a plurality of conductive lines.
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
A system including a memory device and a processing device, operatively coupled with the memory device, wherein the processing device is configured to perform operations. The processing device performs a read operation on the memory device to determine a codeword. The processing device generates, from the read operation, a set of count values representing respective characteristics associated with the codeword. The processing device provides the set of count values as an input to a log-likelihood ratio (LLR) estimator machine learning (ML) model. The processing device receives an output from the LLR estimator ML model, wherein the output comprises an LLR output corresponding to the codeword. The processing device performs an error correction code (ECC) operation on the codeword using the LLR output.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
G06N 3/084 - Backpropagation, e.g. using gradient descent
A decoding operation is performed by receiving a command to read a correction matrix comprising multiple bit-values from memory of a decoder. The decoding operation also includes, responsive to receipt of the command, generating, using circuitry of a decoder, a predetermined correction matrix comprising a same bit-value. The decoding operation further includes providing the predetermined correction matrix to a decision engine to perform the decoding operation.
Methods, systems, and devices for die rebuild operations for improved access performance in a memory system are described. A memory system may select a fold rate based on an amount of valid data in the memory system to balance a speed at which the fold operations are performed with a capacity for the memory system to perform other access operations while performing the fold operations. For example, after detecting a die failure, the memory system may recover data stored to one or more first block stripes. The memory system may transfer the recovered data from the first block stripes to second block stripes within the memory system according to a fold rate that is based on an amount of valid data included in the memory system. By selecting a fold rate dynamically, the memory system may perform operations to access other stored data in parallel with performing the fold operations.
Embodiments of the disclosure are drawn to apparatuses, systems, and methods for managing sPPR undo operations based on activation count values of original rows after a repair. After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During an sPPR operation, an address of an original row of memory may be associated with an open repair address instead, such as when the original row is determined to be damaged or defective. The sPPR repair may be reversed by performing an sPPR undo operation. While the repair row is associated with the original row, the activation count of the original row may become corrupted, and it may be necessary to reset the activation count associated with the original row during a repair undo operation to prevent unnecessary refresh operations occurring on the original row and adjacent rows.
Protection of access to a tensor in outsourcing deep learning computations via shuffling. For example, the tensor in the computation of an artificial neural network can be partitioned into portions of different sizes. The computing tasks can be generated for operating on the portions such that the results of the computing tasks can be combined to obtain the result of a computing task operates on the tensor in the computation of the artificial neural network. The computing tasks can be shuffled for distribution out of order to external entities. The partitioning and shuffling can prevent the external entities from accessing and/or reconstructing the tensor.
Methods, apparatuses and systems related to dynamically adjusting a variable ganging size for a ganged reset read utilized in a transient scan. The transient scan may implement memory operations at memory cells to transition the memory cells from a stable state to a transient state or to maintain the memory cells in the transient state. The variable ganging size may be dynamically adjusted according to real-time operating parameters.
Systems, methods, and apparatus are provided for substrate isolation in a three-dimensional (3D) memory array. A 3D memory device can include a substrate, an isolation layer on the substrate, a vertical stack on the isolation layer, and a vertical opening through the vertical stack to the isolation layer.
Methods, systems, and devices for factory and field states for memory systems are described. When a memory system enters a factory setting, the memory system may be configured to store a first value to one or more first one-time-programmable (OTP) memory elements of the memory system. In response to the one or more first OTP memory elements indicating the first value, the memory system may enable access to one or more operations of the memory system associated with a first operation state. Prior to exiting the factory setting, the memory system may be configured to store a second value to one or more second OTP memory elements of the memory system. In response to the one or more second OTP memory elements indicating the second value, the memory system may disable access to the one or more operations associated with the first operation state.
A microelectronic device includes a stack structure, a memory array region, and an extension region horizontally neighboring the memory array region. The stack structure comprises levels of conductive material vertically alternating with levels of insulative material. The extension region includes an array extension region abutting the array region, and a select gate drain (SGD) contact region at least partially horizontally overlapping the array extension region. The SGD contact region comprises SGD contact structures extending vertically to one of the levels of conductive material within an upper section of the stack structure. The device includes a word line (WL) contact region horizontally neighboring the SGD contact region of the extension region. The WL contact region comprises WL contact structures individually in contact with another one of the levels of conductive material within a lower section of the stack structure and extending vertically through the entire vertical height of the stack structure.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
43.
BUFFERING FORCE UNIT ACCESS COMMANDS FOR BOOT-UP PROCEDURES
Methods, systems, and devices for buffering force unit access commands for boot-up procedures are described. Techniques described herein may enable a memory system to delay writing data associated with force unit access (FUA) commands to a non-volatile memory until a trigger condition is satisfied. That is, the memory system may store data associated with each FUA command in a buffer until reception of a last FUA command of a set of FUA commands in the boot-up procedure. The memory system may write the data associated with each FUA command to the non-volatile memory after the trigger is satisfied. In some examples, the memory system may indicate, to the host system, that the data has been written to the non-volatile memory prior to writing the data to the non-volatile memory.
Methods, systems, and devices for voltage selection for memory systems are described. A memory system may include a first interface including a first power supply and a second power supply input providing power to one or more memory devices at a first and second voltage level, and a third power supply input providing power to a controller of the memory system at a third voltage level. The memory system may further include a second interface coupled with a corresponding interface of a host system. The second interface may include circuitry configuring one or more pins to output a fixed combination of signals indicating a set of voltage levels, or the controller of the memory system may configure the one or more pins to output a selected combination of signals. The set of voltage levels may include settings for the first, second, and third voltage levels.
Methods, systems, and devices for dynamic voltage selection for memory systems are described. A memory system may include an interface coupled with a corresponding interface of a host system, where the interface may include one or more pins operable to dynamically output a combination of signals indicating a set of voltage levels. During operation, the memory system may monitor a quantity of operating parameters, and may output the combination of signals via the one or more pins indicating a set of voltage levels selected in accordance with a change in one or more of the operating parameters. A host system may be operable to monitor one or more corresponding pins for an updated combination of signals, and may output an indication of the set of voltage levels to a power supply which may provide corresponding voltage levels for one or more power supply inputs to the memory system.
The disclosure provides a 3D memory device with various staircase arrangements in a staircase region between two memory patches each including memory cells arranged in a 3D array. The staircase includes vertical conductive elements extending from groups of sub-word line drivers (SWDs) arranged above the staircase region to stacks of horizontal word lines (WLs) extending through the two patches and the in-between staircase region. The conductive elements couple SWDs selected from the SWD groups to the associated WLs in the WL stacks. The conductive elements have lengths to match depths of the WLs. The shortest and longest conductive elements are coupled to the top and bottom WLs, respectively. The WLs may be in a first die such as an array die and the SWDs may be in a second die such as a CMOS die bonded to the array die.
Disclosed in some examples are methods, systems, devices, and architectures which provide for techniques for memory device and memory fabric redundancy within distributed memory systems. In some examples, two memory devices are paired and each stores a same set of data such that writes to the memory devices are duplicated and reads may be satisfied from either device. In some examples, a memory processing unit (MPU) may be incorporated into the memory architecture to support these paired memory devices. The MPU may be placed between the host and a multi-planed memory fabric which connects to multi-ported CXL memory devices. In some examples, the MPU may also enable the use of alternative fabric links. That is, if a memory fabric link between the MPU and a memory device is unavailable, an alternative link may be utilized to restore connectivity to a memory device.
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
G06F 11/16 - Error detection or correction of the data by redundancy in hardware
A microelectronic device comprises vertical stacks of memory cells, each of the vertical stacks of memory cells comprising a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, and a conductive pillar structure in contact with the vertical stack of access devices. The microelectronic device further comprises transistor structures vertically overlying the vertical stacks of memory cells and comprising semiconductive material, and a protective liner material horizontally intervening between the semiconductive material and the conductive pillar structure of each of the vertical stacks of memory cells. Related methods are also described.
A 3D memory device includes sense amplifier drivers which are positioned adjacent to the sense amplifiers. The memory device may include memory patches with memory cells organized in a 3D array. The sense amplifiers and sense amplifier drivers are positioned above the memory patches. In some embodiments the sense amplifier drivers are positioned above the patch and next to a sense amplifier region. In some embodiments the sense amplifier drivers are within the sense amplifier region, for example between two rows of sense amplifiers. In some embodiments, portions of the sense amplifier drivers may overlap portions of the adjacent row(s) of sense amplifiers.
Methods, systems, and devices for data preservation after a supply voltage decrease in a memory system are described. In response to a voltage supply failure, a memory system may write data from a non-retention area of a volatile memory to a retention area of the volatile memory before resetting the memory system, the data intended for storage in a non-volatile memory device of the memory system. After resetting, the memory system may write the data from the retention area of the volatile memory to the non-retention area of the volatile memory. The memory system may then write the data from the non-retention area of the volatile memory to the non-volatile memory device.
Methods, systems, and devices for memory system reporting of data access frequency statistics are described. A host system may output a request to the memory system for access frequency information for a set of data. The memory system or the host system may generate access frequency labels for the set of data using one or more metrics indicative of the access frequency for the set of data and available to the memory system. In some examples, the memory system may output one or more measurements to the host system, and the host system may generate the access frequency labels in accordance with the one or more measurements. In some examples, the memory system may generate the access frequency labels. The memory system may output the one or more access frequency labels to the host system, or the memory system may store the one or more access frequency labels in metadata.
Methods, apparatuses and systems related to dynamically adjusting a variable ganging size for a ganged reset read utilized in a transient scan. The transient scan may implement memory operations at memory cells to transition the memory cells from a stable state to a transient state or to maintain the memory cells in the transient state. The variable ganging size may be dynamically adjusted according to real-time operating parameters.
A semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes moisture impermeable layer. The assembly includes a first substrate and a second substrate electrically connected to a surface of the first substrate. The assembly includes a layer between the two substrates with the moisture impermeable layer between the layer and the surface of the first substrate. The layer may be non-conductive film, die attach film, capillary underfill, or the like. A portion of the surface of the first substrate may include a solder mask between the moisture impermeable layer and the first substrate. The moisture impermeable layer prevents, or at least inhibits, moisture within the first substrate from potentially creating voids in the layer. The moisture impermeably layer may be a polyimide, a polyimide-like material, an epoxy, an epoxy-acrylate, parylene, vinyltriethoxysilane, or combination thereof. The moisture impermeable layer may have a high electrical resistance.
A plurality of context data structures are maintained. Each context data structure corresponds to an active region of a memory device. Each context data structure comprises an indicator characterizing the corresponding active region open or closed. A write request directed to a first active region is received. Responsive to determining that a first indicator of the first context data structure characterizes the first active region as open, the host data is written to the first active region, and at least a portion of the host data is padded to satisfy a predetermined write size of the memory device. The first active region is determined to have reached a capacity based on data written to the first active region including the padded data. The first active region is indicated to have reached capacity the first active region is characterized as closed.
A system and method for reading data from a memory device. The system and method receive a request to program data to an individual word line (WL) of the memory device. The system and method, in response to receiving the request to program the data, perform a coarse programming operation using a first type of programming scheme as a first programming phase associated with programming the data to the individual WL. The system and method perform, as a second programming phase, a fine programming operation using a second type of programming scheme after performing the coarse programming operation to complete programming the data to the individual WL of the memory device.
A 3D memory device includes multiple memory patches each of which includes a 3D array of memory cells arranged at the intersection of word lines running in a first direction, local digit lines (LDLs) running in a second direction, and global digit lines (GDLs) running in a third directions. The GDLs are organized in pairs, with each pair coupled to a sense amplifier. In an example arrangement, an area between memory array patches may contain capacitors. For example, the capacitors may be for managing internal voltages of the memory device. In some embodiments, the memory cells directly adjacent to the capacitor region may be dummy memory cells to act as a buffer between active memory cells and the capacitors located in the capacitor region.
G11C 11/4099 - Dummy cell treatmentReference voltage generators
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
Methods, systems, and devices for partitioned transferring for write booster are described. Techniques are described for a memory system to transfer data from a buffer associated with a write booster mode to higher-density blocks of the memory system based on a type of the data stored in the buffer. A first type of data may be transferred from the buffer to the higher-density blocks before a second type of data may be transferred from the buffer to the higher-density blocks. Prioritizing the transfer of data from the buffer to the higher-density block based on the type of data may reduce a write amplification associated with the memory system.
A 3D memory device includes multiple memory patches each of which includes a 3D array of memory cells arranged at the intersection of word lines running in a first direction, local digit lines (LDLs) running in a second direction, and global digit lines (GDLs) running in a third directions. The GDLs are organized in pairs, with each pair coupled to a sense amplifier. In an example arrangement, an area between memory patches on a CMOS die may be a peripheral region that contains circuit components for the memory device. In some embodiment, the area directly below the peripheral region on the array die may be generally not be used. In some embodiments, capacitors may be placed in the peripheral region of the array die to manage voltages generated by components on the CMOS die. In some embodiments, other components may be placed in the peripheral region of the array die.
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
In some implementations, a memory system may receive, from a host system, a write command associated with a first set of data and a first set of parity information. The memory system may perform, using a shared write/read parity circuit of the memory system and the first set of parity information, a write parity check for the first set of data. The memory system may receive, from the host system, a read command associated with a second set of data and a second set of parity information. The memory system may perform, using the shared write/read parity circuit of the memory system and the second set of parity information, a read parity check for the second set of data.
A system and method for programming data to a memory device are disclosed. The system and method receive a command associated with programming data to a portion of a memory device. The system and method determine an individual programming scheme from a plurality of programming schemes available on the memory device based on the received command and program data to the portion of the memory device using the determined individual programming scheme.
Methods, systems, and devices for techniques for a fragment cursor are described. A memory system may receive one or more write commands, each write command corresponding to a data fragment. The memory device may store the data fragments to a cursor (e.g., a fragment cursor) in a cache upon receiving the write commands, the cursor configured to store data fragments with a size less than a fragment size threshold (e.g., a page). The memory system may detect a memory management operation (e.g., power down, cache synchronization, data relocation, etc.) and write the cached data fragments to a block of memory cells of a memory device using the cursor. In some examples, the cursor may have a different associated mapping unit than other cursors of the memory system.
Apparatuses, systems, and methods for a refresh scheme that refreshes word lines in a same tier in 3D-DRAM. The 3D memory device includes multiple memory patches each of which includes a 3D array of memory cells arranged at the intersection of word lines running in a first direction, local digit lines (LDLs) running in a second direction, and global digit lines (GDLs) running in a third directions. The 3D memory array may be refreshed on a word line-by-word line basis as part of a refresh operation. During the refresh operation, one or more word lines may be refreshed in the 3D memory device. The word lines being refreshed may all be at a same tier of the 3D memory device. The tier may represent the depth at which the refreshed word line exists within a stack of word lines in the 3D memory array.
A processing device in a memory sub-system identifies a plurality of read retry offset voltages having respective check-fail bit counts that are within a target check-fail bit count range for a programming level of a memory device, performs one or more auto-read calibration operations for each of the plurality of read retry offset voltages, and determines respective syndrome weights for sense words read from the memory device using each of the plurality of read retry offset voltages. The processing device further identifies a read retry offset voltage of the plurality of read retry offset voltages having a lowest respective syndrome weight, and performs an error recovery operation using the identified read retry offset voltage.
A memory device includes a memory array die corresponding to a memory array, an access circuitry die corresponding to peripheral circuitry to support access operations with respect to the memory array, and a bonding layer disposed between the memory array die and the access circuitry die to form an interconnection between the memory array and the access circuitry. In some embodiments, the access circuitry die further integrates a local media controller corresponding to the memory array. In some embodiments, the local media controller is located external to the access circuitry die.
Methods, systems, and devices for buffering force unit access commands for boot-up procedures are described. Techniques described herein may enable a memory system to delay writing data associated with force unit access (FUA) commands to a non-volatile memory until a trigger condition is satisfied. That is, the memory system may store data associated with each FUA command in a buffer until reception of a last FUA command of a set of FUA commands in the boot-up procedure. The memory system may write the data associated with each FUA command to the non-volatile memory after the trigger is satisfied. In some examples, the memory system may indicate, to the host system, that the data has been written to the non-volatile memory prior to writing the data to the non-volatile memory.
A memory system can include a plurality of memory devices accessible as a plurality ranks and rank select logic. The rank select logic can be coupled to the plurality of memory devices. The rank select logic receives a plurality of data signals from a host via a data bus. The rank select logic can also couple the plurality data lines to the memory devices of a selected one of the plurality of ranks while preventing data signals from being provided to the memory devices of unselected ranks.
On-die temperature control for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a semiconductor device assembly includes first and second semiconductor dies directly bonded to each other. The semiconductor dies each includes conductive pads and resistive heating components in a dielectric layer, where the resistive heating components are located proximate to the conductive pads to supply localized thermal energy to the conductive pads in response to electric current flowing through the resistive heating components. In some embodiments, the conductive pads of the first semiconductor die are directly bonded to the conductive pads of the second semiconductor die at a first temperature less than a second temperature for the thermal expansion of the conductive pads absent the localized thermal energy generated by the resistive heating components.
H10N 10/17 - Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the structure or configuration of the cell or thermocouple forming the device
Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. Memory cells are in the memory-cell tiers and individually comprise a horizontal transistor having a gate, a capacitor side, and a digitline side. A capacitor is electrically coupled with the horizontal transistor on the capacitor side. A digitline is electrically coupled with the horizontal transistor on the digitline side. Immediately-vertically-adjacent of the memory-cell tiers comprise an upper memory-cell tier and a lower memory-cell tier. The insulative tiers comprise an insulator that is vertically between the immediately-vertically-adjacent memory-cell tiers. The insulator comprises a void-space that is vertically between the gate of the upper memory-cell tier and the gate of the lower memory-cell tier. The void-space is directly against at least one of (a) and (b), where: (a) a bottom surface of the gate of the upper memory-cell tier; and (b) a top surface of the gate of the lower memory-cell tier. Other embodiments, including method, are disclosed.
A 3D memory device includes multiple memory patches each of which includes a 3D array of memory cells arranged at the intersection of word lines running in a first direction, local digit lines (LDLs) running in a second direction, and global digit lines (GDLs) running in a third directions. The GDLs are organized in pairs, with each pair coupled to a sense amplifier. In an example arrangement, one GDL of the pair may be in a first metal layer while the other GDL of the pair may be in a second metal layer. The folded GDL arrangement may allow more flexibility in the placement of the sense amplifiers. For example, rather than being placed between two array sections that they are associated with, the sense amplifiers may be at the edge of a single section that they are associated with.
Implementations described herein relate to repairing lanes associated with memory devices. In some implementations, a memory device may detect, using a lane repair block, that a lane of the memory device is associated with a lane failure, wherein the lane repair block is employed prior to a first physical (PHY) latch that is between a through-silicon via (TSV) associated with the memory device and a data queue (DQ) pad associated with the memory device. The memory device may map, using the lane repair block, the lane associated with the lane failure to an alternate lane associated with one or more alternate blocks.
Methods, systems, and devices for data transfer between buffers are described. A memory system may be configured to transfer, from one or more memory devices of the memory system to a buffer of the memory system, a block of data that is associated with a memory management operation. The memory system may set a value of a flag associated with the buffer to a first value based on transferring the block of data to the buffer. The first value may indicate that the block of data satisfies a size threshold. The memory system may transmit the block of data to the host system based on the value of the flag associated with the buffer having the first value indicating that the block of data satisfies the size threshold.
A memory device may include a memory array including multiple levels of memory cells that are each separated from another level by a respective dielectric layer. A memory cell at a first level of the memory array may include a channel portion and a capacitor operable to store a logic state of the memory cell. A first portion of the capacitor may be located between the channel portion and a voltage source coupled with the memory cell. A second portion of the capacitor may be in a cavity in a dielectric layer between the first level and a second level of the memory array. The second portion of the capacitor may be located between the channel portion and a word line coupled with a channel portion of a second memory cell at the second level.
An apparatus includes a stacking interposer configured to support dies attached to top and bottom surfaces thereof to form a subassembly. The stacking interposer includes internal connections that couple wirebonding pads on a top side thereof to the dies attached on the top and bottom surfaces. The subassembly may be stacked with one or more matching subassemblies, and bond wires connect the wirebonding pads on each of the subassemblies, thereby the dies attached to each of the interposers, to corresponding locations on a packaging substrate.
Methods, systems, and devices for voltage selection for memory systems are described. A memory system may include a first interface including a first power supply and a second power supply input providing power to one or more memory devices at a first and second voltage level, and a third power supply input providing power to a controller of the memory system at a third voltage level. The memory system may further include a second interface coupled with a corresponding interface of a host system. The second interface may include circuitry configuring one or more pins to output a fixed combination of signals indicating a set of voltage levels, or the controller of the memory system may configure the one or more pins to output a selected combination of signals. The set of voltage levels may include settings for the first, second, and third voltage levels.
Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.
A microelectronic device including a vertical channel access device that includes a semiconductor pillar. The semiconductor pillar includes a first doped region, a channel region vertically above the first doped region, and a second doped region vertically above the channel region. The vertical channel access device includes a gate electrode horizontally offset from and vertically overlapping the channel region of the semiconductor pillar and a gate dielectric material horizontally interposed between the gate electrode and the semiconductor pillar. The microelectronic device includes a dipole-forming material at a vertical position of the second doped region of the semiconductor pillar of the vertical channel access device, the dipole-forming material directly physically contacting the gate dielectric material and effectuating a fixed polarization effect at an interface of the gate dielectric material and the dipole-forming material.
Methods, systems, and devices for file-based garbage collection are described. A host system may divide a logical address space corresponding to one or more files into multiple zones, each zone of the multiple zones being allocated a respective set of logical block addresses (LBAs). Additionally, the host system may replace a first LBA allocated to a first zone of the multiple zones with a second LBA in response to the first LBA being invalid and store, in response to replacing the first LBA with the second LBA, a mapping between the second LBA and an identifier of a file of the one or more files corresponding to the first zone to memory of the host system. Further, the host system may update, as part of file-based garbage collection, the second LBA to be a third LBA in response to reading the identifier of the file from the memory.
Stacked semiconductor devices and associated systems and methods are disclosed herein. A stacked semiconductor device according to the present technology can include a base substrate, a bridge package integrated with the base substrate, and a plurality of dies carried by the base substrate adjacent to the controller die. The bridge package includes an interposer, a controller integrated with a lower surface of the interposer, and a wire bond bridge integrated with an upper surface of the interposer. The controller is coupled to the base substrate and the wire bond bridge via the interposer. The plurality of dies can include a first tier and a second tier carried by the first tier. The first tier includes a plurality of first dies coupled to the active surface via first wire bonds. The second tier includes a plurality of second dies coupled to the wire bond bridge via second wire bonds.
An integrated circuit includes a package substrate and a memory device disposed on the package substrate. The memory device includes a first stack comprising a plurality of first semiconductor dies, and a second stack comprising a plurality of second semiconductor dies. The integrated circuit also includes a fanout controller assembly that is mounted on the package substrate. The fanout controller assembly includes a controller substrate and a controller die disposed on the controller substrate. The controller die is encased in a mold, and a plurality of through-mold-vias (TMVs) are disposed adjacent the controller die. The TMVs extend from a top surface of the mold to the controller substate. A plurality of bondfingers are disposed on a top surface of the mold and electrically couple to respective TMVs.
Methods, systems, and devices for virtual block structure for random read operations are described. A memory system may implement sub-virtual blocks within each virtual block of the memory system. To use an implemented sub-virtual block architecture, the memory system may write to a first sub‑virtual block of a virtual block before writing to a second sub‑virtual block of the virtual block. The memory system may perform various access operations at the non‑volatile memory of the memory system by accessing the first sub‑virtual block or the second sub‑virtual block of the virtual block. In some examples, after writing to and reading from the sub-virtual blocks, the memory system may perform an erase operation on all sub‑virtual blocks of the virtual block simultaneously.
A compute device includes a compute die, an on-chip cache with one or more volatile memory dies and one or more non-volatile memory dies, and a memory controller all disposed on the package substrate. The controller detects an occurrence of a checkpoint trigger event, responsive to detecting the occurrence of the checkpoint trigger event, initiates a checkpointing operation to collect first state information associated with the compute device and operations executed by the compute die, and sends the first state information to a second compute device in a group of compute devices, the second compute device to store the first state information in non-volatile memory thereon.
A semiconductor device assembly includes a circuit substrate; a semiconductor die arranged on the circuit substrate; a heat transfer layer arranged on the semiconductor die, the heat transfer layer configured to transfer heat generated by the semiconductor die away from the semiconductor die; and a package casing that partially encapsulates the semiconductor die and the heat transfer layer. The package casing includes a plurality of fin structures and a plurality of channels arranged over the heat transfer layer. The plurality of channels extend from an ambient environment into the package casing to the heat transfer layer to expose portions of the heat transfer layer to the ambient environment. The plurality of channels are configured to receive, from the heat transfer layer, the heat generated by the semiconductor die, and dissipate the heat into the ambient environment, away from the heat transfer layer and the package casing.
Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, a semiconductor device assembly includes a memory array region, an insulative layer, an intrinsic semiconductive region between the memory array region and the insulative layer, and a doped semiconductive region that is contained within a lateral zone that is between the intrinsic semiconductive region and the insulative layer.
Disclosed herein are methods, apparatuses and systems related to detecting and managing erroneous temperature readings during operations. The apparatus may be configured to obtain prior operating temperature readings. When the obtained temperature reading satisfies an initial trigger, the apparatus may determine a synthetic temperature reading based on the prior temperature readings, outputs of other sensors, or a combination thereof.
Methods, systems, and devices for adjustment to multi-phase clock to reduce skew variation caused by power rail bounce at an onset of a burst of data are described. In accordance with examples as described herein, a memory system may be configured to reduce skew variations between a multi-phase clock and a differential clock caused by power rail bounce during a burst write operation. The memory system may include circuitry including a block of detection/pulse generation circuitry configured to detect a leading phase of the multi-phase clock at an onset of a burst write operation and generate pulse signaling that is indicative of the leading phase. The circuitry may further a block of adder circuitry that is configured to determine, based at least in part on using the pulse signaling, one or more timing adjustments that compensate for the skew variations.
G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
Stacked semiconductor devices and associated systems and methods are disclosed herein. A stacked semiconductor device according to the present technology can include a base substrate, a bridge package integrated with the base substrate, and a plurality of dies carried by the base substrate adjacent to the controller die. The bridge package includes an interposer, a controller integrated with a lower surface of the interposer, and a wire bond bridge integrated with an upper surface of the interposer. The controller is coupled to the base substrate and the wire bond bridge via the interposer. The plurality of dies can include a first tier and a second tier carried by the first tier. The first tier includes a plurality of first dies coupled to the active surface via first wire bonds. The second tier includes a plurality of second dies coupled to the wire bond bridge via second wire bonds.
An integrated circuit includes a package substrate and a memory device disposed on the package substrate. The memory device includes a first stack comprising a plurality of first semiconductor dies, and a second stack comprising a plurality of second semiconductor dies. The integrated circuit also includes a fanout controller assembly that is mounted on the package substrate. The fanout controller assembly includes a controller substrate and a controller die disposed on the controller substrate. The controller die is encased in a mold, and a plurality of through-mold-vias (TMVs) are disposed adjacent the controller die. The TMVs extend from a top surface of the mold to the controller substate. A plurality of bondfingers are disposed on a top surface of the mold and electrically couple to respective TMVs.
A microelectronic device includes memory cells respectively including a vertical channel access device including a semiconductor pillar including a source region, a drain region, and a channel region vertically extending from and between the source region and the drain region and a gate electrode horizontally neighboring a sidewall of the semiconductor pillar, the gate electrode vertically overlapping the channel region of the semiconductor pillar. The memory cells respectively also including a storage node device vertically below and coupled to the vertical channel access device. The microelectronic device includes digit line structures individually vertically overlying and coupled to the vertical channel access device of a respective one of the memory cells of the memory array structure, each of the digit line structures contacting a top surface and sidewalls of the semiconductor pillar of the vertical channel access device to which the digit line structure is coupled.
A memory device includes a memory array with a plurality of blocks and control logic to receive a request to perform a program operation on the memory array, determine an operating temperature of the memory device, modify a previously determined calibrated wordline start voltage based on the operating temperature to form a modified start voltage, and cause the modified start voltage to be applied to the memory array during the program operation.
In some implementations, a memory apparatus may compress a physical page table associated with a logical-to-physical (L2P) table, to obtain a compressed version of the physical page table, wherein the physical page table is associated with logical block address (LBA) and physical address pairs, wherein the compressed version is associated with a set of groups of LBAs and an exception list, and wherein the compressed version includes an indication of physical addresses associated with respective starting LBAs included in the set of groups and includes sequentiality indications for respective groups from the set of groups. The memory apparatus may receive, from a host system, a command indicating an LBA that is associated with the physical page table. The memory apparatus may perform a lookup operation using the compressed version of the physical page table to identify a physical address associated with the LBA.
Methods, systems, and devices for power envelope modification for memory systems based on time to thermal throttle are described. A memory system may dynamically change the power limit based on operating conditions associated with the memory system. For example, the memory system may measure the time before entering a thermal throttle mode. If the time is relatively short, the memory system may decrease the power limit, which may cause the time before entering the thermal throttle mode during a subsequent burst of host activity to increase. Alternatively, if the time is relatively long, the memory system may increase the power limit, which may cause the time before entering the thermal throttle mode during a subsequent burst of host activity to decrease.
The present disclosure configures a system component, such as memory sub-system controller, to perform empty page scan operations. The controller, in response to a request to perform an empty page scan operation, identifies a portion of a set of memory components that is empty and ready to be programmed. The controller generates an order in which to perform the empty page scan operation for a plurality of regions of the identified portion of the set of memory components. The controller determines whether a first region of the plurality of regions in the order fails the empty page scan operation before a second region of the plurality of regions is scanned. The controller terminates the empty page scan operation early to prevent performing the empty page scan operation for one or more remaining regions of the plurality of regions of the identified portion.
A microelectronic device package assembly includes a package board and a stiffener device attached to the package board. The package board has a first side and a second side. The stiffener device includes an upper stiffener, a lower stiffener, and one or more damper devices. The upper stiffener is above the first side of the package board and has a die side and a package side. The lower stiffener is interposed between the upper stiffener and the package board and has a damper side and a board side. The lower stiffener includes through-package anchors extending from the board side and through the package board. The one or more damper devices are interposed between and are in contact with each of the upper stiffener and the lower stiffener. Microelectronic devices and electronic systems are also described.
A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, word lines coupled to the memory cells, and isolation material overlying the memory cells, the digit lines, and the word lines. An additional microelectronic device structure assembly comprising control logic devices and additional isolation material overlying the control logic devices is formed. The additional isolation material of the additional microelectronic device structure assembly is bonded to the isolation material of the microelectronic device structure assembly to attach the additional microelectronic device structure assembly to the microelectronic device structure assembly. The memory cells are electrically connected to at least some of the control logic devices after bonding the additional isolation material to the isolation material. Microelectronic devices, electronic systems, and additional methods are also described.
Apparatuses, systems, and methods for correcting latch upset events in a trim register are described. An example method includes sending a command, from a controller, to access at least one block of a plurality of blocks of a non-volatile memory. The method can further include receiving a failure message associated with reading the at least one block. The method can further include, in response to receiving the failure message, resetting trim data associated with the plurality of blocks.
Methods, systems, and devices for error tracking by a memory system are described. A memory system transmit indications of corrupt data without storing (e.g., internally storing) the indication. In some examples, a memory system may read data (e.g., from an associated memory device) and detect an error in the data. The memory system may generate an indication of the error and may transmit the indication to a host device. In other examples, a host device may transmit corrupted data with an indication of such. The memory system may store the corrupt data (e.g., an inverted version of the corrupt data) and, upon receiving a subsequent read command, may transmit the corrupt data to the host system with an indication that the data is corrupt.
A host system connected to a memory sub-system via a connection to configure memory services provided by the memory sub-system to the host system over the connection. The memory sub-system can allocate a portion of its memory resources to provide storage services to the host system, and allocate another portion of its memory resources to provide memory services to the host system. In response to a request from the host system over the connection, the memory sub-system can update configuration data of the memory services and provide the memory services according to the parameters specified by the request. The request can be implemented in the protocol over the connection for storage access, or in the protocol over the connection for memory access. The request can be implemented via a store instruction, a write command, or another command having another command identifier.
In some implementations, a memory device may identify a key-value pair set associated with a root node, wherein the key-value pair set includes a plurality of key-value pairs, and wherein the root node is associated with a log-structured merge-tree. The memory device may determine that a plurality of keys in the key-value pair set are associated with a leaf node based on the plurality of keys corresponding to an edge key associated with the leaf node, wherein the leaf node is associated with the log-structured merge-tree. The memory device may associate the key-value pair set with the leaf node based on a metadata update of the key-value pair set, wherein the key-value pair set becomes decoupled from the root node.
This document discloses techniques, apparatuses, and systems for providing a semiconductor device assembly with a substrate for vertically assembled semiconductor dies. A semiconductor assembly is described that includes a semiconductor die coupled to a substrate such that an active surface of the semiconductor die is substantially orthogonal to a top surface of the substrate. The substrate includes a surface having a recessed slot at which a side surface of the semiconductor die couples. The semiconductor die includes a contact pad that couples to a contact pad at the recessed slot. In doing so, the techniques, apparatuses, and systems herein enable a robust and cost-efficient semiconductor device to be assembled.
A memory device can include an array of memory cells comprising groups of memory cells, the groups including at least one redundant group for repairing a defective group. The memory device can include a controller coupled to the array. Responsive to receiving a memory access command, the controller can detect whether a defective group is present. If a defect is present, sensing operations are not performed for the defective group. If no defect is present, sensing operations are not performed for the redundant group.
