Methods, systems, and devices for write booster buffer and hibernate are described. The memory system may initiate a first operation to enter a first power mode having a lower power consumption than a second power mode. In some cases, the memory system may determine whether a quantity of data stored in a buffer of single-level cells associated with write booster information satisfies a threshold based on initiating the first operation. The memory system may determine whether to perform a second operation to transfer the quantity of data stored in the buffer of single-level cells to a portion of memory comprising multiple level cells based on determining whether the quantity of data satisfies the threshold. The memory system may enter the first power mode based on determining to perform the second operation to transfer the quantity of data from the buffer to the portion of memory.
An integrated circuit construction comprises conductive vias that are individually directly above and directly electrically coupled to individual operative transistors. Insulator islands individually extend upwardly from individual inoperative transistors. Insulating material surrounds individual of the insulator islands and individual of the conductive vias. Insulative material is directly above the insulating material. Conducting vias individually extend through the insulative material. Some of the conducting vias are directly above and directly against individual of the conductive vias. Another some of the conducting vias are directly above individual of the insulator islands. Other embodiments, including method, are disclosed.
Implementations described herein relate to memory device hardware host read actions based on lookup operation results. In some implementations, a memory device may include one or more components configured to receive, by a hardware component of the one or more components and from a host device, a request to read data. The hardware component may be configured to perform a first lookup operation to determine whether the data is associated with a write data entry in a cache memory. The hardware component may be configured to perform a second lookup operation associated with an address of the data in a memory, where the second lookup operation is performed irrespective of a first result of the first lookup operation. The hardware component may be configured to perform one or more actions based on the first result and a second result of the second lookup operation.
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
Methods, systems, and devices for array stabilization in memory architectures are described. A memory device may include a first array region with a first block of memory cells and a first selection region. The memory device may include a second array region of the memory die with a second block of memory cells and a second selection region. The first and second selection regions may include respective sets of transistors that couple memory cells of the first block and the second block with various access lines. The memory device may include an electrical isolation region positioned between the first array region and the second array region. The electrical isolation region may include first dielectric material portions having a first width between the first selection region and the second selection region and second dielectric material portions having a second width between the first selection region and the second selection region.
A method of forming a microelectronic device includes forming an etch-selective liner on a staircase structure having steps defined by preliminary tiers respectively including insulative material and sacrificial material. First openings are formed within a horizontal area of the staircase structure and vertically extending through the etch-selective liner and the preliminary tiers. The sacrificial material of the preliminary tiers are replaced with conductive material to form tiers respectively including the insulative material and the conductive material. Portions of the etch-selective liner horizontally adjacent to the first openings are laterally recessed to form second openings. The conductive contacts are within the second openings. The conductive contacts respectively includes a first portion vertically extending through the tiers and the etch-selective liner, and a second portion outwardly horizontally projecting from and unitary with the first portion.
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/20 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
Methods, systems, and devices related to sense amplifiers of a memory device serving as a Static Random Access Memory (SRAM) cache. For example, a memory array can be coupled to sense amplifiers. In a first mode, the sense amplifiers can be electrically disconnect from digit lines of the memory array. In the first mode, data and metadata of a cache line can be stored in the sense amplifiers when electrically disconnected from the number of digit lines. In the first mode, a portion of the data can be communicated, based on the metadata, from the sense amplifiers to the processing device. In a second mode, the sense amplifiers can connect to the memory array and sense data from the memory array.
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
8.
Track Runtime Memory Latency Changes to Improve Dynamic Allocation of Memory Provided over Multiple Connections
A system including: a compute express link fabric; a plurality of memory devices connected to the compute express link fabric; at least one processor connected to the compute express link fabric; and a main memory connected to the at least one processor. The system is configured to: identify a plurality of memory regions in the main memory and the plurality of memory devices; determine runtime latency to access the plurality of memory regions; identify, based on the runtime latency and among the plurality of memory regions, a first memory region as a source region; receive a memory allocation request; and allocate, in response to the memory allocation request, a chunk of random access memory from the source region.
A microelectronic device includes a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers, the stack structure divided into blocks by filled slot structures, each of the blocks comprising: a memory array region; staircase structures having steps; and crest regions interposed in a first horizontal direction between horizontally neighboring pairs of the staircase structures, and contact structures within the first crest region of each of the blocks and vertically extending through the stack structure to a source tier underlying the stack structure, the contact structures comprising: first contact structures in electrical communication with control logic circuitry; and second contact structures electrically isolated from the control logic circuitry, at least some the first contact structures relatively more centrally positioned with each of the blocks in a second horizontal direction orthogonal to the first horizontal direction than at least some of the second contact structures.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
Various example embodiments provide for multi-wordline programming of a memory device with data loss prevention, which can be used by a memory sub-system. In particular, various example embodiments use a certain sequence of memory device commands to avoid multi-wordline data loss during cache programming of a memory device.
A printed circuit board (PCB) land pad for a three-pin metal–oxide–semiconductor field-effect transistor (MOSFET) component comprises four pads with a split pad for a drain terminal of the MOSFET component. The PCB land pad comprises: a first pad to connect a gate terminal of the MOSFET component to a PCB; a second pad to connect a source terminal of the MOSFET component to the PCB; a third pad corresponding to connect a drain terminal of the MOSFET component to the PCB; and a fourth pad to connect the drain terminal of the MOSFET component to the PCB.
Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a semiconductor substrate and an active region in the semiconductor substrate. The integrated assembly may include a first epitaxial structure on an upper surface of the semiconductor substrate, the first epitaxial structure having a first thickness in a first direction, and a second epitaxial structure on an upper edge of the semiconductor substrate, the second epitaxial structure having a second thickness in a second direction different than the first direction, where the second direction is oblique to the semiconductor substrate, and where the second thickness is less than the first thickness.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
13.
SEMICONDUCTOR WAFERS WITH BURIED CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS
Semiconductor device assemblies including one or more semiconductor wafers with buried connectors and associated systems and methods are disclosed herein. In some embodiments, a semiconductor wafer includes one or more dielectric layers defining a frontside and a backside of the semiconductor wafer, integrated circuitry formed on or within the dielectric layers, and an array of connectors formed within the dielectric layers. The array of connectors can be arranged in a geometric pattern. Individual ones of the array of connectors can be oriented along a direction extending between the frontside and the backside of the semiconductor wafer. A first subset of the array of connectors can be exposed at least one of the frontside or the backside of the semiconductor wafer. A second subset of the array of connectors can be fully embedded in the one or more dielectric layers.
An apparatus includes a ceramic capacitor comprising a ceramic component and one or more metal components; and an encapsulation layer that encapsulates the ceramic capacitor from an external environment, wherein at least one surface of the ceramic component of the ceramic capacitor is finished to strengthen a bond capability between the at least one surface and the encapsulation layer.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
This disclosure is directed to a system for high efficiency storage in high capacity non-volatile solid state applications. The system includes a memory device and a processing device operatively coupled to the memory device. The processing device performs operations including receiving a request to program data, storing the data by default in a first type of storage with multi-level memory cells having a first number of levels, and bypassing a second type of storage with fewer levels. Upon detecting a condition, the processing device transfers the data to a third type of storage with a greater number of levels than the first type. This method optimizes storage efficiency and performance by dynamically managing data storage based on the portion of user logical block addresses that contain user data.
High-voltage semiconductor devices with extended active areas (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a high-voltage semiconductor device includes a high-voltage N-well formed in a substrate. The high-voltage N-well includes a mask edge corresponding to a location of an N-well junction formed in the substrate. The device further includes (i) an active area and (ii) a local deep trench isolation region positioned within the substrate and laterally adjacent to the high-voltage N-well. The active area can extend beyond the mask edge of the high-voltage N-well such that a region of the active area is positioned between the mask edge of the high-voltage N-well and the local deep trench isolation region. The extended active area is expected to improve breakdown voltage characteristics of the device when using local deep trench isolation.
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
Some embodiments of the disclosure provide a method for forming cell contacts of a memory device, the method comprising forming two layers in a plurality of gaps for separation of cell contacts, wherein the two layers include a first layer on surfaces of the gaps and a second layer on the first layer, the second layer filling the gaps covered by the first layer. The second layer separates cell contacts formed in cell contact halls from each other. The method effectively achieves sufficient separation of the cell contacts while at the same time achieving the sufficient cell contacts size to prevent or mitigate defects due to high resistance of the cell contacts.
Methods, systems, and devices for replacement policy for access granularity in memory subsystems are described. The memory system may include one or more extra capacity dies configured to store corrected data from failed memory dies. A failed memory die may include a threshold quantity of errors. The memory system may identify one or more failed memory dies and may correct errors in the stored data using a data correction scheme supported by the memory system. The memory system may select at least one extra capacity die and may write the corrected data to the selected extra capacity die. The memory system may write null data in the failed memory die to replace the data including the errors. The extra capacity die may thereby act as a replacement for at least a portion of the failed memory die.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
19.
CHARGE TRAPPING NOT OR (NOR) FLASH MEMORY ARCHITECTURES
Methods, systems, and devices for charge trapping not or (NOR) flash memory architectures are described. The devices described herein may implement a Fowler-Nordheim charge trapping NOR memory architecture. For example, a memory system may be manufactured that includes multiple NOR memory cells in a pier and pillar architecture. In such examples, the memory system may include multiple piers, where each pier may have a plurality of first cells at a first end of the pier and a plurality of second cells at a second end of the pier. Each pier may be positioned between a first pillar and a second pillar, where such pillars may be utilized to access the memory cells at each pier. In some examples, every other pillar may not include memory cells (e.g., may be a dielectric pillar), which may enable Fowler-Nordheim programming of the memory cells.
H10B 43/20 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
A memory device comprises memory and control circuitry. The control circuitry can receive a command to access the memory. Responsive to receiving the command to access the memory, the control circuitry can provide command data of the command to pipe latch circuitry and error correction code (ECC) circuitry. The memory device further includes pipe latch circuitry to receive command data of the command from the control circuitry and maintain the command data for a period of time of a duration longer than error calculation time of the ECC circuitry.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
An apparatus includes: a substrate having first conductivity type; a through-silicon via going through from the top surface to the bottom surface of the substrate; an insulating film surrounding a side surface of the through-silicon via; a first well having second conductivity type in a top portion of the substrate; and a second well having first conductivity type just below the first well in the substrate; wherein one side of the first well and the second well is substantially in contact with the insulating film.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H10D 62/60 - Distribution ou concentrations d’impuretés
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
Methods, systems, and devices for techniques for reducing or preventing data knock out are described. A memory device includes an array of memory cells; data lines coupled to the array of memory cells; one or more sense amplifiers coupled to the data lines; and a memory controller. The memory controller is configured to perform, for data sensing operations comprising sensing at least at a first sensing level and a second sensing level: causing precharging of the data lines, causing the one or more sense amplifiers to sense, at the first sensing level, the data lines to obtain data stored in the array of memory cells, and keeping the data lines pre-charged even if at least one of the data lines is not sensed at the second sensing level.
G11C 16/24 - Circuits de commande de lignes de bits
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
23.
METHODS AND SYSTEMS TO BOOST BIT LINE VOLTAGE BIASING
Methods, systems, and devices for techniques for boosting bit line voltage biasing. A memory device includes bit lines and controller. The controller, during a program operation of strings of memory cells, identifies, based on a characteristic corresponding to the bit lines, first and second bit line groups. The controller, during the program operation, causes the first bit line group to receive a voltage at a first voltage level. The controller, during the program operation, causes the first bit line group to transition to a floating state such that the first bit line group is electrically isolated. The controller, during the program operation, causes the second bit line group to receive the voltage at the first voltage level. The first and second bit line groups are capacitively coupled such that the voltage level of the first bit line group is boosted from the first voltage level to a second voltage level.
Methods, systems, and devices for minimum memory clock estimation procedures are described. For instance, a device, such as a host device, may truncate a value of a first parameter associated with a first duration for a clock coupled with a memory array to perform a clock cycle and may determine a value of a second parameter that is inversely proportional to a combination of the truncated first parameter and a correction factor. The device may determine a quantity of clock cycles associated with a second duration for accessing one or more memory cells of the memory array based on adjusting a third parameter associated with the second parameter. The device may access the one or more memory cells of the memory array based on the determined quantity of clock cycles.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
Methods, systems, and devices for techniques to balance log structured merge trees are described. A computing system may rebalance a tree structure having an ordered set of leaf nodes by splitting or joining leaf nodes of the tree structure. To split a leaf node, the computing system may select a key to evenly partition key and value data stored in the leaf. The computing system may place each key block of the leaf node having keys less than or equal to the selected key in a first new leaf node, and may place each key block of the leaf node having keys greater than the selected key in a second new leaf node. To join leaf nodes of the tree structure, the computing system may place each key block and each value block of the leaf node and the adjacent leaf node in a new leaf node.
Methods, systems, and devices for write buffer flush techniques are described. A memory system may be triggered to flush (e.g., transfer, write) data from a volatile memory device to a non-volatile memory device of the memory system. The memory system may support flushing data to blocks including single level cells (SLCs) or blocks including multiple-level memory cells. The memory system may determine whether a quantity of the data to be flushed satisfies a threshold quantity of data. If the quantity of data fails to satisfy the threshold quantity of data, the memory system may flush the data to a block including SLCs, which may be referred to as a small chunk SLC cursor. The SLC cursor may temporarily store the flushed data, such as at least until the threshold quantity of data is satisfied in the volatile memory device and/or to data recovery in case of a power loss event.
A device for deep learning acceleration with mixed precision may include a first data port configured to receive a map data segment and a second data port configured to receive a kernel data segment. The device may include a precision mode port configured to receive an indication of an input precision mode that indicates a word length for the map data segment and for the kernel data segment. The device may include a multiplier component configured to generate a multiplier component output based on the input precision mode and based on multiplying the map data segment and the kernel data segment. The device may include an adder component configured to generate an adder component output based on the input precision mode and based on the multiplier component output. The device may include an output port configured to output the adder component output.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
28.
CHARGE TRAPPING NOR FLASH MEMORY FOR STACKED MEMORY ARCHITECTURES
Methods, systems, and devices for charge trapping not-OR (NOR) flash memory for stacked memory architectures are described. A memory device may include one or more three-dimensional (3D) charge trapping NOR flash memory dies in a stack of memory dies. In some examples, the stack of memory dies may also include one or more volatile memory dies, while in other examples the stack of memory dies may primarily include charge trapping NOR memory dies. The stack of memory dies may also include a logic die configured to access each of the memory dies of the stack using one or more vias, channels, or other components associated with the stack. In some examples, the logic die may access the memory dies of the stack in response to an access command received from a graphics processing unit (GPU) or other processing circuitry of the memory device.
Methods, systems, and devices for host-side alignment to a multi-phase internal clock of a memory system are described. An apparatus may be configured to implement host-side alignment to a multi-phase internal clock of the memory system. Techniques to implement host-side alignment may include a host system issuing a synchronization pattern to the memory system. The memory system may, based on the synchronization pattern, provide a return mapping that indicates a degree of alignment between a clock of the host system and phases of a multi-phase internal clock of the memory system. Based on the indication, the host system may implement a timing offset that synchronizes the host system with the memory system, thereby enabling information that is subsequently transmitted from the host system to be decoded by the memory system.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
30.
MEMORY DEVICE INCLUDING TRENCH LINER BETWEEN BLOCKS
Some embodiments include apparatuses and methods of forming the apparatuses. One of the methods includes: a structure including a conductive region; first memory cells and first control gates associated with the first memory cells located over the structure; second memory cells and second control gates associated with the second memory cells located over the structure; and a dielectric structure between the first memory cells and the second memory cells and separating the first control gates from the second control gates. The dielectric structure extends into the conductive region and includes a liner adjacent a portion of the conductive region. The liner includes a dielectric constant different from a dielectric constant of silicon dioxide.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
31.
Memory Circuitry And Methods Used In Forming Memory Circuitry
Memory circuitry comprises vertically alternating insulative tiers and memory-cell tiers. Memory cells in the memory-cell tiers individually comprise a horizontal transistor and a capacitor electrically coupled therewith. Immediately-x-direction-adjacent channel regions of the transistors that are in the same memory-cell tier have facing z-direction sides that oppose one another in the x-direction. Insulating material is horizontally between the immediately-x-direction-adjacent channel regions. The insulating material is directly against the z-direction sides of the immediately-x-direction-adjacent channel regions and extends horizontally continuously there-between along the x-direction. Other embodiments, including method, are disclosed.
Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. The insulative tiers comprise insulative material that is vertically between immediately-vertically-adjacent of the memory-cell tiers. A portion of the insulative material is laterally beyond digitline-side edges of access lines vertically between insulator material that is in the immediately-vertically-adjacent memory-cell tiers between immediately-x-direction-adjacent digitlines. In such circuitry, (b) is being less than (a), where (a): minimum horizontal distance between the gate insulator of immediately-horizontally-x-direction-adjacent horizontal transistors and (b): minimum vertical thickness of the insulator material where vertically between the portions of the insulative material of immediately-vertically adjacent insulative tiers. Methods are disclosed.
Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. Memory cells in the memory-cell tiers individually comprise a horizontal transistor having a gate, a capacitor side, and a digitline side. A capacitor is electrically coupled with the horizontal transistor on the capacitor side. A digitline is electrically coupled with the horizontal transistor on the digitline side. Immediately-vertically-adjacent of the memory-cell tiers comprise an upper memory-cell tier and a lower memory-cell tier. The insulative tiers comprise an insulator that is vertically between the immediately-vertically-adjacent memory-cell tiers. The insulator comprises a void-space that is vertically between the gate of the upper memory-cell tier and the gate of the lower memory-cell tier. Methods are disclosed.
Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. Memory cells in the memory-cell tiers individually comprise a horizontal transistor having a gate, a capacitor side, and a digitline side. A capacitor is electrically coupled with the horizontal transistor on the capacitor side. A digitline is electrically coupled with the horizontal transistor on the digitline side. A void-space is in individual of the memory-cell tiers laterally between the digitline and the gate. Other embodiments, including method, are disclosed.
In some implementations, a memory apparatus may obtain, from a host system, a first message comprising data and link parity information associated with the data. The memory apparatus may determine that the data includes one or more errors based on the link parity information. The memory apparatus may store a first value indicating that the data includes the one or more errors. The memory apparatus may provide, as part of a read request for the data, a second message comprising the data and a second value, the second value indicating that the data includes the one or more errors.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
Systems and methods include a memory device that includes an internal voltage generator configured to receive a voltage level setting. The internal voltage generator also is configured to generate an internal voltage based at least in part on the voltage level setting. The memory device also includes ZQ calibration circuitry that is configured to receive the internal voltage from the internal voltage generator and to perform ZQ calibration using the received internal voltage.
Stealth wafer separation techniques for wafer-to-wafer bonding (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a method comprises creating, using an infrared (IR) laser, dislocations in a first wafer that delineate a first portion of the first wafer from a second portion of the first wafer; (b) bonding the first portion of the first wafer to a second wafer; and (c) separating the second portion of the first wafer from the first portion generally along the dislocations. The dislocations can include (i) a first array of dislocations that is vertically oriented with respect to the first wafer and/or (ii) a second array of dislocations that is horizontally oriented with respect to the first wafer. The dislocations can be created before or after bonding the first wafer to the second wafer.
Methods, systems, and devices for host-side alignment to a multi-phase internal clock of a memory system are described. An apparatus may be configured to implement host-side alignment to a multi-phase internal clock of the memory system. Techniques to implement host-side alignment may include a host system issuing a synchronization pattern to the memory system. The memory system may, based on the synchronization pattern, provide a return mapping that indicates a degree of alignment between a clock of the host system and phases of a multi-phase internal clock of the memory system. Based on the indication, the host system may implement a timing offset that synchronizes the host system with the memory system, thereby enabling information that is subsequently transmitted from the host system to be decoded by the memory system.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
Methods, systems, and devices for staircase formation in a memory array are described. A liner composed of a first liner material may be deposited on a tread and a first portion of the liner may be doped. After doping the first portion of the liner, a second portion of the liner may be converted into a second liner material using a chemical process. After converting the second portion of the liner into the second liner material, the first portion of the liner material may be removed so that a subsequent removal process can expose a first sub-tread. After exposing the first sub-tread, the second portion of the liner may be removed so that a second sub-tread is exposed.
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
Methods, systems, and devices for charge trapping not-OR (NOR) flash memory for stacked memory architectures are described. A memory device may include one or more three-dimensional (3D) charge trapping NOR flash memory dies in a stack of memory dies. In some examples, the stack of memory dies may also include one or more volatile memory dies, while in other examples the stack of memory dies may primarily include charge trapping NOR memory dies. The stack of memory dies may also include a logic die configured to access each of the memory dies of the stack using one or more vias, channels, or other components associated with the stack. In some examples, the logic die may access the memory dies of the stack in response to an access command received from a graphics processing unit (GPU) or other processing circuitry of the memory device.
An example apparatus includes a first wiring layer including a first wiring pattern having a first end and a second end, a second wiring layer located above the first wiring layer and including a second wiring pattern and a third wiring pattern having a third end, a first via conductor coupled between the first end of the first wiring pattern and the second wiring pattern, and a second via conductor coupled between the second end of the first wiring pattern and the third end of the third wiring pattern. At least a part of the third wiring pattern extends along the first wiring pattern so as to overlap the first wiring pattern.
Methods, systems, and devices for buffer expansion for random write operations are described. Implementations provide buffer expansion for random write operations used to store L2P address translation table data under certain recognized operation workloads.
Methods, systems, and devices for buffer expansion for random write operations are described. Implementations provide buffer expansion for random write operations used to store L2P address translation table data under certain recognized operation workloads.
Memory locations within the memory system controller are typically allocated for use during various operations. During different operational workloads, the amount of memory required for each of these different allocated memory areas may vary. By recognizing the entry of the memory system into a workload of random write operations, the memory system controller may expand a buffer size used to store the portion of the L2P address translation table data used during the write operations to retain larger portions of the L2P address translation table in the buffer.
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB]
G06F 12/0873 - Mappage de mémoire de mémoire cache vers des dispositifs ou des parties de dispositifs de stockage
43.
SELECTIVE CAVITY MERGING FOR ISOLATION REGIONS IN A MEMORY DIE
Methods, systems, and devices for selective cavity merging for isolation regions in a memory die are described. For example, formation of material structures of a memory die may include depositing a stack of alternating layers of a first material and a second material over a substrate of the memory die, forming a pattern of cavities through the stack of alternating material layers, and forming voids between layers of the first material based on removing portions of the second material. An electrical isolation region may be formed between portions of the memory die based on depositing a dielectric material in at least some of the cavities and in at least a portion of the voids between the layers of the first material.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
During a command bus training, the bus training circuitry can receive data from a bus and latch the data at the first plurality of flip-flops. The bus training circuitry can also provide the data from the first plurality of flip-flops to the XOR circuitry and provide the data from the XOR circuitry to the second plurality of flip-flops. The bus training circuitry can further latch the data at the second plurality of flip-flops and sample the data from the second plurality of flip-flops for training of a timing of the bus.
H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
H03K 19/21 - Circuits OU EXCLUSIF, c.-à-d. donnant un signal de sortie si un signal n'existe qu'à une seule entréeCircuits à COÏNCIDENCES, c.-à-d. ne donnant un signal de sortie que si tous les signaux d'entrée sont identiques
Methods, systems, and devices for dynamic parity group management for memory are described. In some instances, a first set of parity bits may be generated for a first group of pagelines and may be stored to a memory system. The memory system may detect a condition (e.g., a data recovery condition) associated with a first page of the first group of pagelines and may move the data to a second page. The memory system may generate a second set of parity bits using the first set of parity bits and a representation of the data stored to the first page. In some examples, the memory system may determine that a third page of the first group of pagelines includes an error (e.g., an uncorrectable error) and may recover the associated data using the second set of parity bits.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
A system and method for reducing peak power and improving performance during data transfers on a communication bus are disclosed. The system includes a staggering controller within a system controller that manages the timing of data transfers across multiple channels by enforcing a programmable timeout between the initiation of transfers. This approach mitigates the adverse effects of simultaneous data transfers, such as transient currents, by spreading out the current demand over time. In some examples, the timing window may be dynamically adjusted based on operational metrics like temperature and power consumption.
System and techniques for managing block addresses in a memory device are described herein. A request for the memory device to perform an operation can include a node identifier. The memory device can access a node based on the node identifier and identify a physical block in the memory device from a reference to the physical block stored in the node. The memory device can then perform the operation using the physical block as identified from the node.
A semiconductor device can include a semiconductor substrate singulated from a device wafer having had multiple semiconductor devices formed thereon. The semiconductor substrate can include a first corner, a first sidewall extends in a first direction from the first corner, and a second sidewall extending in a second direction from the first corner. The first sidewall can include a first laser modification extending along the first direction and the second sidewall can include a second laser modification extending along the second direction. A portion of the second sidewall between the first corner and the second laser modification can (i) exclude laser modification, or (ii) the second laser modification can be offset from the first corner along the second direction.
A processing device, operatively coupled with a memory device, determines, based on an error count at an area within a first die of the memory device, a usage type associated with the first die. The processing device identifies, based on the usage type associated with the first die, a set of cells residing on the first die to perform a programming operation in a manner avoiding the area within the first die. The processing device performs the programming operation on the set of cells.
Methods, systems, and devices for manufacturing a charge trap memory system are described. The method of manufacturing may include forming first pillars that extend through a stack of layers of the memory system, forming first cavities that extend though the stack of layers and are each positioned between respective pairs of the first pillars, forming piers in the first cavities, forming second cavities that extends through the stack of layers by removing some of the material of the first pillars, and forming second pillars in the second cavities.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
51.
Memory Circuitry And Methods Used In Forming Memory Circuitry
Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. Memory cells in the memory-cell tiers individually comprise a horizontal transistor having a gate, a capacitor side, and a digitline side. A capacitor is electrically coupled with the horizontal transistor on the capacitor side. A digitline is electrically coupled with the horizontal transistor on the digitline side. The insulative tiers comprise insulative material that is vertically between immediately-vertically-adjacent of the memory-cell tiers. A portion of the insulative material is laterally beyond a digitline-side edge of the gates of the immediately-vertically-adjacent memory cells. The portion tapers towards the digitline. Other embodiments, including method, are disclosed.
In some implementations, a memory apparatus may obtain, from a host system, a command indicating that the memory apparatus is to provide data to the host system. The memory apparatus may identify a status of one or more fault mode registers based on the command. The memory apparatus may provide, to the host system, a message comprising the data and comprising the status of the one or more fault mode registers.
Systems and methods include a memory device that includes ZQ calibration circuitry that includes a ZQ resistor. The system also includes multiple driver unit circuitries configured to be calibrated using the ZQ resistor. At least one of the plurality of driver unit circuitries includes multiple sub-drivers. The multiple sub-drivers include a first set of sub-drivers each having a first impedance and a second set of sub-drivers each having a second impedance that is different than the first impedance.
Methods, systems, and devices for memory recovery partitions are described. A memory system may include a memory array configured with one or more logical partitions. In some examples, a primary boot image may be stored to a first logical partition and a recovery boot image may be stored to a second logical partition. During a boot operation, the memory system may determine whether the primary boot image includes one or more errors. If the primary boot image includes relatively few (or no) errors, the memory system may boot using the primary boot image. If the primary boot image includes a relatively high quantity of errors (e.g., higher than a threshold quantity of errors), the memory system may autonomously load a recovery boot image stored to the second logical partition.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
Methods, systems, and devices for reducing charge migration in a memory system are described. The memory system may receive a command to program a first set of memory cells with first data. The memory system may generate a scrambling seed to scramble the first data. Before programming the scrambled data, the memory system may compare a first set of states in the scrambled data with a second set of states in second data to determine an aggregate difference between the sets of states. If the aggregate difference is less than a threshold, the memory system may program the first set of memory cells with the first data. If the aggregate difference is greater than a threshold, the memory system may generate a new scrambling seed to rescramble the first data and determine a new aggregate difference by comparing states of the rescrambled data to the states of the second data.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A method for performing random read operations on memory cells is provided. The method comprises receiving identification of a list of target blocks of the array of memory cells that need to be opened for random read operations. The method further comprises opening the list of target blocks before performing read operations on any one of the list of target blocks. The method further comprises performing read operations on the list of target blocks. The method further comprises closing the list of target blocks.
A system and method for dynamic power management in computing devices such as memory devices. The system includes a controller and multiple memory dies connected via a power management bus. The controller dynamically claims and releases power tokens based on current and projected power needs, optimizing power distribution and improving performance. The method involves determining power requirements, claiming power tokens, and waiting for power tokens to be released by memory dies when the system exceeds its power budget. This approach ensures efficient power usage, reduces latency, and enhances overall system performance by preventing power allocation inefficiencies.
Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. Each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. Each of the sections can be directly coupled together. Further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. The wirebonds can be directly coupled to the exposed surface of the uppermost section.
Implementations described herein relate to memory device log data storage. In some implementations, a memory device may store a first data stream associated with a first type of log data in a circular buffer. The memory device may store a second data stream associated with a second type of log data in another memory location. The memory device may detect an event included in the second data stream that is associated with an attribute level that satisfies a threshold. The memory device may write data stored in the circular buffer after a time at which the event is detected to a non-volatile memory based on the attribute level satisfying the threshold, wherein the data stored in the circular buffer is stored in the non-volatile memory in connection with data associated with the event.
A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry including transistors at least partially overlying the first semiconductor structure, and a first isolation material covering the first semiconductor structure and the control logic circuitry. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material of the second microelectronic device structure is bonded to the first isolation material of the first microelectronic device structure to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Microelectronic devices, electronic systems, and additional methods are also described.
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory device. The memory device includes levels of conductive materials interleaved with levels of dielectric materials and a memory cell pillar extending through the levels of conductive materials and the levels of dielectric materials. The memory cell pillar includes: a first dielectric material; a second dielectric material; a memory storage material between the first dielectric material and the second dielectric material; a semiconductor material adjacent the second dielectric material; a recess between a portion of the first dielectric material, a portion of the second dielectric material, and a portion of the memory storage material; and a third dielectric material filled in the recess.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
A first portion of a bitmap from a set of bitmaps designated as a current active bitmap at a first point in time is modified responsive receiving a write request for a target page within a namespace of a memory device during migration of the namespace. The first portion containing a bit associated with the target page. The modified first portion is stored. Whether a second portion of a bitmap from the set of bitmaps designated as the current active bitmap at a second point in time matches the modified first portion is determined. The second portion contains a bit associated with the target page. The current active bitmap has not changed from the first point in time is determined responsive to determining that the second portion matches the modified first portion.
This disclosure concerns a system for dynamically controlling L2P table deallocation. The system receives a request to deallocate a set of entries of a logical-to-physical (L2P) table associated with a memory device, the set of entries corresponding to a memory device region comprising a plurality of logical translation units (LTUs) and, in response to receiving the request, deallocates a front set of LTUs of the region and a tail set of the LTUs of the region leaving a non-deallocated portion of the region. The system divides the non-deallocated portion of the region into a plurality of sub-regions and computes a size associated with a write command received from a host. The system dynamically selects a number of sub-regions in the plurality of sub-regions of the non-deallocated portion to deallocate based on the size associated with the write command.
A system and method are provided for reading data from a memory device. The system and method receive a request to read data from a portion of a memory device. The system and method, in response to receiving the request to read the data, determine whether the portion of the memory device is available for writing data. The system and method selectively apply boundary word line (WL) offset values to read one or more WLs of the portion of the memory device in addition to applying inner WL offset values in response to determining whether the portion of the memory device is available for writing data.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
65.
EMBEDDED SILICON GERMANIUM WITH IMPLANT THROUGH SPACER FLOW
A variety of applications can include an electronic device having a transistor with embedded silicon germanium underneath spacers without divots to the active areas of the transistors underneath the spacers. The spacers can be structured on and contacting sidewalls of the gate stacks of the transistors. The lack of divots provides the contact of the spacers to the active areas without an oxide or with a thin native oxide and provides a uniform channel-structure-to-drain interface. A transistor of the electronic can have a silicon germanium channel structure under a gate dielectric with extensions laterally from the ends of the gate dielectric and an embedded silicon germanium source/drain contacting an extension of the silicon germanium channel structure, with a spacer on and contacting the extension, with the spacer being structured without an oxide contacting the extension or with a thin native oxide between and contacting the spacer and the extension.
A system and method for reading data from a memory device are provided. The system and method determine a center of valley (CoV) shift for an individual memory die and generate a read offset by program-erase count (PEC) (ROBP) lookup table individually associated with the individual memory die based on the determined CoV shift, the ROBP lookup table including read level offset values for different word line groups and PEC counts. The system and method apply the ROBP lookup table to adjust read levels for the individual memory die during memory operations to compensate for threshold voltage degradation.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 29/56 - Équipements externes pour test de mémoires statiques, p. ex. équipement de test automatique [ATE]Interfaces correspondantes
67.
APPARATUS WITH THERMAL DISTRIBUTION NETWORK AND METHODS FOR OPERATING THE SAME
Methods, apparatuses, and systems related to a thermal distribution network are described. The thermal distribution network includes thermally conductive material configured to route thermal energy, generated by a supporting device, along a vertical path and through one or more portions of a semiconductor device stacked over the supporting device.
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
In some implementations, a programmable processor of a memory system may receive, from a host system, programming information, the programming information indicating one or more near memory processing (NMP) tasks that are to be performed by the programmable processor. The programmable processor may execute the one or more NMP tasks based on the programming information.
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
Methods, systems, and devices for techniques for bit line contact active area reduction are described. In some examples, the memory system may include multiple silicon structures vertically extending through an oxide layer. The multiple silicon structures may include a first set of silicon structures that are each coupled with a respective bit line of the memory system and a second set of silicon structures that are coupled with a respective memory component of the memory system. The memory system may also include multiple nitride structures that each at least partially surround a respective silicon structure of the first set of silicon structures.
Methods, systems, and devices for error control for compressed and uncompressed regions of memory are described. A memory system may configure an uncompressed region of memory to operate according to a first error control capability and may configure a compressed region of memory to operate according to a second error control capability. The second error control capability may be capable of correcting relatively more errors than the first error control capability. The memory system may detect and correct a correctable error associated with the uncompressed memory or the compressed memory using the first error control capability or the second error control capability, respectively. In some examples, the memory system may configure the uncompressed region to switch to operating according to the second error control capability based on detecting one or more errors.
Methods, systems, and devices for sub-channel switching using redundant pins are described. The described techniques may enable a host system to switch from communicating with a memory system via a first set of pins associated with a first sub-channel to communicating with the memory system via a second set of pins associated with a second sub-channel based on detecting a fault associated with the first set of pins. In some examples, the host system may communicate via both the first set of pins and the second set of pins. The memory system may perform a comparison between data received via the first set of pins and the second set of pins, and may indicate to the host system if a difference is detected. The host system may switch to communicating via one of the first set of pins or the second set of pins based on detecting the difference.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
Methods, systems, and devices for efficient read disturb scanning are described. A memory system may limit a quantity of word lines scanned as part of a read disturb scan. For example, the memory system may select a threshold quantity of word lines of a block for the read disturb scan based on a characterization of the word lines, such as selecting one or more word lines having higher bit error rates than other word lines of the block. The memory system may perform the read disturb scan on the selected one or more word lines to determine respective failure bit counts of the selected word lines and exclude unselected word lines of the block from the read disturb scan. The memory system may determine whether to perform a refresh operation on the block based on whether a respective failure bit count satisfies a threshold failure bit count.
Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.
H03M 13/15 - Codes cycliques, c.-à-d. décalages cycliques de mots de code produisant d'autres mots de code, p. ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
In accordance with examples as described herein, a memory system may initialize a data optimization operation by transmitting signaling to a host system. For example, the memory system may identify data associated with non-sequential logical block addresses (LBAs), and may indicate the discontinuous LBAs to the host system. In response, the host system may indicate which of the discontinuous LBAs represent sequential data. Accordingly, the memory system may sequentialize the one or more of the discontinuous LBAs to defragment the associated data.
A system includes a memory device; and a processing device, operatively coupled to the memory device, the processing device to perform operations including: determining an offset value associated with a set of memory cells of the memory device, wherein the offset value corresponds to a temperature range associated with an error handing operation directed to the set of memory cells; and responsive to determining that a temperature measured at the memory device falls in the temperature range, adjusting, based on the offset value, a temperature compensation value used in a subsequent error handling operation.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 29/56 - Équipements externes pour test de mémoires statiques, p. ex. équipement de test automatique [ATE]Interfaces correspondantes
Systems and methods include self-training an equalizer of a semiconductor device using the semiconductor device. The semiconductor device receives an indication of a condition for re-training of the equalizer. The semiconductor device operates the equalizer based on trained values derived during the self-training. The semiconductor device also determines that the condition has been met, and in response, the semiconductor device re-trains the equalizer without invocation of re-training by a host device coupled to the semiconductor device.
G11C 29/12 - Dispositions intégrées pour les tests, p. ex. auto-test intégré [BIST]
G11C 29/20 - Dispositifs pour la génération d'adressesDispositifs pour l'accès aux mémoires, p. ex. détails de circuits d'adressage utilisant des compteurs ou des registres à décalage à rétroaction linéaire [LFSR]
A memory subsystem that includes a memory device, a first host interface, a serial interface controller that provides host access to a boot partition of the memory device using the first host interface, a second host interface, and a high-speed interface controller that provides host access to a user partition of the memory device using the second host interface.
Methods, systems, and devices for block replacement using combined blocks are described. A memory system may receive a command to perform an access operation on a block of the memory system. The memory system may determine whether a block pool includes a second block configured to replace the block based on a failure to perform the access operation. The memory system may generate a combined block for replacing the block based on determining an absence of the second block in the block pool. The combined block may be generated by combining two half good blocks (HGBs) in a same plane of the memory system as the block. In some cases, a second block pool may be generated and the combined block may be stored to the second block pool. The memory system may select the combined block from the second block pool and replace the block with the combined block.
A system includes a first memory device; a second memory device; and a processing device, operatively coupled with the first memory device and the second memory device, to perform operations including: allocating a first portion of the second memory device to a first namespace of a plurality of namespaces of the second memory device and allocating a first portion of the first memory device to a first address mapping data structure for storing metadata of the first namespace. A size of the first address mapping data structure is calculated using a first address mapping granularity level of the first address mapping data structure and a capacity of the first portion of the second memory device. The operations further include allocating a second portion of the second memory device to a second namespace of the plurality of namespaces of the second memory device and allocating a second portion of the first memory device to a second address mapping data structure for storing metadata of the second namespace. A size of the second address mapping data structure is calculated using a second address mapping granularity level of the second address mapping data structure and a capacity of the second portion of the second memory device.
A method includes dividing an on-die capacitor of a memory device into a plurality of capacitor banks, charging the plurality of capacitor banks sequentially during an initialization of the memory device, determining a supply voltage for the memory device is below a threshold voltage, and discharging the plurality of capacitor banks sequentially to provide power to the memory device in response to determining the supply voltage is below the threshold voltage.
A system comprises a memory device and a processing device, the processing device operatively coupled with the memory device to perform operations. Responsive to determining a block satisfies a checking pool threshold criterion, the processing device assigns the block to from an active pool to a checking pool. The processing device performs a reliability checking (RC) scan on the block. The processing device determines, based on a reliability metric associated with the block and determined from the RC scan, whether the block satisfies a retirement threshold criterion. Responsive to determining that the block satisfies the retirement threshold criterion, the processing device retires at least a portion of the block, wherein memory operations can no longer be performed on the retired portion of the block.
G11C 29/00 - Vérification du fonctionnement correct des mémoiresTest de mémoires lors d'opération en mode de veille ou hors-ligne
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
82.
Performing Serialized Update Procedures during a Refresh Period
Apparatuses and techniques for performing serialized update procedures during a refresh period are described. In example aspects, a memory device performs a normal refresh operation, which refreshes multiple rows simultaneously. The refreshed rows are associated with different refresh sections and different column segments. While refreshing the rows and prior to an end of a refresh cycle time (tRFC), the memory device updates, in a serialized manner, usage-based-disturbance data that is stored within the refreshed rows. In particular, the memory device performs, in series, multiple update procedures, which overwrites values of the usage-based-disturbance data that are stored within the refreshed rows. For example, the multiple update procedures can set values of activation counts that are stored within the refreshed rows to a predetermined value. By performing the multiple update procedures in series, the memory device can utilize appropriate column repair solutions to access the usage-based-disturbance data and avoid a potential conflict on global input/output (GIO) lines.
A memory device is polled for status information about an array operation being performed at the memory device. The status information is obtained from the memory device based on the polling. One or more polling parameters are adjusted based on the status information.
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory device. The memory device includes levels of conductive materials interleaved with levels of dielectric materials and a memory cell pillar extending through the levels of conductive materials and the levels of dielectric materials. The memory cell pillar includes: a first dielectric material; a second dielectric material; a memory storage material between the first dielectric material and the second dielectric material; a semiconductor material adjacent the second dielectric material; a recess between a portion of the first dielectric material, a portion of the second dielectric material, and a portion of the memory storage material; and a third dielectric material filled in the recess.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes one or more semiconductor pillars extending vertically from a substrate, the one or more semiconductor pillars including respective upper portions having a first width in a horizontal direction and the one or more semiconductor pillars including respective lower portions having a second width in the horizontal direction, where the first width is greater than the second width. The integrated assembly may further include a dielectric material extending between the one or more semiconductor pillars, where the respective upper portions extend over respective portions of the dielectric material.
A memory device can include one or more core dies and an interface die. A read clock signal having a first frequency may be generated on the interface die and provided to circuitry on the interface die. The read clock signal is provided from the interface die to the core die(s). Access operations (e.g., read operations) are performed on a memory array on at least one core die based on the read clock signal. The data read from the memory array(s) is provided to the interface die. A data clock signal having a second frequency is generated on the interface die based on the read clock signal. The read data is output from the interface die based on the data clock signal. In some instances, pulses in the data clock signal are aligned with rising and falling edges of the pulses in the read clock signal.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
Devices and techniques that provide for a wafer-on-wafer interconnect architecture that optimizes wafer usage and reduces general-purpose input/output (GIO) delay are described herein. A memory device may include a complementary metal-oxide-semiconductor (CMOS) wafer, the CMOS wafer including controller circuitry and a secondary memory device; and a memory array wafer comprising a memory array of a plurality of memory cells, the memory array wafer stacked on the CMOS wafer using wafer-on-wafer interconnect architecture, the plurality of memory cells arranged in pages, rows, and columns, wherein the secondary memory device is configured to store metadata for at least a portion of the pages.
Control logic in a memory device executes a read operation of at least a portion of first data stored in a first page buffer associated with a first memory plane of a plurality of memory planes of the memory device. A write operation is executed to cause second data associated with the at least the portion of the first data to be written to a second page buffer of the memory device.
Methods, systems, and devices for error correction code (ECC) coverage extension in a memory system are described. In a first technique, the memory system may correct, using a first ECC scheme, data bits read from a first memory die that has failed, the data bits included in a first codeword protected by the first ECC scheme. The memory system may generate, using a second ECC scheme and after correcting the data bits using the first ECC scheme, a second codeword that includes the data bits based on the memory system having a threshold quantity of failed memory dies. The memory system may write the data bits of the second codeword to a second memory die previously used to store parity bits for the first codeword.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
90.
CHARGE TRAPPING FLASH NOR MEMORY IN MEMORY SYSTEMS
Methods, systems, and devices for charge trapping flash NOR memory in memory systems are described. A memory system may include processing circuitry configured to perform one or more operations, a not-or (NOR) memory device coupled with the processing circuitry via a first interface, and a volatile memory device coupled with the NOR memory device via a second interface and the processing circuitry. Accordingly, the NOR memory device may be configured to provide first data, such as one or more model parameters for an artificial intelligence model, to the processing circuitry via the first interface as part of performing a first operation of the one or more operations. The volatile memory device may be configured to communicate second data, such as updated model parameters, with the NOR memory device via the second interface and the processing circuitry as part of performing a second operation of the one or more operations.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
91.
TECHNIQUES FOR CONCURRENTLY-FORMED CAVITIES IN THREE-DIMENSIONAL MEMORY ARRAYS
Methods, systems, and devices for techniques for concurrently-formed cavities in three-dimensional memory arrays are described. As part of forming a memory die, a plurality of cavities may be formed by a set of one or more material removal operations, and different subsets of the plurality of cavities may be used to form different features of the memory die. In some examples, a sacrificial region may be formed in accordance with one or more material addition or removal operations, and such a sacrificial region may include openings that support the formation of various structures of a memory device. After the formation of such structures, the sacrificial region may be isolated from an active region by merging a subset of the previously-formed plurality of cavities.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
Methods, systems, and devices for accessing dummy word lines using a TSV are described. Techniques described herein may enable a memory system to include a via (e.g., a through-silicon via (TSV)) that is exposed through an opening in a substrate on a side of the substrate opposite one or more word lines and “dummy” word lines. As described herein, a via may refer to a contact that may enable biasing of a conductive line and quantifying performance of a conductive line. The TSV may extend to a same height as the substrate or may extend to a height above the substrate. The TSV may be in direct or indirect contact with the dummy word lines (e.g., via a Schottky contact, an oxide fuse, or neither the Schottky contact or oxide fuse). In some examples, the memory system may include a separate TSV coupled with each dummy word line.
The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.
Methods, systems, and devices for manufacturing a charge trap memory system are described. The method of manufacturing may include forming first pillars that extend through a stack of layers of the memory system, forming first cavities that extend though the stack of layers and are each positioned between respective pairs of the first pillars, forming piers in the first cavities, forming second cavities that extends through the stack of layers by removing some of the material of the first pillars, and forming second pillars in the second cavities.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire
95.
PAGE REQUEST INTERFACE SUPPORT IN HANDLING POINTER FETCH WITH CACHING HOST MEMORY ADDRESS TRANSLATION DATA
A method includes buffering, in a pointer buffer of host interface circuitry of a processing device, a plurality of pointers associated with a memory command. The memory command is one of a write command or a non-logical block address read command. The method includes sending address translation requests to an address translation circuit, of the host interface circuitry, for respective translation units of the memory command, each translation unit comprising a subset of the plurality of pointers. The method includes triggering a page request interface handler to send a page miss request to a translation agent of a host system upon an address translation request for a translation unit of the memory command missing at a cache of the address translation circuit. The page miss request includes a virtual address of the translation unit. The method includes discarding the plurality of pointers from a pointer buffer.
G06F 12/1045 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB] associée à une mémoire cache de données
96.
MANAGING NAMESPACE MAPPING, TRUSTED COMPUTING GROUP RANGES, AND ENCRYPTIONS IN A MEMORY SUB-SYSTEM
A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to modify one or more regions of the memory device; identifying one or more mapping structures associated with each region of the one or more regions of the memory device; determining that a counter satisfies a threshold criterion, wherein the counter indicates a number of memory access commands at the one or more regions; creating a copy of each mapping structure associated with each region; and modifying the copy of each mapping structure according to the request to modify the one or more regions of the memory device.
Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a base layer, a dielectric interposer coupled to the base layer and including a first outer surface facing the base layer and an opposing second outer surface facing away from the base layer and spaced apart from the first outer surface in a direction, a first electrical-connection cut-in in the second outer surface that extends, in the direction, toward the first outer surface, and one or more first electrical connections disposed within the first electrical-connection cut-in such that at least a portion of the one or more first electrical connections does not extend, in the direction, beyond the second outer surface.
Apparatuses and methods for performing read operations using an offset based upon slow charge loss characteristics are provided. One example apparatus can include a controller configured to apply a read voltage to a word line in the array of memory cells during a read operation on the word line, wherein the read voltage includes an offset associated with a slow charge loss characteristic of the word line.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
99.
ALLOCATION OF MEMORY FROM A MEMORY SPACE OF A MEMORY SUB-SYSTEM TO ACCESS A STORAGE SPACE OF THE MEMORY SUB-SYSTEM
A memory sub-system having first memory cells configured to provide a memory space, and second memory cells configured to provide a storage space. A controller of the memory sub-system is configured to: allocate, in response to a memory allocation request from a host system connected to the memory sub-system, a block of memory from the memory space; and communicate, to the host system, a starting memory address of the block of memory. The memory allocation request can be retrieved from a submission queue configured for the memory sub-system in accordance of a storage access protocol (e.g., non-volatile memory express (NVMe)); and the starting memory address can be provided in a completion record for the memory allocation request in a completion queue in accordance of the storage access protocol.
A memory sub-system having a memory space accessible to a host system using a memory access protocol and a storage space accessible to the host system using a storage access protocol. The memory sub-system is configured to: execute a storage access request identifying a logical block address in the storage space; store information indicating resources used in execution of the storage access request; receive a notification indicating a completion of access made via at least the storage access request; and free the resources based on the information and in response to the notification. For example, the resources can include a block of memory allocated from the memory space and/or used during the execution of the storage access request.
