The embodiments herein relate to structures of MIM capacitors including a sealed void and methods of forming the same. According to an aspect of the present disclosure, a structure is provided. The structure includes a MIM capacitor having a first electrode and a second electrode over the first electrode. A conductive via is laterally adjacent to the second electrode and electrically connected to the first electrode. A void extends around an outer perimeter of the second electrode.
Structures including a photonic device, such as a spot-size converter, and an undercut, and related methods. The structure comprises a photonic device, a semiconductor substrate, and a dielectric layer disposed between the photonic device and the semiconductor substrate. The dielectric layer includes a plurality of D-shaped openings that are laterally offset from the photonic device, and each of the plurality of D-shaped openings has a first sidewall portion that is curved and a second sidewall portion that is substantially planar.
Embodiments of the disclosure provide a gate structure including a jutted region over a corner segment of a semiconductor region. A structure according to the disclosure includes a semiconductor region within a substrate. The semiconductor region includes a first edge, a second edge oriented perpendicularly to the first edge, and a first corner segment connecting the first edge to the second edge. A gate structure includes a jutted region including a curvilinear portion(s) or angled linear portion(s) over corner segment(s).
Disclosed is a charge pump circuit including: a single primary charge pump stage or multiple primary charge pump stages connected in series; a pass transistor connected between an output node of the primary charge pump stage (or of the last of the multiple primary charge pump stages, if applicable) and an output terminal; and a supplementary charge pump stage. The supplementary charge pump stage receives the same input voltage as the primary charge pump stage (or the same input voltage as the last of the multiple primary charge pump stages, if applicable) and controls the gate of the pass transistor to reduce ripple at the output terminal. A capacitive load can also be connected to the output terminal to reduce ripple and the size of the capacitive load can be selected to achieve a desired balance between the amount of ripple and circuit size.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
5.
Field plate structure to reduce self-heating in transistor and related method
A structure includes a transistor, e.g., HEMT, with a field plate positioned laterally to a side of an active gate and including a first portion extending over the active gate. A dielectric layer isolates a lower surface of the first portion from an upper surface of the active gate. A field plate contact includes interconnect layers located directly over the active gate and electrically coupled to the first portion directly over the active gate. The field plate contact allows electrical operation of the field plate, but also acts as a thermally conductive path from the active gate through the interconnect layers to cool likely hot spots within the transistor.
H10D 64/00 - Electrodes of devices having potential barriers
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
6.
Bi-directional semiconductor-controlled rectifier with dual-level isolation structures and method
Disclosed is a semiconductor structure including a device (e.g., a bi-directional semiconductor-controlled rectifier, such as a bi-directional silicon-controlled rectifier (BDSCR)) and, within the device, at least two dual-level isolation structures. Each dual-level isolation structure includes a first section at the top surface of the semiconductor substrate and one or more second sections extending through the first section deeper into the semiconductor substrate. The dual-level isolation structures are positioned within the device so as to increase well resistance. By increasing well resistance, the trigger voltage of the device can be reduced without increasing device size. Also disclosed is a method of forming dual-level isolation structures within such a device.
H10D 62/815 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wellsSemiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
7.
VOLTAGE REGULATOR INCLUDING A PAIR OF FEEDBACK CONTROL LOOPS FOR DRIVE TRANSISTOR CONTROL
A low drop-out voltage regulator (LDO) circuit structure includes a drive transistor with first connected to an input voltage node, a second terminal connected to an output voltage node and a voltage divider, and a third terminal (i.e., a control terminal). The structure employs a pair of concurrently operating feedback control loops between a feedback voltage node of the voltage divider and the control terminal to continuously adjust a control voltage applied to the control terminal and thereby reduce ripple of an output voltage (Vout) at the output voltage node. A first feedback control loop includes comparator and a push capacitor connected between the feedback voltage node and the control terminal. The second feedback control loop includes an operational amplifier connected between the feedback voltage node and the control terminal. The first feedback control loop operates a faster speed than the second to quickly initiate the necessary control voltage adjustments.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
The present disclosure relates to semiconductor structures and, more particularly, to Hall effect sensors and methods of manufacture. The structure includes: a semiconductor material; a buried isolation layer below the semiconductor material; a deep trench structure having conductive material and within the semiconductor material and contacting the buried isolation layer; a plurality of shallower trench structures having the conductive material and partially within the semiconductor material and remote from the buried isolation layer; and a doped region within the semiconductor material adjacent to the plurality of shallower trench structures.
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
The present disclosure relates to semiconductor structures and, more particularly, to a transistor integration scheme and methods of manufacture. The structure includes: a first device on a semiconductor substrate; and a second device on the semiconductor substrate, the second device having a recessed channel region below a surface of the first device.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Structures that include an isotopically-depleted semiconductor layer and methods of forming such structures. The structure comprises a semiconductor layer comprising a semiconductor material having an isotope with a concentration that is less than a natural abundance of the first isotope and greater than zero parts per million.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
GlobalFoundries Dresden Module One Limited Liability Company & Co. KG (Germany)
Inventor
Kleimaier, Dominik Martin
Dünkel, Stefan
Mulaosmanovic, Halid
Zhao, Zhixing
Abstract
A device with inverter functionality and a tunable trigger voltage includes a PFET and an NFET connected in series. The FETs are multi-gated and at least one FET is a threshold voltage (VT) programmable FET. In some embodiments, both FETs are dual-gated (i.e., have two gates) with at least one gate of the two gates being programmable (i.e., configured for VT programmability). In these embodiments, the device includes an input node connected to primary gates of the FETs and additional nodes connected to VT-programmable secondary gates of the FETs, respectively. Alternatively, the device includes an input node connected to secondary gates of the FETs and additional nodes connected to VT-programmable primary gates of the FETs, respectively. Alternatively, the device includes an input node connected to primary gates of the FETs and another input node connected to secondary gates of the FETs, where the primary gates and/or secondary gates are programmable.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
12.
ISOLATION STRUCTURE FOR MULTI-VOLTAGE INTEGRATED CIRCUIT
Disclosed are embodiments of an integrated circuit (IC) including a first IC section operating in a first voltage domain, a second IC section operating in a second voltage domain, and an isolation structure between the two sections. The isolation structure can include a trench isolation region within a semiconductor layer, isolating first PFETs and, optionally, isolating second PFETs. The isolating first PFETs can be series-connected and can include a first portion of the semiconductor layer between a functional PFET of the first IC section and a first edge of the trench isolation region. Additionally, the isolating first PFETs can operate in the first voltage domain and can be biased so as to remain always off. The isolating second PFETs can be similarly configured between a functional PFET of the second IC section and a second edge of the trench isolation region opposite the first edge.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
13.
NEURON CIRCUITS FOR A SPIKING NEURAL NETWORK BASED ON A VOLTAGE-CONTROLLED MAGNETIC-TUNNEL-JUNCTION LAYER STACK
Structures for a spiking neural network including a magnetic-tunnel-junction layer stack and methods of forming such structures. The structure comprises a leaky-integrate-fire neuron including a magnetic-tunneling-junction layer stack, and a power source connected to the magnetic-tunneling-junction layer stack. The power source is configured to provide a plurality of voltage pulses to the magnetic-tunneling-junction layer stack.
Disclosed is a charge pump circuit including: a single primary charge pump stage or multiple primary charge pump stages connected in series; a pass transistor connected between an output node of the primary charge pump stage (or of the last of the multiple primary charge pump stages, if applicable) and an output terminal; and a supplementary charge pump stage. The supplementary charge pump stage receives the same input voltage as the primary charge pump stage (or the same input voltage as the last of the multiple primary charge pump stages, if applicable) and controls the gate of the pass transistor to reduce ripple at the output terminal. A capacitive load can also be connected to the output terminal to reduce ripple and the size of the capacitive load can be selected to achieve a desired balance between the amount of ripple and circuit size.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 1/15 - Arrangements for reducing ripples from DC input or output using active elements
15.
CAPACITIVE JUNCTION BETWEEN CONDUCTIVE LINE AND CONDUCTIVE PILLAR WITH METHODS TO FORM SAME
Structures of the disclosure include a first conductive line within a dielectric material. The dielectric material extends over the first conductive line. A second conductive line is within the dielectric material and substantially vertically aligned with the first conductive line. A conductive pillar is within the dielectric material between the first conductive line and the second conductive line. The conductive pillar includes an upper surface contacting a lower surface of the second conductive line or a lower surface contacting an upper surface of the first conductive line. A vertical thickness of the conductive pillar is less than a vertical thickness between the first conductive line and the second conductive line. a first capacitive junction is between the conductive pillar and one of the first conductive line and the second conductive line. A second capacitive junction is between the conductive pillar and a horizontally adjacent conductive pillar.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 - Layout of the interconnection structure
16.
Field-effect transistors with heterogenous doped regions in the substrate of a silicon-on-insulator substrate
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a silicon-on-insulator substrate including a semiconductor layer, a semiconductor substrate, and a dielectric layer between the semiconductor layer and the semiconductor substrate. The semiconductor substrate includes first and second doped regions, the first doped region has a first conductivity type, and the second doped region has a second conductivity type different from the first conductivity type. The structure further comprises first and second source/drain regions in the semiconductor layer, and a gate structure laterally between the first source/drain region and the second source/drain region. The first source/drain region overlaps with the first doped region, and the second source/drain region overlaps with the second doped region.
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
The present disclosure relates to semiconductor structures and, more particularly, to devices with a three dimensional channel and methods of manufacture. The structure includes: a drift region within a semiconductor substrate; a shallow trench isolation structure within the drift region; and a gate structure within the shallow trench isolation structure and extending to an upper surface of the semiconductor substrate adjacent to the drift region.
Embodiments of the disclosure provide a bipolar transistor structure with a ferroelectric material. A structure of the disclosure may include a base over a substrate. The base includes a first portion laterally between an emitter and a collector, and a second portion over the first portion. A ferroelectric spacer is adjacent the second portion of the base. Other structures include a ferroelectric layer over a back gate terminal of a substrate. A base is on the ferroelectric layer. The base includes a first portion laterally between an emitter and a collector, and a second portion over the first portion.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A pre-driver includes first, second, third, and fourth P-channel field effect transistors (PFETs) with voltage ratings equal to a low first voltage (V1). Between power rails at V1 and at a higher second voltage (V2), the first and third PFETs are series-connected and the second and fourth PFETs are also series-connected. The third and fourth PFETs are cross-coupled. The first and second PFETs have gates that receive a pre-driver input signal (Pin) that switches between V2 and ground and an inverted pre-driver input signal (Pinb), respectively. At an output node between the first and third PFETs, the pre-driver outputs a driver input signal (Din) that switches between V2 and V1. A circuit includes this pre-driver (e.g., connected between a voltage level shifter and a driver or connected between a voltage level shifter and a buffer).
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
20.
THREE-DIMENSIONAL INTEGRATED CIRCUIT (3DIC) AND 3DIC DESIGN METHOD AND SYSTEM
A three-dimensional integrated circuit (3DIC) design method and system includes metal stack and bonding pitch optimization to improve power, performance, and area (PPA). The resulting 3DIC includes a first chip and a second chip. A last metal level of the second chip can be bonded to the last metal level of the first chip by bonding elements. The bonding pitch of the bonding elements can be at least as large as the pitches of the first chip last metal level and the second chip last metal level. The metal stack configurations of each chip may be the same or different. With different metal stack configurations, the total numbers of metal levels on each chip, the thicknesses of the metal levels on each chip and/or the pitches of the last metal levels on each chip may be different.
Structures for a photonic chip that enable the measurement of the group velocity of light in a photonic component and methods of forming such structures. The structure comprises a photonic component having an input and an output, a first waveguide core including a first section coupled to the input of the photonic component, and a second waveguide core including a second section coupled to the output of the photonic component. The structure further comprises a first reflector adjacent to the first section of the first waveguide core, and a second reflector adjacent to the second section of the second waveguide core.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/126 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind using polarisation effects
A disclosed low noise amplifier (LNA) includes a common-emitter amplifier (CE-A), a common-gate amplifier (CG-A) and various passive devices in CE-A and CG-A. CE-A includes an NPN-type bipolar junction transistor (BJT) with emitter and collector (E/C) regions and a base region between the E/C regions and connected to an input node. CG-A includes P-channel field effect transistor (PFET) with source and drain (S/D) regions, a channel region between the S/D region, and a gate adjacent to the channel region. The drain region of the PFET is connected to an output node. Additionally, a common inductor, collector region of the BJT, and source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) with the BJT and FET on different chips and with passive devices in back end of the line regions between the BJT and FET.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Structures including a photonic device with thermal isolation and related methods. The structure comprises a semiconductor substrate including a first cavity, a second cavity, and a wall between the first cavity and the second cavity. The structure further comprises a photonic device over the first cavity, the second cavity, and the wall, and a dielectric layer between the photonic device and the wall of the semiconductor substrate.
H01L 31/024 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 31/0232 - Optical elements or arrangements associated with the device
H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
24.
FLASH MEMORY CELL ARRAYS WITH A CONTROL GATE STRAP
Structures for a flash memory cell array and methods of forming a structure for a flash memory cell array. The structure comprises a first gate stack including a first control gate and a second gate stack including a second control gate. The first control gate has a first sidewall, a second sidewall opposite from the first sidewall, and a gate strap region, and the gate strap region includes a projection extending outwardly from the first sidewall of the first control gate. The second control gate has a first sidewall and a second sidewall opposite from the first sidewall, and the second sidewall of the second control gate faces the second sidewall of the first control gate.
The disclosure provides structures and methods to provide a discontinuous barrier film between an emitter and base of a bipolar transistor. A structure according to the disclosure includes a discontinuous barrier film vertically interposed between an emitter and a base of a heterojunction bipolar transistor. Methods of the disclosure include: forming a collector terminal within a semiconductor substrate; forming a base terminal on the collector terminal; forming a discontinuous barrier film on the base terminal; and forming an emitter terminal over the base terminal and the discontinuous barrier film to define a bipolar transistor. The discontinuous barrier film is vertically interposed between the emitter terminal and the base of the bipolar transistor.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge devices and methods of manufacture. The structure includes: a semiconductor material comprising an emitter region, a base region, and a collector region; a thermally grown insulator region on the semiconductor material which extends over a junction of the base region and the collector region; a first field plate on the thermally grown insulator region, the first field plate being electrically connected to the emitter region; and a second field plate on the thermally grown insulator region, the second field plate being electrically connected to the collector region.
The present disclosure relates to semiconductor structures and, more particularly, to a device with improved latch-up immunity and methods of manufacture. The structure includes: a semiconductor substrate including a layer of a first conductivity type; a first semiconductor material over the layer of the first conductivity type, the first semiconductor layer including the first conductivity type and a layer of a second conductivity type; a second semiconductor material of the second conductivity type over the layer of the second conductivity type; and a deep trench isolation structure electrically connecting to the layer of the first conductivity type, the deep trench isolation layer extending through the first semiconductor material and the second semiconductor material.
The disclosed subject matter relates generally to an inductor structure integrated in a semiconductor device formed from bonded wafers, in which the semiconductor device has a three-dimensional inductor structure aligned vertically between two integrated circuit (IC) components. The inductor structure has a first metal level and a second metal level, the first metal level being in a different wafer from the second metal level.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A structure includes a first chip having a first surface and a second chip having a second surface adjacent to the first surface of the first chip. The first chip includes a first optical component and an optical waveguide protrusion adjacent to the first optical component. The optical waveguide protrusion extends above the first surface of the first chip. The second chip includes a second optical component and a groove adjacent to the second optical component. The groove extends from the second surface of the second chip and into a portion of the second chip. The optical waveguide protrusion is positioned in the groove in the second chip.
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
30.
STRUCTURES INCLUDING A PHOTODETECTOR AND MULTIPLE DEEP TRENCHES
Structures including a photodetector, such as a single-photon avalanche diode, and related methods. The structure comprises a semiconductor layer, a photodetector including a well in the semiconductor layer, and a deep trench isolation region including a first conductor layer extending through the semiconductor layer. The deep trench isolation region surrounds the photodetector. The structure further comprises a bond pad, and an electrical connection including a second conductor layer extending from the bond pad through the semiconductor layer.
The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.
H10D 84/60 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of BJTs
A structure including a first fin-type field effect transistor (finFET) in a first semiconductor fin. The first finFET includes a channel region between a first source/drain (S/D) region and a second S/D region; and a gate all around (GAA) structure. The GAA structure includes an outer gate region over the channel region and a buried gate region under of the channel region and extending between the first S/D region and the second S/D region. The outer gate region and the buried gate region each include a gate metal layer and a gate dielectric layer. The gate dielectric layer is thicker in the buried gate region than in the outer gate region.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Embodiments of the disclosure provide a structure and related method for a capacitive junction between a silicide layer and an electrode. A structure of the disclosure includes a silicide layer on a substrate. A dielectric layer is over the substrate and the silicide layer. An electrode is within a wiring layer on the dielectric layer. The dielectric layer defines a capacitive junction between the silicide layer and the electrode.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
34.
METHOD AND SYSTEM EMPLOYING LINEAR DISTANCE MARKER-BASED DESIGN LAYOUT ANALYSIS
Disclosed design methods and systems employ linear distance marker(s) (LDM(s)) placed over a layout (e.g., of a device or cell) to be analyzed. Nodes are inserted into LDM(s) at intersections with edges of layout shapes. Node-to-node distances (d) for node-to-node segments on LDM(s) are calculated. Design rules with distance specifications (D) are identified and assigned to the segments. A first table is generated and includes, for each segment, the design rule, d, and D. A second table is generated and includes, for each segment in a user-specified subset of segments, the design rule and either D or a user-specified compacted distance specification (C). An output table is generated and includes, for each segment in the subset, the design rule, d, and either D or C. The output table can be analyzed manually and/or automatically to determine if compaction is feasible. Additional embodiments use LDMs to profile devices within a layout.
The present disclosure relates to semiconductor structures and, more particularly, to a device with a self-aligned inner spacer sidewall structures. The structure includes: a gate structure on a semiconductor substrate; a gate metal connecting to the gate structure and offset from edges of the gate structure; and inner sidewall spacers on an upper surface of the gate structure and surrounding the gate metal.
The present disclosure relates to semiconductor structures and, more particularly, to a device with inner and outer spacer structures and methods of manufacture. The structure includes: a gate structure on a semiconductor substrate; a gate metal connecting to the gate structure; inner sidewall spacers contacting and surrounding the gate metal; a passivation layer on the inner sidewall spacers; and outer sidewall spacers on the passivation layer and adjacent to sides of the gate structure.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A transceiver front-end (FE) includes a receiver from an I/O pad to an amplifier (e.g., a low noise amplifier (LNA)) and a transmitter from the I/O pad to another amplifier (e.g., a power amplifier (PA)). The receiver further includes a variable inductor connected at one end to the I/O pad and connectable at the opposite end to ground by a switch. The LNA is connected to a node between portions of the inductor. When receiving, the switch is opened so the inductor exhibits low inductance for LNA impedance matching. When transmitting, the switch is closed so the inductor exhibits high inductance for blocking leakage to the LNA. Additionally, or alternatively, the transmitter includes a variable capacitor connected to the I/O pad. When receiving, the capacitor is programmed to exhibit low capacitance for optimal LNA performance. When transmitting, the capacitor is programmed to exhibit high capacitance for optimal PA performance.
H04B 1/525 - Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
A multiplexing circuit for a memory, including: a first parallel branch for coupling a program voltage to a first bitline corresponding to a first bit cell of the memory during a program mode of the memory; and a second parallel branch for coupling a program inhibit voltage to a plurality of additional bitlines corresponding to a plurality of additional bit cells of the memory during a program inhibit mode of the memory, wherein the first parallel branch couples an erase inhibit voltage to the plurality of additional bitlines during an erase inhibit mode of the memory, and wherein the second parallel branch couples an erase voltage to the first bitline during an erase mode of the memory.
A structure including a first emitter-collector (E/C) layer over a substrate. The structure further includes an intrinsic base layer over the first E/C layer and a second E/C layer over the intrinsic base layer. The structure includes an extrinsic base layer on the intrinsic base layer and adjacent the second E/C layer. The structure includes a gate structure on the intrinsic base layer and overhanging a lateral sidewall of the intrinsic base.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
The present disclosure relates to semiconductor structures and, more particularly, to devices with an outer conductive spacer and methods of manufacture. The structure includes: a gate structure; a gate metal connecting to the gate structure; inner spacers contacting and surrounding the gate metal; a passivation layer on the inner spacers; and outer conductive spacers on the passivation layer and adjacent to sides of the gate structure.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
The disclosure provides a structure and method for an inductor having a winding with a first segment connected to two second segments. An inductor according to the disclosure includes a plurality of windings coupled together in series about a magnetic core. At least one of the plurality of windings includes a first segment in a first wiring layer and extending over a width of the magnetic core. A second segment is within a second wiring layer and coupled to the first segment through a vertical interconnect. The second segment includes two sub-segments separated by a gap along a length of the magnetic core.
A radio frequency (RF) switch includes a transistor stack with different sections having different configurations for achieving different parasitic capacitances. Specifically, a first section is connected to an input terminal and a second section is connected between the first section and an output terminal. The second section has over-gate gaps for reduced source-to-drain capacitance, whereas the first section does not. Additionally, gate-to-source/drain contact spacing can be larger in the second section than in the first section, transistor layout length can be longer in the second section than in the first section and/or source and drain interconnect interdigitation can be less in the second section than in the first section. Optionally, sub-sections of the series-connected transistors within the first and/or second sections also have different configurations. Thus, numbers and sizes of compensation capacitors within the switch and overall chip area consumed by the switch are reduced while maintaining a high Pmax.
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
H03K 17/041 - Modifications for accelerating switching without feedback from the output circuit to the control circuit
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
In a disclosed Schmitt trigger, an input stage includes a first p-channel field effect transistor (PFET) and a second PFET, which are connected in series to a VDD rail, and a first n-channel field effect transistor (NFET) and a second NFET, which are connected in series between ground and the second PFET. An output stage includes additional FETs for hysteresis. The first PFET and first NFET are different from the other FETs and have a higher voltage rating. For example, the first PFET and first NFET can be buried oxide field effect transistors (BOXFETs) and the other FETs can be laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs)). Gates of the first PFET and first NFET are connected to an input node. Gates of the second PFET and NFET are connected to receive reference voltages to prevent safe operating area (SOA) violations and control trigger voltage levels.
H03K 3/3565 - Bistables with hysteresis, e.g. Schmitt trigger
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A structure, including an insulator within a substrate. The substrate includes a first active region adjacent a first sidewall of the insulator and a second active region adjacent a second sidewall of the insulator opposite the first sidewall. The structure further includes a conductive bridge over the insulator and coupling the first active region of the substrate to the second active region of the substrate. The structure includes a gate dielectric layer over the conductive bridge, a first work function metal over the first active region, and a second work function metal over the second active region.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 27/085 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
45.
BUFFERED THIN FILM RESISTOR WITH METAL-INSULATOR-METAL (MIM) INTEGRATION
The present disclosure relates to semiconductor structures and, more particularly, to a buffered thin film resistor (TFR) with metal-insulator-metal (MIM) capacitor integration and methods of manufacture. The structure includes: a first buffer contact on a substrate; a second buffer contact on the substrate, the second buffer contact being on a same wiring level as the first buffer contact; a stack of resistive thin films contacting the first buffer contact and the second buffer contact, the stack of resistive thin films extending on the substrate between the first buffer contact and the second buffer contact; and electrical contacts that are in physical contact to a top plate of the stack of resistive thin films.
H01L 27/01 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
46.
INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM EMPLOYING PARASITIC DIODE ANALYSIS
Disclosed are embodiments of computer-aided design (CAD) methods and systems that employ one or more electronic design automation (EDA) tools to flag parasitic diodes within a layout or netlist (depending upon the embodiments). In one embodiment, information contained in process design kit (PDK) tables (e.g., a first table with layer-specific design rules for devices in a processing technology and a second table with descriptions of parasitic diodes in the processing technology) can be used to identify any parasitic diodes within a displayed portion of an IC design layout. Once identified, parasitic diodes can be flagged within the displayed portion of the layout to provide visual cues intended to draw a user's attention to the parasitic diodes during the design process to ensure that any unintended or unwanted parasitic diodes are either accounted for when predicting IC performance or removed from the design to avoid a negative impact on performance.
Structures that include a semiconductor layer formed by lateral epitaxial growth and methods of forming such structures. The structure comprises a first semiconductor layer that includes first and second sections, and that comprises a first single-crystal semiconductor material. The structure further comprises a second semiconductor layer that includes a section and a semiconductor region, and that comprises one or more second single-crystal semiconductor materials. The semiconductor region extends between the second section of the first semiconductor layer and the section of the second semiconductor layer. An opening penetrates at least partially through the first semiconductor layer and through the second semiconductor layer. The opening is oriented along a (100) crystal plane of the first single-crystal semiconductor material, and the semiconductor region borders the opening. A dielectric layer is positioned between the first section of the first semiconductor layer and the section of the second semiconductor layer.
G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
48.
STRUCTURES INCLUDING A SEMICONDUCTOR LAYER FORMED BY LATERAL EPITAXIAL GROWTH
Structures that include a semiconductor layer formed by lateral epitaxial growth and methods of forming such structures. The structure comprises a first semiconductor layer including a first section and a second section adjacent to the first section, a second semiconductor layer including a section and a semiconductor region that projects from the second section of the first semiconductor layer to the section of the second semiconductor layer, and a dielectric layer disposed between the first section of the first semiconductor layer and the section of the second semiconductor layer. The section and the semiconductor region of the second semiconductor layer comprise one or more single-crystal semiconductor materials.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
C30B 1/02 - Single-crystal growth directly from the solid state by thermal treatment, e.g. strain annealing
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
The present disclosure relates to semiconductor structures and, more particularly, to a device triggered silicon control rectifiers (SCR) and methods of manufacture. The structure includes: a first device comprising a first shallow diffusion region of a first conductivity type within a first well of a second conductivity type and a second shallow diffusion region of the first conductivity type within the first well of the second conductivity type.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
50.
EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR (EDMOS) FIELD EFFECT TRANSISTOR (FET) WITH DUAL THICKNESS SEMICONDUCTOR MATERIAL
The present disclosure relates to semiconductor structures and, more particularly, to an extended drain metal oxide semiconductor (EDMOS) field effect transistor (FET) with a fully depleted region comprising a dual thicknesses semiconductor material and methods of manufacture. The structure includes: a semiconductor on insulator (SOI) material including a first portion with a first thickness and a second portion with a second thickness; a gate structure on the SOI material over the first portion with the first thickness; and sidewall spacers adjacent to the gate structure, with at least one sidewall spacer extending over both the first portion with the first thickness and the second portion with the second thickness.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a layer stack including a first dielectric layer and a second dielectric layer. The first dielectric layer includes a portion between the second dielectric layer and a semiconductor substrate. The structure further comprises a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, and a gate electrode on the layer stack. The gate electrode is laterally between the first and second source/drain regions, and the gate electrode overlaps with the portion of the first dielectric layer and the second dielectric layer. The structure further comprises a spacer laterally between the first source/drain region and the second dielectric layer.
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
Structures for a photonics chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector including a pad and a semiconductor layer on the pad. The pad includes a side edge and a first waveguide core that extends from the side edge adjacent to the semiconductor layer. The structure further comprises a second waveguide core including a section adjoined to the side edge of the pad adjacent to the first waveguide core.
Embodiments of the disclosure provide a crystalline semiconductor layer between a bipolar transistor structure and a field effect transistor (FET) structure. The structure includes a dielectric layer on a back-gate semiconductor layer, a bipolar transistor structure on the dielectric layer, FET structure on the dielectric layer, and a crystalline semiconductor layer on the dielectric layer between the bipolar transistor structure and the FET structure. The crystalline semiconductor layer includes a terminal of the bipolar transistor structure and a terminal of the FET structure.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises a first semiconductor layer including a first portion, a second portion, and a third portion between the first portion and the second portion, a first terminal including a first semiconductor region on the first portion of the first semiconductor layer, a second terminal including a second semiconductor region on the second portion of the first semiconductor layer, an intrinsic base laterally disposed between the first terminal and the second terminal, and an extrinsic base on the intrinsic base. The intrinsic base includes a doped region in the third portion of the first semiconductor layer, and the doped region has a dopant depth profile with a dopant concentration that is asymmetrical relative to the first terminal and the second terminal.
Embodiments of the disclosure provide a structure including a first back-gate well adjacent a second back-gate well. A bipolar transistor (BT) is over the first back-gate well and includes a base structure laterally between a set of emitter/collector (E/C) terminals and extending longitudinally away from the set of E/C terminals. A field effect transistor (FET) is over the second back-gate well and includes a gate structure laterally between a set of source/drain (S/D) terminals and extending longitudinally away from the set of S/D terminals toward the BT. The gate structure is coupled to the base structure.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
56.
PHOTODETECTORS WITH AN ADJOINED SLOTTED WAVEGUIDING STRUCTURE
Structures for a photonics chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector including a pad and a semiconductor layer on the pad. The structure further comprises a waveguiding structure including a first waveguide core, a second waveguide core, a slot between the first waveguide core and the second waveguide core, and a plurality of waveguide core segments. The waveguiding structure is adjoined to a side edge of the pad adjacent to the semiconductor layer. Each of the plurality of waveguide core segments includes a portion that is disposed in the slot.
The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
The present disclosure relates to semiconductor structures and, more particularly, to electrostatic devices and methods of manufacture. The structure includes: a device having a collector region, an emitter region, and a base region; an oxidation structure within the base region; and an isolation structure abutting the oxidation structure and extending between the base region and the emitter region.
A serpentine resistor within a back end of line (BEOL) level of a substrate includes a plurality of first sections oriented in a first horizontal direction, at least one second section oriented in a second horizontal direction, a plurality of vertical sections, and at least one lateral turn between the first horizontal direction and the second horizontal direction. The serpentine resistor may have a serpentine shape in the vertical plane and the horizontal plane, and may extend between two bonded substrates, providing higher resistance values compared to conventional BEOL resistors.
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
The present disclosure relates to semiconductor structures and, more particularly, to a transistor triggered silicon control rectifier (SCR) and methods of manufacture. The structure includes: a vertical silicon controlled rectifier; and a triggering device adjacent to the vertical silicon controlled rectifier, the triggering device and the vertical silicon controlled rectifier sharing a diffusion region within a semiconductor substrate.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
The present disclosure relates to semiconductor structures and, more particularly, to a device triggered silicon control rectifier (SCR) and methods of manufacture. The structure includes: a vertical silicon controlled rectifier; a lateral triggering device including a first diffusion region, a second diffusion region and a third diffusion region, the third diffusion region being shared with the vertical silicon controlled rectifier; and a body contact over the first diffusion region.
H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
The present disclosure relates to semiconductor structures and, more particularly, to a differential circuit with automatic parasitic neutralization and gain boost and methods of manufacture. The structure includes a plurality of auxiliary circuit devices with back-gate controls to perform a boost gain, and a differential pair of circuit devices which are connected to the auxiliary circuit devices.
The present disclosure relates to semiconductor structures and, more particularly, to under-body source contact structures and methods of manufacture. The structure includes: a gate structure on a semiconductor layer; a drift region within the semiconductor layer, below the gate structure; a body region within the semiconductor layer, below the gate structure; a contact region within the body region, the contact region being devoid of a silicide contact; and a silicide contact remote from the contact region within the semiconductor layer.
A structure including a semiconductor layer having a body region of a first conductivity type and a first electrode including a doped region of a second conductivity type in the semiconductor layer is provided. The doped region is adjacent to the body region. The doped region includes a first portion and a second portion extending laterally from the first portion. The first portion has a first width and the second portion has a second width. The first width is greater than the second width. A ferroelectric layer is arranged on the semiconductor layer over the body region. A second electrode is arranged on the ferroelectric layer. The first portion and the second portion of the doped region partially underlap the second electrode.
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
G11C 11/14 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using thin-film elements
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a semiconductor substrate including a trench, and a field-effect transistor including a first and second source/drain regions in the semiconductor substrate, a gate dielectric inside the trench, and a gate on the gate dielectric. The gate and the gate dielectric are disposed laterally between the first and second source/drain regions.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
66.
STACKED TRENCH CAPACITORS AND METHODS OF MAKING THEREOF
Stacked trench capacitors and methods of making the same are provided. Stacked trench capacitor comprises a first conductive layer and a second conductive layer in a first dielectric layer over a first semiconductor substrate, and a third conductive layer and a fourth conductive layer in a second dielectric layer. The first and second conductive layers are spaced by a first insulator layer, and the third and fourth conductive layers are spaced by a second insulator layer, and the second conductive layer is directly contacting the third conductive layer. A second semiconductor substrate is over the fourth conductive layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01G 4/012 - Form of non-self-supporting electrodes
Structures for an optical component, such as an optical reflector or an Echelle grating, and methods of forming such structures. The structure comprises a first waveguide core positioned in a vertical direction over a semiconductor substrate. The first waveguide core includes a tapered section and a plurality of segments separated by a plurality of gaps. A second waveguide core, which is positioned in the vertical direction relative to the first waveguide core, includes a portion positioned adjacent to the first waveguide core.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/124 - Geodesic lenses or integrated gratings
G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
Structures for a waveguide escalator, as well as methods of forming such structures. The structure comprises a first waveguide core on a substrate, a second waveguide core, and a back-end-of-line stack including a third waveguide core disposed between the first waveguide core and the second waveguide core. The third waveguide core comprises a layer stack that includes a first layer, a second layer, and a third layer between the first layer and the second layer. The first layer and the second layer comprise a first dielectric material with a first refractive index, and the third layer comprises a second dielectric material with a second refractive index that is less than the first refractive index.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
69.
HETEROJUNCTION BIPOLAR TRANSISTOR WAFERS WITH BACKSIDE SUB-COLLECTOR CONTACT
The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor wafers with backside sub-collector contact and methods of manufacture. The structure includes: a first chiplet comprising a first device with a backside contact; and a second chiplet connected to the first chiplet, the second chiplet comprising a second device with a frontside contact.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor and methods of manufacture. The structure includes: a collector region; an extrinsic base comprising an emitter opening with an angled sidewall; an emitter within the emitter opening; and an intrinsic base between the emitter and the collector.
A system for phase imbalance calibration, including: an in-phase (I) signal channel including an analog-to-digital converter (ADC) for sampling an I signal to provide a sampled I signal; a quadrature (Q) signal channel including an ADC for sampling a Q signal to provide a sampled Q signal; a sampling clock for controlling the sampling of the ADC on the I signal channel and the sampling of the ADC on the Q signal channel; and sampling clock delay circuitry for adjusting one of a sampling start time of the ADC on the I channel and a sampling start time of the ADC on the Q channel relative to one another such that the sampled I signal and the sampled Q signal are in phase.
A structure and method include a transistor with semiconductor nanosheets, which extend between source/drain regions and which include at least a lowermost semiconductor nanosheet and an uppermost semiconductor nanosheet above the lowermost semiconductor nanosheet. The transistor includes inner gate sections below the center portions of each semiconductor nanosheet and an outer gate section with a horizontal portion above the center portion of the uppermost semiconductor nanosheet and with vertical portions on opposing sides of the semiconductor nanosheets and inner gate sections. Inner spacers are below the end portions of each semiconductor nanosheet. Outer spacers are adjacent the sidewalls of the outer gate section (including above end portions of the uppermost semiconductor nanosheet), are wider than the inner spacers, and extend onto proximal portions of the source/drain regions. Additional outer spacers are adjacent to the outer spacers (e.g., on the proximal portions or on taller and wider distal portions).
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
A power switch, including: a PFET including a gate, a source coupled to a source voltage, and a drain for outputting a supply voltage; and a level shifter, wherein the level shifter includes: an input node for receiving an input voltage, wherein the input voltage includes first and second voltage levels; a supply node for receiving the supply voltage, wherein the supply voltage includes third and fourth voltage levels; and an output node for outputting an output voltage, wherein the output node is coupled to the gate of the PFET; wherein, when the input voltage is at the first voltage level, the output voltage is at the first voltage level and the PFET is in a conducting state; and wherein a voltage between the gate and drain of the PFET and a voltage between the gate and source of the FET do not exceed a maximum voltage of the PFET.
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
74.
Shielded inductor structures and methods of forming the same
A structure including a first chip and a second chip stacked over the first chip is provided. The first chip includes a first dielectric over a substrate. The second chip includes a second dielectric over the first dielectric. An inductor is arranged at least in part in the first dielectric of the first chip. An electromagnetic shield structure is arranged around the inductor. The electromagnetic shield structure includes a lower shield portion extending at least partially through the first dielectric of the first chip and an upper shield portion extending at least partially through the second dielectric of the second chip. The electromagnetic shield structure is formed in part in the BEOL metallization structure in each of the first chip and the second chip in a heterogenous integration process.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
75.
IC structure with MFMIS memory cell and CMOS transistor
An IC structure includes an MFMIS memory cell on a semiconductor substrate, and a CMOS transistor adjacent the MFMIS memory cell on the same semiconductor substrate. A method provides co-integration of the MFMIS memory cell with the CMOS transistor. The method may optionally co-integrate an MFIS memory cell. The IC structure and method provide a lower cost approach to forming MFMIS memory cells, which provide a number of advantages over MFIS memory cells.
The present disclosure relates to semiconductor structures and, more particularly, to a device triggered silicon control rectifier (SCR) and methods of manufacture. the structure includes: a vertical silicon controlled rectifier having a diffusion region in a well of a semiconductor substrate; a vertical triggering device sharing the diffusion region with the vertical silicon controlled rectifier; and a body contact adjacent to the vertical triggering device and electrically connecting to the well.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
77.
STRUCTURE WITH BARRIER-FREE METAL VIA AND METAL WIRE INCLUDING NON-COPPER CONDUCTOR, AND METHOD TO FORM SAME
A structure including a barrier-free metal via over a substrate and in a dielectric layer. The structure further includes a barrier-free metal wire in the dielectric layer and over the barrier-free metal via and coupled to at least an exposed portion of the barrier-free metal via. The barrier-free metal via and the barrier-free metal wire each include a non-copper conductor. By using non-copper conductors in the structure, the structure is substantially without liners and has improved performance without creating or increasing parasitic capacitance.
H01B 1/02 - Conductors or conductive bodies characterised by the conductive materialsSelection of materials as conductors mainly consisting of metals or alloys
H01B 1/04 - Conductors or conductive bodies characterised by the conductive materialsSelection of materials as conductors mainly consisting of carbon-silicon compounds, carbon, or silicon
78.
STRUCTURE WITH FERROELECTRIC MEMORY STACKS HAVING DIFFERENT SWITCHING VOLTAGES AND RELATED METHODS
GlobalFoundries Dresden Module One Limited Liability Company & Co. KG (Germany)
Inventor
Dünkel, Stefan
Kleimaier, Dominik Martin
Mulaosmanovic, Halid
Müller, Johannes
Abstract
The disclosure provides a structure with ferroelectric memory stacks having different switching voltages, and methods to provide the same. A structure of the disclosure includes a first ferroelectric memory stack over a substrate. The first ferroelectric memory stack has a first switching voltage. A second ferroelectric memory stack is serially coupled to the first ferroelectric memory stack over the substrate. The second ferroelectric memory stack has a second switching voltage, different from the first switching voltage.
Structures for a photonics chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector, a first waveguide core coupled to the photodetector, and a second waveguide core coupled to the photodetector. The structure further comprises a third waveguide core including a section disposed laterally between a section of the first waveguide core and a section of the second waveguide core.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
A semiconductor device includes a first substrate, a second substrate bonded to the first substrate, and at least one thermally conductive structure that extends through a portion of the first substrate and a portion of the second substrate and is vertically aligned with an active region of the first substrate. The at least one thermally conductive structure is electrically insulated from electrically active structures in the semiconductor device. The thermally conductive structure acts as a heat sink to transfer heat from the active region.
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
81.
Structures for a field-effect transistor that include a spacer structure
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a silicon-on-insulator substrate including a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a semiconductor layer on the dielectric layer. The structure further comprises a gate electrode on the semiconductor layer. The gate electrode comprises a single-crystal semiconductor material. The structure further comprises a spacer structure including a first portion that overlaps with a side surface of the dielectric layer and a second portion that overlaps with a portion of the semiconductor substrate adjacent to the side surface of the dielectric layer.
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
82.
FULLY DEPLETED SEMICONDUCTOR-ON-INSULATOR SWITCH WITH BUILT-IN ELECTROSTATIC DISCHARGE PROTECTION
A disclosed semiconductor structure includes a semiconductor layer including a switch area with side-by-side first and second portions and an RF switch with built-in ESD/power surge protection. The RF switch includes series-connected transistors, which include, within the first portion of the switch area, source/drain regions and channel regions positioned laterally between the source/drain regions; and parallel gates adjacent to the channel regions, respectively, and traversing the first portion of the switch area without extending further onto the second portion. Outer source/drain regions are silicided and contacted, whereas inner source/drain regions are unsilicided and uncontacted. The second portion of the switch area is in contact with the source/drain regions in the first area, is unsilicided, and is either undoped or low doped. Thus, the second portion makes up resistive elements connected in parallel to the series-connected transistors.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor integrated silicon controlled rectifier and methods of manufacture. The structure includes: a first region having a first dopant type provided in a semiconductor substrate; a second region having a second dopant type provided in the semiconductor substrate; an isolation region between the first region and the second region; a first semiconductor layer vertically contacting the first region, the first semiconductor layer having a dopant type opposite from the first dopant type; a second semiconductor layer vertically contacting the second region, the second semiconductor layer having a dopant type opposite from the second dopant type; a polysilicon material vertically contacting the first semiconductor layer; and a single crystalline semiconductor material vertically contacting the first semiconductor layer and the second semiconductor layer.
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Structures for a photonic chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector including a pad, a first semiconductor layer on the pad, and a second semiconductor layer on the pad. The second semiconductor layer is laterally spaced from the first semiconductor layer. The structure further comprises a first waveguide core connected to the pad adjacent to the first semiconductor layer, and a second waveguide core connected to the pad adjacent to the second semiconductor layer.
H10F 30/223 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PIN barrier
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
H10F 71/00 - Manufacture or treatment of devices covered by this subclass
H10F 77/122 - Active materials comprising only Group IV materials
Structures including a photodetector, such as a single-photon avalanche diode, and related methods. The structure comprises a semiconductor layer having a device region and a top surface, and a photodetector including a first well in the device region and a second well. The first well is disposed between the second well and the top surface. The structure further comprises a deep trench isolation region that extends from the top surface into the semiconductor layer. The deep trench isolation region surrounds a perimeter of the device region, and the deep trench isolation region comprises a dielectric material. The structure further comprises a contact including a conductor layer that extends from the top surface of the semiconductor layer to the second well. The contact has a first discrete position about the perimeter of the device region.
H10F 30/225 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10F 71/00 - Manufacture or treatment of devices covered by this subclass
A contactless current sensing circuit for sensing current in a conductive wire on a dielectric substrate of a printed circuit board (PCB) includes a plurality of magnetic tunneling junction (MTJ) structures including first and second MTJ structures on a first side of the conductive wire, and third and fourth MTJ structures on a second side of the conductive wire opposite to the first side. The MTJ structures are located within the H-field induced by a current flowing through the conductive wire.
Layout design for an electronic device may be performed by providing a representation of a first layout to a client and providing, in response to an input from the client, a collection of design information calculated according to the first layout to the client. The collection of design information may include a dimension extracted from the first layout, and may further include parasitics information related to the dimension, margin information related to a ground rule applicable to the dimension, or both. The collection of design information may be provided to the client as a real-time response to inputs received from the client. By providing the parasitics information, the margin information, or both to the client, the design of sub-ground-rule layouts may be performed in less time and using fewer resources than would otherwise be the case.
Structures for a high-voltage field-effect transistor that include a deep trench isolation region and methods of forming such structures. The structure comprises a semiconductor substrate, a semiconductor layer on the semiconductor substrate, and a doped layer between the semiconductor layer and the semiconductor substrate. The structure further comprises a trench isolation region including a metal layer that extends through the semiconductor layer and the doped layer into the semiconductor substrate.
Structures for a photonics chip that enable external communication and methods of forming such structures. The structure comprises a spot-size converter, a body on a semiconductor substrate, and a dielectric layer on the semiconductor substrate. The body includes a surface adjacent to the spot-size converter and a reflector on the surface. The dielectric layer includes a recess disposed above the spot-size converter and the reflector.
The embodiments herein relate to stacked semiconductor structures including a passive device and methods of forming the same. A semiconductor structure is provided. The semiconductor structure includes a substrate, a first active layer, a second active layer, a first interconnection structure, a second interconnection structure, a first interlayer dielectric stack, and a passive device. The first active layer is in the substrate and the second active layer is vertically over the first active layer. The first interconnection structure is between the first active layer and the second active layer. The second interconnection structure is between the first interconnection structure and the second active layer. The first interlayer dielectric stack is between the first interconnection structure and the second interconnection structure. The passive device is in the first interlayer dielectric stack.
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
The present disclosure relates to semiconductor structures and, more particularly, to vertical heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base above the collector region; an emitter above the intrinsic base region; and an extrinsic base on the intrinsic base and adjacent to the emitter, wherein the collector region includes an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region and the base region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
The disclosure provides a structure and method for an inductor with windings having different widths. A structure may include an inductor including a plurality of windings about a magnetic core. Each winding has a first segment within a first wiring layer coupled to a second segment within a second wiring layer. The plurality of windings includes a first winding having a first width along a same direction as a length of the magnetic core and a second winding having a second width along the same direction as the length of the magnetic core. The second width is larger than the first width.
H01F 1/14 - Magnets or magnetic bodies characterised by the magnetic materials thereforSelection of materials for their magnetic properties of inorganic materials characterised by their coercivity of soft-magnetic materials metals or alloys
93.
SINGLE ENDED SENSE AMPLIFIER WITH CURRENT PULSE CIRCUIT
Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
94.
Laterally-diffused metal-oxide-semiconductor devices with a field plate
Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming same. The structure comprises a semiconductor substrate including a trench, a source and a drain in the semiconductor substrate, a gate laterally positioned between the trench and the source, and a field plate inside the trench. The field plate is laterally positioned between the gate and the drain. The structure further comprises a gate dielectric between the gate and the semiconductor substrate. The gate dielectric includes a first section adjacent to the field plate and a second section adjacent to the source. The first section is thicker than the second section.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Embodiments of the disclosure provide a structure including a first emitter/collector (E/C) layer over a substrate. A base structure is over the substrate and adjacent a first horizontal end of the first E/C layer. A bounding structure is over the substrate and adjacent a second horizontal end of the first E/C layer. The bounding structure, in some implementations, may include a gate conductor or a base material. A spacer is between the first E/C layer and the bounding structure.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A disclosed memory structure includes memory cells connected to first and second cell supply voltage lines. A programming circuit enables programming of a low cell supply voltage (Vcsl) on the first cell supply voltage line and includes transistors with different threshold voltages connected to ground and further connectable, via switches, to the first cell supply voltage line. The programming circuit can further include an additional switch connected between ground and the first cell supply voltage line. In an operational mode, the first cell supply voltage line is discharged to ground via the additional switch. In the retention mode, one of the transistors of the programming circuit is connected by a corresponding switch to the first cell supply voltage line for programming of Vcsl. Optionally, the memory structure can be implemented in FDSOI and the transistors of the programming circuit can also be back biased for fine tuning of Vcsl.
The present disclosure relates to semiconductor structures and, more particularly, to a silicon control rectifier (SCR) and methods of manufacture. The structure includes: a doped region in a semiconductor substrate; at least two regions of semiconductor material comprising opposite doping types over the doped region; and polysilicon regions over respective ones of the least two regions of semiconductor material.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
98.
SWITCHING MEMORY ELEMENTS ACCESSED BY HETEROJUNCTION BIPOLAR TRANSISTORS
Structures that include a switching memory element and methods of forming a structure including a switching memory element. The structure comprises a switching memory element, and a two-terminal access device including a first terminal coupled to the switching memory element, a second terminal, and a semiconductor layer between the first terminal and the second terminal. The semiconductor layer is electrically floating in the structure.
A structure including a first chip and a second chip stacked over and bonded to the first chip at a bonding interface is provided. The first and second chips form a device stack. The first chip includes a first dielectric and first interconnects arranged in the first dielectric. The second chip includes a second dielectric over the first dielectric and second interconnects arranged in the second dielectric. A trench capacitor is arranged in the device stack. The trench capacitor extends through the second chip, the bonding interface and at least partially into the first chip.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Structures for an integrated circuit having a watermark and related methods. The structure comprises a first semiconductor structure including at least one feature with a variation relative to a second semiconductor structure including the at least one feature without the variation. The variation provides a watermark for identifying a Process Design Kit used to form the first semiconductor structure.
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
