Systems, methods, and computer program products provide for time critical packet transmission. An electronic device may include a transceiver and a processor that is configured to receive or transmit, via the transceiver, a plurality of packets having respective headers conforming to a layer below a network layer, and the first header of a first packet of the plurality of packets may include a source address and a hop limit field. The packet may be transmitted according to the layer below the network layer, thereby providing a smaller packet.
An example apparatus includes: first circuitry configured to verify a set of reference voltages is stable; and second circuitry including a first transistor, a second transistor, a first number of parallel transistors, and a second number of parallel transistors, the second circuitry configured to, in response to the verification: produce a trip voltage based on: a comparison of a threshold voltage of the first transistor and a threshold voltage of the second transistor; and a reference voltage selected from the set and provided to a control terminal of the first transistor; and adjust the value of the trip voltage based on a comparison between a first current mirror having a first number of parallel transistors and a second current mirror connected to a second number of parallel transistors.
An example radar system includes transmit, receive and processing circuitry. In operation, the radar system transmits first and second sets of chirp signals in which each chirp signal of the first set of chirp signals has an induced phase shift, receives reflected signals based on the transmitted first and second sets of chirp signals, and generates respective first and second sets of digital signals. Fourier Transform (FT) operations are performed on the first and second sets of digital signals to generate first and second arrays, respectively. The radar system identifies a first peak in the first array and a second peak in the second array representing an object in a field of view. The first and second peaks are at corresponding positions in the first and second arrays, respectively. The radar system then compares the phases of the first and second peaks to determine an actual phase shift for the induced phase shift.
Systems, methods, and computer program products provide for time critical packet transmission. An electronic device may include a transceiver and a processor that is configured to receive or transmit, via the transceiver, a plurality of packets having respective headers (610) conforming to a layer below a network layer, and the first header of a first packet of the plurality of packets may include a source address (625) and a hop limit field (623). The packet may be transmitted according to the layer below the network layer, thereby providing a smaller packet.
An integrated circuit includes a first transistor coupled between a power input and a power output, the first transistor being an N-type transistor and having a first transistor control input; a first amplifier stage having a reference input, a feedback input, and a first amplifier output, the feedback input coupled to the power output; a second amplifier stage having an amplifier input and a second amplifier output, the amplifier input coupled to the first amplifier output, and the second amplifier output coupled to the first transistor control input; and a first biasing circuit coupled to the first transistor control input, the first biasing circuit having an electrical control input coupled to the power output.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/563 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including two stages of regulation, at least one of which is output level responsive, e.g. coarse and fine regulation
G05F 1/595 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load semiconductor devices connected in series
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
6.
DIELECTRIC LAYERS IN MAGNETIC MOLD COMPOUND INDUCTOR PACKAGES
In examples, a semiconductor package comprises a semiconductor die, and an inductor coupled to the semiconductor die. The inductor comprises a first metal coil having a first end coupled to the semiconductor die and a second end; a second metal coil vertically spaced from the first metal coil and having a third end coupled to the second end and a fourth end coupled to the semiconductor die; a magnetic mold compound (MMC) between the first and second metal coils, the MMC including conductive ions; and an insulative layer between the first and metal coils.
H01F 27/32 - Insulating of coils, windings, or parts thereof
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
Diodes for ESD protection devices are described. The diodes have low capacitance. In an example, a semiconductor device includes a substrate, an n-type epitaxial layer on the n-type substrate in a first region of the n-type substrate, and a p-type epitaxial layer on the n-type epitaxial layer with an interface between the n-type and p-type epitaxial layers. The p-type epitaxial layer has a first concentration of p-type dopants throughout the p-type epitaxial layer. Also, the semiconductor device includes a p-type dopant distribution straddling across the interface, the p-type dopant distribution having a first peak concentration of p-type dopants greater than the first concentration, and an n-type dopant distribution straddling across the interface, the n-type dopant distribution having a second peak concentration of n-type dopants. The second peak concentration is substantially same as the first peak concentration.
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
An example cascode voltage regulator circuit includes a first transistor coupled to an input voltage terminal and configured as a source follower to provide an output voltage at a source terminal, a second transistor coupled in series between the source terminal of the first transistor and an output terminal, the second transistor configured as a current limiter, and a current mirror coupled between respective first and second control terminals of the first and second transistors, the current mirror configured to receive a first current indicative of a source follower current flowing through the first transistor and to turn off the second transistor by coupling the first and second control terminals together responsive to the source follower current exceeding a threshold. In an example, the first transistor is a drain-extended NMOS device and the second transistor is a drain-extended PMOS device.
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
G05F 1/573 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
Systems and methods determine whether to switch to a second communication protocol from a first communication protocol based on energy detection. The energy detection may be used to indicate use of a channel defined by the second communication protocol. Energy detection on that channel may be accompanied by energy detection on an adjacent or close-by channel. If energy is detected on the channel and on an adjacent or a close-by channel, then that may indicate interference by a third communication protocol rather than by use of the channel on the second communication protocol. However, if energy is detected on the channel and not on the adjacent or close-by channel, then that may be an indication of use of the channel rather than interference.
H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
Described embodiments include a charger circuit with a charge pump having a charge pump input and a charge pump output. The charge pump input is coupled to an input voltage terminal. A current sink is coupled between the charge pump output and a ground terminal, and has a current sink control terminal. A transistor is coupled between the input voltage terminal and an output voltage terminal, and has a control terminal. A driver circuit has a driver input, a driver output, a positive rail input, and a negative rail input. The driver output is coupled to the control terminal. The positive rail input is coupled to the charge pump output. The negative rail input is coupled to the output voltage terminal.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
11.
DISTRIBUTED MECHANISM FOR FINE-GRAINED TEST POWER CONTROL
An example circuit, e.g., an integrated circuit, comprises processor cores, each of which includes multiple memory blocks; power control circuits respectively coupled to the processor cores; isolation circuits respectively coupled to the processor cores; and controller circuitry coupled to each of the processor cores, to each of the power control circuits, and to each of the isolation circuits. The controller circuitry is configured to select a subset of processor cores of the processor cores and a subset of memory blocks of the subset of processor cores for testing; and cause non-selected memory blocks of the processor cores to be at least one of power gated, clock gated, and isolated from the selected subset of memory blocks.
In a described example, a semiconductor wafer can include a first monitor structure in a scribe line adjacent to a die, the first monitor structure including a first source region, a first drain region, and a first gate region. The first gate region can include a first elongated finger extending longitudinally between the first source region and the first drain region, as viewed from a top plan view. The semiconductor wafer can include a second monitor structure in the scribe line, the second monitor structure including one or more second source regions, one or more second drain regions, and a plurality of second gate regions. The second gate regions can include a second elongated finger extending longitudinally over a respective region of the die between the one or more second source regions and the one or more second drain regions, as viewed from the top plan view.
A circuit includes a first transistor and a second transistor. The circuit also includes a third transistor and a fourth transistor. Additionally, the circuit includes a switch network coupled to the first transistor, to the second transistor, to the third transistor, and to the fourth transistor. Also, the circuit includes a first buffer having an input and an output, where the output is coupled to the second transistor and a second buffer having an input and an output, where the output is coupled to the first transistor. Additionally, the circuit includes a third buffer having an input and an output, the input coupled to the input of the first buffer and the output coupled to the third transistor; and a fourth buffer having an input and an output, where the input is coupled to the input of the second buffer and the output is coupled to the fourth transistor.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/44 - Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
In some examples, a device comprises: a substrate having a cavity, the cavity having a bottom surface; a die pad in the cavity; and a semiconductor die in the cavity and having a first segment coupled to the die pad and a second segment suspended over and facing the bottom surface.
Systems and methods may perform sequential automatic test pattern generation (on parallel memory units. In one example, an array of logic gates (330-335) may output enable signals to cause multiple memory units (360, 361) to be enabled in parallel. Test pattern generation and test control logic (210) may perform forward path testing, backward path testing, and any other appropriate testing on the enabled memory units (360, 361). The systems and methods may then move on to another group of memory units, which are enabled in parallel and tested in parallel.
One example includes a bulk bin system. The system includes a bin receptable comprising a first poka-yoke mating feature and a bulk bin configured to accommodate storage of bulk components. The bulk bin can be configured to rest on the bin receptacle and includes a second poka-yoke mating feature extending from an inner surface of the bulk bin. The second poka-yoke mating feature can be configured to engage with the first poka-yoke mating feature when the bulk bin is provided in the bin receptacle. The system further comprises a cover plate that is secured to the bulk bin via a securing feature. The cover plate includes a cover portion that extends along and is approximately aligned with the inner surface of the bulk bin to cover the second poka-yoke mating feature.
An example multiphase power converter circuit includes a first power stage is configured to provide a first phase output signal at a first switching output based on a first control signal. The first power stage includes first open fault detection circuitry configured to disable detecting and/or reporting of an open fault condition responsive to the first control signal. A second power stage is configured to provide a second phase output signal at a second switching output based on a second control signal. The second power stage includes second open fault detection circuitry configured to enable detecting and/or reporting of the open fault condition responsive to the second control signal having a value to turn off the second power stage. The second open fault detection circuitry is further configured to detect the open fault condition based on a voltage at the second switching output.
H02H 7/12 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for convertersEmergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for rectifiers for static converters or rectifiers
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
The present disclosure generally relates to a semiconductor device having a slanted field plate. In an example, a semiconductor device includes a semiconductor substrate, a gate, a drain contact, a source contact, and a field plate. The gate is on a surface of the semiconductor substrate. The drain contact and a source contact are on the semiconductor substrate. The field plate is over the surface of the semiconductor substrate and extends from one side of the gate towards the drain contact. The field plate includes multiple field plate portions. Each of the multiple field plate portions has a uniform respective slope with respect to the surface, and the multiple field plate portions have different slopes.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
An example device comprising: first clock divider circuitry to be coupled to a first clock; first counter circuitry configured to be coupled to the first clock divider circuitry, the first counter circuitry configured to increment based on the first clock and a second clock; second clock divider circuitry to be coupled to a third clock; second counter circuitry configured to be coupled to the second clock divider circuitry, the second counter circuitry configured to increment based on the third clock and the second clock; and comparison circuitry coupled to the first and second counter circuitry.
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/12 - Synchronisation of different clock signals
G06F 11/16 - Error detection or correction of the data by redundancy in hardware
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H03K 5/26 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
A circuit includes a microcontroller having a clock output and a data output. The microcontroller includes a serial-peripheral interface (SPI) circuit, a pulse-width modulation (PWM) generator, and a central processing unit (CPU). The SPI circuit is configured to provide an SPI clock signal and an SPI data signal to the data output. The PWM generator is configured to provide a continuous PWM signal to the clock output. The CPU is coupled to the SPI circuit and the PWM generator, and the CPU has executable instructions configured to synchronize the PWM signal to the SPI clock signal.
A method comprises: forming a die including a cavity; coupling an anchor to the die; coupling a first resonator to a side of the anchor, in which the first resonator is suspended over the cavity and is operable to bend towards or away from a bottom of the cavity; and coupling a second resonator to the side of the anchor, in which the second resonator is suspended over the cavity, at least a part of the first resonator is laterally between the side of the anchor and a part of the second resonator, and the first resonator is operable to bend in an opposite direction from the second resonator.
H03H 3/007 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
A method includes receiving, by a MMU for a processor core, an address translation request from the processor core and providing the address translation request to a TLB of the MMU; generating, by matching logic of the TLB, an address transaction that indicates whether a virtual address specified by the address translation request hits the TLB; providing the address transaction to a general purpose transaction buffer; and receiving, by the MMU, an address invalidation request from the processor core and providing the address invalidation request to the TLB. The method also includes, responsive to a virtual address specified by the address invalidation request hitting the TLB, generating, by the matching logic, an invalidation match transaction and providing the invalidation match transaction to one of the general purpose transaction buffer or a dedicated invalidation buffer.
Methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. An example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.
A programmable switch converter controller for a power stage with a switch, an inductor, and a diode, includes a pulse-width modulator. The pulse-width modulator is configured to: generate an on-time interval (Ton) that is fixed or proportional to a demand signal proportional to a load adapted to be coupled to an output of the power stage; generate an off-time interval (Toff) that is inversely proportional to the product of a voltage across the inductor while the switch is off and a demand signal proportional to the load; initiate Ton when Toff elapses; and initiate Ton responsive to an external trigger signal.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
One example includes a circuit (104). The circuit (104) includes a transistor device (106) arranged between a first terminal and a second terminal and a transistor device controller (108) configured to control operation of the transistor device (106). The circuit (104) further includes a current limit controller (110) that includes a current limit circuit (112) configured to regulate an amplitude of operational current through the transistor device (106) between the first and second terminals during a normal operating mode, and a testing system (116) configured to conduct a calibration current provided by an automated testing equipment (ATE) device (102) through an internal test resistor (118) for the ATE device (102) to determine a resistance value of the internal test resistor (118) during a test mode to facilitate testing of the current limit circuit (112) via a test current provided by the ATE device (102) between the first and second terminals through the transistor device (106) based on the determined resistance value of the internal test resistor (118).
A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.
A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as hardware logic on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.
Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/0871 - Allocation or management of cache space
30.
ENTERING PROTECTED PIPELINE MODE WITHOUT ANNULLING PENDING INSTRUCTIONS
Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, and wherein the first instruction is configured to utilize a first memory location, begin execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction configured to utilize the first memory location, determining that the first instruction and the second instruction utilize the first memory location, and stalling execution of the second instruction based on the determining.
An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a transaction handling block that dynamically maps the most frequently accessed data segments into faster access memory. The technique creates shadow copies of the most frequently accessed data segments in the faster access memory, which is associated with lower latency. Access frequencies of the data segments for which shadow copies are provided are updated dynamically based on use. The technique is flexible for different memory hierarchies.
In some examples, a method includes determining, during a boot sequence of a controller, a hash value for data of a block of a flash storage device, the block including executable code, determining a bit pattern based on a randomly generated number, extracting a subset of data bits of the hash value according to the bit pattern to obtain a snippet, and storing the snippet to a secure storage device.
A method comprises creating an electronic circuit design having a plurality of electronic components, creating an analog simulation model of the electronic circuit design, and executing the analog simulation model to generate one or more simulation logs representing simulated operation of the electronic circuit design. The method also comprises generating a neural network model based on the one or more simulation logs, the neural network model comprising a plurality of weights and generating a mathematical simulation model based on the neural network model.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
A method comprises creating an electronic circuit design having a plurality of electronic components, simulating operation of the electronic circuit design, and creating a behavior model of the electronic circuit design. The method further comprises eliminating one or more data points created in the behavior model to generate a trimmed behavior model, generating a real number model based on the trimmed behavior model, the real number model comprising a plurality of weights, and generating a simulation model based on the plurality of weights.
Systems and methods may perform sequential automatic test pattern generation (ATPG) on parallel memory units. In one example, a first array of logic gates may output enable signals to cause multiple memory units to be enabled in parallel. Test pattern generation and test control logic may perform forward path testing, backward path testing, and any other appropriate testing on the enabled memory units. The systems and methods may then move on to another group of memory units, which are enabled in parallel and tested in parallel.
An example apparatus includes: voltage divider circuitry configured to determine a common mode voltage of a differential pair of signals having a first voltage and a second voltage; a first amplifier coupled to the voltage divider circuitry, the first amplifier configured to determine a difference between the common mode voltage and a reference common mode voltage; current compensation circuitry coupled to the first amplifier, the current compensation circuitry configured to generate a first current and a second current responsive to the difference between voltages; and a second amplifier coupled to the voltage divider circuitry and the current compensation circuitry, the second amplifier to compensate the first voltage with the first current and the second voltage with the second current.
A device includes a communication interface, a command processing circuit, a clock synchronization circuit, and a controllable clock source. The command processing circuit has a command input, a reference frequency output, and a reference phase output. The command input is coupled to the communication interface. The clock synchronization circuit has a reference frequency input, a reference phase input, and a frequency control output. The reference frequency output is coupled to the reference frequency input, and the reference phase input coupled to the reference phase output. The clock synchronization circuit includes a frequency synchronization circuit and a phase synchronization circuit. The controllable clock source has a frequency control input and a clock output. The frequency control input is coupled to the frequency control output.
A circuit includes a receiver configured to couple to an antenna, configured to have a wakeup mode and an active mode, and to transition from the wakeup mode to the active mode in response to a wakeup signal received through the antenna. The receiver includes an impedance matching circuit coupled with the antenna, a low-noise amplifier coupled with the impedance matching circuit, a mixer coupled with the low-noise amplifier, a radio-frequency reference clock generator coupled with the mixer, a low-pass filter coupled with the mixer, an analog-to digital-converter coupled with the low-pass filter, and a control circuit configured to transition the receiver from the wakeup mode to the active mode in response to the wakeup signal. The low-noise amplifier, the mixer, the radio frequency reference clock generator, and the analog-to-digital converter are configured to be duty-cycled between a sleep state and an active wakeup receive state during the wakeup mode.
In described examples, an integrated circuit (IC) (1000) includes a fast Fourier transform (FFT) engine (604), a first memory (1012), a second memory (1014), a conjugate symmetric combiner (CSC) (516), and a control circuit (1004) and (1006) coupled to control them. The first and second memories (1012) and (1014) are coupled to the FFT engine (604), and the CSC (516) is coupled to the first and second memories (1012) and (1014) and the FFT engine (604). The FFT engine (604) receives and processes a first stream of samples to generate a second stream of samples. In a first phase, the FFT engine (604) provides a first portion of the second stream of samples to the first memory (1012). In a second phase, the FFT engine (604) provides a second portion of the second stream of samples to the second memory (1014), the first memory (1012) provides the first portion of the second stream of samples to the CSC (516), and the CSC (516) responsively generates a third stream of samples.
G06F 17/14 - Fourier, Walsh or analogous domain transformations
G06F 7/48 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices
G06F 7/501 - Half or full adders, i.e. basic adder cells for one denomination
A method of forming an integrated circuit includes forming a first trench that extends into the semiconductor substrate. A silicon nitride layer is deposited over the semiconductor substrate. The silicon nitride layer extends into the first trench. A second trench is formed that extends through the silicon nitride layer into the semiconductor substrate. The second trench is spaced apart from the first trench. An oxide layer is formed that fills the second trench. The silicon nitride layer outside the first trench is removed.
An example apparatus includes: error detection circuitry having an input and an output, the error detection circuitry configured to integrate a difference between a voltage of the input of the error detection circuitry and a reference voltage to produce an integrated error voltage; peak controller circuitry coupled to the error detection circuitry, the peak controller circuitry to compare a control current to a first reference current to generate a peak control current, the control current based on an integrated error voltage, the peak control current to increase an output current of converter circuitry; and valley controller circuitry coupled to the error detection circuitry and the peak controller circuitry, the valley controller circuitry to compare the control current to a second reference current to generate a valley control current, the valley control current to decrease the output current of the converter circuitry.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
42.
METHODS AND APPARATUS FOR SELECTIVE ENCRYPTION OF EXECUTE IN PLACE (XIP) DATA
An example apparatus includes: interface circuitry; and programmable circuitry configured to: obtain a set of processor instructions; select a first subset of processor instructions from the set; encrypt the first subset of processor instructions; select a second subset of processor instructions from the set; compute a plurality of message authentication codes (MACs) corresponding to the second subset of processor instructions; cause the interface circuitry to write the set of processor instructions to an external memory; and cause the interface circuitry to write a description of the first subset of processor instructions, a description of the second subset of processor instructions, and the plurality of MACs to the external memory.
G06F 7/58 - Random or pseudo-random number generators
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
An apparatus includes an amplifier having an input. An interface has inputs and an output. The interface is configured to: invert each bit of a value received at a first input of the interface to produce an inverted value; and provide the inverted value at the output. A processor has an input coupled the output of the interface, has first output coupled to a second input of the interface, and has a second output coupled to the input of the amplifier. The processor is configured to determine whether to set an adjustable gain setting of an audio processing block to the inverted value.
An apparatus includes a first power stage circuit having a first output and a power terminal, and a second power stage circuit having a second output and the power terminal. The apparatus further includes a control circuit having a control input, a first control output, and a second control output. In an example, the control input is coupled to the power terminal, the first control output is coupled to the first output, and the second control output is coupled to the second output. In an example, the control circuit is configured to, responsive to a first voltage at the power terminal being below a threshold voltage, set the first and second outputs to a second voltage.
Disclosed examples include microelectronic devices, e.g. integrated circuits, which include a source region and a drain region extending into a semiconductor substrate, the semiconductor substrate having a second conductivity type, the source region and drain region having an opposite first conductivity type. A channel region having the first conductivity type extends between the source region and the drain region. A gate electrode over the channel region has a first portion and a second portion. The first portion has the second conductivity type and a first dopant concentration. The second portion extends from the first portion toward the source region and has the second conductivity type and a second higher dopant concentration. A self-aligned implant is used to simultaneously implant dopants near the source end of the gate electrode and in the semiconductor substrate near the source region.
A method includes receiving a first measurement signal representing a first time between transitions of a motor commutation state. The method further includes receiving a second measurement signal representing a second time between transitions of a motor floating terminal voltage. The method further includes determining a motor speed state based on a combination of the first and second measurement signals, determining a motor commutation state based on the motor speed state and the motor floating terminal voltage; and providing a control signal to a motor inverter based on the motor commutations state.
In some aspects, an integrated circuit comprises an input voltage terminal, a capacitor terminal, a first NMOS transistor connected to the input voltage terminal, a first PMOS transistor connected to a first NMOS gate terminal of the first NMOS transistor and connected to the capacitor terminal, the first PMOS transistor having a first PMOS gate terminal, a second PMOS transistor connected to the first NMOS gate terminal of the first NMOS transistor, the second PMOS transistor having a second PMOS gate terminal, a switched output terminal, a second NMOS transistor connected to the switched output terminal, a third NMOS transistor connected to the switched output terminal, an inverter, and a complementary metal oxide semiconductor (CMOS) transistor pair, the CMOS transistor pair having an input connected to the third NMOS transistor and an output connected to a second PMOS gate terminal of the second PMOS transistor.
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A semiconductor package includes a semiconductor wafer having a first connection pad and a second connection pad spaced apart by a semiconductor region of the semiconductor wafer. Portions of the semiconductor wafer are covered by a protective overcoat. The semiconductor package also includes a cap wafer mounted to the semiconductor wafer and overpassing the semiconductor region of the semiconductor wafer. The cap wafer extends between the first connection pad and the second connection pad of the semiconductor wafer. The semiconductor package further includes an insulation material overlaying the cap wafer. The insulation material comprising vias to the first connection pad and the second connection pad, the vias being filled with a conductive material.
In examples, a power device comprises a first wide bandgap semiconductor die including a high-side transistor; a second wide bandgap semiconductor die including a low-side transistor; and a conductive device coupled to the first and second wide bandgap semiconductor dies. The conductive device comprises a first layer including a first metal member having fingers at first and second ends of the first metal member, a second metal member having fingers interleaved with fingers of the first metal member at the first end, and a third metal member having fingers interleaved with fingers of the first metal member at the second end. The conductive device also comprises multiple layers in vertical alignment with the first layer, the first, second, and third metal members extending through the multiple layers. The conductive device also comprises a dielectric material covering the first layer and the multiple layers. The power device comprises a connection layer coupling the conductive device to each of the first and second wide bandgap semiconductor dies, with the connection layer including the first, second, and third metal members, and with the first metal member having connection layer fingers at the first and second ends of the first metal member. The second metal member has connection layer fingers interleaved with connection layer fingers of the first metal member at the first end, and the third metal member has connection layer fingers interleaved with connection layer fingers of the first metal member at the second end.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
50.
SEMICONDUCTOR DEVICE PACKAGE WITH INTEGRAL THERMAL DISSIPATION STRUCTURE
An example includes: a package substrate having a die pad with a device side surface and a thermal pad on an opposite side surface; a thermal dissipation structure mounted to the die pad, the thermal dissipation structure including a thermally conductive insulator core and thermal conductors on a device side surface and on a substrate mount surface opposite the device side surface; at least one semiconductor device die mounted to the device side surface of the thermal dissipation structure; electrical connections formed between leads on the package substrate and bond pads on the at least one semiconductor device die; and mold compound covering the electrical connections, the at least one semiconductor device, and portions of the package substrate, portions of the leads of the package substrate forming terminals, and the thermal pad exposed from the mold compound and forming a thermal pad for a semiconductor device package.
A method forms an integrated circuit, by steps including, in a first implant, forming in a semiconductor substrate a first and second region of a first semiconductor type, each of the first and second region having a first dopant concentration; in a second implant, forming in the semiconductor substrate a third and fourth region of the first semiconductor type, the third region at least partially overlapping the first region and the fourth region at least partially overlapping the second region, each of the third and fourth region having a second dopant concentration different than the first dopant concentration; forming a transistor source within the first and third regions; and forming one of a diode anode or a diode cathode in the second and fourth regions.
A method includes forming, on a dielectric layer of an integrated circuit, a first layer of a first material, forming, on the first layer, a second layer of a second material, and patterning the second layer to expose the first layer. Via the patterned second layer, the exposed first layer is etched to form protrusion structures of the first layer and the second layer and grooves between adjacent ones of the protrusion structures. The method also includes forming a graphitic carbon layer on at least part of the second layer of the protrusion structures, and depositing carbon nanotubes into the grooves between the adjacent ones of the protrusion structures.
An example system includes: a first device having a ground plane at a first voltage, a first transmission terminal, and a second transmission terminal; a second device having a ground plane at a second voltage, a first receiver terminal, and a second receiver terminal; wherein the first device is configured to: operate in either a linear mode or a saturation mode based on a magnitude of electromagnetic interference; and during the linear mode or the saturation mode, use the first transmission terminal and second transmission terminal to transmit a differential signal to the second device.
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
B60L 50/60 - Electric propulsion with power supplied within the vehicle using propulsion power supplied by batteries or fuel cells using power supplied by batteries
In described examples, an integrated circuit (IC) includes a fast Fourier transform (FFT) engine, a first memory, a second memory, a conjugate symmetric combiner (CSC), and a control circuit coupled to control them. The first and second memories are coupled to the FFT engine, and the CSC is coupled to the first and second memories and the FFT engine. The FFT engine receives and processes a first stream of samples to generate a second stream of samples. In a first phase, the FFT engine provides a first portion of the second stream of samples to the first memory. In a second phase, the FFT engine provides a second portion of the second stream of samples to the second memory, the first memory provides the first portion of the second stream of samples to the CSC, and the CSC responsively generates a third stream of samples.
An integrated circuit (IC) includes: first and second transistors having a respective first terminal, a respective second terminal, and a respective control terminal; and cascode circuitry having a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first terminal of the cascode circuitry is coupled to the control terminal of the first transistor. The second terminal of the cascode circuitry is coupled to the control terminal of the second transistor. The third terminal of the cascode circuitry is coupled to the second terminal of the first transistor. The fourth terminal of the cascode circuitry is coupled to the second terminal of the second transistor. The IC also includes dynamic biasing circuitry having a first terminal and a second terminal. The first terminal of the dynamic biasing circuitry is coupled to the first terminals of the first and second transistors.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
56.
INTEGRATED HIGH VOLTAGE ELECTRONIC DEVICE WITH HIGH RELATIVE PERMITTIVITY LAYERS
A magnetic assembly includes a multilevel lamination or metallization structure with a core dielectric layer, dielectric stack layers, a high permittivity dielectric layer, and first and second patterned conductive features, the dielectric stack layers having a first relative permittivity, the high permittivity dielectric layer extends between and contacting the first patterned conductive feature and one of the dielectric stack layers or the core dielectric layer, the high permittivity dielectric layer has a second relative permittivity, and the second relative permittivity is at least 1.5 times the first relative permittivity to mitigate dielectric breakdown in isolation products.
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
Techniques related to measuring a time-of-flight (ToF), comprising switching a first measuring station to a main operating mode, transmitting, by the first measuring station, a first ToF packet to a remote device, switching the first measuring station to a receive mode to receive a first ToF response packet from the remote device, receiving, by the first measuring station, the first ToF response packet, determining, a time interval between transmitting of the first ToF packet and receiving the first ToF response packet, receiving a plurality of time intervals from one or more other measuring stations, determining a ToF measurement based on the first time interval and the plurality of time intervals, switching the first measuring station to a secondary operating mode, and transmitting to a second measuring station, an indication to switch to the main operating mode.
An integrated circuit includes one or more central processing unit (CPU) cores configured to cause a first ultrasonic transducer to generate ultrasonic signals into a fluid moving in a pipe and the first or a second ultrasonic transducer to receive the ultrasonic signals from the fluid. The CPU core(s) also compute a first value indicative of at least one of a standard deviation and a time correlation based on the received ultrasonic signals. The CPU core(s) further determine a second value indicative of a volume of gas bubbles in the fluid using the computed first value indicative of the at least one of the standard deviation and time correlation.
G01F 1/66 - Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by measuring frequency, phase shift or propagation time of electromagnetic or other waves, e.g. using ultrasonic flowmeters
G01F 1/667 - Arrangements of transducers for ultrasonic flowmetersCircuits for operating ultrasonic flowmeters
G01F 1/7082 - Measuring the time taken to traverse a fixed distance using acoustic detecting arrangements
G01F 1/712 - Measuring the time taken to traverse a fixed distance using auto-correlation or cross-correlation detection means
G01F 1/74 - Devices for measuring flow of a fluid or flow of a fluent solid material in suspension in another fluid
An example (500) includes; a package substrate (515) having a die pad with a device side surface and a thermal pad (509) on an opposite side surface; a thermal dissipation structure (516) mounted to the die pad and that includes a thermally conductive insulator core (421) and thermal conductors on a device side surface (527) and on a substrate mount surface (526) opposite the device side surface; a semiconductor die (405) mounted to the device side surface of the thermal dissipation structure; electrical connections (520) formed between leads (519) on the package substrate and bond pads on the semiconductor die; and mold compound (523) covering the electrical connections, the semiconductor die, and portions of the package substrate, portions of the leads of the package substrate forming terminals (511), and the thermal pad (509) exposed from the mold compound and forming a thermal pad for a semiconductor device package (500).
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
Methods and apparatus for optical filtering. In one example, a device includes a spatial light modulator (102) having a two-dimensional array of square, rectangular, or diamond pixels, and a controller (110) coupled to the spatial light modulator (102). The controller (110) can be configured to write image data (114) representing an image to the spatial light modulator (102) to control the spatial light modulator (102) to display the image for a frame period, and during the frame period, spatially reposition the image on the array of pixels over a plurality of positions, each individual position of the plurality of positions being maintained for a respective time period, wherein the respective time period is selected according to one or more non-negative coefficients of an anti-aliasing filter transfer function (402).
G09G 5/36 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory
G09G 3/00 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 5/391 - Resolution modifying circuits, e.g. variable screen formats
H04N 9/31 - Projection devices for colour picture display
An electronic device includes first leads along a first side, second leads along a second side, first and second dies, and a magnetic assembly with a multilevel lamination structure with first and second windings and a conductive guard trace. The lamination structure includes the first winding in a first level, and the second winding in a different level. The guard trace is between the first patterned conductive feature and the second side of the package structure. A first set of electrical connections couple the first die, the first winding, and one of the first conductive leads in a first circuit, and a second set of electrical connections couple the second die, the second winding, the guard trace and one of the second conductive leads in an isolated second circuit.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
H01L 23/00 - Details of semiconductor or other solid state devices
A method for coding unit partitioning in a video encoder is provided that includes performing intra-prediction on each permitted coding unit (CU) in a CU hierarchy of a largest coding unit (LCU) to determine an intra-prediction coding cost for each permitted CU, storing the intra-prediction coding cost for each intra-predicted CU in memory, and performing inter-prediction, prediction mode selection, and CU partition selection on each permitted CU in the CU hierarchy to determine a CU partitioning for encoding the LCU, wherein the stored intra-prediction coding costs for the CUs are used.
H04N 19/192 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding the adaptation method, adaptation tool or adaptation type being iterative or recursive
H04N 19/103 - Selection of coding mode or of prediction mode
H04N 19/107 - Selection of coding mode or of prediction mode between spatial and temporal predictive coding, e.g. picture refresh
H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
H04N 19/169 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/51 - Motion estimation or motion compensation
H04N 19/52 - Processing of motion vectors by encoding by predictive encoding
H04N 19/593 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques
Fault detection circuits and methods. An example of a fault detection circuit includes a comparator configured to compare a voltage at a voltage terminal with a reference voltage, a digital logic circuit coupled to a test terminal and configured to receive, responsive to the voltage at the voltage terminal being less than the reference voltage as indicated by the comparator, a test signal, the digital logic circuit including at least one digital logic gate, and an edge detection circuit configured to (a) monitor a signal produced at an output of the at least one digital logic gate, and (b) based on the signal failing to transgress a threshold within a time period, providing a fault signal indicating detection of a fault at the test terminal.
A voltage monitoring circuit is configured to monitor the input voltage in a power converter and to assert a reset signal to disable operation of the power converter in response to the input voltage falling below a threshold level. The voltage monitoring circuit may include a power-on-reset (POR) block that asserts the reset signal in response to the input voltage falling below a first threshold at a first rate, and a brown-out block that asserts the reset signal in response to the input voltage falling below a second threshold at a faster second rate (e.g., the input voltage falls quickly to zero or near zero such as during a brown-out event). The brown-out block includes a backup supply voltage that maintains some positive voltage level even in the absence of the input voltage for a certain period of time and a discharge circuit designed to quickly assert the reset signal.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
65.
FAULT DETECTION FRONT END ARCHITECTURE IN RESOLVER
In some examples, a method includes applying a bias voltage to a resolver system. The method also includes receiving a sensed signal, the sensed signal varying in value based on a position of a rotary element. The method also includes attenuating the sensed signal to form an attenuated signal. The method also includes performing fault detection on the attenuated signal to detect faults in the resolver system. The method also includes processing the attenuated signal to determine the position of the rotary element.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
A device that includes a lead structure and a coil is provided. The lead structure, of an electrically conductive material, has a lead structure width. The coil, of the electrically conductive material, includes first and second coil ends and a number of windings of the electrically conductive material extending between the first and second coil ends. The lead structure width is greater than a largest cross sectional dimension of the windings.
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
In examples, a method for manufacturing a package comprises coupling first and second semiconductor dies to a first surface of a conductive terminal; applying a dry film to a second surface of the conductive terminal opposite the first surface; removing a portion of the dry film contacting the second surface to form a dry film opening, the dry film opening having a linear, non-curved edge extending along a width of the conductive terminal; etching the second surface through the dry film opening; removing the dry film; plating the second surface; and sawing through the conductive terminal to form the package.
In an example, a circuit includes a differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal. The differential input circuit includes a first transistor having a first transistor control terminal and first and second terminals. The differential input circuit includes a second transistor having a second transistor control terminal and first and second terminals, the first terminals of the first and second transistors coupled together. The circuit includes a first capacitor having the first capacitor terminal and having another terminal coupled to the first transistor control terminal. The circuit also includes a second capacitor having the second capacitor terminal and having another terminal coupled to the second transistor control terminal. The circuit includes a first offset correction input coupled to the first transistor control terminal and a second offset correction input coupled to the second transistor control terminal.
H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
In a described example, a position sensor can include a first magnetic field sensor unit having a first sensor output, a second magnet field sensor unit having a second sensor output, one or more coils having one or more footprints overlapping the first and second magnetic field sensor units, and a processing circuit having a first sensor input, a second sensor input, a current terminal, and a sensing output, the first sensor input coupled to the first sensor output, the second sensor input coupled to the second sensor output, and the current terminal coupled to the one or more coils.
G01D 18/00 - Testing or calibrating apparatus or arrangements provided for in groups
G01D 5/14 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
70.
WAFER-LEVEL CHIP SCALE PACKAGE TRANSIENT VOLTAGE SUPPRESSION DIODE DEVICE
An example arrangement includes a semiconductor device having at least two vertical diode devices spaced from one another by isolation trenches. Each of the vertical diode devices includes: a first diffusion region of a first P-type or N-type conductivity formed in a device side surface of the semiconductor die, the first diffusion region extending into a first epitaxial layer of a second P-type or N-type conductivity opposite the first conductivity type; the first epitaxial layer formed over a semiconductor substrate of the first P-type or N-type conductivity. The semiconductor substrate includes a backside surface facing away from the device side surface of the semiconductor die; metal contacts on the device side surface of the semiconductor die are electrically coupled to the first diffusion region; and stud bumps formed on the metal contacts and arranged to form terminals of the semiconductor device.
H01L 21/784 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
One example includes a circuit. The circuit includes a transistor device arranged between a first terminal and a second terminal and a transistor device controller configured to control operation of the transistor device. The circuit further includes a current limit controller that includes a current limit circuit configured to regulate an amplitude of operational current through the transistor device between the first and second terminals during a normal operating mode, and a testing system configured to conduct a calibration current provided by an automated testing equipment (ATE) device through an internal test resistor for the ATE device to determine a resistance value of the internal test resistor during a test mode to facilitate testing of the current limit circuit via a test current provided by the ATE device between the first and second terminals through the transistor device based on the determined resistance value of the internal test resistor.
An example apparatus includes: a first transistor having a first terminal, a second terminal, and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor, the second terminal of the second transistor coupled to the second terminal of the first transistor; first driver circuitry having a terminal coupled to the control terminal of the first transistor; second driver circuitry having a terminal coupled to the control terminal of the second transistor; and gate balancing circuitry having a first terminal and a second terminal, the first terminal of the gate balancing circuitry coupled to the control terminal of the first transistor and the terminal of the first driver circuitry, the second terminal of the gate balancing circuitry coupled to the control terminal of the second transistor.
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
73.
METHODS AND APPARATUS TO PROTECT AGAINST VOLTAGE GLITCH ATTACKS IN MICROCONTROLLERS
Methods, apparatus, systems, and articles of manufacture are disclosed to protect against voltage glitch attacks in microcontrollers. An example apparatus includes logic circuitry operable to, in response to a voltage glitch, pause processing circuitry; number generator circuitry operable to generate a number; a counter operable to, after the voltage glitch ends, adjust a count corresponding to the number; and the logic circuitry operable to unpause the processing circuitry after the count reaches a value.
G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
74.
FAULT DETECTION FRONT END ARCHITECTURE IN RESOLVER
In some examples, a method (400) includes applying a bias voltage to a resolver system (402). The method also includes receiving a sensed signal, the sensed signal varying in value based on a position of a rotary element (404). The method also includes attenuating the sensed signal to form an attenuated signal (406). The method also includes performing fault detection on the attenuated signal to detect faults in the resolver system (408). The method also includes processing the attenuated signal to determine the position of the rotary element (410).
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
G01R 1/04 - HousingsSupporting membersArrangements of terminals
G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
G01R 15/18 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using inductive devices, e.g. transformers
G01D 5/244 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing characteristics of pulses or pulse trainsMechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means generating pulses or pulse trains
G01D 5/20 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
An apparatus (150) includes a circuit (202) including a circuit input (151), a circuit output (152), and a circuit terminal (233). A current mirror (210) has a mirror input (211) and a mirror output (212). The mirror input (211) is coupled to the circuit terminal (233). A logic gate (228) has a logic gate input (226) coupled to the mirror output (212). A resistor (R1) is coupled between the mirror output (212) and a supply reference terminal (106). A transistor (MO) has a control input and a current terminal. The control input is coupled to the circuit input (151). The current terminal is coupled to the circuit output (152).
H03K 17/22 - Modifications for ensuring a predetermined initial state when the supply voltage has been applied
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 17/06 - Modifications for ensuring a fully conducting state
Fault detection circuits and methods. An example of a fault detection circuit (300) includes a comparator (202) configured to compare a voltage at a voltage terminal with a reference voltage (Vref), a digital logic circuit (204) coupled to a test terminal (SW) and configured to receive, responsive to the voltage at the voltage terminal being less than the reference voltage as indicated by the comparator (202), a test signal, the digital logic circuit (204) including at least one digital logic gate (312), and an edge detection circuit (310) configured to (a) monitor a signal produced at an output of the at least one digital logic gate (312), and (b) based on the signal failing to transgress a threshold within a time period, providing a fault signal indicating detection of a fault at the test terminal (SW).
An example apparatus includes a read queue to store a first read request to access a first storage, sequencing circuitry coupled to the read queue, and prioritization circuitry coupled to the sequencing circuitry and coupled to the first storage and a second storage via a shared bus. The example sequencing circuitry is to sequence a portion of a second request to access the second storage to be interleaved with a wait interval of the first read request, the second request queued after the first read request. Additionally, the example prioritization circuitry is to generate a first transaction to access the first storage over the shared bus and a second transaction to access the second storage over the shared bus concurrently with the first transaction, the first transaction based on the first read request, the second transaction based on the second request.
A power supply system may include multiple DC-to-DC (direct current) voltage regulators coupled in parallel to a load, and control circuitry to control the parallel-operating regulators. The control circuitry may include a first share control circuit, a second share control circuit, and a voltage regulation circuit. The first and second share control circuits may operate together with the voltage regulation circuit to control, respectively, the parallel-operating regulators to regulate a common output voltage. Additionally, first and second share control circuits may operate together with the voltage regulation circuit to control respective share of the load current by the parallel-operating regulators.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
The present disclosure generally relates to a corrugated capacitor in an integrated circuit (IC). In an example, an IC includes a first corrugated conductive layer, a second corrugated conductive layer, and a corrugated dielectric layer. The first corrugated conductive layer and the second corrugated conductive layer are over a semiconductor substrate. The corrugated dielectric layer is between the first corrugated conductive layer and the second corrugated conductive layer. Various examples may achieve a larger surface areas for respective plates of a capacitor for a given lateral footprint of the capacitor.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
An apparatus includes a circuit including a circuit input, a circuit output, and a circuit terminal. A current mirror has a mirror input and a mirror output. The mirror input is coupled to the circuit terminal. A logic gate has a logic gate input coupled to the mirror output. A resistor is coupled between the mirror output and a supply reference terminal. A transistor has a control input and a current terminal. The control input is coupled to the circuit input. The current terminal is coupled to the circuit output.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
An apparatus includes a charge transfer circuit, a control circuit, and a processing circuit. The charge transfer circuit has a first terminal, a second terminal, a third terminal, and a control input. The control circuit has a control output coupled to the control input. The processing circuit has a first input, a second input, and an output. The processing circuit is configured to receive a first signal at the first input and receive a second signal at the second input. The first signal represents a current through the charge transfer circuit. The second signal represents at least one of a first voltage between the first and second terminals or a second voltage between the second and third terminals. The processing circuit is also configured to provide a third signal based on the first and second signals at the output.
A processor in a device is configured to access a power policy for the device, where the power policy indicates a relationship between power consumption by the device and another performance variable of the device. The processor is also configured to produce an operating point for the device based at least in part on the power policy. The processor is also configured to provide information regarding the operating point to a management entity that manages the device.
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.
A method includes detecting a voltage of the battery, detecting a current of the battery, determining a depth of discharge of the battery based on the voltage and the current of the battery, and controlling terminating charging of the battery responsive to the determined depth of discharge of the battery reaching a depth of discharge threshold. A system includes a battery gauge circuit and a processor coupled to the battery gauge circuit. The battery gauge circuit has a voltage sense input and a current sense input and is configured to determine a depth of discharge of a battery based on a battery voltage at the voltage sense input and a battery current at the current sense input. The processor is configured to control terminating charging of the battery responsive to the determined depth of discharge reaching a depth of discharge threshold.
Integrated circuit packaging with cavities and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor die and a housing enclosing portions of the semiconductor die. The housing defines an opening that extends from a surface of the semiconductor die to an external environment, the housing formed of a first material. The example apparatus includes a second material disposed within the opening to block exposure of the semiconductor die to the external environment.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
Radar systems are provided for transmitting radar signals using one or more flexible dielectric waveguides (DWGs), each having a core member surrounded by a cladding, in which the core and cladding have different dielectric constants. A single radar circuit may be used to generate radar signals that are distributed, via the DWGs, to multiple launch structures placed at various locations on a vehicle. In an example, a launch structure, coupled to a port of the radar circuit, has an outer surface that is configured to couple to an inner surface of a body part of an external structure to emit a radar signal through the outer surface in a path that extends through the body part, in which the body part is non-transparent to light and does not have an opening in the path of the radar signal.
A method for pseudo channel hopping in a node of a wireless mesh network is provided that includes scanning each channel of a plurality of channels used for packet transmission by the node, wherein each channel is scanned for a scan dwell time associated with the channel, updating statistics for each channel based on packets received by the node during the scanning of the channel, and changing scan dwell times of the plurality of channels periodically based on the statistics.
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
H04W 40/22 - Communication route or path selection, e.g. power-based or shortest path routing using selective relaying for reaching a BTS [Base Transceiver Station] or an access point
H04W 84/18 - Self-organising networks, e.g. ad hoc networks or sensor networks
88.
VOLTAGE CONVERTER WITH AVERAGE INPUT CURRENT CONTROL AND INPUT-TO-OUTPUT ISOLATION
A circuit includes a comparator circuit having a first input, a second input, a first output and a second output. The circuit also includes the first input configured to receive an input voltage of a power supply circuit and the second input configured to receive an output voltage of the power supply circuit. Additionally, the circuit includes the first output to provide the larger of the input voltage or the output voltage and the second output to provide a logic low signal responsive to the input voltage being less than the output voltage, and to provide a logic high signal responsive to the input voltage being greater than or equal to the output voltage.
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
89.
METHODS AND APPARATUS TO RENDER 3D CONTENT WITHIN A MOVEABLE REGION OF DISPLAY SCREEN
A method includes projecting, by a first projector, a first image to a first region, the first image having a first angular resolution and a first number of views. The method also includes projecting, by a second projector, a second image to a second region, the second image having a second angular resolution and a second number of views, where the second region is within the first region, the second angular resolution is greater than the first angular resolution, and the second number of views is greater than the first number of views.
H04N 9/31 - Projection devices for colour picture display
H04N 13/302 - Image reproducers for viewing without the aid of special glasses, i.e. using autostereoscopic displays
H04N 13/32 - Image reproducers for viewing without the aid of special glasses, i.e. using autostereoscopic displays using arrays of controllable light sourcesImage reproducers for viewing without the aid of special glasses, i.e. using autostereoscopic displays using moving apertures or moving light sources
H04N 13/361 - Reproducing mixed stereoscopic imagesReproducing mixed monoscopic and stereoscopic images, e.g. a stereoscopic image overlay window on a monoscopic image background
H04N 13/363 - Image reproducers using image projection screens
H04N 13/383 - Image reproducers using viewer tracking for tracking with gaze detection, i.e. detecting the lines of sight of the viewer's eyes
90.
CONTROL CIRCUITRY FOR PARALLEL-OPERATING VOLTAGE REGULATORS
A power supply system may include multiple DC-to-DC (direct current) voltage regulators (202 and 204) coupled in parallel to a load (208), and control circuitry (206) to control the parallel-operating regulators. The control circuitry may include a first share control circuit (280), a second share control circuit (282), and a voltage regulation circuit (284). The first and second share control circuits may operate together with the voltage regulation circuit to control, respectively, the parallel¬ operating regulators to regulate a common output voltage. Additionally, first and second share control circuits may operate together with the voltage regulation circuit to control respective share of the load current by the parallel-operating regulators.
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Comparator circuitry (200) for power converters. In an example, a circuit includes a comparator (204) having a first comparator input, a second comparator input, and a comparator output, the comparator coupled to a supply terminal (216). The circuit further includes a first transistor (302) coupled between a boot terminal (120) and the first comparator input and having a control terminal coupled to a switching terminal (104), and a second transistor (304) coupled between the boot terminal (120) and the second comparator input and having a control terminal coupled to the switching terminal (104). Also, a third transistor (316) is coupled between the supply terminal (216) and the second comparator input, and a voltage reference generator (324) is coupled to the supply terminal (216) and to a control terminal of the third transistor (316).
An apparatus includes a charge transfer circuit (202), a control circuit, and a processing circuit (110). The charge transfer circuit (202) has a first terminal, a second terminal, a third terminal, and a control input. The control circuit has a control output coupled to the control input. The processing circuit (110) has a first input, a second input, and an output. The processing circuit (110) is configured to receive a first signal at the first input and receive a second signal at the second input. The first signal represents a current through the charge transfer circuit. The second signal represents at least one of a first voltage between the first and second terminals or a second voltage between the second and third terminals. The processing circuit (110) is also configured to provide a third signal based on the first and second signals at the output.
An emulated wireless access point (AP) at a first PMC device (PMC1) establishes a first tunneled direct link setup (TDLS) session between a first station module (STA1) incorporated into the PMC1 and a second station module (STA2) incorporated into a second PMC device (PMC2). Following establishment of the TDLS session, the wireless AP is allowed to sleep; and most infrastructure management duties are handled by the STA1 during the session. PMC device battery charge may be conserved as a result. The emulated wireless AP may also establish a second TDLS link to a third station module (STA3) incorporated into a third PMC device (PMC3). The STA1 may then bridge data traffic flow between the STA2 and the STA3. Such bridging operation may enable communication between two PMC devices otherwise unable to decode data received from the other.
In described examples, a circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.
In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
G06F 7/24 - Sorting, i.e. extracting data from one or more carriers, re-arranging the data in numerical or other ordered sequence, and re-recording the sorted data on the original carrier or on a different carrier or set of carriers
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
G06F 7/53 - Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
G06F 7/57 - Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups or for performing logical operations
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter
G06F 9/345 - Addressing or accessing the instruction operand or the result of multiple operands or results
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
G06F 12/1009 - Address translation using page tables, e.g. page table structures
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
A circuit includes a current emulation circuit having an output and a current measurement circuit having an input and an output. The circuit also includes a first switch having a first terminal and a second terminal, the first terminal coupled to the output of the current measurement circuit and a second switch having a first terminal and a second terminal, the first terminal coupled to the output of the current emulation circuit and the second terminal coupled to the second terminal of the first switch. Additionally, the circuit includes a third switch having a first terminal and a second terminal, the first terminal coupled to the first terminal of the first switch and the second terminal coupled to the first terminal of the second switch.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.
A technique for convergence verification including receiving a data object representation of a first circuit block, receiving one or more assumptions associated with the first circuit block, identifying a synchronization scheme coupled to a port of the first circuit block, determining that the synchronization scheme is within a threshold flip-flop depth, identifying, based on the determination that the synchronization scheme is within the threshold flip-flop depth, a type of the synchronization scheme and a flip-flop depth between the synchronization scheme and the port, generating first convergence information for the first circuit block based on the identified type and flip-flop depth of the synchronization scheme, and outputting the generated convergence information.
In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetchs the lower half level two cache line employing fewer resources than an ordinary prefetch.
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
