In a circuit for DC-DC voltage converters, an amplifier has first and second inputs coupled to a reference voltage terminal and an output voltage terminal, respectively. A comparator has first and second inputs coupled to an amplifier output and a switching terminal, respectively. A logic circuit has inputs coupled to the comparator output and a clock terminal. A driver circuit has first and second inputs coupled to first and second logic outputs, respectively. A first transistor having a first control terminal coupled to the first driver output is coupled between a supply voltage terminal and the switching terminal. A second transistor is coupled between the switching terminal and a ground terminal, and has a second control terminal coupled to the second driver output. A threshold detection circuit is configured to provide a threshold signal responsive to a current through the second transistor crossing a current threshold.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03F 3/345 - DC amplifiers in which all stages are DC-coupled with semiconductor devices only with field-effect devices
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
A method for interconnecting bond pads of semiconductor dies or devices with corresponding leads in a lead frame with printed conductive interconnects in lieu of bond wires and an apparatus resulting from the above method. More specifically, some examples include printing an insulating foundation path from bond-pads on a semiconductor die to leads of a lead frame to which the semiconductor die is attached. A foundation conductive trace is printed on top of the insulating foundation path from each bond pad on the die to a corresponding lead of the lead frame. Optionally, on top of the conductive trace, a cover insulating cover layer is applied on exposed portions of the conductive interconnects and the foundation insulating layer. Preferably, this can be the same material as foundation layer to fully adhere and blend into a monolithic structure, rather than separate layers. Optionally, a protective layer is then applied on the resulting apparatus.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
3.
WIRELESS CONNECTION ESTABLISHMENT BETWEEN PERIPHERAL DEVICE AND MULTIPLE CENTRAL DEVICES
A method includes receiving, by a peripheral device, a first connection request from a first central device; providing, by the peripheral device, a first indication of an anchor point time to the first central device before establishing a first wireless connection with the first central device; and responding, by the peripheral device, to the first connection request and establishing the first wireless connection using a first anchor point based on the first indication.
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
H04W 76/11 - Allocation or use of connection identifiers
H04W 76/40 - Connection management for selective distribution or broadcast
4.
METHODS AND APPARATUS TO CAPTURE SWITCH CHARGE INJECTIONS AND COMPARATOR KICKBACK EFFECTS
An example apparatus includes: controller circuitry configured to: provide switch signals to capacitive digital to analog converter (C-DAC) circuitry, the C-DAC circuitry including switches; configuring the switches into a third configuration begin an Auto Zero (AZ) phase with a third switch in a closed state; configuring the switches into a fourth configuration to repeat the transition of the third switch to the open state corresponding to a first configuration; configuring the switches into a fifth configuration to repeat the transition of a first switch and a second switch to the open state corresponding to a second configuration; configuring the switches into a sixth configuration to repeat the transition of the third switch to the closed state corresponding to a second configuration; and performing an AZ decision with the switches in the sixth configuration.
H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type
H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
H03M 1/16 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
H03M 1/80 - Simultaneous conversion using weighted impedances
A communication circuit includes network formation circuitry configured to establish a wireless network between a primary wireless transceiver and a secondary wireless transceiver. The communication circuit also includes data transfer circuitry configured to perform data transfers between the primary wireless transceiver and the secondary wireless transceiver. The communication circuit further includes resynchronization circuitry configured to resynchronize the secondary wireless transceiver with the established wireless network within a target time interval.
H04B 1/7156 - Arrangements for sequence synchronisation
H04B 1/3805 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving with built-in auxiliary receivers
H04W 72/0453 - Resources in frequency domain, e.g. a carrier in FDMA
A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.
A short detection circuit includes a first transistor, a switched load circuit, a second transistor, a switched capacitor circuit, and a comparator. The first transistor is configured to conduct a load current. The switched load circuit is coupled to the first transistor. The switched load circuit is configured to switchably draw a test current. The second transistor is coupled to the first transistor. The second transistor is configured to conduct a sense current. The sense current includes first and second portions that are respectively representative of the load current and the test current. The switched capacitor circuit is coupled to the second transistor. The switched capacitor circuit is configured to generate a short detection voltage representative of the second portion. The comparator has a first comparator input coupled to the switched capacitor circuit. The comparator is configured to compare the short detection voltage to a short threshold voltage.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
8.
CIRCUITS AND METHODS TO CALIBRATE MIRROR DISPLACEMENT
A method includes setting first and second capacitor plates of a capacitive structure to an initial displacement position; applying a known control voltage to at least one of the first and second capacitor plates to generate a first displacement; measuring a first capacitance of the capacitive structure at the first displacement; setting the first and second capacitor plates to a second displacement; measuring a second capacitance of the capacitive structure at the second displacement; determining the difference between the first and second capacitances to determine the difference between the first and second displacements; and adjusting the control voltage based on results of the determining operation.
G01B 7/06 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width, or thickness for measuring thickness
G01B 7/14 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring distance or clearance between spaced objects or spaced apertures
G01R 17/00 - Measuring arrangements involving comparison with a reference value, e.g. bridge
G01R 27/26 - Measuring inductance or capacitanceMeasuring quality factor, e.g. by using the resonance methodMeasuring loss factorMeasuring dielectric constants
G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
9.
ENABLING DOWN LINK RECEPTION OF SYSTEM AND CONTROL INFORMATION FROM INTRA-FREQUENCY NEIGHBORS WITHOUT GAPS IN THE EVOLVED-UTRA SYSTEMS
Simplified communication between user equipment and a neighboring cell not the primary cell is achieved by restricting the transmission parameters, such as bandwidth, of the neighboring cell transmission and provision of a simplified secondary baseband processor in the user equipment.
Disclosed herein are systems and methods for executing a neural network (NN) across multiple processing cores. In an example embodiment, a system includes processing circuitry comprising a first processing core and a second processing core, such that the second processing core is coupled to the first processing core. Prior to executing a current layer of the NN, the second processing core determines a synchronization status of the first processing core with respect to a previous layer of the NN. Next, the second processing core executes the current layer of the NN based on data computed by the first and second processing cores with respect to the previous layer of the NN. Upon executing the current layer of the NN, the second processing core updates the first processing core with a synchronization status of the second processing core with respect to the current layer of the NN.
A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.
H10D 1/68 - Capacitors having no potential barriers
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
12.
METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH
Methods, apparatus, systems and articles of manufacture are disclosed for multi-banked victim cache with dual datapath. An example cache system includes a storage element that includes banks operable to store data, ports operable to receive memory operations in parallel, wherein each of the memory operations has a respective address, and a plurality of comparators coupled such that each of the comparators is coupled to a respective port of the ports and a respective bank of the banks and is operable to determine whether a respective address of a respective memory operation received by the respective port corresponds to the data stored in the respective bank.
G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 12/0806 - Multiuser, multiprocessor or multiprocessing cache systems
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/0817 - Cache consistency protocols using directory methods
G06F 12/0853 - Cache with multiport tag or data arrays
G06F 12/0855 - Overlapped cache accessing, e.g. pipeline
G06F 12/0864 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
G06F 12/0884 - Parallel mode, e.g. in parallel with main memory or CPU
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 12/121 - Replacement control using replacement algorithms
G06F 12/126 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
G06F 12/127 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning using additional replacement algorithms
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G11C 29/44 - Indication or identification of errors, e.g. for repair
13.
LINEAR APPROXIMATION OF A COMPLEX NUMBER MAGNITUDE
An example device includes a multiplexer configured to receive a first digital output value indicating whether a first inequality condition with respect to first and second input values is true or false, and a second digital output value indicating whether a second inequality condition with respect to the first and second input values is true or false. Such device further includes calculation circuitry coupled to the multiplexer and configured to receive the first and second input values and calculate an output value representative of a linear combination of the first and second input values as specified by a select signal that is based on the first and second digital output values.
G06F 7/48 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices
G06F 17/14 - Fourier, Walsh or analogous domain transformations
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
14.
COMMUNICATION INTERFACE WITH CALIBRATING DELAY CIRCUIT
In described examples, a device includes a transmitter, a receiver, and a control circuit. The transmitter transmits a clock signal, and the receiver receives a response signal. The control circuit is coupled to the transmitter and the receiver. The control circuit causes the transmitter to transmit a first clock signal with a first clock period, and to transmit a second clock signal with a second clock period greater than the first clock period. The control circuit determines whether a first pattern of a signal responsive to the first clock signal is the same as a second pattern of a signal responsive to the second clock period. If the patterns are the same, the control circuit delays the clock signal with a delay responsive to the first clock period to generate a delayed clock signal. The receiver samples response signals using the delayed clock signal during normal operation of the device.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
An integrated circuit (IC) includes a tristatable output buffer having a control input. The IC includes an input buffer having a buffer output. The IC further includes a delay circuit having a delay circuit input, a first delay circuit output, and a second delay circuit output. The delay circuit input is coupled to the buffer output. The IC also includes a tristate circuit coupled to the first delay circuit output and to the second delay circuit output. The tristate circuit having a tristate circuit output coupled to the control input.
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
In examples, a device (300) comprises an optical waveguide (326) and first and second ports (330, 334) on the optical waveguide, the second port larger than the first port. The device also comprises a first set of lenses (316) optically coupled to the first port and a second set of lenses (336) optically coupled to the second port.
A circuit (100) for testing a DUT (104) (device under test) includes an inductor (112) coupled to a first switch (140), and the first switch (140) is coupled to a second switch (148). The circuit (100) includes a test module (108) coupled to the first switch (140) and the second switch (148). The test module (108) includes a DUT (104). The circuit (100) also includes a TVS (146) (transient voltage suppressor) coupled to the second switch (148).
H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage
An electronic device includes: opposite first and second sides; opposite third and fourth sides; a molded package structure; a semiconductor die having a backside metal structure exposed outside the molded package structure along the second side; and conductive metal first leads along the third and fourth sides, each one of the first leads having a first portion and a second portion, the first portion having a side exposed outside the molded package structure along the first side, and the second portion enclosed by the molded package structure and spaced apart from the first side by a non-zero distance.
An integrated circuit (IC) including a capacitive HV isolation component and a method of fabrication thereof is disclosed. A SiN bilayer is disposed directly underneath a top electrode of the HV isolation component, where the SiN bilayer includes a top layer with a first RI formed over an underlying SiN layer having a second RI that is greater than the first RI.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
A method of fabricating an electronic device includes attaching a first side of a tape to a first side of a wafer and etching an opposite second side of the tape using a laser. The method includes planarizing an opposite second side of the wafer with the first side of the wafer attached to the first side of the tape, and separating a semiconductor die from the wafer after grinding the second side of the wafer.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
B23K 26/40 - Removing material taking account of the properties of the material involved
A circuit includes: multi-bit analog-to-digital conversion circuitry; an interpolation circuit; a filter; and a digital delta-sigma modulator. The multi-bit analog-to-digital conversion circuitry has a first terminal and a second terminal. The interpolation circuit has a first terminal and a second terminal. The first terminal of the interpolation circuit is coupled to the second terminal of the multi-bit analog-to-digital conversion circuitry. The filter has a first terminal and a second terminal. The first terminal of the filter is coupled to the second terminal of the interpolation circuit. The digital delta-sigma modulator has a first terminal and a second terminal. The first terminal of the digital delta-sigma modulator is coupled to the second terminal of the filter.
Analog-to-digital converter (ADC) circuitry including a delay domain ADC that outputs converted analog input data along with a delay domain clock. A clock delay driver outputs a digital domain clock, an early clock leading the digital domain clock signal, and a late clock lagging the digital domain clock. An output latch latches the ADC output by the digital domain clock signal. The circuitry includes a timing error detection circuit with inputs receiving the delay domain clock, the early clock, and the late clock. The timing error detection circuit outputs early and late fail flags responsive to detecting timing errors of the digital domain clock relative to the early and late clocks, respectively. Timing loop circuitry has an input coupled to the error flag output of the timing error detection circuitry, and an output coupled to a control input of the clock delay driver.
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
In an example, a circuit includes clock data recovery (CDR) circuitry having an input and an output. The circuit also includes a delay circuit having an input coupled to the output of the CDR circuitry, and having an output. The circuit includes a multi-phase oscillator having an input coupled to the output of the delay circuit, and having an output. The circuit also includes a divider having an input coupled to the output of the multi-phase oscillator, and having an output coupled to the input of the CDR circuitry.
H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
24.
METHODS AND APPARATUS TO DETERMINE A FREQUENCY OF A SIGNAL
An example apparatus includes: comparison circuitry configured to determine first and second frequencies from a plurality of clock count ranges and a clock count value, the plurality of clock count ranges each having a range of possible count values corresponding to possible frequencies, the first and second frequencies correspond to the clock count ranges that include the clock count value; comparator circuitry configured to generate a temperature indication based on a comparison of a temperature voltage to a reference temperature voltage; and overlap determination circuitry configured to select one of the first or second frequencies based on the comparator circuitry.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
G06F 1/08 - Clock generators with changeable or programmable clock frequency
An example apparatus includes: current driver circuitry configured to supply power to a stepper motor; and controller circuitry coupled to the current driver circuitry, the controller circuitry configured to: determine a first duty cycle of power transferred to the stepper motor by the current driver circuitry during a first operation of the stepper motor, the first operation to supply power using currents of a target magnitude; determine an previous duty cycle of power transferred to the stepper motor by the current driver circuitry during a second operation of the stepper motor, the second operation of the stepper motor to supply power using currents of the target magnitude; and determine changes in a mechanical load applied to the stepper motor responsive to a comparison of the first duty cycle to the previous duty cycle.
A described example includes: a package substrate including a mounting pad, at least one die pad, a first set of conductive leads, and a second set of conductive leads spaced from the first set of conductive leads; a semiconductor die mounted to the at least one die pad with a first die attach material; a laminate transformer with integral magnetic material mounted on the mounting pad with a second die attach material; first electrical connections of wire bonds or ribbon bonds between the bond pads of the semiconductor die and the first set of conductive leads; second electrical connections of wire bonds or ribbon bonds between the bond pads of the semiconductor die and the laminate transformer with integral magnetic material; and mold compound covering the electrical connections, the semiconductor die, the laminate transformer with integral magnetic material and portions of the package substrate.
A circuit for testing a DUT (device under test) includes an inductor coupled to a first switch, and the first switch is coupled to a second switch. The circuit includes a test module coupled to the first switch and the second switch. The test module includes a DUT. The circuit also includes a TVS (transient voltage suppressor) coupled to the second switch.
An example apparatus includes a first die having a first terminal. The apparatus includes a second die having a second terminal. The apparatus includes an isolation channel coupled between the first terminal of the first die and the second terminal of the second die. The apparatus includes control circuitry disposed on the first die, the control circuitry to cause transmission of a power signal over the isolation channel and at least one of cause transmission of a control data signal over the isolation channel or detect a feedback data signal over the isolation channel. Other examples are described.
A motor controller that is operable to control a motor includes drive current generation circuitry having an output coupled to the motor. The motor controller further includes a velocity control path. The velocity control path includes angular velocity estimation circuitry having an input adapted to be coupled to the motor, a velocity comparator having first input coupled to a target velocity input and a second input coupled to an output of the angular velocity estimation circuitry, and an adaptive velocity controller having a first input coupled to an output of the velocity comparator and having an output coupled to a first input of the drive current generation circuitry. The motor controller further includes controller parameter determination circuitry having a first input coupled to the output of the angular velocity estimation circuitry and having an output coupled to a second input of the adaptive velocity controller.
An apparatus includes a modulation control circuit and a modulated signal generation circuit. The modulation control circuit has a control output, the modulation control circuit configured to provide, at the control output, a control signal indicative of a frequency adjustment rate of a modulated signal. The modulated signal generation circuit has a control input and an output, the control input coupled to the control output, the modulated signal generation circuit configured to provide the modulated signal at the output and adjust a modulation frequency of the modulated signal at the modulation frequency adjust rate responsive to the control signal.
Described examples include an integrated circuit having a transistor with a first gate on a first gate insulating layer. The transistor also has second gate separated from the first gate by a gate gap. The integrated circuit also includes a channel well at the gate gap extending under the first gate and the second gate. The transistor has a first source in the channel adjacent to an edge of the first gate. The transistor having a second source formed in the channel adjacent to an edge of the second gate separated from the first source by a channel gap. The transistor has at least one back-gate contact, the at least one back-gate contact separated from the first gate by a first back-gate contact gap and separated from the second gate by a second back-gate contact gap.
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/62 - Electrodes ohmically coupled to a semiconductor
A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.
G06F 12/0817 - Cache consistency protocols using directory methods
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/084 - Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
G06F 12/0846 - Cache with multiple tag or data arrays being simultaneously accessible
G06F 12/0855 - Overlapped cache accessing, e.g. pipeline
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
H03M 13/01 - Coding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
An apparatus comprises: a first oscillator circuit having a first terminal and a second terminal; a second oscillator circuit having a third terminal and a fourth terminal; a first circuit having a first positive input, a first negative input, a first positive output, and a first negative output, the first positive input coupled to the first terminal, the first negative input coupled to the second terminal, the first positive output coupled to the third terminal, and the first negative output coupled to the fourth terminal; and a second circuit having a second positive input, a second negative input, a second positive output, and a second negative output, the second positive input coupled to the fourth terminal, the second negative input coupled to the third terminal, the second positive output coupled to the first terminal, and the second negative output coupled to the second terminal.
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
34.
DETECTION OF DISPLAYPORT ALTERNATE MODE COMMUNICATION AND CONNECTOR PLUG ORIENTATION WITHOUT USE OF A POWER DISTRIBUTION CONTROLLER
This disclosure generally relates to USB TYPE-C, and, in particular, DISPLAYPORT Alternate Mode communication in a USB TYPE-C environment. In one embodiment, a device determines a DISPLAYPORT mode and determines an orientation of a USB TYPE-C connector plug. A multiplexer multiplexes a DISPLAYPORT transmission based in part on the determined orientation of the USB TYPE-C connector plug.
A system (100) includes: a power stage (106) having a first terminal (108), a second terminal (110), a third terminal ( 112), and a fourth terminal (114); and a controller (148) having a first terminal ( 149), a second terminal (150), a third terminal (151), a fourth terminal (152), and a fifth terminal (153). The first terminal (149) of the controller (148) is coupled to the fourth terminal (114) of the power stage (106). The second terminal (150) of the controller (148) is coupled to the third terminal (112) of the power stage (106). The third terminal (151) of the controller (148) is coupled to the first terminal (108) of the power stage (106). The fourth terminal (152) of the controller (148) is coupled to the second terminal (110) of the controller (106). The controller (106) includes an adaptive slope compensation circuit (168) configured to: obtain input parameters (IN_P); adjust a scaling factor responsive to the input parameters (IN_P); adapt a slope compensation current responsive to the scaling factor; and output a slope compensation signal (I ASC) responsive to the adapted slope compensation current.
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
A semiconductor device (3600, 4300) includes a semiconductor substrate (102), a pedestal dielectric layer (202b), a collector layer (902), a base layer (1102), and an emitter layer (1602). The semiconductor substrate (102) includes a bipolar junction transistor region (104). The pedestal dielectric layer (202b) is in the bipolar junction transistor region (104) and is over an upper surface (120) of the semiconductor substrate (102). The collector layer (902) is on the upper surface (120) of the semiconductor substrate (102) and is through the pedestal dielectric layer (202b). The base layer (1102) is on the collector layer (902) and an upper surface (120) of the pedestal dielectric layer (202b). The pedestal dielectric layer (202b) extends laterally over the upper surface (120) of the semiconductor substrate (102) from the base layer (1102). The emitter layer (1602) is on the base layer (1102).
H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs
A circuit (200) includes first, second, third, and fourth transistors (202, 204, 206, 208), and a capacitor (214). The first transistor (202) has a first terminal, a second terminal, and a control terminal. The second transistor (204) has a first terminal, second terminal, and a control terminal. The capacitor (214) has a first conductor coupled to the second terminal of the first transistor, and a second conductor coupled to the second terminal of the second transistor. The third transistor (206) has a first terminal coupled to the first terminal of the second transistor (204), a second terminal, and a control terminal coupled to the control terminal of the first transistor (202). The fourth transistor (208) has a first terminal coupled to the first terminal of the first transistor (202), a second terminal coupled to the second terminal of the third transistor (208), and a control terminal coupled to the control terminal of the second transistor (204).
In examples, a device comprises an optical waveguide and first and second ports on the optical waveguide, the second port larger than the first port. The device also comprises a first set of lenses optically coupled to the first port and a second set of lenses optically coupled to the second port.
System and methods are provided. An example system includes multiple peripherals including a first peripheral and a second peripheral, in which the first peripheral is associated with a first channel and a second channel; and a credential allocator circuit to generate a unique identification value for each of the first channel, the second channel and the second peripheral. The system further includes mapping circuitry to map a first function of the system to the first channel, map a second function of the system to the second channel, and map a third function of the system to the second peripheral; map each identification value generated by the credential allocator circuit to a corresponding function value and a corresponding traffic class value; and map each identification value generated by the credential allocator circuit to a corresponding address space value. A firewall of the system is initialized to recognize the identification values generated by the credential allocator circuit.
A controller area network including one or more first network nodes biased from a first power supply voltage, and a second network node biased from a second, lower, power supply voltage. The second network node includes a transmitter driving a differential voltage onto bus lines to communicate a dominant bus state at a second dominant state common mode voltage, a receiver coupled to the bus lines, sense circuitry to sense a common mode voltage at the bus lines, and control circuitry to control a recessive state common mode voltage in response to the sensed dominant state common mode voltage.
H04B 1/405 - Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency with multiple discrete channels
An example apparatus includes: bandwidth estimator circuitry configured to: obtain a first memory transaction; and determine a consumed bandwidth associated with the memory transaction; and gate circuitry configured to: permit transmission of the memory transaction to a memory controller circuitry; determine whether to gate a second memory transaction generated by a source of the first memory transaction based on the consumed bandwidth of the first memory transaction; and when it is determined to gate the second memory transaction, prevent transmission of the second memory transaction for an amount of time based on the consumed bandwidth.
Radar systems, devices, methods, and non-transitory mediums storing instructions for causing execution of radar signal processing operations are provided. Multiple chirps are transmitted, in which each chirp includes a first chirp segment having a first bandwidth spanning a first frequency range and a second chirp segment having a second bandwidth spanning a second, different, frequency range. For each chirp, the second chirp segment is transmitted a specific time after the first chirp segment. The chirps are sampled to generate first and second sets of sampled data corresponding to the first chirp segments and second chirp segments, respectively. After processing the sets of sampled data individually to obtain first and second frequency representations, respectively, phase compensation is applied to the second frequency representation, the result of which is then combined with the first frequency representation to obtain a set of aggregate data, on which a transform is performed to generate range and velocity data.
In an example, a method includes storing code for a first central processing unit (CPU) executing a first application in a first region of a memory, and storing code for a second CPU executing a second application in a second region of the memory. The method includes storing shared code for the first CPU and the second CPU in a third region of the memory. The method includes storing read-write data for the first CPU in a fourth region of the memory and storing read-write data for the second CPU in a fifth region of the memory. The method includes translating a first address from a first unique address space for the first CPU to a shared address space in the third region, and translating a second address from a second unique address space for the second CPU to the shared address space in the third region.
A method for automatic generation of calibration parameters for a surround view (SV) camera system is provided that includes capturing a video stream from each camera comprised in the SV camera system, wherein each video stream captures two calibration charts in a field of view of the camera generating the video stream; displaying the video streams in a calibration screen on a display device coupled to the SV camera system, wherein a bounding box is overlaid on each calibration chart, detecting feature points of the calibration charts, displaying the video streams in the calibration screen with the bounding box overlaid on each calibration chart and detected features points overlaid on respective calibration charts, computing calibration parameters based on the feature points and platform dependent parameters comprising data regarding size and placement of the calibration charts, and storing the calibration parameters in the SV camera system.
H04N 17/00 - Diagnosis, testing or measuring for television systems or their details
B60R 1/27 - Real-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles for viewing an area outside the vehicle, e.g. the exterior of the vehicle with a predetermined field of view providing all-round vision, e.g. using omnidirectional cameras
An example apparatus includes an input terminal; an output terminal; a delay circuit including an input terminal and an output terminal, the input terminal coupled of the delay circuit coupled to the input terminal; a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a supply voltage terminal, the second input terminal of the comparator coupled to a reference voltage terminal; and a logic AND gate including a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal of the logic AND gate coupled to the output terminal of the comparator, the second input terminal of the logic AND gate coupled to the output terminal of the delay circuit, the third input terminal of the logic AND gate coupled to the input terminal, and the output terminal of the logic AND gate coupled to the output terminal.
An example semiconductor package comprises a patch antenna formed in a first conductor layer of a multilayer package substrate. The multilayer package substrate comprises conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers. The multilayer package substrate has a board side surface opposite a device side surface. The semiconductor package further comprises a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the patch antenna. An antenna horn is mounted to the device side surface and aligned with the patch antenna using a mounting structure. The semiconductor package further comprises a reflector formed on a second conductor layer in the multilayer package substrate. The second conductor layer is positioned closer to the board side surface of the multilayer package substrate compared to the patch antenna.
H01Q 19/10 - Combinations of primary active antenna elements and units with secondary devices, e.g. with quasi-optical devices, for giving the antenna a desired directional characteristic using reflecting surfaces
47.
MULTI-LEVEL MICROELECTROMECHANICAL SYSTEM STRUCTURE WITH NON-PHOTODEFINABLE ORGANIC POLYMER SPACER LAYERS
In an example, a MEMS device includes an anti-reflective coating layer formed on a substrate of the MEMS device. The device includes a hinge formed on the substrate, where an edge of the hinge on the substrate is aligned with an edge of the anti-reflective coating layer. The device includes a mirror coupled to the hinge.
A reference signal generation circuit includes a voltage-to-current (V2I) converter having a terminal. A first current mirror has a first terminal and a second terminal. The first terminal is coupled to the terminal of the V2I converter. A second current mirror has a first terminal, a second terminal, and a third terminal. The first terminal of the second current mirror is coupled to the second terminal of the first current mirror. A third current mirror has a first terminal coupled to the second terminal of the first current mirror. The third current mirror is coupled to the third terminal of the second current mirror.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
49.
MICROELECTRONIC PACKAGE WITH RAISED CONNECTOR FOR EXTERNAL COMPONENT
A semiconductor package is configured for electrically connecting an external component to a top surface of the semiconductor package. The semiconductor package includes a raised connector that extends from a lead frame portion, vertically through encapsulation material, and is exposed at the top surface. A semiconductor component is electrically connected to the lead frame portion. The raised connector includes a vertical column and a horizontal pad, contiguous with each other. The raised connector has a continuous core, which is electrically conductive, extending throughout the vertical column and throughout the horizontal pad. The vertical column is attached to the lead frame portion. A top surface of the horizontal pad is exposed at a top surface of the encapsulation material. The raised connector may include two or more vertical columns. The semiconductor package may include two or more raised connectors, each attached to the lead frame portion.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
50.
PRETAP EQUALIZABLE CONTINUOUS TIME LINEAR EQUALIZER
A circuit includes first, second, third, and fourth transistors, and a capacitor. The first transistor has a first terminal, a second terminal, and a control terminal. The second transistor has a first terminal, second terminal, and a control terminal. The capacitor has a first conductor coupled to the second terminal of the first transistor, and a second conductor coupled to the second terminal of the second transistor. The third transistor has a first terminal coupled to the first terminal of the second transistor, a second terminal, and a control terminal coupled to the control terminal of the first transistor. The fourth transistor has a first terminal coupled to the first terminal of the first transistor, a second terminal coupled to the second terminal of the third transistor, and a control terminal coupled to the control terminal of the second transistor.
In one example, a method includes forming in a process chamber a first oxide film on a first metallic layer, forming in the process chamber a nitride film on the first oxide film, and forming in the process chamber a second oxide film on the nitride film. Forming the nitride film includes performing a process loop N number of times. The process loop includes depositing a nitride layer and performing an in-situ treatment of the nitride layer. N is a real number greater than one. The nitride film includes N nitride layers as a result of performing the process loop N number of times.
C23C 16/02 - Pretreatment of the material to be coated
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
Embodiments disclosed herein relate to antenna switching in radar applications. In an example, a system including a first antenna sub-circuit, a second antenna sub-circuit, and a receiver sub-circuit is provided. The first antenna sub-circuit is configured to couple to a first antenna and includes a first balun, a first transistor, and a first low-noise amplifier. The second antenna sub-circuit is configured to couple to a second antenna and includes a second balun, a second transistor, and a second low-noise amplifier. The receiver sub-circuit includes a transformer having a first set of terminals coupled to the first and second low-noise amplifiers and a second set of terminals coupled to a mixer, the mixer, a first amplifier, a second amplifier, and an analog-to-digital converter. The receiver sub-circuit is configured to receive a signal from either the first or second antenna sub-circuit based on a state of the first and second transistors.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
In an example, a system includes a pipelined analog-to-digital converter (ADC) having a main path and an auxiliary path. The main path includes a first stage having a sampling switch, a flash ADC having an input coupled to the sampling switch, a digital-to-analog converter (DAC) having an input coupled to an output of the flash ADC, and a first amplifier having an input coupled to an output of the DAC and the sampling switch. The main path includes a second stage coupled to the first stage and an input of a second amplifier. The main path also includes a backend ADC having an input coupled to an output of the second amplifier. The auxiliary path includes a plurality of metastability comparators coupled to the flash ADC.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H03M 1/16 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
54.
INTEGRATED CIRCUIT WITH SILICIDE FORMATION BLOCKING
A method of forming an integrated circuit by forming a first silicon surface, forming a second silicon surface, forming a first silicide blocking layer along the first silicon surface and along the second silicon surface, and forming a second silicide blocking layer along the first silicide blocking layer. The forming of each of the first silicide blocking layer and the second silicide blocking layer includes forming a plasma enhanced chemical vapor deposition (PECVD) layer and exposing the PECVD layer to a noble gas for a time duration. Thereafter, the method removes a portion of the second silicide blocking layer and an underlying portion of the first silicide blocking layer to expose the first silicon surface while leaving at least the first silicide blocking layer over the second silicon surface and silicides the first silicon surface.
An example apparatus includes: comparison circuitry (250) configured to determine first and second frequencies from a plurality of clock count ranges and a clock count value, the plurality of clock count ranges each having a range of possible count values corresponding to possible frequencies, the first and second frequencies correspond to the clock count ranges that include the clock count value; comparator circuitry (135) configured to generate a temperature indication based on a comparison of a temperature voltage to a reference temperature voltage; and overlap determination circuitry (255) configured to select one of the first or second frequencies based on the comparator circuitry.
H03L 7/097 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a comparator for comparing the voltages obtained from two frequency to voltage converters
H03L 1/02 - Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
56.
METASTABILITY ERROR DETECTION AND BER IMPROVEMENT TECHNIQUE IN PIPELINED ADCS
In an example, a system (100) includes a pipelined analog-to-digital converter (ADC) having a main path (120) and an auxiliary path (122). The main path (120) includes a first stage (102) having a sampling switch (110), a flash ADC (112) having an input coupled to the sampling switch (110), a digital -to-analog converter (DAC) (114) having an input coupled to an output of the flash ADC (112), and a first amplifier (118) having an input coupled to an output of the DAC (114) and the sampling switch (110). The main path (120) includes a second stage (104) coupled to the first stage (102) and an input of a second amplifier. The main path (120) also includes a backend ADC (106) having an input coupled to an output of the second amplifier. The auxiliary (122) path includes a plurality of metastability comparators (124) coupled to the flash ADC (112).
H03M 1/16 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
57.
FLASH MEMORY INCLUDING SELF-ALIGNED FLOATING GATES
An integrated circuit (IC) (300) including Flash memory cells with self-aligned floating gates (306) and a method of fabrication thereof is disclosed. A floating gate (FG) layer of polysilicon (306) is deposited and patterned to form FG structures (306) as part of a masking block used in forming isolation trenches (322). A dielectric fill material (326) fills the isolation trenches (322). Subsequently, the dielectric fill material (326) is removed using a CMP process that is configured to stop on the polysilicon of the FG structures (306).
Some aspects relate to a circuit (100) comprising a temperature-dependent circuit (106), a proportional to absolute temperature (PTAT) current sink (110), a complementary to absolute temperature current source (CTAT) current source (108), and a heating element (104). The temperature-dependent circuit (106) is disposed within an integrated circuit package. The PTAT current sink (110) is disposed within the integrated circuit package and has an output terminal. The CTAT current source (108) is disposed within the integrated circuit package and has an output terminal coupled to the output terminal of the PTAT current sink (110). The heating element (104) is disposed within the integrated circuit package and has a control terminal coupled to the output terminal of the PTAT current sink (110) and the output terminal of the CTAT current source (108).
G05F 3/24 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations wherein the transistors are of the field-effect type only
The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, a pedestal dielectric layer, a collector layer, a base layer, and an emitter layer. The semiconductor substrate includes a bipolar junction transistor region. The pedestal dielectric layer is in the bipolar junction transistor region and is over an upper surface of the semiconductor substrate. The collector layer is on the upper surface of the semiconductor substrate and is through the pedestal dielectric layer. The base layer is on the collector layer and an upper surface of the pedestal dielectric layer. The pedestal dielectric layer extends laterally over the upper surface of the semiconductor substrate from the base layer. The emitter layer is on the base layer.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A method of forming at least one of a nitride or oxide layer for an integrated circuit, the method comprising: (i) positioning a semiconductor wafer in a processing chamber, the semiconductor wafer including a wafer front side and the processing chamber including differential surfaces adapted to be coupled to a plasma-igniting external radio frequency source; (ii) depositing one of a nitride or oxide on at least an exposed portion of either the semiconductor wafer or a layer affixed relative to the wafer front side by reacting at least two precursor gases for a selected one of the nitride or oxide layer in the chamber while the plasma igniting external radio frequency source is enabled; and (iii) post-treating the one of a nitride or oxide with the plasma igniting external radio frequency source enabled and with exposure to helium and nitrogen in the absence of at least one of the at least two precursor gases.
A processor includes a plurality of execution units. At least one of the execution units is configured to determine, based on a field of a first instruction, a number of additional instructions to execute in conjunction with the first instruction and prior to execution of the first instruction
Various disclosed embodiments relate to defective pixel detection and optimizing memory storage while carrying out defective pixel detection. An example, system for detecting defective pixels includes a memory to store threshold functions; and a defective pixel detector to apply, for each image pixel received, a select threshold function of the threshold functions to values of nearest-neighbor image pixels to obtain a threshold value; and determine, for each image pixel received, whether the image pixel is defective based on a comparison of a value of the image pixel to the threshold value. A statistics generator receives each image pixel that is determined to be defective; and determines a number of defective image pixels in a specified unit of image pixels and a location of each defective image pixel in the specified unit.
A method for time multiplexing subframes on a serving cell to a user equipment, wherein one set of subframes operate with the legacy LTE transmission format and one set of subframes operate with an evolved transmission format comprising reduced density CRS transmission without a PDCCH control region.
An IC includes first-third power rails over a semiconductor substrate. The first rail has a first polarity different from the second and third rails. The IC includes multiple first cells on the semiconductor substrate in first and second rows. The first row is separated from the second row by the first power rail. Each first cell includes a first height and a first structure having at least one transistor. For each first cell in the first row, the first structure is entirely between the first and second rails. Further, for each first cell in the second row, the first structure is between the first and third rails. The IC includes an extension cell arranged on the semiconductor substrate in the first row. The extension cell includes a second structure having at least one transistor. A portion of the second structure extends into the second row.
A system includes: a power stage having a first terminal, a second terminal, a third terminal, and a fourth terminal; and a controller having a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of the controller is coupled to the fourth terminal of the power stage. The second terminal of the controller is coupled to the third terminal of the power stage. The third terminal of the controller is coupled to the first terminal of the power stage. The fourth terminal of the controller is coupled to the second terminal of the controller. The controller includes an adaptive slope compensation circuit configured to: obtain input parameters; adjust a scaling factor responsive to the input parameters; adapt a slope compensation current responsive to the scaling factor; and output a slope compensation signal responsive to the adapted slope compensation current.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Various embodiments of the present disclosure relate to pruning the data of a neural network, and in particular, to removing the unnecessary weights from the various channels of the neural network. In one example embodiment, a technique for pruning the weights of a neural network is provided. The technique first includes identifying weights to prune from a channel of the neural network based on a sparsity target and a weight threshold. Once identified, the technique includes determining a pruning factor for pruning the identified weights based on a current training epoch, an initial training epoch, a final training epoch, and a desired pruning pace. Next, the technique includes, over multiple training epochs, reducing each of the identified weights by multiplying the identified weights by the pruning factor. Finally, the technique includes removing the identified weights from the channel that have been reduced to below a threshold value.
A high frequency wireless device includes a three-dimensional (3D) antenna structure mounted on a PCB including a first antenna connected to a first waveguide feed and second antenna connected to a second waveguide feed. A packaged device on the PCB has a top metal surface including a transmit (Tx) radiating structure under the second waveguide feed and a receive (Rx) radiating structure under the first waveguide feed, and an RF connection from the top metal surface to its bottom surface. An IC die is flipchip attached to the bottom surface including at least one Rx channel and at least one Tx channel connected by the RF connection to the Rx and Tx radiating structures. Protruding metal features are on the dielectric layer under the first and second waveguide feeds on ≥2 sides of the Tx and the Rx radiating structure to create a waveguiding wall structure for directing signals.
An IC is coupled to a power stage having a first half bridge having first and second transistors and a second half bridge having third and fourth transistors. A controller has a first control output to provide first-fourth control signals to the first-fourth transistors. The controller asserts the first-fourth control signals to implement a state sequence. The state sequence includes a first state in which the first and fourth transistors are ON, a second state in which the first and third transistors are ON, a third state in which the second and fourth transistors are ON, and a fourth state in which the second and third transistors are ON. During each switching cycle, the controller implements the first and fourth states with one of the second or third states implemented between the first and fourth states, with every n switching cycles alternating implementation of the second or third states.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
69.
GROUP III-V IC WITH DIFFERENT SHEET RESISTANCE 2-DEG RESISTORS
An integrated circuit (IC) includes a lower group III-N layer having a first composition over a substrate, and an upper group III-N layer having a different second composition over the lower group III-N layer. A gate electrode of a High Electron Mobility Transistor (HEMT) is located over the upper group III-N layer. First and second resistor contacts make a conductive connection to the lower group III-N layer. An unbiased group III-N cover layer is located on the upper group III-N layer in a resistor area including a high Rs 2-DEG resistor, where the unbiased group III-N cover layer is positioned between the first and second contacts.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 1/47 - Resistors having no potential barriers
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
In a described example, a circuit includes a plurality of line switches, each having a line input terminal, a line terminal and a line control terminal. Each of the line input terminals is coupled to a light emitting diode (LED) voltage terminal and each line terminal is coupled to a respective LED line terminal of a plurality of LED line terminals. A discharge circuit has a plurality of discharge inputs, in which each discharge input is a coupled to a respective line terminal. The discharge circuit includes a plurality of discharge switches, each having a discharge input terminal, a discharge output terminal and a discharge control terminal, in which each discharge input terminal is coupled to a respective LED line terminal. The discharge circuit also includes a current sink circuit coupled between each discharge output terminal and a ground terminal.
H05B 45/59 - Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDsCircuit arrangements for operating light-emitting diodes [LED] responsive to LED lifeProtective circuits for reducing or suppressing flicker or glow effects
H05B 45/44 - Details of LED load circuits with an active control inside an LED matrix
71.
FLASH MEMORY INCLUDING SELF-ALIGNED FLOATING GATES
An integrated circuit (IC) including Flash memory cells with self-aligned floating gates and a method of fabrication thereof is disclosed. A floating gate (FG) layer of polysilicon is deposited and patterned to form FG structures as part of a masking block used in forming isolation trenches. A dielectric fill material fills the isolation trenches. Subsequently, the dielectric fill material is removed using a CMP process that is configured to stop on the polysilicon of the FG structures.
A circuit includes first, second third, and fourth transistors coupled in series, and a control circuit coupled to the first, second, third, and fourth transistors. The control circuit includes a clock generator, a current sense circuit, and a zero current differentiation zone (ZC_DF) circuit. The clock generator is configured to generate first and second clocks. The second clock is in quadrature with the first clock. The current sense circuit is configured to sense a current flowing through the first transistor. The ZC_DF circuit is configured to define a ZC_DF interval starting at an edge of the second clock and ending at turn-on of the fourth transistor. The control circuit is configured to operate the first, second, third, and fourth transistors in a discontinuous conduction mode (DCM), and, in DCM, turn off the first transistor during the ZC_DF interval responsive to the current flowing through the first transistor being negative.
An electronic device includes a semiconductor die attached to a lead frame or substrate, conductive first and second metal clips attached to the lead frame or substrate, a molded package structure that encloses the semiconductor die and has a top side with first and second recesses that extend into the molded package structure to top sides of the respective first and second metal clips, and an electronic component having conductive metal first and second terminals that extend into the respective first and second recesses and are electrically connected to the top sides of the respective first and second metal clips.
An example apparatus includes a counter, an analog-to-digital converter, communication circuitry, and control circuitry configurable. The example analog-to-digital converter is configurable to sample a first voltage at a first node on a bus. The example communication circuitry is configurable to set a second node on the bus to a second voltage. Additionally, the example control circuitry is configurable to increment the counter when the first voltage does not satisfy a threshold value and, when the first voltage satisfies the threshold value, assign an address for the device based on a value of the counter.
In described examples, an integrated circuit includes a first pin, a second pin, a processor, a bus monitor, a clock circuit, and a transceiver. The processor provides to the transceiver and the bus monitor an instruction that indicates an instructed target address, a read/write flag, and a memory address. The transceiver provides to the first pin and the bus monitor a clock signal, and provides to the second pin and the bus monitor a message so that the message includes a messaged target address, the read/write flag, and the memory address. The bus monitor compares the instructed target address to the messaged target address, and provides a signal to the processor in response to the comparison.
A method comprises creating an electronic circuit design having a plurality of electronic components, defining a fault condition imposable during a simulation of the electronic circuit design, and generating a simulation model based on the electronic circuit design. The method also comprises generating a simulation fault model representing the fault condition and executing a simulation of the simulation model to simulate operation of the electronic circuit design. During the execution of the simulation, the method comprises controlling the simulation fault model to begin an imposition of the fault condition within the simulation model, simulating circuit behavior of the simulation model in response to the imposition of the fault condition, controlling the simulation fault model to cease the imposition of the fault condition within the simulation model, and simulating circuit behavior of the simulation model in response to the cessation of the imposition of the fault condition.
G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
77.
METHODS AND APPARATUS TO PROVIDE REGISTER INFORMATION OF SEMICONDUCTOR CHIPS
An example apparatus includes: accessing, by storage interface circuitry, chip information, the chip information corresponding to a semiconductor chip; removing, by at least one processor circuit, redundant information from the chip information to generate deduplicated chip information; classifying, by the at least one processor circuit, the deduplicated chip information into first classified chip information and second classified chip information, the first classified chip information corresponding to a first access permission, the second classified chip information corresponding to a second access permission; and causing, by the at least one processor circuit, storing (block 808) of the first classified chip information in a first classified file in memory and the second classified chip information in a second classified file in the memory.
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
78.
INTEGRATED CIRCUIT WITH MULTI-APPLICATION IMAGE PROCESSING
In described examples, an integrated circuit includes first, second, third, and fourth image processing blocks, a data selection circuitry, and a pipeline memory. An input of the first image processing block receives raw image data. An input of the second image processing block is coupled to an output of the first image processing block. An input of the third image processing block is coupled to an output of the second image processing block. A first input of the data selection circuitry is coupled to an output of the first image processing block, and a second input of the data selection circuitry is coupled to an output of the second image processing block. A data input of the pipeline memory is coupled to an output of the data selection circuitry, and an output of the pipeline memory is coupled to an input of the fourth image processing block.
H04N 23/81 - Camera processing pipelinesComponents thereof for suppressing or minimising disturbance in the image signal generation
H04N 23/84 - Camera processing pipelinesComponents thereof for processing colour signals
H04N 23/88 - Camera processing pipelinesComponents thereof for processing colour signals for colour balance, e.g. white-balance circuits or colour temperature control
79.
Method and System for Compression of Radar Signals
A radar system is provided that includes a compression component configured to compress blocks of range values to generate compressed blocks of range values, and a radar data memory configured to store compressed blocks of range values generated by the compression component. In an example, the compression component parameter determination engine to determine a compression parameter for a type of compression to yield a compressed output of the block of range values that is less than or equal to a specified size. The compression parameter may be a scale factor, or may be a Golomb parameter and a scale factor, depending on the type of compression. The compression component further includes an encoder to compress, using the type of compression, the block of range values to generate a compressed block of range values based on the compression parameter.
G01S 13/18 - Systems for measuring distance only using transmission of interrupted, pulse modulated waves wherein range gates are used
G01S 13/34 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
G01S 13/58 - Velocity or trajectory determination systemsSense-of-movement determination systems
G01S 13/931 - Radar or analogous systems, specially adapted for specific applications for anti-collision purposes of land vehicles
H03M 7/40 - Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
A Bluetooth (BT) device includes a host processor and a BT controller coupled by a Host Controller Interface (HCI) including a Host Controller Transport Layer and a HCI Driver. The host processor implements an applications layer and includes HCI firmware for communicating via the Host Controller Transport Layer with the BT controller. The BT controller includes a processor coupled to a memory and to a transceiver, and a RF driver. The HCI firmware also includes HCI command code for a user to define a topology of the BT network including configuring the BT device in a current chain including a plurality of BT devices including configuring from which BT device it receives data from and which BT device it forwards data to. For communicating data across the BT network the BT device forwards the data without host processor involvement in at least resending the data back to its BT controller.
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
A microelectronic device includes a resistive differential alignment monitor (RDAM), including a first variable-width resistor and a second variable-width resistor, which are members of a conductor level. Each of the resistors include a wide portion and a narrow portion. The RDAM further includes a vertical connector to each of the wide portion and the narrow portion of the first variable-width resistor, and to the wide portion and the narrow portion of the second variable-width resistor. The vertical connectors are members of a vertical connector level. Test terminals are coupled to the vertical connectors. The vertical connectors to the first variable-width resistor and the vertical connectors to the second variable-width resistor are separated by equal distances and are oriented anti-parallel to each other. The RDAM may be used to estimate a misalignment distance between the members of the vertical connector level and the members of the conductor level.
G01D 5/165 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying resistance by relative movement of a point of contact and a resistive track
H01C 10/46 - Arrangements of fixed resistors with intervening connectors, e.g. taps
A wireless network with network-level channel hopping. A wireless network includes a wireless device. The wireless device includes a receiver, a data channel selector, and a transmitter. The receiver is configured to receive a beacon signal comprising a beacon sequence value. The data channel selector is configured to select, as a pseudorandom function of the beacon sequence value, a data channel on which to transmit in an interval following reception of the beacon signal. The transmitter is configured to transmit on the data channel selected by the channel selector.
A method for encoding video data is provided that includes determining whether or not a parent coding unit of a coding unit of the video data was predicted in intra-prediction block copy (IntraBC) mode and, when it is determined that the parent coding unit was not predicted in IntraBC mode: computing activity of the coding unit, determining an IntraBC coding cost of the coding unit by computing the IntraBC coding cost of the coding unit using a two dimensional (2D) search when the activity of the coding unit is not than an activity threshold, and computing the IntraBC coding cost of the coding unit using a one dimensional (1D) search when the activity of the coding unit is less than the activity threshold, using the IntraBC coding cost to select an encoding mode from one of a plurality of encoding modes, encoding the coding unit using the selected encoding mode.
A network includes at least two nodes that employ a routing protocol to communicate across a network. One of the nodes is a parent node and another of the nodes is a child node of the parent node. An address generator assigns a unique network address to the child node by appending an address value of a number of bits to a parent address of the parent node to create the unique network address for the child node.
Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.
H04N 19/184 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being bits, e.g. of the compressed video stream
H04N 19/60 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
86.
Constraining Slice Header Processing Overhead in Video Coding
A method for encoding a picture of a video sequence in a bit stream that constrains slice header processing overhead is provided. The method includes computing a maximum slice rate for the video sequence, computing a maximum number of slices for the picture based on the maximum slice rate, and encoding the picture wherein a number of slices used to encode the picture is enforced to be no more than the maximum number of slices.
H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
H04N 19/13 - Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
H04N 19/15 - Data rate or code amount at the encoder output by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
H04N 19/157 - Assigned coding mode, i.e. the coding mode being predefined or preselected to be further used for selection of another element or parameter
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/184 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being bits, e.g. of the compressed video stream
H04N 19/463 - Embedding additional information in the video signal during the compression process by compressing encoding parameters before transmission
H04N 19/625 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]
H04N 19/86 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving reduction of coding artifacts, e.g. of blockiness
In examples, a sensor package includes a semiconductor die, a sensor on the semiconductor die, and a ring encircling the sensor. The sensor and an inner surface of the ring are exposed to an exterior environment of the sensor package. The sensor package includes a mold compound covering the semiconductor die and abutting an outer surface of the ring.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.
An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs
Methods, apparatus, systems and articles of manufacture to trim temperature sensors are disclosed. An example method includes: sampling a first value indicative of a temperature of a first die of a multi-chip module (MCM) with a first temperature sensor, the first die including a first transistor having a channel including a first material; and calibrating a second temperature sensor configured to sample a second value indicative of a temperature of a second die including a second transistor have a second channel including a second material, the calibrating based on the first value.
An apparatus includes a counter having a clock input, a count value input, a third input, and an output. A multiplexer has a first input, a second input, a selection input, and an output. A delay circuit has a first input coupled to the clock input of the counter, a second input coupled to the output of the counter, a first output and a second output. The first output is coupled to the first input of the multiplexer, and the second output is coupled to the second input of the multiplexer. A fractional control circuit has a first output coupled to the selection input of the multiplexer and has a second output coupled to the third input of the counter.
A semiconductor device includes a substrate, a semiconductor layer stack on the substrate, and a gate, a source, and a drain formed on or in the semiconductor layer stack. The semiconductor layer stack may include a non-silicon channel layer and a barrier layer on the channel layer. At least one of the substrate or the semiconductor layer stack includes a diode, a first terminal of the diode electrically coupled to the source, and a second terminal of the diode electrically coupled to the drain.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
In examples, a semiconductor package includes a substrate including a build-up film isolation layer and first and second pre-preg layers contacting opposing lateral sides of the build-up film isolation layer, the first pre-preg layer including a first metallization, and the second pre-preg layer including a second metallization not in physical contact with the first metallization. The package also includes solder mask layers on top and bottom surfaces of the substrate, a first semiconductor die coupled to the first metallization, and a second semiconductor die coupled to the second metallization, the first and second semiconductor dies configured to operate in separate voltage domains. The package also includes a mold compound covering the substrate and the first and second semiconductor dies.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
94.
REFERENCE-LESS ELECTRO-THERMAL LOOP WITH WINDOW MONITOR
Some aspects relate to a circuit comprising a temperature-dependent circuit, a proportional to absolute temperature (PTAT) current sink, a complementary to absolute temperature current source (CTAT) current source, and a heating element. The temperature-dependent circuit is disposed within an integrated circuit package. The PTAT current sink is disposed within the integrated circuit package and has an output terminal. The CTAT current source is disposed within the integrated circuit package and has an output terminal coupled to the output terminal of the PTAT current sink. The heating element is disposed within the integrated circuit package and has a control terminal coupled to the output terminal of the PTAT current sink and the output terminal of the CTAT current source.
Described embodiments include a fault monitoring system comprising a fault logic circuit having a fault logic input adaptable to be coupled to sensor inputs, and first and second fault logic outputs. The fault logic circuit compares a plurality of data values provided by respective sensor inputs to respective fault thresholds, and provides respective fault signals at the first fault logic output responsive to a fault event in which a respective data value exceeds its respective fault threshold. A timer has a timer input coupled to the reset output, and a timer output. A data register has a first data register input coupled to the write control output, a second data register input coupled to the timer output, and a data register output. The data register receives fault data that includes an event identifier, a timer value, and a timer expiration indicator.
A network includes an intermediate node to communicate with a child node via a wireless network protocol. An intermediate node synchronizer in the intermediate node facilitates time synchronization with its parent node and with the child node. A child node synchronizer in the child node to facilitates time synchronization with the intermediate node. The intermediate node synchronizer exchanges synchronization data with the child node synchronizer to enable the child node to be time synchronized to the intermediate node before the intermediate node is synchronized to its parent node if the intermediate node has not synchronized to its parent node within a predetermined guard time period established for the child node.
Excessive latencies and power consumption are avoided when a large number of leaf nodes (LNs) contend simultaneously to join a time slotted channel hopping wireless communication network having a root node (RN) interfaced to LNs by one or more intermediate nodes (INs). A first plurality of shared transmit/receive slots (STRSs) is allocated for at least one IN, and a second plurality of STRSs is advertised for use by contending LNs, where the first plurality is larger than the second plurality. When a LN joins, its STRSs are re-defined such that most become shared transmit-only slots (STOSs) and no STRSs remain. The numbers of STRSs allocated to INs may vary inversely with their hop counts from the RN. One or more STOSs may be added for each of one or more INs in response to a predetermined network condition.
Authentication of a networked device with limited computational resources for secure communications over a network. Authentication of the device begins with the supplicant node transmitting a signed digital certificate with its authentication credentials to a proxy node. Upon verifying the certificate, the proxy node then authenticates the supplicant's credentials with an authentication server accessible over the network, acting as a proxy for the supplicant node. Typically, this verification includes decryption according to a public/private key scheme. Upon successful authentication, the authentication server creates a session key for the supplicant node and communicates it to the proxy node. The proxy node encrypts the session key with a symmetric key, and transmits the encrypted session key to the supplicant node which, after decryption, uses the session key for secure communications. In some embodiments, the authentication server encrypts the session key with the symmetric key.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
99.
Temporal Motion Data Candidate Derivation in Video Coding
A method for derivation of a temporal motion data (TMD) candidate for a prediction unit (PU) in video encoding or video decoding is provided. The derived TMD candidate is for inclusion in an inter-prediction candidate list for the PU. The method includes determining a primary TMD position relative to a co-located PU in a co-located largest coding unit (LCU), wherein the co-located PU is a block in a reference picture having a same size, shape, and coordinates as the PU, and selecting at least some motion data of a secondary TMD position as the TMD candidate when the primary TMD position is in a bottom neighboring LCU or in a bottom right neighboring LCU of the co-located LCU, wherein the secondary TMD position is determined relative to the co-located PU.
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/109 - Selection of coding mode or of prediction mode among a plurality of temporal predictive coding modes
H04N 19/167 - Position within a video image, e.g. region of interest [ROI]
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
H04N 19/463 - Embedding additional information in the video signal during the compression process by compressing encoding parameters before transmission
H04N 19/52 - Processing of motion vectors by encoding by predictive encoding
H04N 19/593 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques
A method for decoding an encoded video bit stream in a video decoder is provided that includes determining a scan pattern type for a transform block to be decoded, decoding a column position X and a row position Y of a last non-zero coefficient in the transform block from the encoded video bit stream, selecting a column-row inverse transform order when the scan pattern type is a first type, selecting a row-column inverse transform order when the scan pattern type is a second type, and performing one dimensional (1D) inverse discrete cosine transformation (IDCT) computations according to the selected transform order to inversely transform the transform block to generate a residual block.
G06F 17/14 - Fourier, Walsh or analogous domain transformations
H04N 19/122 - Selection of transform size, e.g. 8x8 or 2x4x8 DCTSelection of sub-band transforms of varying structure or type
H04N 19/134 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/18 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a set of transform coefficients
H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
H04N 19/46 - Embedding additional information in the video signal during the compression process
H04N 19/48 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using compressed domain processing techniques other than decoding, e.g. modification of transform coefficients, variable length coding [VLC] data or run-length data
H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
