A semiconductor device includes a first resistor element. The first resistor element includes a first resistor, and a second resistor electrically connected in series to the first resistor. The first resistor and the second resistor are each made of a first material. One of a temperature coefficient of an electrical resistance value of the first resistor and a temperature coefficient of an electrical resistance value of the second resistor is a positive value. The other of the temperature coefficient of the electrical resistance value of the first resistor and the temperature coefficient of the electrical resistance value of the second resistor is a negative value.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/373 - Cooling facilitated by selection of materials for the device
A semiconductor device includes a variable-resistance memory cell array, a sense amplifier electrically connected to the variable-resistance memory cell array, and a clamp voltage generation circuit electrically connected to the sense amplifier. The sense amplifier includes an amplification unit that amplifies a voltage at a sense node, a first clamp circuit having first and second NMOS transistors whose gate terminals are electrically connected, a second clamp circuit having third and fourth NMOS transistors whose gate terminals are electrically connected, a fifth NMOS transistor electrically connected to the variable-resistance memory cell array, a reference resistor, and a sixth NMOS transistor electrically connected to the reference resistor.
A semiconductor device includes a variable-resistance memory cell array, a sense amplifier electrically connected to the variable-resistance memory cell array, and a clamp voltage generation circuit electrically connected to the sense amplifier. The sense amplifier includes an amplification unit that amplifies a voltage at a sense node, a first clamp circuit having first and second NMOS transistors whose gate terminals are electrically connected, a second clamp circuit having third and fourth NMOS transistors whose gate terminals are electrically connected, a fifth NMOS transistor electrically connected to the variable-resistance memory cell array, a reference resistor, and a sixth NMOS transistor electrically connected to the reference resistor.
The first and third NMOS transistors are connected in series between the sense node and the fifth NMOS transistor, and the second and fourth NMOS transistors are connected in series between the sense node and the sixth NMOS transistor.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
A semiconductor device includes: a first electric-current generator circuit generating a first electric current having a positive temperature coefficient and not having dependency on a first power-supply voltage; a second electric-current generator circuit generating a second electric current having a negative temperature coefficient and not having dependency on the first power-supply voltage; and a third electric-current generator circuit generating a third electric current neither having dependency on the temperature nor the first power-supply voltage, based on the first electric current and the second electric current.
A data transfer device that divides and transfers the transfer target data in a burst manner from a transmission-side device to a reception-side device includes a storage device and a control device that controls the storage device to store one piece of the input transfer target data, controls the storage device so that data transfer is performed at a set burst length as a data length of divided data when the one piece of the data is divided by a division number until a last part of the data is sensed, and when the last part of the data is sensed, controls the storage device to adjust the burst length so that a data length of the data coincides with a total of data lengths of data to be transferred, and to transfer the data at the adjusted burst length.
Improve the reliability of semiconductor device. The protective cell ESD1a comprises a group of MISFETS 1QA constituted by a plurality of n-type MISFETs 1Q, and a pair of MISFET groups 2QA constituted by a plurality of p-type MISFETs 2Q. The group of MISFETs 1QA and the pair of MISFET groups 2QA are electrically connected to the power wiring and the ground wiring, respectively, to electrically short-circuit them. The pair of MISFET groups 2QA outputs a signal to turn on a plurality of MISFETs 10 to each gate electrode of the plurality of MISFETs 1Q. The group of MISFETs 1QA is provided between the pair of MISFET groups 2QA.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A resist pattern having an opening portion that exposes a part of a conductive film located on a gate insulating film is formed on the conductive film. Next, an anisotropic etching treatment is performed using the resist pattern as a mask to selectively remove the conductive film exposed from the resist pattern and to form a gate pattern and a dummy gate pattern from the remaining conductive film. Next, an oblique ion implantation is performed using the resist pattern as a mask to form a p-type body region in a semiconductor substrate.
The method for transporting the semiconductor wafer involves the steps of preparing the non-contact chuck provided with an optical sensor and the semiconductor wafer having a first main surface, positioning the non-contact chuck so that the optical sensor and the first main surface face each other with a predetermined interval therebetween, measuring a first intensity, which is the intensity of a reflected light from the first main surface, by illuminating the first main surface with a light from the optical sensor before bringing the non-contact chuck close to the first main surface, bringing the non-contact chuck close to the first main surface and maintaining the semiconductor wafer in a non-contact state by blowing gas to the first main surface from the non-contact chuck, and disengaging the non-contact chuck from the semiconductor wafer by moving the non-contact chuck away from the first main surface.
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
A debugging system includes first and second semiconductor devices and a log analysis apparatus. Each of the first and second semiconductor devices executes software to generate a trace log, a first execution log, and a second execution log. The first semiconductor device transfers the trace log and the first execution log to the log analysis apparatus. The second semiconductor device transfers the trace log and the second execution log to the log analysis apparatus. The log analysis apparatus identifies the processing order of the first execution log and the second execution log based on time stamps given to the trace logs, the first execution log, and the second execution log transferred from the first and second semiconductor devices, and generates analysis data by combining the first and second execution logs according to the identified processing order. The analysis data is used for analyzing a cause of an error.
A semiconductor device includes: a field plate electrode formed in an inner portion of a trench through a first insulating film, the trench being formed in a semiconductor substrate; and a gate electrode formed over the field plate electrode through a second insulating film. The first insulating film includes a stacked film made of a first oxide film in contact with the semiconductor substrate and a second oxide film in contact with the field plate electrode, and an inclination of an upper surface of the first insulating film changes at a boundary between the first oxide film and the second oxide film.
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
10.
SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SEMICONDUCTOR DEVICE, AND PROGRAM
A Semiconductor device capable of performing efficient signal processing, to provide a control method and a program of the semiconductor device. The semiconductor device includes a first signal processing unit, a second signal processing unit, and a control unit. The control unit includes: a detection unit that detects the process amount of the second process in which the first signal processing unit or the second signal processing unit executes; a prediction unit that predicts the process amount of the second process to be executed next based on the process amount of the detected second process; and a distribution unit that distributes the first process to the first signal processing unit and the second signal processing unit according to the process amount of the predicted second process.
A semiconductor device includes, in a gate finger region, a gate potential trench formed on a main surface side of a semiconductor substrate, predetermined potential trenches formed so as to sandwich the gate potential trench on the main surface side of the semiconductor substrate, a drift region of a first conductivity type formed in a first region between the gate potential trench and the predetermined potential trench, and a well region of a second conductivity type, which is a region above the drift region and formed in a second region on a side of the predetermined potential trench opposite to a side where the gate potential trench is located.
The present invention suppresses an increase in manufacturing cost and reduces switching noise. A field-effect transistor having a gate electrode embedded in a trench in an upper surface of a semiconductor substrate, a source region formed in the semiconductor substrate, and a drain region formed on a lower surface of the semiconductor substrate is provided with a gate wiring formed on the semiconductor substrate and being electrically connected to the gate electrode, a gate pad formed on the semiconductor substrate, a first resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned ON, a second resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned OFF, and a rectifier diode included in the first resistor or the second resistor between the gate pad and the gate wiring.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Enhancing the performance of semiconductor devices by reducing the operating voltage of a ferroelectric memory equipped with a ferroelectric film. On a semiconductor substrate, forming a laminated body including a paraelectric film, which is an insulating film, and the ferroelectric film made of three or more layers of ferroelectric layers to on the insulating film, and forming a metal film and a gate electrode on the ferroelectric film. By discretely placing impurity particles between the ferroelectric layers that are in contact with each other, the crystallinity of the ferroelectric film is enhanced.
A plurality of wirings included in a wiring substrate includes: a plurality of first wirings for propagating a first clock signal and a first chip select signal to first and second memory devices mounted on a front surface; and a plurality of second wirings for propagating a second clock signal and a second chip select signal to third and fourth memory devices mounted on a back surface. The plurality of first wirings is provided in a wiring layer, which is closer to the front surface, of a plurality of wiring layers, and the plurality of second wirings is provided in a wiring layer, which is closer to the back surface, of the wiring layers.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
15.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a ferroelectric memory cell, and the ferroelectric memory cell includes a select transistor and a memory transistor. A gate dielectric film of the select transistor includes a ferroelectric film, and a gate dielectric film of the memory transistor includes a ferroelectric film.
A semiconductor device has: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type differing from the first conductivity type in the first semiconductor layer; a third semiconductor layer of the second conductivity type in the second semiconductor layer and having a higher impurity concentration than the second semiconductor layer; a fourth semiconductor layer of the first conductivity type on the third semiconductor layer; a fifth semiconductor layer of the first conductivity type on the fourth semiconductor layer and having a higher impurity concentration than the fourth semiconductor layer; a sixth semiconductor layer of the second conductivity type in the second semiconductor layer and having a higher impurity concentration than the third semiconductor layer; and a seventh semiconductor layer of the second conductivity type having the same impurity concentration distribution as the third semiconductor layer in a depth direction.
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
According to one embodiment, a semiconductor device includes: a semiconductor substrate having an upper surface and a lower surface; a first conductive layer formed above the semiconductor substrate; and a second conductive layer formed on the upper surface of the first conductive layer, in which, when viewed from above, the second conductive layer is formed in a region inside an end edge of the first conductive layer, the thickness of the second conductive layer is larger than the thickness of the first conductive layer, the thermal conductivity of the second conductive layer is larger than the thermal conductivity of the first conductive layer, and the resistivity of the second conductive layer is smaller than the resistivity of the first conductive layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
A semiconductor device includes a semiconductor substrate, a first semiconductor region formed in the semiconductor substrate, a second semiconductor region surrounding the first semiconductor region in plan view, a first conductive layer formed on the first semiconductor region, a first electrode formed on the first conductive layer, a cathode region connected to the first electrode via the first conductive layer, a second conductive layer in contact with the first semiconductor region, a second electrode formed on the second conductive layer, and a first region disposed between a region in contact with the first conductive layer of the first semiconductor region and the cathode region in a direction along the upper surface of the semiconductor substrate, and the first region is in contact with a lower surface of the second conductive layer. A depth of the first region is greater than a depth of the cathode region.
On a lower layer side of a temperature sensing diode, trenches are periodically formed in a semiconductor substrate. A source field plate is arranged in the trenches via an insulating film. A P type diffusion layer is formed between adjacent trenches. The source field plate and the P type diffusion layer are connected to a source potential.
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
A semiconductor device includes a processor including a first register set and a second register set. In a first period, the processor selects the second register set as an active register set, and executes a first virtual machine by use of second context data. In a second period, the processor selects the first register set as the active register set, and executes a hypervisor by use of first context data. In the second period, the processor performs a processing of saving the second context data and a processing of reading third context data. In a third period, the processor selects the second register set as the active register set, and executes a second virtual machine by use of the third context data.
A semiconductor device with high performance is provided. A semiconductor device according to the present disclosure includes a semiconductor substrate having a plurality of trenches provided along a first direction, a field plate electrode having a plurality of recess portions and a plurality of thinning-out portions which are alternately disposed in the first direction, and being provided in the trench, an oxide film provided on the field plate electrode, and a gate electrode formed on the oxide film and disposed in each of the recess portions. In the adjacent trenches, the gate electrodes are disposed to be shifted in the first direction.
A semiconductor device includes a first terminal, an oscillation circuit that generates a first clock signal and a second clock signal, an AD conversion circuit, a correction circuit that corrects the digital signal obtained by the AD conversion circuit based on a correction data stored in a memory circuit and outputs the digital signal, an averaging circuit, a sampling circuit, a current generation circuit, and a superposition circuit, the correction data is generated based on an output of the sampling circuit when a dispersion current is superposed on a detection current, and is stored in the memory circuit.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
23.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: a semiconductor chip having a source electrode pad and mounted on a die pad via a die bonding material; a wire electrically connected with the source electrode pad of the semiconductor chip; and a sealing body sealing the semiconductor chip and the wire. The wire and the source electrode pad are made of different types of metals to each other. A wire bonding layer made of sintered metal is interposed between the source electrode pad and the wire. The wire is electrically connected with the source electrode pad via the wire bonding layer.
An interrupt reception unit receives an interrupt request. In response to a received interrupt request, an interrupt processing unit performs an interrupt process of a first priority or an interrupt process of a second priority having a lower priority than the first priority. An interrupt suppression control unit controls the number of interrupt processes of the second priority processed by the interrupt processing unit in a cycle time according to a suppression condition. The suppression condition is set on the basis of a cycle in which the interrupt process of the second priority occurs and the total number of the interrupt processes of the second priority occurring within a period corresponding to the cycle.
Since an electrode formed on an insulating film may be separated from the insulating film in a semiconductor device, the present invention makes it possible to prevent the separation of the electrode from the insulating film. A semiconductor device includes a semiconductor substrate, an insulating film, and an electrode. The insulating film is formed on the semiconductor substrate. The electrode is formed on the insulating film. The semiconductor device also includes an anchor member. The anchor member is in contact with the insulating film and the electrode, at an outer peripheral portion of the electrode.
A semiconductor device includes a semiconductor substrate, a first semiconductor region formed in the semiconductor substrate, a buried region formed in the semiconductor substrate, a second semiconductor region disposed over the buried region, a third semiconductor region disposed over the buried region, a drain region formed in the second semiconductor region, a source region formed in the third semiconductor region, and a gate electrode layer formed on an upper surface of the semiconductor substrate. The first semiconductor region includes a first region formed between the third semiconductor region and the buried region, and a second region formed between the second semiconductor region and the buried region. The semiconductor substrate, the first semiconductor region, and the second semiconductor region each have a first conductivity type. The buried region and the third semiconductor region each have a second conductivity type opposite the first conductivity type.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device including: a semiconductor chip mounted on a wiring substrate such that a main surface of the semiconductor chip faces a front surface of an insulating film of the wiring substrate; and a bump electrically connecting a land and an electrode pad. Here, in cross-sectional view, a center of the land is shifted in a direction from a center of an opening portion, which exposes a part of the land, of the insulating film toward a center of the semiconductor chip is provided.
A semiconductor device includes three types of cells as a plurality of logic gates. A first cell includes a p-type MOSFET having a first threshold voltage and an n-type MOSFET having a second threshold voltage. A second cell includes a p-type MOSFET having a third threshold voltage and an n-type MOSFET having a fourth threshold voltage. A third cell includes a p-type MOSFET having the third threshold voltage and an n-type MOSFET having the second threshold voltage. An absolute value of the first threshold voltage is higher than an absolute value of the third threshold voltage, and an absolute value of the second threshold voltage is higher than an absolute value of the fourth threshold voltage.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
29.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A pad is formed on an interlayer insulating film, and an insulating film is formed to cover the interlayer insulating film and the pad. An opening is formed in the insulating film to expose a part of the pad. In the opening, a nickel plating film is formed on the pad, a first gold plating film is formed on the nickel plating film, and a second gold plating film is formed on the first gold plating film. A phosphorus concentration of the nickel plating film is 2% by mass or more and 7% by mass or less.
H01L 23/00 - Details of semiconductor or other solid state devices
C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
C23C 18/32 - Coating with one of iron, cobalt or nickelCoating with mixtures of phosphorus or boron with one of these metals
C23C 18/44 - Coating with noble metals using reducing agents
A controller for controlling a power stage having a plurality of phases is presented. The controller generates a control signal; sends the control signal to the plurality of phases via a first link; receives from each phase a feedback signal via a second link; sums the plurality of feedback signals and derives an average current per phase.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
31.
NON-LINEAR TRANSIENT IMPROVEMENTS IN CURRENT MODE CONTROLLERS
A method of increasing a transient response of a current mode controller and a current mode controller with an improved transient response are provided. The current mode controller is configured to control a high side switch and a low side switch. The current mode controller includes a pulse width modulation generator.
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
A semiconductor device includes fuse circuits, and each of the fuse circuits includes fuse elements and cutting transistors. The fuse elements and the cutting transistors are arranged in a first direction of a first main surface of a semiconductor substrate, respectively, and each of the fuse elements is surrounded by each of deep trench isolation parts in plan view. In plan view, each of the cutting transistors is surrounded by each of power supply parts, and the power supply parts are integrally surrounded by the deep trench isolation part. The cutting transistors are formed in a well region, and each of the power supply parts has the same conductivity type as the well region and is formed in the well region.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
33.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An n-type drift region and a p-type well region are formed in a semiconductor substrate. An n-type first drain region and an n-type second drain region are formed in the n-type drift region, and an n-type source region and an n-type semiconductor region are formed in the p-type well region. An impurity concentration of the n-type semiconductor region is lower than an impurity concentration of the n-type source region. A gate electrode includes an n-type first gate electrode portion and an n-type second gate electrode portion extending in the Y direction, and a p-type gate connection portion connecting the first gate electrode portion and the second gate electrode portion. In plan view, the n-type source region is arranged between the first gate electrode portion and the second gate electrode portion.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes a CPU configured to execute an instruction, a first register configured to store an address of the instruction currently being executed, a second register configured to store a return address when a function branch occurs, and a generation circuit configured to generate and output function branch information indicating an address of a function branch destination when the function branch occurs. The generation circuit is configured to determine whether or not the function branch has occurred based on values of the first register and the second register before and after instruction execution by the CPU, and, when determining that the function branch has occurred, output the value of the first register after the instruction execution by the CPU as the function branch information.
A semiconductor device includes an insulating film, and a polysilicon film formed on the insulating film. The semiconductor device includes, in plan view, a first region including a first semiconductor element formed of the polysilicon film, and a second region including a second semiconductor element. A first contact hole formed in the first region extends through the polysilicon film. An ohmic contact is formed between a metal embedded in the first contact hole and the polysilicon film on a side surface of the first contact hole.
A non-transitory computer readable medium stores a program for causing a co-simulation apparatus including a first simulator, a second simulator, a first communication path, and a second communication path to execute a co-simulation method. The first simulator stores first data in a first shared memory via the first communication path. In addition, the first simulator divides information related to a first address of the first shared memory in which the first data is stored into pieces of a size defined by an FMI standard, and transmits the pieces of information to the second simulator via the second communication path. The second simulator reads the first data stored in the shared memory by using the first address via the first communication path.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
A semiconductor device includes a dummy field structure in a non-element forming region. The dummy field structure includes a deep n-type well, an n-type well, a trench, a conductor layer, a first n-type semiconductor region, a second n-type semiconductor region, and a third n-type semiconductor region. The semiconductor device includes not only a first parasitic bipolar transistor but also a second parasitic bipolar transistor.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
An IGBT includes a first trench gate electrode extending in a first width direction, and a second trench gate electrode facing the first trench gate electrode. A first position range in the first width direction of a first channel region formed by the first trench gate electrode and a second position range in the first width direction of a second channel region formed by the second trench gate electrode differ from each other.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
39.
BATTERY MANAGEMENT SYSTEM, BATTERY MANAGEMENT METHOD, AND PROGRAM
The battery management system includes a first communication connection checking unit, a second communication connection checking unit, and an estimating unit. The first communication connection checking unit checks the communication state of the first communication connection that connects the microcontroller and the battery managing unit that obtains the cell voltage and the pack temperature. The second communication connection checking unit checks the communication state of the second communication connection that connects the microcontroller and the measuring unit that measures the pack voltage and pack current. The estimating unit estimates the charge/discharge information for controlling the charge/discharge of the battery based on the information that the microcontroller MC1 can be obtained, in accordance with the communication state of the first communication connection and the second communication connection.
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
40.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor layer having an N type drift region, a P type body region on the N type drift region, and an N type source region on the P type body region; an insulating layer on the semiconductor layer; a first opening provided in the insulating layer; a second opening provided in the semiconductor layer and extending from the N type source region to the P type body region so as to overlap the first opening in plan view; an insulating film arranged on a sidewall of the second opening; a first metal layer provided on the insulating layer, on the semiconductor layer of the first opening, on the insulating film, and on the semiconductor layer of the second opening; and a second metal layer provided on the first metal layer.
Reliability of a semiconductor device is improved. An insulating film is formed in an inner portion of a trench and on an upper surface of a semiconductor substrate. A field plate electrode is formed on the insulating film to fill the inner portion of the trench. The field plate electrode is recessed toward a bottom portion of the trench by etching process. Etching process using mixed gas containing CF4 gas and O2 gas is performed to an upper surface of the field plate electrode. A silicon oxide film is formed on the upper surface of the field plate electrode by thermal oxidation process.
A semiconductor chip is mounted on a die pad via a solder material. The semiconductor chip includes a plurality of corners including a first corner. A recess portion is formed in the die pad at an upper surface of the die pad. The semiconductor chip is mounted on the die pad such that the first corner is located at an inside of the recess portion. The first corner is located farthest from a center of a sealing body, among the plurality of corners. The solder material has: a first portion that is located between the semiconductor chip and a bottom surface of the recess portion; and a second portion that is located between the semiconductor chip and the upper surface of the die pad. A thickness of the solder material in the first portion is greater than a thickness of the solder material in the second portion.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
43.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A lower electrode is formed in a first wiring layer. In a second wiring layer located over the first wiring layer, two wirings having a thickness greater than that of the lower electrode are formed. Between the first wiring layer and the second wiring layer, a dielectric film and an upper electrode are formed over the lower electrode. A resistor element is formed over the two wirings. The lower electrode, the dielectric film, and the upper electrode function as a capacitor element.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
44.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Reliability of a semiconductor device is improved. A resistance element and a trench form a closed path in plan view.
Reliability of a semiconductor device is improved. A resistance element and a trench form a closed path in plan view.
The semiconductor device includes: first and second contact members each electrically connecting a gate pad and the resistance element; third and fourth contact members each electrically connecting a gate wiring and the resistance element; and fifth to eighth contact members each electrically connecting a first conductive member and the resistance element. A current path passing from the gate pad to the gate wiring through the first conductive member is made of the plurality of contact members and the resistance element. The first conductive member functions together with the fifth to eighth contact members to form a bypass path for reducing the current that flows through some sections of the closed path made of the resistance element.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A semiconductor device includes a semiconductor chip in which a plurality of circuit blocks is formed. The plurality of circuit blocks includes a plurality of logic circuits. Each of the plurality of logic circuits includes an inverter circuit. The inverter circuit outputs a signal according to the result of a logical operation of a first signal and a second signal after being precharged by a trigger signal.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
H03K 19/17704 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
H03K 19/17728 - Reconfigurable logic blocks, e.g. lookup tables
H03K 19/1776 - Structural details of configuration resources for memories
A semiconductor device includes a first power supply voltage line to which a power supply voltage is supplied, a second power supply voltage line, a first impedance element provided between the first power supply voltage line and the second power supply voltage line, a first reference voltage line to which a reference voltage is supplied, a second reference voltage line, a second impedance element provided between the first reference voltage line and the second reference voltage line, an electronic circuit provided between the second power supply voltage line and the second reference voltage line and performing a predetermined processing on an input signal, and provided in series between the second power supply voltage line and the second reference voltage line, and having gates connected to drains, a first transistor which is a P-channel MOS transistor, and a second transistor which is an N-channel MOS transistor.
A silicon film in amorphous state is formed on a semiconductor substrate located in first to fourth regions. The silicon film located in the first region and the fourth region is removed such that the silicon film located in the second region and the third region is left. A polycrystalline silicon film is formed by crystallizing the silicon film by a heat treatment.
Performance of a semiconductor device is improved. A semiconductor device includes a semiconductor chip, a sealing body having an upper surface and a lower surface, a plurality of leads, and a metal plate exposed from the sealing body at the upper surface of the sealing body. An outer lead portion of each of the plurality of leads includes a portion extending from the upper surface toward the lower surface in a thickness direction of the sealing body. The portion includes an end of the outer lead portion. When it is assumed that the lower surface is a reference surface in side view, in the thickness direction of the sealing body, a distance from the end of the outer lead portion to the reference surface is less than a distance from the upper surface to the reference surface.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
49.
SYSTEMS AND METHODS FOR GATE CURRENT SHAPING FOR GATE DRIVERS
Gate drivers, systems and methods are described. A gate driver can generate a gate current for driving a power switch in a system. A circuit can define a waveform shape of the gate current. The defined waveform shape of the gate current can cause a current of the power switch to have a constant slew rate.
A semiconductor substrate includes a p-type substrate region, an n-type buried layer on the p-type substrate region, and a p-type semiconductor layer on the n-type buried layer. In the semiconductor layer, an n-type semiconductor region is formed so as to surround a transistor in plan view and to reach the n-type buried layer from a main surface of the semiconductor substrate. A DTI region is formed so as to penetrate through the n-type semiconductor region and the n-type buried layer and reach the p-type substrate region.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device, a switching method, and a program that can prevent an overcurrent from flowing through a winding inside the motor are provided. The semiconductor device 100a, based on at least one of the inductance value and the resistance value of the winding inside the motor 10, a determination unit 363 for determining whether the current value of the winding exceeds the threshold after a predetermined time, based on the determination result of the determination unit 363 comprising a switch unit 364 for switching the control mode of the motor 10.
H02P 29/024 - Detecting a fault condition, e.g. short circuit, locked rotor, open circuit or loss of load
H02P 23/14 - Estimation or adaptation of motor parameters, e.g. rotor time constant, flux, speed, current or voltage
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
52.
COMMUNICATION CONTROLLER AND COMMUNICATION CONTROL METHOD
A communications controller is disclosed. The communications controller includes a data transfer unit and a protocol engine. The communications controller further includes a circuit configured to control transfer of data from the data transfer unit to the protocol engine in dependence upon a process identifier which identifies a process entity requiring the protocol engine to transmit data for the process entity.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
53.
PROBE TESTING APPARATUS, PROBE TESTING SYSTEM AND PROBE CARD
A probe testing apparatus includes a wafer stage, a temperature sensor, a temperature adjustment mechanism, and a controller. The wafer stage includes a wafer mounting surface on which a semiconductor wafer is mounted. The temperature sensor includes a temperature observation point exposed on the wafer mounting surface, and directly measures a temperature of a rear surface of the semiconductor wafer mounted on the wafer mounting surface. The temperature adjustment mechanism adjusts a temperature of the wafer stage by heating or cooling the wafer stage. The controller controls the temperature adjustment mechanism in such a manner that a measured temperature by the temperature sensor becomes a target temperature.
A first conductive pattern is formed on a semiconductor substrate and formed from a first conductive film. A second conductive film having a first portion on the semiconductor substrate, a second portion on an upper surface of the first conductive pattern, and a third portion connecting the first portion and the second portion so as to cover a side surface of the first conductive pattern, is formed. The upper surface of the third portion is higher than the upper surface of the first portion. The second portion is patterned. The second portion and a part of the third portion are selectively removed. By patterning the first conductive pattern and the second conductive film, a first gate electrode is formed from a part of the first conductive pattern, and a second gate electrode is formed from a part of the first portion.
A semiconductor device includes a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip. One of the first semiconductor chip and the second semiconductor chip includes a first switch. The other of the first semiconductor chip and the second semiconductor chip includes a second switch. The third semiconductor chip includes a first transformer. A signal is transmitted from the first semiconductor chip to the second semiconductor chip by the first transformer when the first switch is turned off while the second switch is turned on. A signal is transmitted from the second semiconductor chip to the first semiconductor chip by the first transformer when the second switch is turned off while the first switch is turned on.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H02M 7/00 - Conversion of AC power input into DC power outputConversion of DC power input into AC power output
56.
SEMICONDUCTOR MEASUREMENT DEVICE AND SEMICONDUCTOR MEASUREMENT METHOD
According to an embodiment, a semiconductor measurement device includes a CBCM circuit having a first terminal and a connection terminal and a potential difference application circuit connected to the connection terminal, the potential difference application circuit having a second terminal and applying a predetermined potential difference with respect to an output of the first terminal. The semiconductor measurement device obtains the parasitic capacitance of a measurement system from a capacitance in a connected state in which the first terminal and the second terminal are connected to a transistor and a capacitance in a disconnected state in which the first terminal and the second terminal are disconnected from the transistor, and calculates the capacitance of the transistor.
G01R 27/26 - Measuring inductance or capacitanceMeasuring quality factor, e.g. by using the resonance methodMeasuring loss factorMeasuring dielectric constants
G01R 31/26 - Testing of individual semiconductor devices
A semiconductor device includes a semiconductor substrate, an insulating film, a first coil, a second coil, a third coil, a fourth coil, a first guard ring and a second guard ring. The first coil and the second coil are formed on the semiconductor substrate. The third coil faces the first coil through the insulating film. The fourth coil faces the second coil through the insulating film. The first guard ring is formed to surround the third coil in plan view. The second guard ring is formed to surround the fourth coil in plan view. The first guard ring and the second guard ring are adjacent to each other while being spaced apart from each other in plan view.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
58.
INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD AND PROGRAM
To appropriately estimate the amount and direction of movement of a moving object, an information processing apparatus has an acquisition unit that acquires each image captured at each point in time by a shooting device mounted on the moving object; a determination unit that determines the type of movement of the moving object based on the respective images; and an estimation unit that, based on a first image and a second image captured at a time interval corresponding to the type of movement from the first image, estimates the amount and direction of movement of the moving object from the first point in time when the first image was captured to the second point in time when the second image was captured.
A semiconductor device capable of verifying whether or not correct acquirement of image data from a sensor has been successful is provided. A semiconductor device includes: a reception interface circuit receiving a plurality of packets including a plurality of line data, respectively, and outputting an image composite signal generated by linking a line synchronization signal with each of the plurality of line data; and a capture circuit provided at a subsequent stage of the reception interface circuit. The capture circuit includes: a line counter receiving, as its input, the line synchronization signal included in the image composite signal, and counting the number of times of the input of the line synchronization signal; and a comparator comparing a count value counted by the line counter with a preset expected value of the number of lines, and outputting an error signal if the count value and the expected value do not match each other.
To provide a semiconductor device and a memory module capable of correctly maintaining the phase relationship between a data signal and a data strobe signal that determines the latch timing of the data signal. A variable delay circuit VDLYs_A generates respective data strobe signals DQSin, DQSin_M by delaying an input data strobe signal MDQS by delay amounts ST1, ST2. A timing adjustment circuit TMCT adjusts the delay amount ST1 based on the determination of matching/mismatching between a data signal DQo from a main slicer SLr and a data signal DQo_M from a monitor slicer SLr_M, while changing the delay amount ST2,
A current sense circuit is provided. The circuit includes a current mirror circuit QN1, QN2, and diode-connected QP1, QP2, QP3, and QP4 with their bases connected together, stacking such that the diode-connected side (QN1, QP1, QP3) aligns and connecting the emitter of QP2 to the collector of QP4. Furthermore, the gates of MP1 and MP2 are connected to the collector of QN2 and QP2, respectively. Additionally, the source of MP1 is connected to the drain of MP3 via the source of MP2 and also connected to the source of a Sense MOS. Moreover, the emitter of QP4 is connected to the source of MP4 via R1, and the drain of MP4 is connected to the source (OUT terminal) of a Main MOS. Furthermore, the gates of MP3 and MP4 are connected to the emitters of QN1 and QN2.
A semiconductor device having a semiconductor chip with a first circuit, a second circuit, a third circuit, a first protection element, and a resistor circuit, the first circuit and the third circuit mutually input and output unidirectional or bidirectional signals via the second circuit, the first protection element is electrically connected to a first node which electrically connects a first terminal and the second circuit, and the resistor circuit is provided between the first node and a second node which electrically connects the first terminal, the first circuit, and the second circuit and is located upstream of the first node.
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
63.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device includes: a step of forming a sealing body, and a step of irradiating a laser light to a region, which is covering a part of each of the plurality of leads, of the sealing body. Each of the plurality of leads of a lead frame LF includes a first portion having a first upper surface and a first lower surface opposite the first upper surface, and a second portion having a thickness smaller than the first portion. The second portion has a second upper surface, and a second lower surface opposite the second upper surface. In the step of irradiating the laser light, the second lower surface is exposed from the sealing body by selectively irradiating the region with the laser light.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A semiconductor nonvolatile memory device or the like capable of narrowing a cell voltage distribution range while suppressing write delay is provided. The semiconductor nonvolatile memory device includes: a plurality of gate lines; a plurality of bit lines intersecting the plurality of gate lines; and a plurality of memory cells connected to respectively intersection points between the gate lines and the bit lines. The plurality of memory cells are connected to one gate line selected from among the plurality of gate lines respectively via the different bit lines, and the semiconductor nonvolatile memory device further includes a plurality of write bit line current or voltage control circuits respectively controlling bit line currents in order to simultaneously perform writing into the plurality of memory cells.
A semiconductor device includes a semiconductor chip having a plurality of layers formed on a surface. Here, a power supply wiring to which a power supply voltage is supplied, a ground wiring to which a ground voltage is supplied, MOS transistors connected to the power supply and ground wirings, and a trigger circuit, which is electrically connected to a gate electrode of the MOS transistor via a first wiring, are formed in the plurality of layers. The MOS transistors and the trigger circuit are formed in a first layer, the first wiring is formed in a second layer which is an upper layer of the first layer, and the first wiring includes a first portion extending in a first direction and a second portion which extends in a second direction intersecting the first direction and is electrically connected to the first portion.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
66.
SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SEMICONDUCTOR DEVICE, AND CONTROL PROGRAM
A semiconductor device according to this disclosure includes: a comparator circuit; a counter circuit; and a latch circuit that stores a count value of the counter circuit at a timing when an output signal of the comparator circuit changes, the counter circuit includes: a multiphase signal generator; and a plurality of flip-flop circuits including a first-stage flip-flop and second-stage and subsequent flip-flops, the first-stage flip-flop takes in an inverted signal of an output signal of a flip-flop in a final stage and each of the second-stage and subsequent flip-flops takes in an output signal of a flip-flop in a preceding stage in synchronization with each of the plurality of clock signals, and an output signal of each of the plurality of flip-flop circuits is output as a count signal of the count value.
H04N 25/633 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current by using optical black pixels
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H04N 25/40 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
Access time from a CPU to a register can be reduced while complication of software is prevented. A semiconductor device includes: a decoder circuit determining a write-source process; a write-enable setting storage circuit storing a write-enable setting that indicates a processor enabled to execute writing into each bit of a write-destination register; a masking/merging circuit generating a value to be written back into the write-destination register on the basis of the write-enable setting and the write-source processor; and a write-back circuit writing back the value to be written back into the write-destination register.
A semiconductor device includes a non-volatile memory (NVM) capable of data-writing even after the semiconductor device is shipped. When a read request is made, the semiconductor reads and outputs the content stored in the area of the NVM in place of the replacement target data in the instruction codes stored in a read only memory. Therefore, after shipping of the semiconductor device, even if a defect such as fragility in the code used at the start of the semiconductor device is found, replacement data in place of 10 the data to be replaced it can be obtained. That is, the semiconductor device, replacement process using the modified patches of Boot ROM cord is enabled.
A method of manufacturing a semiconductor device includes, after a wire bonding step, a step of determining a quality as to whether or not a whole of an end portion of a wire is located within a bonding region. A semiconductor chip includes a plurality of position determining opening patterns arranged in a region located around a main opening portion including the bonding region in plan view. The bonding region has a rectangular shape having an area smaller than an opening area of the main opening portion in plan view. The bonding region is defined by the plurality of position determining opening patterns.
A semiconductor device is protected from glitch attacks (FIA). A reset data transfer controller RDTC executes N times of data transfer, transferring data DT stored in a first memory MEM1a to a main register REGm during the first data transfer, and transferring data DT stored in the first memory MEM1a to a sub-register REGs during the Nth data transfer. A comparison circuit CMP1 determines the match/mismatch between the data DTm transferred to the main register REGm and the data DTs transferred to the sub-register REGs, and outputs a determination result signal RS representing the determination result. A system controller SYSC activates a processor PRC when the determination result signal RS indicates a match, and causes the reset data transfer controller RDTC to execute the N times of data transfer again when it indicates a mismatch.
High speed of an analog-digital converter of a semiconductor device is achieved. A voltage quantizer circuit includes: a first comparator including a first input transistor inputting differential input voltages, and defining a value of a first bit of a digital signal; and a second comparator including a second input transistor being different from the first input transistor, and defining a value of a second bit of the digital signal. A correction code decision circuit decides a correction code for correcting a common-mode voltage of the differential input voltages, based on a conversion end signal output from the voltage quantizer circuit. A common-mode voltage regulator circuit regulates the common-mode voltage by adding or subtracting a corrected voltage based on the correction code to or from the differential input voltages.
A semiconductor device includes a semiconductor substrate, a multilayer wiring structure formed on the semiconductor substrate, a guard ring formed so as to surround a circuit formation region and penetrate the multilayer wiring structure, and a pad formed on the multilayer wiring structure. A protective film is formed so as to cover the multilayer wiring structure, the guard ring, and the pad. A trench is formed so as to penetrate the protective film and reach an inside of the multilayer wiring structure. The trench is formed so as to surround the guard ring. The guard ring includes a wiring formed on the multilayer wiring structure. The trench is spaced apart from and adjacent to the wiring. A bottom surface of the trench is inclined so as to be continuously deepened in a direction from the circuit formation region toward a peripheral region surrounding the circuit formation region.
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
73.
ON-CHIP NOISE MEASUREMENT IN A TRANSCEIVER, METHOD AND SYSTEM THEREOF
According to an aspect, a transceiver comprises a transmitter section having a first PLL (phased locked loop) providing a first reference signal to the transmitter section, a receiver section having a second PLL providing a second reference signal to the receiver section, a coupler coupling the second PLL to the transmitter section when the transceiver is operative in a test mode measuring a first noise component introduced by the first PLL. The first reference signal is coupled to the receiver section internally within the transceiver as a local reference signal to the receiver section both in the test mode and a functional mode.
A failure analysis device is for analyzing a failure of the semiconductor device equipped with a logic circuit and a memory circuit. It has a storage device and a processor. The storage device stores fail bit data obtained by testing the memory circuit and failure diagnosis data obtained by failure diagnosis for test results of the logic circuit. The processor extracts the fail I/O value from the fail bit data, extracts the data of the memory connection port which is the connection port to the memory circuit from among the estimated failure parts included in the failure diagnosis data, and determines match/not-match between the fail I/O value and the port ID value included in the data of the memory connection port.
Systems and methods for sensing and processing biosignals are described. An example system can include a first device configured to sense at least one biosignal and a second device. The second device can receive the at least one biosignal from the first device. The second device can receive power via a first wireless interface. The second device can charge a rechargeable battery using the received power. The second device can receive a signal via the first wireless interface, wherein the signal encodes credentials of a user. The second device can demodulate the signal to decode the user credentials. The second device can authenticate the user credentials. The second device can, in response to authentication of the user credentials, communicate the at least one biosignal to a user device via a second wireless interface.
H02J 50/20 - Circuit arrangements or systems for wireless supply or distribution of electric power using microwaves or radio frequency waves
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
A failure detection circuit is provided in the target circuit having a first circuit area for operating in synchronization with the first clock signal, a first detection circuit for outputting a first detection result obtained by transitioning the voltage level in synchronization with the first clock signal, the first clock signal a second detection circuit for outputting a second detection result obtained by transitioning the voltage level in synchronization with, and a first comparison circuit for outputting a first comparison result by comparing the first detection result and the second detection result. Accordingly, by the failure detection circuit, it is possible to detect the failure accurately.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
According to one embodiment, the semiconductor device 1 includes a semiconductor substrate having an upper surface and a lower surface, and an emitter wiring, wherein when viewed from the upper surface side, the semiconductor substrate has an active region including a plurality of IGBTs, a termination region, and a main junction region, wherein the semiconductor substrate of the main junction region has an N− type drift layer and a P type junction impurity layer, wherein the semiconductor substrate of the termination region has an N− type drift layer and a P type floating layer, wherein at least the main junction region has a trench electrode provided inside the trench, and a trench insulating film provided between the trench electrode and the semiconductor substrate, and wherein the trench electrode and the P type junction impurity layer are connected to the emitter wiring.
A first surface of a die pad has: a first region; a second region that includes points respectively overlapping with four corners of a semiconductor chip; and a third region that is located around the second region. Also, a plurality of grooves is formed in the die pad at the second region. Also, each of the plurality of grooves terminates at a position not reaching each of the first region and the third region. Also, the plurality of grooves includes: a plurality of first grooves each extending in an extending direction of one of two diagonal lines of the semiconductor chip; and a plurality of second grooves each extending in an extending direction of another one of the two diagonal lines. Also, in each of the plurality of first grooves is arranged so as to intersect with one or more of the plurality of second grooves.
A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.
A carrier tape includes a first layer component having a recess and a first opening in a center of the recess, and a second layer component housed in the recess, the second layer having a center arranged parallel to the recess, a step part arranged around the center by a step falling from the center, a second opening overlapping the first opening arranged in the center, and a third opening arranged in the step part.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
A semiconductor device according to the embodiment includes a semiconductor chip having a first MOSFET formed in a first region of a semiconductor substrate, a detection element formed in a second region within the first region, a source electrode formed above the first region and connected to a source of the first MOSFET, and a source electrode material arranged to cover the detection element and stitch-bonded to the source electrode.
To reduce the time required for data writing. A semiconductor memory device is provided, comprising a memory cell having a gate electrode including a selection gate and a memory gate, a source line connected to a source, and a bit line connected to a drain, an extraction part that extracts a current flowing from the source side to the drain side during writing in the memory cell from the bit line, a discharge part that has a higher ability to pass current than the extraction part and lowers the voltage of the bit line, a charge part that has a higher ability to pass current than the discharge part and applies a voltage to the bit line, and a control part that, when starting to write to the memory cell, lowers the voltage of the bit line by the discharge part and applies a voltage to the bit line by the charge part.
Improve the reliability of a semiconductor device. A resistive element Rg is filled in a trench TR formed in a well region PW of a semiconductor substrate. The resistive element Rg and the trench TR have an endless shape in plan view. The resistive element Rg is connected to a first contact member PG that is electrically connected to a gate pad GP, and a second contact member PG that is electrically connected to a gate wiring GW. Furthermore, a third contact member PG, which electrically connects an emitter electrode EE to the well region PW, is positioned in an area surrounded by an endless shape of the resistive element Rg, between the first and second contact members PG in a Y direction.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
Providing a memory device that initializes memory cell data in a batch by specifying initialization data, or a memory device that initializes memory cell data in a batch by partially masking the initialization area. A memory device is provided that includes a control circuit that receives an initialization mode signal transmitted from an initialization control circuit and generates an internal clock and a write control signal, an IO (Input/Output) input circuit that applies a Low level to the True side or Bar side of a bit line according to initialization data transmitted from the initialization control circuit, and a selection circuit that simultaneously selects multiple word lines and multiple bit lines, and writes the initialization data simultaneously into a memory cell connected to the selected word lines and bit lines.
In plan view, an electrode pad of a semiconductor chip includes: a first region that contains a center of an exposed portion of the electrode pad; a second region that is located around the first region; and a third region that is located around the first region and that is located between the first region and the second region. Here, a first groove that separates a plurality of semiconductor elements formed in a semiconductor substrate from each other is formed in the semiconductor substrate. The semiconductor substrate includes: a fourth region that overlaps with the third region but not overlaps with each of the first region and the second region, and a fifth region that overlaps with the first region but not overlaps with the third region. And, the first groove is formed in the semiconductor substrate at the fifth region but not at the fourth region.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
The technology of improving the adhesion of the barrier metal film is provided. The semiconductor device includes: a floating region formed between a trench gate electrode and a trench emitter electrode; a stacked film formed on the floating region; an interlayer insulating film formed on the stacked film; a plug penetrating the interlayer insulating film and reaching the stacked film; a barrier metal film formed to cover the interlayer insulating film and the plug; and a metal film formed on the barrier metal film.
A semiconductor device includes a first well region, a second well region, a body region, and a cathode region. The impurity concentration of the body region is higher than the impurity concentration of the first well region, and the impurity concentration of the second well region is higher than the impurity concentration of the body region. In plan view, the body region includes the cathode region, and the cathode region includes the second well region. The cathode region configures a cathode of a Zener diode, and the first well region, the second well region, and the body region configure an anode of the Zener diode.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A controller for controlling a power stage having one or more phases is presented. The controller includes a reference circuit that generates a reference signal; a ramp generator generating a feedback ramp signal based on a feedback signal of the power stage; and a modulator generating a control signal for controlling at least one phase of the power stage. The control signal may include a series of pulses in which each pulse is associated with a corresponding phase of the power stage.
A power converter controller is presented. The controller includes a ramp generator for generating a ramp signal and a ramp adjuster. The ramp adjuster compares a feedback signal of the converter with a threshold signal to obtain a comparison signal, and to adjust an amplitude of the ramp signal based on the comparison signal. Also presented is a constant on time COT power converter including the above controller.
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
90.
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DIAGNOSTIC DEVICE
The technology provided enables the acceleration of the clock. The semiconductor device comprises a counter circuit configured to generate a read signal when the count number reaches a predetermined number, a buffer configured to store test data and sequentially output the test data in the order stored when the read signal indicates a valid value, and a first scan test circuit that sequentially captures the test data output from the buffer.
A semiconductor device is provided. The semiconductor device is capable of operating accurately by suppressing errors caused by dielectric relaxation phenomena. The semiconductor device includes a first capacitive element, a first switch circuit, a first inversion signal generating circuit, a second capacitive element, and a negative feedback circuit.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
A semiconductor device has a semiconductor substrate, a first insulating layer, a first inductor, a second insulating layer, a second inductor, a pad and an annular wiring. The first insulating layer is formed on the semiconductor substrate. The first inductor is directly formed on the first insulating layer. The second insulating layer is formed on the first insulating layer such that the second insulating layer covers the first inductor. The second inductor is directly formed on the second insulating layer such that the second inductor faces the first inductor. The pad is directly formed on the second insulating layer. The pad is electrically connected with the second inductor. The annular wiring is electrically connected with the pad. The annular wiring is spaced apart from the second inductor. The annular wiring surrounds the second inductor without forming a vertex in plan view.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Integrated circuits; electronic integrated circuits; large
scale integrated circuits; semi-conductors; semiconductor
chips; semiconductor chipsets; microprocessors;
semi-conductor memories; electronic semi-conductors; circuit
boards; chips [integrated circuits]; computer software;
computer programs; computer hardware and software for use in
implementing internet of things [IoT]; computer hardware;
computer software platforms, recorded or downloadable;
computers and computer peripherals; DC/DC converters; AC/DC
converters; converters, electric; electrical power supplies;
components for electrical power supplies; accessories for
electrical power supplies; electronic power control machines
and apparatus; power control device; electronic power
supplies; electric current control devices; power
distribution or control machines and apparatus; rotary
converters; phase modifiers; solar batteries; accumulators
[batteries]; electrical cells and batteries; current sensors
and testers for measuring semiconductor characteristics;
electric or magnetic meters and testers; electric wires and
cables; telecommunication machines and apparatus; personal
digital assistants; vehicle drive training simulators;
sports training simulators; laboratory apparatus and
instruments; photographic machines and apparatus;
cinematographic machines and apparatus; optical machines and
apparatus; measuring or testing machines and instruments;
magnetic cores; resistance wires; electrodes; game programs
for home video game machines; electronic circuits and
CD-ROMs recorded with programs for hand-held games with
liquid crystal displays; phonograph records; downloadable
music files; downloadable image files; recorded video discs
and video tapes; electronic publications; exposed
cinematographic films; exposed slide films; slide film
mounts; apparatus for recording, transmission or
reproduction of sound or images; magnetic data carriers and
recording discs; data processing apparatus and computers;
electronic agendas; amplifiers; antennas; bar code readers;
electric cables; fiber optic cables; encoded magnetic cards;
cassette players; commutators; compact discs [audio-video];
computer game programs; computer memories; recorded or
downloadable computer programs; computers; printers for use
with computers; electric contacts; control panels for power
distributing; magnetic data media; optical data media;
optical discs; blank magnetic discs; disk drives for
computers; downloadable electronic publications; integrated
circuit cards; inverters [electricity]; lasers, not for
medical purposes; magnetic tapes; meters; modems; electric
monitoring apparatus; monitors for computer; mouse for
computers; digital color photocopiers; portable telephones;
radio pagers; optical character readers; remote control
apparatus; electric resistances; scanners for computer;
electric sockets; sound recording apparatus; sound recording
magnetic discs and video tapes; sound reproducing apparatus;
sound transmitting apparatus; personal stereos; electric
switches; switches; telephone apparatus; thermostats;
telecommunication transmitters; video cassettes; video game
cartridges; video recorders; video telephones; air-gas
producers for laboratory use; thermostats for laboratory
use; hygrostats for laboratory use; glassware for laboratory
experiments; porcelain instruments for laboratory
experiments; furnaces for laboratory experiments; laboratory
experimental machines and apparatus; models/specimens for
laboratory use; tilting pan heads [for laboratory use];
cameras; range finders; photo-developing/printing/enlarging
or finishing apparatus; tripods [for cameras]; bellows
[photography]; spools; slide projectors; self-timers; power
supply equipment for photography flash bulbs; flash lamps;
viewfinders; lens hoods; flash guns; shutter releases;
optical lenses; exposure meters; projectors [projection
apparatus]; transparent sheets [exposed films] for overhead
projectors; photograph developing or finishing apparatus;
cinematographic cameras; projection screens; editing
machines for movie films; lens barrels [for telescopes];
tripods [for telescopes]; periscopes; binoculars; reflectors
[for telescopes]; prisms [telescopes]; telescopes;
magnifying glasses; metallurgical microscopes; biological
microscopes; polarizing microscopes; stereoscopes;
microscopes; temperature indicators; gasometers;
thermometers; water meters; balances/scales; tape measures;
masu [Japanese box-shaped volume measure]; planimeters;
rules; standard-unit measuring machines and apparatus;
pressure gauges/manometers; level gauges; acoustic meters;
tachometers; accelerometers; refractometers; luminoflux
meters; photometers; altimeters; hygrometers;
illuminometers; vibration gauges; noise meters; logs;
speedometers [speed indicators]; calorimeters;
viscosimeters; densitometers/concentration meters;
gravimeters/aerometers; densimeters [density meters];
dynamometers; flowmeters; derived-unit measuring machines
and apparatus; angle gauges; angle dividing apparatus
[measuring instruments]; spherometers; inclinometers;
interferometers; straightness testers; projectors;
graduation checkers [calibration checkers]; length gauges;
screw-thread measuring machines and instruments;
comparators; surface roughness testers; flatness testers;
precision measuring machines and instruments; automatic
pressure controllers; automatic liquid-flow controllers;
automatic fluid-composition controllers; automatic
liquid-level controllers; automatic temperature controllers;
automatic combustion controllers; automatic vacuum
controllers; automatic calorie controllers; programmable
logic controllers; automatic adjusting/regulating machines
and instruments; metal compression testers; metal hardness
testers; metal strength testers; rubber testing machines;
concrete testing machines; cement testing machines; textile
testing machines; plastic testing machines; lumber testing
machines; material testing machines and instruments;
alidades; meteorological instruments; base plates for
measuring instruments; distance measuring machines or
apparatus [range finders]; clinometers; magnetic compasses;
compass needles; gyro compasses; gyromagnetic compasses;
analysis instruments for photogrammetric purposes; levels
[spirit levels]; precision theodolites; measuring rods;
surveying chains; electronic target location apparatus;
transits for surveying; levelling rods for surveying;
sextants; surveying machines and instruments; meridian
transits; astronomical spectroscopes; zenith telescopes;
astrometric measuring apparatus and instruments; electronic
charts for identifying hiding-power of paint; rust-formation
testing pieces; relays; circuit breakers; power controllers;
current rectifiers; connectors; circuit closers; capacitors;
resistors; distributing boxes; distribution boards
[electricity]; fuses; lightning arresters; transformers;
induction voltage regulators; reactors [electricity]; phase
meters; oscillographs; circuit testers; antenna measuring
apparatus; detectors; magnetic measuring apparatus;
frequency meters; vacuum tube characteristic measuring
apparatus; watt hour meters; ammeters; wattmeters;
oscillators; electrical power testers; interphones;
automatic telephone exchange apparatus; manual telephone
exchange apparatus; telephone sets; teletypewriters;
automatic telegraph apparatus; phototelegraphy apparatus;
manual telegraph apparatus; facsimile machines; audio
frequency transmission apparatus; cable-type
carrier-frequency apparatus; power-line-type
frequency-carrier apparatus; open-wire-type
frequency-carrier apparatus; carrier-frequency repeaters;
transmission machines and apparatus for telecommunication;
television receivers; television transmitters; radio
receivers [radios]; radio transmitters; broadcasting
machines and apparatus; portable radio communication
apparatus; aeronautical radio communication apparatus;
multichannel radio communication apparatus for fixed
stations; monochannel radio communication apparatus for
fixed stations; radio communication apparatus for vehicles;
marine radio communication apparatus; radio communication
machines and apparatus; navigation apparatus for vehicles;
beacon apparatus; direction finders; radar apparatus; loran
apparatus; radio machines and apparatus; remote control
telemetering apparatus; loudspeakers/megaphones; compact
disc players; juke boxes; tape recorders; electric
phonographs; record players; audio frequency devices and
apparatus; video disc players; video frequency devices and
apparatus; cabinets for loudspeakers; coils, electric;
magnetic tape erasers; magnetic tape cleaners; magnetic head
erasers; magnetic head cleaners; speakers; stands and racks
for telecommunication machine and apparatus; dials [for
photographic transparencies]; fuses for communication
apparatus; tapes for tape recorders; change-over switches;
distribution boards; pickups; video tapes; indicator lights
for telecommunication apparatus; electrical phonomotors;
headphones; protectors for telecommunication apparatus;
microphones; record cleaners [cleaning apparatus for
phonograph records]; blank record discs; cleaning apparatus
for phonograph records; parts and accessories for
telecommunication machines and apparatus; geiger counters;
cyclotrons; X-ray apparatus, not for medical use; betatrons,
not for medical use; magnetic surveying machines; magnetic
object detectors; shielding cases for magnetic discs;
seismic wave surveying machines; hydrophone machines and
apparatus; ultrasonic depth sounders; ultrasonic flaw
detectors; ultrasonic sensors; electrostatic copying
machines; remote control apparatus for opening and closing
doors; electronic microscopes; desk-top computers; word
processors; X-rays tubes, not for medical use; tubes for
photographic instruments; vacuum tubes; rectifier tubes;
cathode ray tubes; discharge tubes; electron tubes;
thermistors; diodes; transistors; electronic circuits and
CD-ROMs recorded with program for handheld liquid crystal
display game; pre-recorded video discs and tapes;
semi-conductor devices; semi-conductor integrated circuits
including CPU; electronic circuits; magnetic drums, magnetic
discs, magnetic tapes, CD-ROMs, electronic circuits and
other storage mediums recorded with a program for developing
and designing of semi-conductor devices, integrated circuits
including CPU, electronic circuits and other electronic
machines; microcontrollers; microcomputers; programs for
microcomputers; circuits for testing/evaluating of
microcomputers, microcontrollers, microprocessors and
semi-conductor integrated circuits; semi-conductor
integrated circuits; semi-conductor commutators;
downloadable electronic publications for semi-conductors;
silicon wafers for semi-conductors; DVD players; DVD
recorders and digital video cameras; digital still cameras;
video cameras; liquid crystal displays; plasma display
television sets; light emitting diodes [LED]; printed
circuit boards; notebook computers; handheld computers;
personal digital assistants [PDA]; data processing
apparatus; electrostatic copying machines; printers; cathode
ray tube displays; computer peripheral equipment; compact
discs [CD]; digital versatile disks [DVD]; encoded magnetic,
optical and integrated circuit cards; magnetic cards; video
projectors; semi-conductor testing apparatus; computer
software in the field of artificial intelligence. Design of electronic circuit, semiconductor devices,
integrated circuits and large scale integrated circuits;
design and testing of semiconductor for others; designing of
machines, apparatus, instruments [including their parts] or
systems composed of such machines, apparatus and
instruments; design of semiconductor devices; design of
semiconductor chips; design of integrated circuits; design
and updating of computer software; provision of
technological information in relation to semiconductor
including integrated circuits; design of computer-simulated
models; computer programming; technological advice relating
to computers, automobiles and industrial machines; testing
or research in relation to electronic circuit, semiconductor
devices, integrated circuits and large scale integrated
circuits; design, development, testing and inspection of
power management integrated circuits (PMICs); testing and
research services relating to machines, apparatus and
instruments; Software as a service [SaaS]; Platform as a
service [PaaS]; leasing of a database server to third
parties; rental of computers; providing computer programs on
data networks; rental of laboratory apparatus and
instruments; providing meteorological information;
architectural design; surveying; geological surveys;
testing, inspection and research services in the fields of
pharmaceuticals, cosmetics and foodstuffs; research on
building construction or city planning; testing and research
services in the field of preventing pollution; testing and
research services in the field of electricity; testing and
research services in the field of civil engineering;
testing, inspection and research services in the fields of
agriculture, livestock breeding and fisheries; rental of
measuring apparatus; rental of telescopes; rental of
technical drawing instruments; design and development of
computer hardware and software; authenticating works of art;
calibration [measuring]; computer software design; computer
system design; computer systems analysis; consultancy in the
field of computer hardware; consultation in environment
protection; conversion of data or documents from physical to
electronic media; creating and maintaining web sites for
others; data conversion of computer programs and data, not
physical conversion; design of interior decor; dress
designing; duplication of computer programs; engineering;
graphic arts designing; hosting computer sites [web sites];
industrial design; installation of computer software;
maintenance of computer software; material testing;
packaging design; physics [research]; technical project
studies; quality control; recovery of computer data; rental
of computer software; research and development for others;
updating of computer software; styling [industrial design];
technical research; textile testing; underwater exploration;
vehicle roadworthiness testing; consultancy and advice in
the field of design of semi-conductor devices; testing,
checking and research of semi-conductor devices; providing
information about design of semi-conductor
devices/consultancy and advice in the field of design of
semi-conductor devices, testing, checking and research in
the field of semi-conductor devices; guidance and advice in
the field of design of semi-conductor chips; testing,
checking and research in the field of semi-conductor
chips/consultancy and advice in the field of design of
semi-conductor chips, testing, checking and research in the
field of semi-conductor chips; consultancy and advice in the
field of design of integrated circuits; testing, checking
and research in the field of integrated circuits; providing
information about design of integrated circuits/consultancy
and advice in the field of design of integrated circuits,
testing, checking and research in the field of integrated
circuits; design of microcomputers; consultancy and advice
in the field of design of microcomputers; testing, checking
and research in the field of microcomputers; providing
information about design of microcomputers/consultancy and
advice in the field of design of microcomputers, testing,
checking and research in the field of microcomputer; design
of IC cards; consultancy and advice in the field of design
of IC cards; testing, checking and research in the field of
IC cards; providing information about design of IC
cards/consultancy and advice in the field of design of IC
cards, testing, checking and research in the field of IC
cards; design of semi-conductor memory; consultancy and
advice in the field of design of semi-conductor memory;
testing, checking and research in the field of
semi-conductor memory; providing information about design of
semi-conductor memory/consultancy and advice in the field of
design of semi-conductor memory, testing, checking and
research in the field of semi-conductor memory; design of
circuit boards; consultancy and advice in the field of
design of circuit boards; testing, checking and research in
the field of circuit boards; providing information about
design of circuit boards/consultancy and advice in the field
of design of circuit boards, testing, checking and research
in the field of circuit boards; design of semi-conductor
manufacturing apparatus; consultancy and advice in the field
of design of semi-conductor manufacturing apparatus;
testing, checking and research in the field of
semi-conductor manufacturing apparatus; providing
information about design of semi-conductor manufacturing
apparatus/consultancy and advice in the field of design of
semi-conductor manufacturing apparatus, testing, checking
and research in the field of semi-conductor manufacturing
apparatus; design of semi-conductor testing apparatus;
consultancy and advice in the field of design of
semi-conductor testing apparatus; testing, checking and
research in the field of semi-conductor testing apparatus;
providing information about design of semi-conductor testing
apparatus/consultancy and advice in the field of design of
semi-conductor testing apparatus, testing, checking and
research in the field of semi-conductor testing apparatus;
design of semi-conductor checking apparatus; consultancy and
advice in the field of design of semi-conductor checking
apparatus; testing, checking and research in the field of
semi-conductor checking apparatus; providing information
about design of semi-conductor checking
apparatus/consultancy and advice in the field of design of
semi-conductor checking apparatus, testing, checking and
research in the field of semi-conductor checking apparatus;
information relating to the use of electronic calculators;
information relating to the use of microcomputers; provision
of technological information relating to the use of
semi-conductor manufacturing apparatus; information relating
to the use of semi-conductor testing apparatus; information
relating to the use of semi-conductor checking apparatus;
computer programming and maintenance of computer software
and CAD; rental of computer software and CAD; research,
developing and designing of semi-conductor devices,
integrated circuits, CPUS and electronic circuits for
others; surveys, advice, consultation, and providing
information in the field of research, developing, and
designing for others of semi-conductors and devices,
integrated circuits, CPUS and electronic circuits; research,
developing, designing, programming and maintenance of
computer software for others; surveys, advice, consultation,
and providing information in the field of research,
developing, designing, programming and maintenance of
computer software; technical reports for others in the field
of research, developing, designing, programming and
maintenance of semi-conductor devices, integrated circuits,
CPUs and electronic circuits; technical writing for others
in the field of computer software; providing information in
the field of research, developing, and designing for others
of semi-conductor devices, integrated circuits, CPUs and
electronic circuits by means of a global computer network;
providing temporary use of on-line non-downloadable
applications software (for use in the field of
semi-conductor production, for use in electronic circuit
design); evaluation of technologies for manufacturing
semi-conductors for others; providing technology information
for research, developing and designing of semi-conductor
devices, integrated circuits, CPUs and electronic circuits;
mechanical testing and research; rental of semi-conductor
testing apparatus; providing information about rental of
semi-conductor testing apparatus; rental of semi-conductor
checking apparatus; providing information about rental of
semi-conductor checking apparatus; inspection of
semi-conductor manufacturing apparatus, semi-conductor
testing apparatus and semi-conductor checking apparatus;
providing information about inspection of semi-conductor
manufacturing apparatus, semi-conductor testing apparatus
and semi-conductor checking apparatus; providing temporary
use of on-line non-downloadable artificial intelligence
computer programs on data networks.
A semiconductor device is provided. The semiconductor device is capable of operating accurately by suppressing errors caused by dielectric relaxation phenomena. The semiconductor device includes a first capacitive element, a signal cancellation circuit, a sampling circuit, a negative feedback circuit, an AD converter, and an addition-and-subtraction circuit.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
A semiconductor device includes a first dielectric film, a resistor element disposed on the first dielectric film, and a second dielectric film disposed on the resistor element. The resistor element contains silicon, chromium, and carbon. The silicon concentration in the resistor element increases from a center part of the resistor element towards an upper surface of the resistor element, and also increases from the center part of the resistor element towards a lower surface of the resistor element.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
The performance of a semiconductor device can be improved. A plurality of protruding electrodes of a semiconductor chip includes: a plurality of first protruding electrodes arranged at positions overlapping a first region of an insulating layer, a plurality of second protruding electrodes arranged at positions overlapping a second region of the insulating layer, and a plurality of third protruding electrodes arranged at positions overlapping a third region of the insulating layer. The plurality of first protruding electrodes is arranged at a first pitch, the plurality of second protruding electrodes is arranged at a second pitch, and the plurality of third protruding electrodes is arranged at a third pitch different from each of the first pitch and the second pitch.
The reliability of a semiconductor device is improved. In this disclosure, a gate insulating film is formed on a silicon carbide semiconductor substrate in a process using a material gas containing a halogen element and a metal element by an ALD method.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
99.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device including an IGBT with improved switching characteristics is provided. Inside trenches formed inside a semiconductor substrate of an active cell, a trench gate electrode and a trench emitter electrode are formed through a gate insulating film. An n-type hole barrier region is formed inside the semiconductor substrate located between the trenches. A p-type base region is formed inside the hole barrier region. An n-type emitter region is formed inside the base region. A p-type floating region is formed inside the semiconductor substrate of an inactive cell. A depth of the floating region is shallower than each depth of the trenches, and is deeper than a depth of the base region.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
The present invention provides a non-volatile memory system capable of suppressing excessive stress to normal cells and ensuring data retention margin of normal cells. In one embodiment of the non-volatile memory system, it determines whether or not error correction is possible for addresses judged to fail in the erase verify process, counts the number of addresses determined to be error-correctable, and if the number of such addresses is less than or equal to a predetermined number, the erase process is determined to be normal.
