The present invention relates to an epitaxial die and a chip die for a semiconductor light-emitting device, and a manufacturing method thereof, wherein only one of two electrodes is exposed to the outside, and a process of forming a positive ohmic contact electrode (p-ohmic contact electrode) or a negative ohmic contact electrode (n-ohmic contact electrode) is completed in an epitaxial die manufacturing step so as to achieve dramatic thickness reduction and easy reduction of the chip die size, thereby improving the light output.
Embodiments according to the present invention comprise a step of preparing a SiC seed substrate having conductivity; a device region forming step; a first fab process step including a doping process for a SiC power semiconductor device and an electrode forming process in the device region; a seed substrate reforming step; an upper temporary substrate bonding step; and a seed region separation step of separating the SiC seed substrate with the reforming layer as a boundary to form a seed region; and wherein the seed region separation step is performed in a process of cooling from a bonding temperature for bonding the upper temporary substrate, and separation is performed without an external force by thermal/mechanical stress due to a difference in thermal expansion rate and thickness on both sides of the reforming layer as a boundary.
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
Embodiments according to the present invention provide a high-quality GaN HEMT power semiconductor epitaxy wafer having a three-dimensional nitride structure, comprising: a growth substrate; a nucleation region formed on the growth substrate; and a three-dimensional nitride structure region formed on the nucleation region and having a composition ratio that varies along a lateral direction.
Embodiments according to the present invention are an AlN thick film-based GaN HEMT epitaxy wafer comprises a growth substrate made of a semi-insulating material or a conductive material, an AlN nucleation region grown on the growth substrate, an AlN stress control region grown on the AlN nucleation region and having an air void or an Al vacancy, an AlN buffer region grown on the AlN stress control region and not including the air void and the Al vacancy, and an active region grown on the AlN buffer region and including a GaN channel region and an AlGaN barrier region.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
Embodiments according to the present invention provide a high-quality GaN HEMT power semiconductor epitaxy wafer having a three-dimensional nitride structure, comprising: a growth substrate; a nucleation region formed on the growth substrate; and a three-dimensional nitride structure region formed on the nucleation region and having a composition ratio that varies along a lateral direction.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 23/373 - Cooling facilitated by selection of materials for the device
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
6.
EPITAXIAL WAFER FOR GAN HEMT WITH ENHANCED ELECTRICAL INSULATION AND MANUFACTURING METHOD THEREOF
Embodiments according to the present disclosure provide an epitaxy wafer for a GaN HEMT with enhanced electrical insulation, comprising: a growth substrate; a nucleation region grown on the growth substrate; a high-resistance region having electrically high resistance characteristics, which comprises a high-resistance unit region defined by a first region grown as a group III nitride semiconductor doped with carbon and a second region grown as a group III nitride semiconductor on the first region, which is provided on the nucleation region; and an active region including a channel region grown on the high-resistance region and a barrier region grown on the channel region.
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
C30B 25/18 - Epitaxial-layer growth characterised by the substrate
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
7.
METHOD FOR MANUFACTURING GAN HEMT DEVICE USING HOT SELF-SPLIT PROCESS
Embodiments according to the present disclosure provide an epitaxy wafer for a GaN HEMT with enhanced electrical insulation, comprising: a growth substrate; a nucleation region grown on the growth substrate; a high-resistance region having electrically high resistance characteristics, which comprises a high-resistance unit region defined by a first region grown as a group III nitride semiconductor doped with carbon and a second region grown as a group III nitride semiconductor on the first region, which is provided on the nucleation region; and an active region including a channel region grown on the high-resistance region and a barrier region grown on the channel region.
The present invention relates to a method for manufacturing a group 3 nitride semiconductor template and a semiconductor template manufactured thereby, wherein a laser lift-off technique and a chemical lift-off technique are used so that a high-quality group 3 nitride semiconductor layer can be formed on the top of a high heat dissipation support substrate having the same or a similar lattice constant and thermal expansion coefficient.
H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10H 20/825 - Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
9.
EPITAXIAL DIE FOR SEMICONDUCTOR LIGHT-EMITTING DEVICE, SEMICONDUCTOR LIGHT-EMITTING DEVICE INCLUDING SAME, AND MANUFACTURING METHODS THEREOF
The present invention relates to an epitaxial die for a semiconductor light-emitting device emitting blue light or green light, a semiconductor light-emitting device including same, and manufacturing methods thereof, wherein in the epitaxial die only one of two electrodes is exposed to the outside, and a process of forming an ohmic contact electrode can be completed in an epitaxial die manufacturing step.
The present invention relates to: an epitaxial die having a structure enabling easy detection of electrical defects in an epitaxial die before an upper wiring process and easy replacement of a defective epitaxial die; a semiconductor light-emitting device using same; and manufacturing methods thereof.
The present invention relates to: a method for manufacturing a group III nitride semiconductor template, by which a high-quality group III nitride semiconductor layer can be formed on the top of a high heat dissipation support substrate having a lattice constant and thermal expansion coefficient equal or similar to those of the group III nitride semiconductor layer, by using a laser lift off (LLO) technique; and a semiconductor template manufactured thereby.
C30B 33/04 - After-treatment of single crystals or homogeneous polycrystalline material with defined structure using electric or magnetic fields or particle radiation
The present invention relates to a method for manufacturing a semiconductor light-emitting device having color conversion technology applied thereto, wherein color conversion technology has been applied to one epitaxial die in which only one of two electrodes is exposed to the outside and which emits blue or ultraviolet rays, enabling the manufacture of a semiconductor light-emitting device emitting each of blue, green, and red light.
One embodiment of the present invention provides a wafer for an epitaxial aluminum nitride bulk acoustic wave filter device through a hot self-split process, the wafer comprising: a support substrate; a wafer bonding layer positioned on the upper side of the support substrate; an acoustic mirror positioned on the upper side of the wafer bonding layer; a lower electrode formed on the upper side of the acoustic mirror; a piezoelectric thin film disposed on the upper side of the lower electrode and grown into a single crystal structure by means of an epitaxial growth method; and an upper electrode disposed on the upper side of the piezoelectric thin film.
H03H 9/17 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
H03H 9/24 - Constructional features of resonators of material which is not piezoelectric, electrostrictive, or magnetostrictive
14.
EPITAXIAL DIE FOR SEMICONDUCTOR LIGHT-EMITTING DEVICE, SEMICONDUCTOR LIGHT-EMITTING DEVICE INCLUDING SAME, AND MANUFACTURING METHODS THEREOF
The present invention relates to an epitaxial die for a semiconductor light-emitting device emitting red light, a semiconductor light-emitting device including same, and manufacturing methods thereof, wherein in the epitaxial die only one of two electrodes is exposed to the outside, and a process of forming an ohmic contact electrode can be completed in an epitaxial die manufacturing step.
The present invention relates to a method for manufacturing a semiconductor device using a semiconductor growth template, and to a method for manufacturing a semiconductor light-emitting device or a power semiconductor device by using a semiconductor growth template including an ultra-thin type sapphire seed layer.
The present invention relates to a method for manufacturing a group 3 nitride semiconductor template, the method comprising: a growing step of growing a seed layer with a nitrogen polar surface as an upper surface on a growth substrate; a depositing step of depositing a protective layer on the seed layer; a bonding step of bonding the protective layer and a support substrate through a bonding layer; and a removing step of removing the growing substrate to expose a metal polar surface of the seed layer.
The present invention relates to a method for manufacturing a microdisplay panel in which a process for aligning LED stacks and CMOS electrode pads is not required, the method comprising: a first step of preparing a support wafer and a front wafer disposed on the support wafer and including a light-emitting portion in which a group 3-5 compound semiconductor is epitaxially grown, and preparing a back wafer having a plurality of CMOS electrode pads aligned on the upper surface thereof; a second step of bonding the front wafer to the back wafer through a bonding layer so that the light-emitting portion faces the CMOS electrode pads, and then removing the support wafer; and a third step of etching the light-emitting portion and the bonding layer to separate same in preset units, whereby the plurality of LED stacks are respectively aligned on the plurality of CMOS electrode pads.
The present invention relates to a vertically stacked LEDoS micro display panel and a manufacturing method therefor, in which an engineering monolithic epitaxy wafer is used when bonding a front wafer and a back wafer to each other, thus making a process for aligning an LED laminate with a CMOS electrode pad unnecessary, and at the same time, each LED laminate emits only light of a specific color, thus making a color filter unnecessary.
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10H 20/813 - Bodies having a plurality of light-emitting regions, e.g. multi-junction LEDs or light-emitting devices having photoluminescent regions within the bodies
Provided is a method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process, the method comprising: a seed substrate preparation step of preparing a seed substrate on which an epitaxial layer for forming a predetermined element is to be grown; a seed substrate reforming step of irradiating a stealth laser onto the seed substrate so as to form a reforming layer inside the seed substrate; a wafer bonding step of wafer-bonding the seed substrate and a support substrate by means of a predetermined wafer bonding layer; a hot self-split step in which each of seed substrates on two sides, with the reforming layer therebetween, has a structural asymmetry or quantitative difference of thermal properties including a thermal expansion coefficient, so as to be separated, without external force, by means of thermal stress or mechanical stress formed on the reforming layer; and a flattening step of flattening two mutually facing surfaces of a seed area formed to be separated from the seed substrate with the seed substrate and the reforming layer as a boundary.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
20.
METHOD FOR MANUFACTURING GROUP III NITRIDE POWER SEMICONDUCTOR DEVICE USING EPITAXIAL DIES
The present invention relates to a method for manufacturing a Group III nitride power semiconductor device using epitaxial dies, by which a high-quality Group III nitride power semiconductor device can be manufacturing by cutting a substrate having epitaxially grown thereon a Group III nitride semiconductor layer so as to form a plurality of epitaxial dies, and then binding the formed plurality of epitaxial dies to a highly heat-dissipating support substrate.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
The present invention relates to a vertically-laminated microdisplay panel requiring no color filter, the panel comprising: a back wafer, the top surface of which has multiple CMOS electrode pads aligned thereon; multiple LED laminates, each of which includes multiple light emitting units and multiple bonding layers vertically laminated on the back wafer, and which are aligned on the multiple CMOS electrode pads, respectively; and a common electrode formed on the multiple LED laminates, wherein each of the multiple LED laminates emits only a particular color by blocking the light generated from at least one light emitting unit among the multiple light emitting units, or having a short passage formed through at least one light emitting unit among the multiple light emitting units to bypass current so as to prevent the current from being injected into the light emitting unit.
H10H 29/34 - Active-matrix LED displays characterised by the geometry or arrangement of subpixels within a pixel, e.g. relative disposition of the RGB subpixels
The present invention relates to a vertically-laminated microdisplay panel requiring no color filter, the panel comprising: a back wafer, the top surface of which has multiple CMOS electrode pads aligned thereon; multiple LED laminates, each of which includes multiple light emitting units and multiple bonding layers vertically laminated on the back wafer, and which are aligned on the multiple CMOS electrode pads, respectively; and a common electrode formed on the multiple LED laminates, wherein each of the multiple LED laminates emits only a particular color by having a short passage formed through at least one light emitting unit among the multiple light emitting units to bypass current so as to prevent the current from being injected into the light emitting unit.
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10H 20/813 - Bodies having a plurality of light-emitting regions, e.g. multi-junction LEDs or light-emitting devices having photoluminescent regions within the bodies
The present invention pertains to a method for manufacturing a semiconductor template, in which a high-quality, highly crystalline Group III metal polar surface is obtained by performing a substrate bonding process only once by selectively growing AlxGa1-xN materials having different polarities on a nominal on-axis c-plane sapphire substrate or Si(111) initial growth substrate without using an expensive off-angle sapphire substrate.
Disclosed is a group III nitride-based epitaxial wafer for HEMP power semiconductors, the wafer comprising: a growth substrate; a nucleation region grown on the growth substrate; and a stress-relieving AlN region grown on the nucleation region and having Ga or In vacancies of nanoscale sizes, or microscale voids.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
25.
METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR TEMPLATE AND GROUP III NITRIDE SEMICONDUCTOR TEMPLATE MANUFACTURED THEREBY
The present invention relates to a method for manufacturing a Group III nitride semiconductor template and a Group III nitride semiconductor template manufactured thereby and, more specifically, to a method for manufacturing a Group III nitride semiconductor template and a Group III nitride semiconductor template manufactured thereby, wherein a seed layer is formed of a single-crystal metal oxide having a corundum crystal structure so that a high-quality Group III nitride semiconductor device active layer can be re-grown.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
26.
METHOD FOR MANUFACTURING GROUP III NITRIDE POWER SEMICONDUCTOR DEVICE, AND GROUP III NITRIDE POWER SEMICONDUCTOR DEVICE MANUFACTURED ACCORDING THERETO
The present invention relates to a method for manufacturing a group III nitride power semiconductor device, and a group III nitride power semiconductor device manufactured according thereto, and, more specifically, to: a method for manufacturing a group III nitride power semiconductor device in which a GaN buffer layer in a conventional power semiconductor device structure is removed and an AlN intermediate layer having high resistance and high heat dissipation performance is provided; and a group III nitride power semiconductor device manufactured according thereto.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
27.
METHOD OF MANUFACTURING CHIP-ON-WAFER FOR MICRO LED DISPLAY
The present invention relates to a method of manufacturing a chip-on-wafer for a micro LED display, the method, using a chip-on-wafer method to manufacture a lateral chip, a flip chip, and a vertical chip for a micro LED display, etching an undoped semiconductor region (uGaN) and an n-type semiconductor region (nGaN) of a semiconductor layer without damaging the chips to allow thickness of the semiconductor layer to be significantly reduced.
H10H 20/00 - Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
H10H 20/82 - Roughened surfaces, e.g. at the interface between epitaxial layers
H10H 20/857 - Interconnections, e.g. lead-frames, bond wires or solder balls
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
28.
METHOD FOR MANUFACTURING GROUP 3 NITRIDE SEMICONDUCTOR TEMPLATE USING DOUBLE SEED LAYER
The present invention relates to a method for manufacturing a Group 3 nitride semiconductor template using a double seed layer, in which a high-quality Group 3 nitride power semiconductor device layer is grown through a double seed layer comprising a first seed layer formed ex-situ at a low temperature and a second seed layer formed in-situ at a high temperature, so that a vertical leakage current can be minimized.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
The present invention relates to a method of producing an epitaxial wafer, the method comprising the steps of: forming a first layer on a growth substrate wafer; depositing a material layer on the first layer; and patterning the material layer to form a plurality of protrusions spaced apart from each other at predetermined intervals. According to the present invention, crystalline defects are hardly generated in regions having protrusions, and crystalline defects such as threading dislocations and the like are only generated on surfaces between the protrusions in conjunction with the growth of materials such as GaN, AlGaN, AlN, etc. Therefore, the crystallinity of epitaxial growth on a GaN-on-Si epitaxial wafer can be greatly improved. Accordingly, the performance and reliability of a HEMT power device and an LED optical device can be improved.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
30.
METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR TEMPLATE WITH IMPROVEMENT IN QUALITY OF BONDING LAYER
The present invention relates to a method for manufacturing a group III nitride semiconductor template with an improvement in the quality of a bonding layer and, more specifically, to a method for manufacturing a group III nitride semiconductor template including a high-quality group III nitride semiconductor seed layer, wherein the quality of the bonding layer can be significantly improved by performing heat treatment on the bonding layer in two steps, according to the temperature.
The present invention relates to a chip-on-wafer manufacturing method for a micro LED display, which can manufacture a high-quality high-brightness micro LED display chip of 3 ㎛ or less by forming an undoped semiconductor region to a desired thickness without damaging the chip, in manufacturing a lateral chip, a flip chip, and a vertical chip for a micro LED display by using a chip-on-wafer method.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies
H01L 33/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
32.
METHOD FOR MANUFACTURING CHIPS ON WAFER FOR MICRO LED DISPLAY
The present invention relates to, in manufacturing, by using a chip on wafer method, a lateral chip, a flip chip, and a vertical chip for a micro LED display, a method for manufacturing chips on wafer for a micro LED display, in which, by molding an undoped semiconductor area to a desired thickness without chip damage, high-quality chips of 3 μm or less for high-luminance micro LED displays may be manufactured.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/38 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes with a particular shape
H01L 33/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
33.
METHOD FOR MANUFACTURING CHIP-ON-WAFER FOR MICRO LED DISPLAY
The present invention relates to a method for manufacturing a chip-on-wafer for a micro LED display, whereby a lateral chip, a flip chip, and a vertical chip for a high-quality, high-brightness micro LED display having a thickness of at most 3 ㎛ can be manufactured by molding an undoped semiconductor region to a desired thickness without damaging the chips when manufacturing the chips for a micro LED display using a chip-on-wafer method.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/06 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
H01L 33/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies
H01L 33/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
34.
VERTICALLY-LAMINATED MICRODISPLAY PANEL REQUIRING NO COLOR FILTER AND MANUFACTURING METHOD THEREOF
The present invention relates to a vertically-laminated microdisplay panel requiring no color filter, the panel comprising: a back wafer, the top surface of which has multiple CMOS electrode pads aligned thereon; multiple LED laminates, each of which includes multiple light emitting units and multiple bonding layers vertically laminated on the back wafer, and which are aligned on the multiple CMOS electrode pads, respectively; and a common electrode formed on the multiple LED laminates, wherein each of the multiple LED laminates emits only a particular color by blocking the light generated from at least one light emitting unit among the multiple light emitting units, or having a short passage formed through at least one light emitting unit among the multiple light emitting units to bypass current so as to prevent the current from being injected into the light emitting unit.
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/14 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 33/38 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes with a particular shape
H01L 33/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
H01L 33/08 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
35.
METHOD FOR MANUFACTURING SEMICONDUCTOR TEMPLATE HAVING GROUP III METAL POLAR SURFACE
x1-x1-xN materials having different polarities on a nominal on-axis c-plane sapphire substrate or Si(111) initial growth substrate without using an expensive off-angle sapphire substrate.
The present invention relates to a vertically stacked LEDoS micro display panel and a manufacturing method therefor, in which an engineering monolithic epitaxy wafer is used when bonding a front wafer and a back wafer to each other, thus making a process for aligning an LED laminate with a CMOS electrode pad unnecessary, and at the same time, each LED laminate emits only light of a specific color, thus making a color filter unnecessary.
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 33/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
H01L 33/14 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
The present invention relates to a vertically-laminated microdisplay panel requiring no color filter, the panel comprising: a back wafer, the top surface of which has multiple CMOS electrode pads aligned thereon; multiple LED laminates, each of which includes multiple light emitting units and multiple bonding layers vertically laminated on the back wafer, and which are aligned on the multiple CMOS electrode pads, respectively; and a common electrode formed on the multiple LED laminates, wherein each of the multiple LED laminates emits only a particular color by having a short passage formed through at least one light emitting unit among the multiple light emitting units to bypass current so as to prevent the current from being injected into the light emitting unit.
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 33/08 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
H01L 33/14 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
The present disclosure relates to a method of manufacturing an aluminum nitride, the method comprising the steps of: preparing a growth substrate; growing an Al1−v−wGavInwN (0≤v<1, 0≤w<1, v+w<1) layer on the growth substrate; conducting etching so that the Al1−v−wGavInwN (0≤v<1, 0≤w<1, v+w<1) layer becomes a porous Al1−v−wGavInwN (0≤v<1, 0≤w<1, v+w<1) layer with a plurality of voids through decomposition and vaporization of gallium (Ga) and indium (In) therein; forming a plurality of voids in the growth substrate by using the porous Al1−v−wGavInwN (0≤v<1, 0≤w<1, v+w<1) layer as an etching mask; and growing an AlN layer on the porous Al1−v−wGavInwN (0≤v<1, 0≤w<1, v+w<1) layer.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
39.
METHOD FOR MANUFACTURING GROUP 3 NITRIDE SEMICONDUCTOR TEMPLATE USING DOUBLE SEED LAYER
The present invention relates to a method for manufacturing a Group 3 nitride semiconductor template using a double seed layer, in which a high-quality Group 3 nitride power semiconductor device layer is grown through a double seed layer comprising a first seed layer formed ex-situ at a low temperature and a second seed layer formed in-situ at a high temperature, so that a vertical leakage current can be minimized.
The present disclosure relates to a method for manufacturing a non-emitting III-nitride semiconductor stacked structure, the method comprising the steps of: preparing a growth substrate containing silicon (Si); forming a plurality of protrusions on the growth substrate; growing a first buffer layer to cover the plurality of protrusions on the growth substrate; forming a plurality of growth prevention films on the first buffer layer, growing a second buffer layer from the first buffer layer exposed through the growth prevention films; and forming a non-emitting III-nitride semiconductor stacked structure on the second buffer layer.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
The present invention relates to a method for manufacturing a microdisplay panel in which a process for aligning LED stacks and CMOS electrode pads is not required, the method comprising: a first step of preparing a support wafer and a front wafer disposed on the support wafer and including a light-emitting portion in which a group 3-5 compound semiconductor is epitaxially grown, and preparing a back wafer having a plurality of CMOS electrode pads aligned on the upper surface thereof; a second step of bonding the front wafer to the back wafer through a bonding layer so that the light-emitting portion faces the CMOS electrode pads, and then removing the support wafer; and a third step of etching the light-emitting portion and the bonding layer to separate same in preset units, whereby the plurality of LED stacks are respectively aligned on the plurality of CMOS electrode pads.
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/22 - Roughened surfaces, e.g. at the interface between epitaxial layers
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01B 1/22 - Conductive material dispersed in non-conductive organic material the conductive material comprising metals or alloys
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
The present invention relates to a method for manufacturing an ultraviolet light-emitting device and, more specifically, to a method for manufacturing an ultraviolet light-emitting device that is capable of high current application, can emit high-power deep ultraviolet rays, and has a thin film-type chip structure with significantly improved heat dissipation ability.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
H01L 33/06 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
H01L 33/22 - Roughened surfaces, e.g. at the interface between epitaxial layers
43.
METHOD FOR MANUFACTURING GROUP III NITRIDE POWER SEMICONDUCTOR DEVICE USING EPITAXIAL DIES
The present invention relates to a method for manufacturing a Group III nitride power semiconductor device using epitaxial dies, by which a high-quality Group III nitride power semiconductor device can be manufacturing by cutting a substrate having epitaxially grown thereon a Group III nitride semiconductor layer so as to form a plurality of epitaxial dies, and then binding the formed plurality of epitaxial dies to a highly heat-dissipating support substrate.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
44.
METHOD FOR MANUFACTURING ULTRA-THIN TYPE SEMICONDUCTOR DIE
The present invention relates to a method for manufacturing an ultra-thin type semiconductor die in which a sapphire substrate of a semiconductor die is molded in an ultra-thin type by bonding, to a second substrate, a semiconductor layer formed on the top surface of a first substrate, and then molding the first substrate in an ultra-thin type, thereby manufacturing a smaller semiconductor light emitting device or power semiconductor device.
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
H01L 21/86 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
H01L 33/38 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes with a particular shape
45.
EPITAXIAL DIE AND CHIP DIE FOR SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND MANUFACTURING METHOD THEREOF
The present invention relates to an epitaxial die and a chip die for a semiconductor light-emitting device, and a manufacturing method thereof, wherein only one of two electrodes is exposed to the outside, and a process of forming a positive ohmic contact electrode (p-ohmic contact electrode) or a negative ohmic contact electrode (n-ohmic contact electrode) is completed in an epitaxial die manufacturing step so as to achieve dramatic thickness reduction and easy reduction of the chip die size, thereby improving the light output.
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 33/38 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes with a particular shape
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 33/20 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
46.
METHOD FOR MANUFACTURING GROUP 3 NITRIDE SEMICONDUCTOR TEMPLATE
The present invention relates to a method for manufacturing a group 3 nitride semiconductor template, the method comprising: a growing step of growing a seed layer with a nitrogen polar surface as an upper surface on a growth substrate; a depositing step of depositing a protective layer on the seed layer; a bonding step of bonding the protective layer and a support substrate through a bonding layer; and a removing step of removing the growing substrate to expose a metal polar surface of the seed layer.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
47.
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SEMICONDUCTOR GROWTH TEMPLATE
The present invention relates to a method for manufacturing a semiconductor device using a semiconductor growth template, and to a method for manufacturing a semiconductor light-emitting device or a power semiconductor device by using a semiconductor growth template including an ultra-thin type sapphire seed layer.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/22 - Roughened surfaces, e.g. at the interface between epitaxial layers
48.
EPITAXIAL DIE FOR SEMICONDUCTOR LIGHT-EMITTING DEVICE, SEMICONDUCTOR LIGHT-EMITTING DEVICE INCLUDING SAME, AND MANUFACTURING METHODS THEREOF
The present invention relates to an epitaxial die for a semiconductor light-emitting device emitting blue light or green light, a semiconductor light-emitting device including same, and manufacturing methods thereof, wherein in the epitaxial die only one of two electrodes is exposed to the outside, and a process of forming an ohmic contact electrode can be completed in an epitaxial die manufacturing step.
H01L 33/38 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes with a particular shape
H01L 33/20 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 33/54 - Encapsulations having a particular shape
H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
49.
EPITAXIAL DIE FOR SEMICONDUCTOR LIGHT-EMITTING DEVICE, SEMICONDUCTOR LIGHT-EMITTING DEVICE INCLUDING SAME, AND MANUFACTURING METHODS THEREOF
The present invention relates to an epitaxial die for a semiconductor light-emitting device emitting red light, a semiconductor light-emitting device including same, and manufacturing methods thereof, wherein in the epitaxial die only one of two electrodes is exposed to the outside, and a process of forming an ohmic contact electrode can be completed in an epitaxial die manufacturing step.
H01L 33/36 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
H01L 33/24 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
H01L 33/30 - Materials of the light emitting region containing only elements of group III and group V of the periodic system
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
The present invention relates to: an epitaxial die having a structure enabling easy detection of electrical defects in an epitaxial die before an upper wiring process and easy replacement of a defective epitaxial die; a semiconductor light-emitting device using same; and manufacturing methods thereof.
H01L 33/38 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes with a particular shape
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
H01L 33/20 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
51.
METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING DEVICE HAVING COLOR CONVERSION TECHNOLOGY APPLIED THERETO
The present invention relates to a method for manufacturing a semiconductor light-emitting device having color conversion technology applied thereto, wherein color conversion technology has been applied to one epitaxial die in which only one of two electrodes is exposed to the outside and which emits blue or ultraviolet rays, enabling the manufacture of a semiconductor light-emitting device emitting each of blue, green, and red light.
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/38 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes with a particular shape
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
52.
METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR TEMPLATE AND SEMICONDUCTOR TEMPLATE MANUFACTURED THEREBY
The present invention relates to: a method for manufacturing a group III nitride semiconductor template, by which a high-quality group III nitride semiconductor layer can be formed on the top of a high heat dissipation support substrate having a lattice constant and thermal expansion coefficient equal or similar to those of the group III nitride semiconductor layer, by using a laser lift off (LLO) technique; and a semiconductor template manufactured thereby.
The present invention relates to a method for manufacturing a group 3 nitride semiconductor template and a semiconductor template manufactured thereby, wherein a laser lift-off technique and a chemical lift-off technique are used so that a high-quality group 3 nitride semiconductor layer can be formed on the top of a high heat dissipation support substrate having the same or a similar lattice constant and thermal expansion coefficient.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/06 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
54.
METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE
The present disclosure relates to a method for manufacturing a semiconductor light emitting device through non-wire bonding, the method comprising the steps of: preparing a semiconductor light emitting die and a support substrate; attaching the semiconductor light emitting die to the support substrate while a second electrical path is exposed, the semiconductor light emitting die being attached such that a conductive bonding structure covering the entire second semiconductor region is tightly bonded to a bonding layer; removing the substrate; and electrically connecting the second electrical path to the remaining semiconductor region among a first semiconductor region and the second semiconductor region through electrical connection through deposition.
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
55.
Method for manufacturing semiconductor light-emitting device
The present disclosure relates to a method of manufacturing a semiconductor light emitting device, the method comprising: providing a growth substrate on which a first semiconductor region, an active region and a second semiconductor region are sequentially formed; bonding a first light transmitting substrate to the second semiconductor region; removing the growth substrate from the first semiconductor region; attaching a second light transmitting substrate through an adhesive layer to the first semiconductor region from which the growth substrate is removed; laser ablating the first light transmitting substrate from the second semiconductor region; exposing part of the first semiconductor region, and forming a first flip chip electrode and a second flip chip electrode on the exposed first semiconductor region and the exposed second semiconductor region, respectively.
The present disclosure relates to a method for manufacturing a non-emitting III-nitride semiconductor stacked structure, the method comprising the steps of: preparing a growth substrate containing silicon (Si); forming a plurality of protrusions on the growth substrate; growing a first buffer layer to cover the plurality of protrusions on the growth substrate; forming a plurality of growth prevention films on the first buffer layer; growing a second buffer layer from the first buffer layer exposed through the growth prevention films; and forming a non-emitting III-nitride semiconductor stacked structure on the second buffer layer.
Disclosed is a method for manufacturing a supporting substrate for a semiconductor light emitting device, the method including: preparing a substrate having a groove; introducing a material into the groove of the substrate, the material serving to form a thermal and/or electrical pass; and compressing the material inwards from both ends of the groove, using a compressing means.
The present disclosure relates to a support substrate for a semiconductor light-emitting device, comprising: a body which includes an upper surface and a lower surface and supports the semiconductor light-emitting device on the upper surface; a first conductive foil electrode and a second conductive foil electrode embedded in the body; a first upper groove and a second upper groove connected from the upper surface to the first conductive foil electrode and the second conductive foil electrode, respectively; a first lower groove and a second lower groove connected from the lower surface to the first conductive foil electrode and the second conductive foil electrode, respectively; and a first expansion electrode and a second expansion electrode which are respectively connected from the first conductive foil electrode and the second conductive foil electrode to the lower surface through the first lower groove and the second lower groove.
The present disclosure relates to a method of manufacturing an LED package, the method comprising the steps of: preparing an LED chip having a vertical structure, the horizontal and the vertical width of which correspond to a size of 200㎛ x 200㎛ or less; surrounding the LED chip with a white or black mold part so that a first electrode and a first semiconductor area are exposed; forming, through the mold part, a first through-hole extending from the lower surface to the upper surface to enable electric communication with the first electrode and a second through-hole extending from the lower surface to a supporting body to enable electric communication with the supporting body; and forming a first extension electrode electrically communicating with the first electrode through the first through-hole and a second extension electrode electrically communicating with the supporting body through the second through-hole.
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
C23C 14/06 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
H10N 30/00 - Piezoelectric or electrostrictive devices
H10N 30/076 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing by vapour phase deposition
H10N 30/079 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing using intermediate layers, e.g. for growth control
The present disclosure relates to a semiconductor light-emitting device and a method for manufacturing same, the semiconductor light-emitting device comprising: a permanent support substrate; a light-emitting part comprising a first semiconductor region, a second semiconductor region and an active area generating light by means of electron-hole recombination; a first electrode electrically connected to the first semiconductor region; a second electrode electrically connected to the second semiconductor region; an interposed layer provided between the second electrode and second semiconductor region to enable electrical communication between the second electrode and second semiconductor region; and a passivation layer exposing the first electrode and second electrode, connecting from the first electrode and second electrode to the interposed layer and light-emitting part, and covering up to the lateral sides of the permanent support substrate.
H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
H01L 33/38 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes with a particular shape
H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
H01L 33/36 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes
H01L 33/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
Disclosed is a semiconductor light emitting device comprising a semiconductor light emitting chip having electrodes; a mold, which has a first surface roughness and includes a bottom portion where the semiconductor light emitting chip is arranged and through holes formed in the bottom portion, with the through holes being comprised of a surface having a second surface roughness different from the first surface roughness, wherein at least one side of the mold facing the semiconductor light emitting chip is made of a material capable of reflecting at least 95% of light emitted by the semiconductor light emitting chip; and conductive parts provided in the through holes for electrical communication with the electrodes.
The present disclosure relates to a method for manufacturing a III-nitride semiconductor device, the method comprising the steps of: growing, on a growth substrate, a III-nitride semiconductor structure having a channel layer and a barrier layer; attaching a temporary substrate to the side of the III-nitride semiconductor structure facing the growth substrate, through a metal adhesive layer; removing the growth substrate; coupling a heat dissipation substrate to the side of the III-nitride semiconductor structure from which the growth substrate has been removed; and removing the temporary substrate.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
65.
METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING DEVICE
The present disclosure relates to a method for manufacturing a semiconductor light-emitting device, the method comprising the steps of: providing a growth substrate on which a first semiconductor region, an active region, and a second semiconductor region are sequentially formed; bonding a first light-transmitting substrate to the second semiconductor region; removing the growth substrate from the first semiconductor region; attaching a second light-transmitting substrate to the first semiconductor region, from which the growth substrate has been removed, by using an adhesive layer; ablating the first light-transmitting substrate from the second semiconductor region by means of laser; exposing a portion of the first semiconductor region; and forming a first electrode of a flip chip and a second electrode of the flip chip in the exposed first semiconductor region and the second semiconductor region, respectively.
A template for growing Group III-nitride semiconductor layers, a Group III-nitride semiconductor light emitting device and methods of manufacturing the same are provided. The template for growing Group III-nitride semiconductor layers includes a growth substrate having a first plane, a second plane opposite to the first plane and a groove extending inwards the growth substrate from the first plane, an insert for heat dissipation placed and secured in the groove, and a nucleation layer formed on a partially removed portion of the first plane.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
The present disclosure relates to a method for manufacturing a semiconductor light emitting device, a semiconductor device including the supporting substrate, and a method for manufacturing the supporting substrate, in which the method includes: providing a first substrate having a first face and a second face opposite to the first face; forming a groove in the first substrate in a direction from the first face to the second face; forming a conducting part in the groove; bonding a second substrate to the first face of the first substrate; and forming, on the second face, a first conducting pad to be in electrical communication with the conducting part.
The disclosed invention relates to a semiconductor light-emitting element comprising: a plurality of semiconductor layers which are provided with a growth substrate eliminating surface on the side where a first semiconductor layer is located; a support substrate which is provided with a first electrical pathway and a second electrical pathway; a joining layer which joins a first surface side of the support substrate with a second semiconductor layer side of the plurality of semiconductor layers, and is electrically linked with the first electrical pathway; a joining layer eliminating surface which is formed on the first surface, and in which the second electrical pathway is exposed, and which is open towards the plurality of semiconductor layers; and an electrical link for electrically linking the plurality of semiconductor layers with the second electrical pathway exposed in the joining layer eliminating surface.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 33/38 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes with a particular shape
H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
H01L 33/06 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
The present disclosure relates to a semiconductor light emitting device, comprising: a supporting substrate having a first surface and a second surface opposite to the first surface; at least one semiconductor stack formed on the first surface, wherein each stack includes a plurality of semiconductor layers grown sequentially using a growth substrate and composed of a first semiconductor layer, a second semiconductor layer, and an active layer generating light via electron-hole recombination, and wherein a growth substrate-removed surface is formed on the side of the first semiconductor layer; a bonded layer, which bonds the second semiconductor layer side of the plurality of semiconductor layers to the first surface side of the supporting substrate; and a bonded layer-removed surface formed on the first surface, being open towards the plurality of semiconductor layer to supply current thereto.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/38 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes with a particular shape
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 33/06 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
patents
