Abstract

An audio amplification device includes a charge pump circuit and an operational amplifier. The charge pump circuit generates an output voltage when receiving a power-on reset signal. The operational amplifier has a first input terminal for receiving a first input signal, a second input terminal for receiving a second input signal, a third input terminal for receiving the output voltage, a fourth input terminal for receiving a switching signal output, and an output terminal. The operational amplifier generates an amplified signal at the output terminal according to the first and second input signals, the output voltage and the switching signal output and outputs the amplified signal to a load circuit. When a level of the power-on reset signal changes from a high logic level to a low logic level, the operational amplifier is controlled by the switching signal output to pull a potential of the output terminal to zero.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage
• H03F 3/185 - Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only with field-effect devices
• H03G 3/30 - Automatic control in amplifiers having semiconductor devices

Abstract

An automatic gain controller includes multiple resistors, multiple switches, a buffer, a charge pump circuit and a voltage level shifter. The resistors are connected in series between an input terminal for receiving an input signal and an inverting input terminal of an operational amplifier. Each of the switches has a first terminal coupled to a corresponding one of the resistors, and a second terminal coupled to the inverting input terminal. The switches are respectively controlled by multiple switching signals so as to be turned on or turned off. The buffer generates a buffer signal according to the voltage at the inverting input terminal. The charge pump circuit generates a boost voltage according to the buffer signal and a clock signal. The voltage level shifter converts voltage levels of multiple control signals according to the buffer signal and the boost voltage to generate and respectively output the switching signals to the switches.

IPC Classes  ?

• H03G 3/30 - Automatic control in amplifiers having semiconductor devices

Abstract

A power stage control circuit applied to a voltage converter includes a current sensing circuit, a control circuit, and a driving circuit, wherein the voltage converter includes a first switch and a second switch. The current sensing circuit senses a current associated with the first switch, and converts current into a sensing voltage. The control circuit performs multiple first logical operations according to the sensing voltage, a second switch driving signal, a zero crossing detection voltage, a compensation voltage, and a reference voltage, in order to generate a modulation signal and a determination signal, for controlling turn-on and turn-off of the first switch and the second switch and dynamically setting an inductor peak current of an inductor, respectively. The driving circuit performs multiple second logical operations according to the modulation signal and the determination signal in order to generate a first switch driving signal and the second switch driving signal.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H02M 1/00 - Details of apparatus for conversion

Abstract

In a power converter, a phase controller divides a full COT control signal into a master COT control signal and at least one slave COT control signal. The master COT control signal triggers a master PWM-signal generator to generate a master PWM signal accordingly, and each slave COT control signal triggers a corresponding slave PWM-signal generator to generate the slave PWM signal for a corresponding slave driver by adjusting a width of each pulse of the corresponding slave COT control signal according to a comparison between a sensed current of a master driver and a sensed current of the corresponding slave driver. Then, the master driver provides a master current output for a load device according to a master PWM signal, and each slave driver provides a slave current output for the load device according to the slave PWM signal corresponding thereto.

IPC Classes  ?

• H02M 1/15 - Arrangements for reducing ripples from DC input or output using active elements
• H02M 1/084 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters using a control circuit common to several phases of a multi-phase system
• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Abstract

An audio amplifier chip includes an audio amplifier, a current providing circuit, a detection circuit, and a control circuit. The audio amplifier is arranged to drive a speaker, wherein the audio amplifier has multiple differential input terminals, and a direct current (DC) blocking capacitor is coupled to one of the multiple differential input terminals. The current providing circuit is arranged to provide at least one current for charging the DC blocking capacitor. The detection circuit is coupled to a node located between the one of the multiple differential input terminals and the DC blocking capacitor, and is arranged to detect whether an external resistor of the audio amplifier chip exists according to an input voltage from the node, in order to generate a detection result. The control circuit is arranged to determine a start-up time of the audio amplifier according to the detection result.

IPC Classes  ?

• H03F 3/183 - Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only

Abstract

A voltage level shifter includes a first voltage regulation unit, a second voltage regulation unit, a first latch unit and an output unit. The first voltage regulation unit and the second voltage regulation unit respectively receive first and second input signals and generate first and second adjustment signals respectively. The first latch unit receives the first and second adjustment signals and generates a first latch signal accordingly. The output unit generates an output signal according to the first latch signal, an input voltage and a control signal. A high logic level voltage of the output signal is greater than the respective high logic level voltages of the first input signal and the second input signal. Wherein, the first voltage regulation unit and the second voltage regulation unit are each a capacitively coupled voltage regulation unit and each includes an input capacitor. The input capacitor has no capacitance to ground at one end.

IPC Classes  ?

• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
• H03K 3/356 - Bistable circuits
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only

Abstract

A charge pump device includes a voltage adjustment unit, an output capacitor, a first output unit and a second output unit. The voltage adjustment unit performs voltage pumping or voltage reducing operation on a power supply voltage according to first to fourth control signals, a positive pump voltage and an negative pump voltage to generate a first voltage adjustment output and a second voltage adjustment output at a first node and a second node respectively. The output capacitor has a first output terminal and a second output terminal. When the first output unit is turned on, the first voltage adjustment output charges the output capacitor through the first output unit, so that the first output terminal generates the positive pump voltage. When the second output unit is turned on, the second voltage adjustment output charges the output capacitor through the second output unit, so that the second output terminal generates the negative pump voltage. When the first output unit is turned on, the second output unit is not turned on. When the second output unit is turned on, the first output unit is not turned on.

IPC Classes  ?

• H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
• H02M 1/00 - Details of apparatus for conversion

Abstract

The oscillator includes a reference current generating circuit, a voltage modulator circuit, and an oscillating circuit. The reference current generating circuit is arranged to generate a reference current. The voltage modulator circuit is arranged to receive a feedback voltage, and perform a voltage modulation operation according to a first reference voltage and the feedback voltage, to generate a modulated voltage. The oscillating circuit is coupled to the reference current generating circuit and the voltage modulator circuit, and arranged to generate an oscillation signal with an oscillation frequency according to the reference current and the modulated voltage.

IPC Classes  ?

• H03K 5/01 - Shaping pulses
• H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device

Abstract

A controller applied to a servomotor includes a flash memory, a microcontroller, and a processing circuit. The flash memory is arranged to store a first program code for controlling the servomotor. The microcontroller is arranged to determine whether an alarm of the servomotor occurs, wherein in response to the alarm of the servomotor occurring, the microcontroller is arranged to store an error log corresponding to the alarm in the flash memory. In addition, a second program code is programmed into the processing circuit in advance, wherein the second program code is a copied version of the first program code; and in response to the alarm of the servomotor occurring, the processing circuit is arranged to execute the second program code.

IPC Classes  ?

• G05B 19/4155 - Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by programme execution, i.e. part programme or machine function execution, e.g. selection of a programme

Abstract

A write leveling system includes a frequency divider, a signal processing circuit, and a data control circuit. The frequency divider is arranged to perform a frequency dividing operation upon a clock signal to generate multiple frequency-divided clock signals. The signal processing circuit is arranged to perform signal processing upon a data strobe signal to generate multiple processed data strobe signals. The data control circuit is arranged to generate a data signal according to the multiple frequency-divided clock signals and the multiple processed data strobe signals, for indicating whether a rising edge of the data strobe signal is located at a first level or a second level of the clock signal, wherein the first level is higher than the second level.

IPC Classes  ?

• G11C 11/4076 - Timing circuits
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A signal recovery system includes multiple frequency dividers, multiple signal recovery circuits, and a data signal generating circuit. The multiple frequency dividers perform a frequency dividing operation upon a clock signal and a data strobe signal, respectively, to generate a set of frequency-divided clock signals and a set of frequency-divided data strobe signals. The multiple signal recovery circuits perform a signal recovery operation upon the set of frequency-divided clock signals and the set of frequency-divided data strobe signals, respectively, to generate a recovered clock signal and a recovered data strobe signal. The data signal generating circuit generates a data signal according to the recovered clock signal and the recovered data strobe signal, for indicating whether a rising edge of the data strobe signal is located at a first level or a second level of the clock signal, wherein the first level is higher than the second level.

IPC Classes  ?

• H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
• H03L 7/08 - Details of the phase-locked loop

Abstract

A method for enabling a permanent magnet synchronous motor (PMSM) to start in a reverse direction may include: estimating a load torque according to a torque and an actual rotational speed of the PMSM, to generate an estimated load torque; controlling the torque according to the estimated load torque to decelerate the PMSM, until the actual rotational speed of the PMSM is reduced to a predetermined target rotational speed; in response to the actual rotational speed of the PMSM being reduced to the predetermined target rotational speed, determining whether an energy of the PMSM is not greater than a threshold value, wherein the energy of the PMSM comprises a potential energy; and in response to the energy of the PMSM not being greater than the threshold value, starting to control the torque for making the PMSM rotate in a forward direction.

IPC Classes  ?

• H02P 21/34 - Arrangements for starting
• H02P 21/00 - Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
• H02P 21/20 - Estimation of torque

Abstract

A Class-D audio amplifier includes a triangular wave generator, a wave reshaping device and a pulse-width modulator. The triangular wave generator generates a first triangular wave. The wave reshaping device generates a second triangular wave by reshaping the first triangular wave. The pulse-width modulator modulates a pair of differential audio input waves with the second triangular wave instead of the first triangular wave to reduce a switching loss of the Class-D audio amplifier.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03K 3/037 - Bistable circuits

Goods & Services

Design of integrated circuits; design of semiconductor chips; design and development of computers and programs for computers; development and creation of computer programmes for data processing; research in the field of computer software; technological research in the field of computer hardware systems; product research and development; technical writing; research and development of new products for others; technological consultation in the technology field of semiconductor; technological consultation in the technology field of integrated circuit.

Goods & Services

Design of integrated circuits; design of semiconductor chips; design and development of computers and programs for computers; development and creation of computer programmes for data processing; research in the field of computer software; technological research in the field of computer hardware systems; product research and development; technical writing; research and development of new products for others; technological consultation in the technology field of semiconductor; technological consultation in the technology field of integrated circuit.

Goods & Services

chips [integrated circuits]; semiconductors; integrated circuits; semiconductor chips; computer memory; computer program; printed circuit boards. design of integrated circuits; design of semiconductor chips; design of computer program; processing of computer data; research of computer software; research of computer hardware; providing research and development; technical writing; research and development of new products for others; semiconductor technology consultancy; integrated circuit technology consultancy.

Goods & Services

chips [integrated circuits]; semiconductors; integrated circuits; semiconductor chips; computer memory; computer program; printed circuit boards. design of integrated circuits; design of semiconductor chips; design of computer program; processing of computer data; research of computer software; research of computer hardware; providing research and development; technical writing; research and development of new products for others; semiconductor technology consultancy; integrated circuit technology consultancy.

Abstract

An audio amplifier includes a loop filter, at least one high pass filter (HPF) circuit, a pulse width modulation (PWM) generator, and a power stage. The loop filter is arranged to receive an audio signal and a feedback signal, and includes a first amplifier and a second amplifier, wherein the first amplifier has a first output node, and is arranged to process the audio signal and the feedback signal; the second amplifier has a first input node, and is arranged to receive a first amplifier input and a second amplifier input; and the first amplifier input is obtained from a signal path coupled between the first output node and the first input node. The at least one HPF circuit is coupled between the first amplifier and the second amplifier, and is arranged generate and output the second amplifier input according to an amplifier output of the first amplifier.

IPC Classes  ?

• H03F 3/187 - Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements

Abstract

A repairable semiconductor memory device includes an input/output bus, a plurality of stacked memory chips, and a redundant repair unit. Each of the memory chips compares a memory address information with an address information to be repaired to generate a first comparison result for determining whether to allow the input/output bus to access the data corresponding to the memory address information in the memory chips. The redundancy repair unit compares the memory address information with the address information to be repaired to generate a second comparison result for determining whether to allow a redundant memory cell corresponding to the memory address information to be coupled to the input/output bus. In this way, the semiconductor memory device can repair any layer of the memory chips to improve the yield to solve the problem of previously having a lower yield.

IPC Classes  ?

• G06F 11/00 - Error detectionError correctionMonitoring
• G06F 11/16 - Error detection or correction of the data by redundancy in hardware
• G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
• G11C 29/18 - Address generation devicesDevices for accessing memories, e.g. details of addressing circuits
• G11C 29/44 - Indication or identification of errors, e.g. for repair

Abstract

A device for estimating the temperature of a loudspeaker's voice coil includes a signal generator, a signal adjuster, an adder, and a temperature estimator. The signal generator generates and outputs an amplified signal to a loudspeaker according to a measurement signal and an audio signal, and senses a voltage and a current of the amplified signal to generate and output a sensory output. The signal adjuster generates and outputs an inverted signal according to the audio signal. The adder adds the sensory output and the inverted signal to generate a blended signal. The temperature estimator obtains an estimated resistance value of the loudspeaker's voice coil according to the blended signal, and generates a temperature signal according to the estimated resistance value, wherein the temperature signal indicates an estimated temperature value of the loudspeaker's voice coil. Additionally, a method for estimating the temperature of the loudspeaker voice coil is provided.

IPC Classes  ?

• G01K 7/16 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements
• H04R 3/00 - Circuits for transducers
• H04R 29/00 - Monitoring arrangementsTesting arrangements

Abstract

A noise elimination device for a Class-D audio amplifier includes a residual signal detector and a multiplexer, wherein the multiplexer is electrically connected with a sigma-delta modulator (SDM) and a pulse width modulator (PWM) of the Class-D audio amplifier and the residual signal detector. The residual signal detector is configured to detect whether an input signal of the Class-D audio amplifier is residual. The multiplexer is configured to output zero data into the pulse width modulator when the residual signal detector detects that the input signal of the Class-D audio amplifier is residual.

IPC Classes  ?

• H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• H03F 3/217 - Class D power amplifiersSwitching amplifiers

Abstract

A bootstrap device used for first and second transistors of a buck-boost converter includes first and second bootstrap circuits. The first bootstrap circuit generates a first bootstrap voltage, and determines, based on a change among a first switching voltage, a voltage level of a source terminal of the first transistor and the first bootstrap voltage, whether to charge according to at least one of a DC input voltage, a DC output voltage, and a second bootstrap voltage. The second bootstrap circuit generates the second bootstrap voltage, and determines, based on a change among a second switching voltage, a voltage level of a source terminal of the second transistor, and the second bootstrap voltage, whether to charge according to at least one of the DC input voltage, the DC output voltage, and the first bootstrap voltage. The bootstrap device improves charging efficiency of bootstrap capacitors.

IPC Classes  ?

• H02M 1/15 - Arrangements for reducing ripples from DC input or output using active elements
• H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H03K 17/06 - Modifications for ensuring a fully conducting state

Abstract

Circuit, method for audio signal processing with excursion estimation compensation, and non-transitory storage medium are provided. The circuit comprises a delay circuit, compensation filter, excursion estimator, peak detector, gain determination circuit, and gain adjustment circuit. The delay circuit is for delaying a digital audio signal to output a delayed digital audio signal. The compensation filter is for generating a compensated digital audio signal according to the digital audio signal for excursion estimation compensation for a speaker type. The excursion estimator is for determining an estimated excursion signal for the speaker type according to the compensated digital audio signal. The gain determination circuit is for generating a gain setting signal according to the estimated excursion signal and a threshold value. The gain adjustment circuit is for generating an adjusted digital audio signal according to the gain setting signal and delayed digital audio signal.

IPC Classes  ?

• H03G 11/00 - Limiting amplitudeLimiting rate of change of amplitude
• H04R 3/00 - Circuits for transducers
• H04R 3/04 - Circuits for transducers for correcting frequency response
• H04R 29/00 - Monitoring arrangementsTesting arrangements

Goods & Services

Motor controller, namely, electronic servo motor controllers and electronic controls for motors

Goods & Services

Downloadable computer operating programs; Recorded computer operating programs; Downloadable computer operating software; Recorded computer operating software; flash memory, namely, semi-conductor memories including a solid state storage for a nonvolatile storage medium that employs integrated circuits; dynamic random-access memory card (DRAM); sensors, namely, sensor chips for scientific use, electronic proximity sensors, and temperature sensors Design of integrated circuits; design of semiconductor chips; research and development of new products for others; design of computer program; providing research and development, namely, scientific research and development and research and development of new products; technical writing; semiconductor technology consultancy in the field of testing and design of semiconductors; integrated circuit technology consultancy in the field of design of integrated circuits

Abstract

A load detection device includes a signal output circuit, comparison circuit, sensing circuit, detection circuit, logic circuit, and control circuit. The signal output circuit outputs a forced current, and generates a bias signal, a first output signal, a second output signal, and a feedback signal depending on the forced current. The comparison circuit compares the reference signal output with the first and second output signals to generate an accurate comparison output for indicating the load state. The sensing circuit generates a sensing signal according to the feedback signal. The detection circuit generates a rough detection output for indicating the load state according to the sensing signal and the first and second output signals. The logic circuit obtains the load state according to the precise comparison output and the rough detection output. The control circuit enables the signal output circuit, comparison circuit, sensing circuit, and logic circuit.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03F 3/187 - Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
• H04R 5/04 - Circuit arrangements
• H04R 29/00 - Monitoring arrangementsTesting arrangements

Abstract

An electronic device and a method for overcurrent detection are disclosed herein. The electronic device causes a high-side offsetting voltage drop and converts a voltage difference between a first voltage at an input terminal of an upper-bridge power component of a power stage and a sum of a first balancing voltage drop and the high-side offsetting voltage drop into a first current. The electronic device further converts a voltage difference between a second voltage of an output terminal of the upper-bridge power component and a second balancing voltage drop into a second current, compares the first current and the second current, and generates a high-side overcurrent protection (OCP) signal with logic high for a driver of the power stage when the first current is stronger than the second current, such that the driver turns off the upper-bridge power component accordingly.

IPC Classes  ?

• H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage
• G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
• G05F 3/26 - Current mirrors
• H03K 3/023 - Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
• H03K 5/22 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
• H03K 17/567 - Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
• H03K 19/0175 - Coupling arrangementsInterface arrangements
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

An inductor driving device includes multiple switching elements and a control circuit, wherein an inductor is driven according to switching of the multiple switching elements. The control circuit is arranged to generate a control signal for controlling the multiple switching elements. In a first mode, the control signal has a constant frequency. In a second mode, the control circuit adjusts a frequency of the control signal and continuously changes a current direction of the inductor, to generate one of multiple audio signals through the inductor.

IPC Classes  ?

• G05B 19/4062 - Monitoring servoloop, e.g. overload of servomotor, loss of feedback or reference
• G08B 3/00 - Audible signalling systemsAudible personal calling systems

Abstract

A capacitance measurement circuit includes a charge to voltage converter (CVC) that includes at least one first variable capacitor, an excitation signal generation circuit, a differential amplifier, a first switch circuit, and at least one second variable capacitor, wherein a parasitic capacitance from a sensing capacitance sensed by a capacitance sensor is reduced by the at least one first variable capacitor. The excitation signal generation circuit is arranged to generate and connect a first excitation signal to the capacitance sensor, and generate and connect a second excitation signal to the at least one first variable capacitor, wherein the first excitation signal and the second excitation signal are out-of-phase, and a voltage amplitude of the first excitation signal is different from a voltage amplitude of the second excitation signal. The inverting input terminal of the differential amplifier is arranged to receive the sensing capacitance from the capacitance sensor.

IPC Classes  ?

• G01R 27/26 - Measuring inductance or capacitanceMeasuring quality factor, e.g. by using the resonance methodMeasuring loss factorMeasuring dielectric constants
• G01D 5/24 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance

Goods & Services

Design of integrated circuits; Research and development of new products for others; Computer programming; Technical writing; Technology consultation and research in the field of computer hardware, computer software, chips, namely, integrated circuits, semiconductors, integrated circuits and flash memory; Product development consulting in the field of computer hardware, computer software, chips, namely, integrated circuits, semiconductors, integrated circuits and flash memory; Research and development and consultation related thereto in the field of computer hardware, computer software, chips, namely, integrated circuits, semiconductors, integrated circuits and flash memory

Goods & Services

Design of integrated circuits; Research and development of new products for others; Computer programming; Technical writing; Technology consultation and research in the field of computer hardware, computer software, chips, namely, integrated circuits, semiconductors, integrated circuits and flash memory; Research and development and consultation related thereto in the field of computer hardware, computer software, chips, namely, integrated circuits, semiconductors, integrated circuits and flash memory; Product development consulting in the field of computer hardware, computer software, chips, namely, integrated circuits, semiconductors, integrated circuits and flash memory

Goods & Services

Design of integrated circuits; Research and development of new products for others; Computer programming; Technical writing; Technology consultation and research in the field of computer hardware, computer software, chips, namely, integrated circuits, semiconductors, integrated circuits and flash memory; Research and development and consultation related thereto in the field of computer hardware, computer software, chips, namely, integrated circuits, semiconductors, integrated circuits and flash memory; Product development consulting in the field of computer hardware, computer software, chips, namely, integrated circuits, semiconductors, integrated circuits and flash memory

Goods & Services

Chips [integrated circuits]; semiconductors; integrated circuits; printed circuits; printed circuit boards; flash memory. Design of integrated circuits; design of semiconductor chip; research and development of new products for others; computer programming; research and development services; technical writing; technical consultancy in the field of semiconductor processing technology; technical consultancy in relation to the production of semiconductors; technical consultancy in the field of semiconductor design services; technical consultancy in the field of integrated circuit technology.

Goods & Services

Computer program and computer software; flash memory; random-access memory; motor controller; sensor. Design of integrated circuits; design of semiconductor chips; research and development of new products for others; design of computer program; providing research and development; technical writing; semiconductor technology consultancy; integrated circuit technology consultancy.

Abstract

A voltage mode controlled linear frequency modulation oscillator comprises a voltage modulation circuit, a reference current generating circuit, and an oscillating circuit. The voltage modulation circuit is configured to generate a modulation voltage according to a feedback voltage and a first reference voltage. The reference current generating circuit, coupled to the voltage modulation circuit, is configured to generate a first reference current according to the modulation voltage and a second reference voltage. The oscillating circuit, coupled to the reference current generating circuit, is configured to generate an oscillating signal with an oscillating frequency according to the first reference current, wherein the oscillating frequency varies with the modulation voltage.

IPC Classes  ?

• H03K 3/0231 - Astable circuits
• H03B 5/04 - Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
• H03K 7/06 - Frequency or rate modulation, i.e. PFM or PRM

Abstract

A loudspeaker excursion prediction system, which is suitable for a loudspeaker protection circuit comprises a low-pass filter circuit, a down-sampling circuit, and an impulse response generation unit. The low-pass filter circuit is configured to generate an audio signal XLPF(t) passing through the low-pass filter circuit according to an audio signal X(t) with a first sampling frequency. A down-sampling circuit, coupled to the low-pass filter circuit, is configured to down-sampling the first sampling frequency of the audio signal XLPF(t) output from the low-pass filter circuit to a second sampling frequency, so as to generate a down-sampled audio signal XLPFDN(t). The impulse response generation unit, coupled to the down-sampling circuit, is configured to generate an excursion prediction value according to a loudspeaker excursion transfer function and the down-sampled audio signal XLPFDN(t).

IPC Classes  ?

• H04R 3/00 - Circuits for transducers
• H03G 3/20 - Automatic control
• H04R 29/00 - Monitoring arrangementsTesting arrangements

Abstract

An abnormal current protection device includes an overcurrent protector and a controller, and the overcurrent protector includes a short-circuit detection unit and an overcurrent detection unit. The short-circuit detection unit is configured to detect whether there is a short-circuit event within a period of debounce time of a protection cycle. The overcurrent detection unit is configured to detect whether there is an overcurrent event after the period of debounce time within the protection cycle. The controller is configured to disable a converter when the short-circuit event is detected, and disable a power stage when the overcurrent event is detected.

IPC Classes  ?

• H02H 3/08 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current
• H02H 1/00 - Details of emergency protective circuit arrangements
• H02H 7/122 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for convertersEmergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for rectifiers for static converters or rectifiers for inverters, i.e. DC/AC converters

Abstract

A method for estimating a rotor angle and a rotor speed of a permanent magnet synchronous motor (PMSM) includes: receiving a d-axis voltage driving signal of the PMSM, and obtaining a first estimated rotor speed of the PMSM according to the d-axis voltage driving signal; receiving a speed command, and obtaining a second estimated rotor speed of the PMSM according to the speed command; performing a weighting adjustment operation upon the first estimated rotor speed and the second estimated rotor speed to obtain a third estimated rotor speed for estimating the rotor speed of the PMSM; and performing an integration operation upon the third estimated rotor speed to obtain an estimated rotor angle for estimating the rotor angle of the PMSM.

IPC Classes  ?

• H02P 23/14 - Estimation or adaptation of motor parameters, e.g. rotor time constant, flux, speed, current or voltage
• H02P 25/022 - Synchronous motors

Abstract

An active clamp photoelectric sensing device includes an input terminal, a first output terminal, a current-to-voltage conversion circuit, and an active clamp circuit. The input terminal receives an input current. The first output terminal outputs a first output voltage. The current-to-voltage conversion circuit is coupled between the input terminal and the first output terminal, and is used to discharge and lower potentials of the input terminal and the first output terminal to a first set voltage according to the state of a reset signal, or is used to gradually increase the first output voltage to a second set voltage. The active clamping circuit is coupled to the current-to-voltage conversion circuit, and is used to clamp the upper limit of the first output voltage to the second set voltage.

IPC Classes  ?

• G01J 1/44 - Electric circuits
• G01J 1/02 - Photometry, e.g. photographic exposure meter Details
• H03F 3/08 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
• H03G 3/30 - Automatic control in amplifiers having semiconductor devices

Abstract

A photoelectric sensing device for cancelling crosstalk includes a first capacitor; a first switch, coupled between a current source and the first capacitor, is turned on according to a driving signal, and enables the current source to charge the first capacitor to generate a first capacitor voltage; a second switch, coupled between the first capacitor and an input terminal, is turned on according to a cancellation signal; a current-voltage conversion circuit, coupled to the second switch, receiving an input current corresponding to a crosstalk signal, and generating a crosstalk voltage corresponding to the input current. Wherein, when the second switch is turned on, the crosstalk voltage is subtracted from the first capacitor voltage to cancellate the crosstalk signal, so as to output a correct sensing voltage.

IPC Classes  ?

• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
• H03K 3/013 - Modifications of generator to prevent operation by noise or interference
• H03K 3/0233 - Bistable circuits
• H03K 17/96 - Touch switches
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only

Abstract

An electronic device includes a sampling circuit and a summing circuit coupled with the sampling circuit. The sampling circuit samples a pulse width of a first input pulse of a PWM input signal since a first time point on a rising edge of a clock pulse of a clock signal. The summing circuit generates a first output pulse of a PWM output signal since a second time point on a falling edge of the clock pulse. A pulse width of the first output pulse is a summation of the pulse width of the first input pulse and a pulse width of a second input pulse of the PWM input signal, and the second input pulse is the next pulse after the first input pulse.

IPC Classes  ?

• H03K 3/017 - Adjustment of width or dutycycle of pulses
• H03K 3/037 - Bistable circuits
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
• H04R 3/00 - Circuits for transducers
• H04R 29/00 - Monitoring arrangementsTesting arrangements

Abstract

A control method applied to a servomotor, wherein the servomotor includes a motor, and the control method includes: setting a mode of the servomotor as a predetermined mode corresponding to a predetermined communication protocol; receiving an input signal from a controller for controlling the motor, wherein the controller is coupled to the servomotor; and switching the mode of the servomotor from the predetermined mode to one of a plurality of candidate modes according to a frequency of the input signal.

IPC Classes  ?

• G05B 19/4155 - Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by programme execution, i.e. part programme or machine function execution, e.g. selection of a programme

Abstract

A charger circuit comprises a constant current charging circuit and a thermal regulation circuit. The constant current charging circuit is configured for generating a charging current, including a charger input terminal for receiving an input voltage, a charge current setting terminal, a charger output terminal for outputting the charging current, a current mirror including a reference current path between the charger input terminal and charge current setting terminal and an output current path between the charger input terminal and charger output terminal, and a feedback amplifier having a positive terminal, a negative terminal for receiving a feedback reference voltage, and a feedback output terminal coupled to the current mirror. The thermal regulation circuit is configured for generating and modulating a thermal regulation voltage with temperature, and outputting the thermal regulation voltage across the positive terminal of the feedback amplifier and the charging current setting terminal.

IPC Classes  ?

• H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

Abstract

An audio amplifier includes a plurality of power stages, a driving circuit, and a power stage control circuit. The driving circuit is arranged to drive the power stages. The power stage control circuit includes a feedback circuit and a control circuit. The feedback circuit is coupled to the power stages, and is arranged to generate a feedback signal according to at least one detection input, wherein the at least one detection input includes at least one of a power, a voltage signal corresponding to a switching time of the power stages, and a voltage signal corresponding to a switching frequency of the power stages. The control circuit is coupled between the feedback circuit and the power stages, and is arranged to generate a control signal according to the feedback signal, wherein the control signal is arranged to dynamically control a number of turned-on power stages in the power stages.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation

Abstract

A capacitance measure circuit includes a charge to voltage converter (CVC), and the CVC includes an excitation signal generation circuit that is arranged to generate and connect an excitation signal to a first terminal of a capacitance sensor, a differential amplifier, a first switch circuit, and at least one first variable capacitor. The inverting input terminal of the differential amplifier is arranged to receive a sensing capacitance value from a second terminal of the capacitance sensor. The first switch circuit is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier, and is connected in parallel with the at least one first variable capacitor at the inverting input terminal and the non-inverting output terminal of the differential amplifier.

IPC Classes  ?

• G01R 27/26 - Measuring inductance or capacitanceMeasuring quality factor, e.g. by using the resonance methodMeasuring loss factorMeasuring dielectric constants
• H03F 3/45 - Differential amplifiers
• H03M 3/00 - Conversion of analogue values to or from differential modulation

Abstract

A control circuit for adaptive noise margin control for a constant on time (COT) converter comprises an input reference terminal, amplifier, first switch device, voltage divider, trigger circuit, and output reference terminal. The amplifier has an input terminal coupled to the input reference terminal receiving a reference voltage signal. The first switch device has a control terminal coupled to an output of the amplifier, a first conduction terminal for receiving a voltage source signal, and a second conduction terminal. The voltage divider is coupled to the second conduction terminal and another input terminal of the amplifier. The trigger circuit, coupled to the voltage divider, is for triggering voltage change of a modified reference voltage signal selectively according to a high-side control signal of the COT converter. The output reference terminal coupled to the second conduction terminal outputs the modified reference voltage signal.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Abstract

Method and circuit for adaptive column-select line signal generation for a memory device are provided. The method comprises the following steps. A first signal is generated in response to a memory access command. A second signal is generated according to a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is asserted, the first candidate signal is asserted when a configurable time interval with respect to a parameter from a register set elapses and the second candidate signal is asserted when a specified time interval elapses, and the selected candidate signal is asserted before a remaining part of the candidate signals after the first signal is asserted. A column-select line signal is generated according to the first signal and the second signal.

IPC Classes  ?

• G11C 11/408 - Address circuits

Abstract

A control circuit for controlling a DC-DC converter is provided. The control circuit comprises a first sensor, second sensor, error amplifier, signal conditioning circuit, first comparison circuit, second comparison circuit, and driver circuit. The error amplifier is configured to receive a feedback voltage and a reference voltage for generating a first voltage. The signal conditioning circuit is configured to receive the first voltage for generating a second voltage and a third voltage. The first comparison circuit is configured to make a comparison based on a first sensing signal from the first sensor and the second voltage for generating a first comparison signal. The second comparison circuit is configured to make a comparison based on a second sensing signal from the second sensor and the third voltage for generating a second comparison signal. The driver circuit is for driving a power stage according to the first and second comparison signals.

IPC Classes  ?

• H02M 1/00 - Details of apparatus for conversion
• H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

Abstract

A device for audio signal processing includes a main processor and two audio processors electrically connected with the main processor. Each audio processor corresponds to a channel of a stereo audio output. The main processor provides an indication signal for the two audio processors. Each audio processor generates a synchronization signal according to the indication signal and performs audio signal processing according to the synchronization signal. The synchronization signals begin simultaneously and have the same frequencies that equal a sampling frequency. Each synchronization signal includes at least one pulse, and a start of each pulse of each synchronization signal is aligned in time with a start of a pulse of the indication signal. The audio signal processing performed by each audio processor begins at an end of one of the at least one pulse in the synchronization signal corresponding to the audio processor.

IPC Classes  ?

• H04R 5/04 - Circuit arrangements
• H04S 1/00 - Two-channel systems

Abstract

An input clock buffer, comprising: a first capacitor; a second capacitor; a first amplifier, configured to generate a first output signal, comprising input terminals coupled to the first capacitor and the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal; a second amplifier, configured to generate a second output signal according to the differential input signal; a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal; and a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.

IPC Classes  ?

• H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
• H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass

Abstract

An integrated circuit die forming method, for forming a plurality of integrated circuit dies on a semiconductor wafer, comprising: forming a first device, a second device in a first die in a first area; forming a metal layer connected to the first device and the second device; forming a third device, a fourth device in a second die in a second area; forming the metal layer connected to the third device and the fourth device, wherein a scribe area exists between the first area and the second area is separated by; wherein the first device and the third device are used for synchronization and are components of a class D amplifier; wherein the second device is used for preventing leakage currents of the first die and the fourth device is used for preventing leakage currents of the second die.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage
• H10D 84/01 - Manufacture or treatment

Abstract

A method for increasing a resolution by N bits performed by a processing circuit of a motor driving system, where N is a positive integer, and the method includes: performing a conversion upon an analog command, to generate a command count value; performing a first N-bit right-shifting operation upon the command count value, to generate an initial output value; performing a logical operation upon the command count value, to generate a low bit value; generating an overflow value according to the low bit value; and determining a final output value according to the initial output value and the overflow value.

IPC Classes  ?

• H02P 6/08 - Arrangements for controlling the speed or torque of a single motor
• H02P 6/06 - Arrangements for speed regulation of a single motor wherein the motor speed is measured and compared with a given physical value so as to adjust the motor speed
• H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
• H02K 11/33 - Drive circuits, e.g. power electronics

Abstract

A control circuit arranged to detect an initial rotor position of a brushless DC motor includes: a voltage integrator circuit, arranged to perform integration upon an input voltage, to generate a plurality of integrated voltages; a PWM generating circuit, arranged to generate and output a plurality of PWM signals to the brushless DC motor through a drive circuit, and stop outputting a PWM signal that is any of the plurality of PWM signals to the brushless DC motor according to an integrated voltage corresponding to the PWM signal; a current receiving circuit, arranged to receive a plurality of feedback currents from the brushless DC motor; a comparison circuit, arranged to perform comparison upon the plurality of feedback currents, to generate a comparison result; and a decision circuit, arranged to detect the initial rotor position according to the comparison result.

IPC Classes  ?

• H02P 6/06 - Arrangements for speed regulation of a single motor wherein the motor speed is measured and compared with a given physical value so as to adjust the motor speed
• H02P 6/182 - Circuit arrangements for detecting position without separate position detecting elements using back-emf in windings
• H02P 6/20 - Arrangements for starting

Abstract

A constant on time converter control circuit and a constant on time converter are provided. The constant on time converter control circuit comprises an error amplifier, a voltage to current converter, and an initial current source. The error amplifier is for receiving a reference voltage signal and a feedback voltage signal and outputting a compensated voltage signal. The voltage to current converter receives the compensated voltage signal and outputs a converted current signal. The initial current source provides an initial current signal. The initial current signal and the converted current signal form a new reference voltage signal. A constant on time OFF time comparator receives the new reference voltage signal and the feedback voltage signal and outputs a control signal. The control signal affects the turning on and turning off of electronic switches to produce an output voltage of a constant on time converter.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H02M 1/00 - Details of apparatus for conversion

Abstract

An audio amplifier with duty ratio control is provided. The audio amplifier comprises a pulse width modulation modulator, a power stage, and a voltage converter. The pulse width modulation modulator is configured to receive an input signal for generating a pulse width modulation signal. The power stage is configured to output an output signal according to a supply voltage and the pulse width modulation signal. The voltage converter is configured to adjust voltage level of the supply voltage according to the pulse width modulation signal. The audio amplifier is configured to adjust the voltage level of the supply voltage when duty ratio of the pulse width modulation signal is greater than a duty ratio threshold.

IPC Classes  ?

• H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage
• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03G 3/30 - Automatic control in amplifiers having semiconductor devices

Abstract

An apparatus for noise reduction in audio signal processing includes a power amplifier, a zero-crossing detector, and a threshold detector. The power amplifier has an input signal terminal for receiving an audio input signal and an output signal terminal. The audio input signal is a digital-to-analog converted version according to a version of a digital audio signal. The power amplifier has an analog gain which is controllable in response to an analog gain control signal. The zero-crossing detector determines a zero-crossing detection signal according to an internal signal provided between the input signal terminal and the output signal terminal. The threshold detector determines a gain setting according to the digital audio signal and the zero-crossing detection signal to generate the analog gain control signal indicating the gain setting, wherein the threshold detector controls the analog gain of the power amplifier according to the analog gain control signal.

IPC Classes  ?

• G10K 11/178 - Methods or devices for protecting against, or for damping, noise or other acoustic waves in general using interference effectsMasking sound by electro-acoustically regenerating the original acoustic waves in anti-phase
• H03G 3/00 - Gain control in amplifiers or frequency changers

Abstract

A driving circuit of a loudspeaker includes a periodic signal generation circuit, a signal processing circuit, a class-D amplifier circuit, a current sensing circuit, and a sample and hold circuit. The periodic signal generation circuit is arranged to generate a periodic signal and a control signal. The signal processing circuit is coupled to the periodic signal generation circuit, and is arranged to generate a pre-driving signal. The class-D amplifier circuit is coupled to the signal processing circuit, and is arranged to drive the loudspeaker according to the pre-driving signal. The current sensing circuit is coupled to the class-D amplifier circuit, and is arranged to generate a current sensing signal. The sample and hold circuit is coupled to the periodic signal generation circuit and the current sensing circuit, and is arranged to sample and hold the current sensing signal according to the control signal, to generate a current sampling signal.

IPC Classes  ?

• H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
• H03F 3/187 - Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03F 3/45 - Differential amplifiers

Abstract

A linear charger includes a constant current charging circuit and a thermal regulation circuit. The constant current charging circuit is arranged to generate a charging current, and includes a first transconductance amplifier, wherein the first transconductance amplifier has a positive terminal, a negative terminal, and an output terminal. The thermal regulation circuit is coupled to the output terminal and the negative terminal of the first transconductance amplifier, and is arranged to generate and modulate a thermal regulation current and an amplifier reference voltage with temperature, and transmit the thermal regulation current and the amplifier reference voltage to the output terminal and the negative terminal of the first transconductance amplifier, respectively.

IPC Classes  ?

• H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

Abstract

A digital buffer device with self-calibration includes a first buffer circuit, detection circuit, and calibration circuit. The first buffer circuit has a buffer input terminal for receiving an input signal and a buffer output terminal as output of the digital buffer device. The detection circuit includes at least one second buffer circuit for receiving at least one reference signal and generating at least one detection signal to indicate circuit characteristic variations of the at least one second buffer circuit. The at least one second buffer circuit is of a same type of buffer as the first buffer circuit. The calibration circuit has a calibration input terminal for receiving the input signal, and a calibration output terminal coupled to the buffer output terminal. The calibration circuit is for calibrating the first buffer circuit to generate an output signal according to the input signal and the at least one detection signal.

IPC Classes  ?

• H03K 19/003 - Modifications for increasing the reliability
• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A signal processing circuit includes a delay locked loop (DLL) circuit, a data output path circuit, and a first phase detector circuit. The DLL circuit is arranged to receive a memory clock signal, and generate a DLL output signal according to the memory clock signal and a DLL feedback signal. The data output path circuit is coupled to the DLL circuit, and is arranged to generate a DQS signal according to the DLL output signal. The first phase detector circuit is coupled to the data output path circuit, and is arranged to receive the memory clock signal and the DQS signal, and detect a phase difference between the memory clock signal and the DQS signal to generate a first phase detection result.

IPC Classes  ?

• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management

Abstract

A method for determining an initial rotor position of a permanent magnet synchronous motor (PMSM) includes: generating a plurality of transient currents by applying a plurality of voltages to each phase stator winding of a three phase stator winding of the PMSM; generating three phase current differences according to the plurality of transient currents; determining a first zone in which the initial rotor position of the PMSM is located according to the three phase current differences, wherein angles between 0-360 degrees are divided into a plurality of zones, and the first zone is selected from the plurality of zones; calculating three line current differences according to the three phase current differences; and determining the initial rotor position of the PMSM according to the first zone and the three line current differences.

IPC Classes  ?

• H02P 6/00 - Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor positionElectronic commutators therefor
• H02P 6/18 - Circuit arrangements for detecting position without separate position detecting elements

Abstract

A comparator circuit with dynamic biasing comprises a comparator, first dynamic biasing generator, first extra biasing device, second dynamic biasing generator, and second extra biasing device. The comparator includes a biasing circuit, input stage, active loads, and output terminal. The input stage has a first input terminal, second input terminal, first current path, and second current path. The comparator is configured to output an output signal at the output terminal according to the first input signal and second input signal. The first dynamic biasing generator is coupled between a first detection node and the first extra biasing device coupled to the biasing circuit. The second dynamic biasing generator is coupled between a second detection node and the second extra biasing device coupled to the biasing circuit. The first and second detection nodes are between the input stage and the active loads.

IPC Classes  ?

• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
• H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
• H03K 5/06 - Shaping pulses by increasing durationShaping pulses by decreasing duration by the use of delay lines or other analogue delay elements
• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits

Abstract

A semiconductor device with contact check circuitry is provided. The semiconductor device includes a plurality of pads, an internal circuit, and a contact check circuit. The plurality of pads includes a first pad and a second pad. The internal circuit is coupled to the plurality of pads. The contact check circuit, at least coupled to the first pad and the second pad, is used for checking, when the semiconductor device is under test, contact connections to the first pad and the second pad to generate a check result signal according to comparison of a first test signal and a second test signal received from the first pad and the second pad with at least one reference signal.

IPC Classes  ?

• G01R 31/68 - Testing of releasable connections, e.g. of terminals mounted on a printed circuit board
• G01R 1/067 - Measuring probes
• H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections

Abstract

A loudspeaker controller for estimating a fundamental resonance frequency of a loudspeaker includes: an amplifier circuit, arranged to generate a driving signal of the loudspeaker according to an audio input signal; a sensing circuit, arranged to sense characteristics of the driving signal to generate a measurement signal; a plurality of band pass filter circuits, arranged to filter the measurement signal to generate a plurality of filter outputs, respectively, wherein the plurality of band pass filter circuits have different passbands; and an estimation circuit, arranged to estimate the fundamental resonance frequency according to the plurality of filter outputs.

IPC Classes  ?

• H04R 29/00 - Monitoring arrangementsTesting arrangements
• H04B 17/309 - Measuring or estimating channel quality parameters

Abstract

A data control circuit includes a first latch circuit, a self-block circuit, a second latch circuit, a third latch circuit, a first data timing-labeled signal generating circuit, and a second data timing-labeled signal generating circuit. The first latch circuit is arranged to receive a data window signal. The self-block circuit is coupled to the first latch circuit, and is arranged to generate a protection signal. The second latch circuit is coupled to the self-block circuit, and is arranged to output a first data timing-labeled signal. The third latch circuit is coupled to the second latch circuit, and is arranged to generate a second data timing-labeled signal. The first data timing-labeled signal generating circuit is arranged to generate a third data timing-labeled signal. The second data timing-labeled signal generating circuit is arranged to generate a fourth data timing-labeled signal.

IPC Classes  ?

• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

A parametric equalizer includes an equalizer circuit, a first protection circuit, a second protection circuit, and a first addition circuit. The equalizer circuit is arranged to receive an input signal, and process the input signal to generate an output signal. The first protection circuit is arranged to generate a first protection signal according to the output signal, the input signal, and a first processed signal. The second protection circuit is arranged to generate a second protection signal according to the input signal and a second processed signal. The first addition circuit is coupled to the first protection circuit and the second protection circuit, and is arranged to combine the first protection signal and the second protection signal to generate an equalizer output signal.

IPC Classes  ?

• H04R 3/14 - Cross-over networks
• H03G 5/00 - Tone control or bandwidth control in amplifiers
• H04R 3/04 - Circuits for transducers for correcting frequency response
• H03G 5/02 - Manually-operated control
• H03G 5/16 - Automatic control

Abstract

A leveling equalizer includes a graphic equalizer circuit, a first multiplication circuit, a second multiplication circuit, an addition circuit, and a gain control circuit. The graphic equalizer circuit processes a first input signal and output a first output signal and a second output signal. The first multiplication circuit multiplies the first output signal and one of an adjustable gain value and a fixed gain value to generate a first adjusted output signal. The second multiplication circuit multiplies the second output signal and another of the adjustable gain value and the fixed gain value to generate a second adjusted output signal. The addition circuit combines the first adjusted output signal and the second adjusted output signal to generate an equalizer output signal. The gain control circuit dynamically adjusts the adjustable gain value according to the equalizer output signal.

IPC Classes  ?

• H03G 5/16 - Automatic control
• H03G 9/02 - Combinations of two or more types of control, e.g. gain control and tone control in untuned amplifiers
• H03G 5/00 - Tone control or bandwidth control in amplifiers
• H03G 3/32 - Automatic control in amplifiers having semiconductor devices the control being dependent upon ambient noise level or sound level

Abstract

A switch circuit provides a first output signal and a second output signal for switching between ternary modulation and quaternary modulation for a target device. A first output signal is provided from one of a first signal, a second signal and a ground signal according to an input signal and a duty signal, wherein the first signal is generated through performing a one-bit left-shift operation for the input signal, and the second signal is generated through adding the input signal and the duty signal. A second output signal is provided from one of a third signal, a fourth signal and the ground signal according to the input signal and the duty signal, wherein the third signal is generated through subtracting the input signal from the duty signal, and the fourth signal is generated through performing a two's-complement transformation and the one-bit left-shift operation for the input signal.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03F 3/38 - DC amplifiers with modulator at input and demodulator at outputModulators or demodulators specially adapted for use in such amplifiers
• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation

Abstract

A method for determining zero crossing occurrence in an alternating current (AC) signal with constant frequency of a permanent magnet synchronous motor (PMSM) includes: sampling the AC signal to obtain a plurality of data points; starting to count a number of consecutive data points that have sampled values with a same sign in a detection range, to generate a count value, wherein the consecutive data points are included in the plurality of data points; determining whether the count value is equal to a zero crossing determination value; and in response to the count value being equal to the zero crossing determination value, determining that a zero crossing occurs at a last data point of the consecutive data points.

IPC Classes  ?

• H02P 6/00 - Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor positionElectronic commutators therefor
• H02P 6/16 - Circuit arrangements for detecting position
• H02P 6/182 - Circuit arrangements for detecting position without separate position detecting elements using back-emf in windings

Abstract

An amplifier with an input stage comprising: a first current mirror; a first input differential pair; a first current source; a second current source; a second input differential pair, wherein the first input differential pair and the second input differential pair receive a reference voltage; a second current mirror; and a voltage control transmission circuit. An extra current path in the first current mirror is formed and a current flowing through the extra current path flows through the second current mirror to a ground when the reference voltage is higher than a first predetermined value. Also, an extra current path in the second current mirror is formed and a current flowing through the extra current path in the second current mirror flows to the first current mirror when the reference voltage is lower than a second predetermined value.

IPC Classes  ?

• G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
• H03F 3/45 - Differential amplifiers
• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation

Abstract

A parametric equalizer includes a first parametric equalizer circuit, a second parametric equalizer circuit, a first multiplication circuit, a second multiplication circuit, an addition circuit, and a weighting control circuit. The first parametric equalizer circuit processes an input signal to output a first output signal. The second parametric equalizer circuit processes the input signal to output a second output signal. The first multiplication circuit multiplies the first output signal and a first weighting value to generate a first adjusted output signal. The second multiplication circuit multiplies the second output signal and a second weighting value to generate a second adjusted output signal. The addition circuit combines the first adjusted output signal and the second adjusted output signal to generate an equalizer output signal. The weighting control circuit dynamically adjusts the first weighting value and the second weighting value according to the equalizer output signal.

IPC Classes  ?

• H03G 5/16 - Automatic control
• G10L 25/21 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the type of extracted parameters the extracted parameters being power information
• H04R 3/00 - Circuits for transducers
• H03G 5/02 - Manually-operated control

Abstract

m degradation or leakage degree of flash cells before or after entering the POEC process. When a preset condition is satisfied, the auto-adjusting verification mechanism of the POEC is switched on to further reduce leakage current. After cycling, the POEC repairs Vt of over-erased cells to a higher level to solve leakage issues. The erase shot count increases due to slower erase speeds after cycling. Therefore, the cycling degree of flash cells is detected by observing the shot number that the erase operation used. When the leakage phenomenon becomes serious, the bit line (BL) leakage current, amount of repaired BLs, and over-erase correction (OEC) shot number will increase during the OEC procedure. Therefore, the leakage degree of flash cells can be detected by inspecting the above data.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
• G11C 16/24 - Bit-line control circuits
• G11C 16/30 - Power supply circuits
• G11C 16/26 - Sensing or reading circuitsData output circuits

Abstract

A direct current (DC) offset protection circuit includes: a DC offset detection circuit and a control circuit. The DC offset detection circuit is arranged to detect whether a DC component exists in pulse-width-modulation (PWM) signals and accordingly generate a DC offset detection result. The control circuit is arranged to control an audio system according to the DC offset detection result. The DC offset detection circuit comprises a PWM polarity judgment circuit, a cascaded integrator-comb (CIC) filter and a DC offset judgment circuit. The PWM polarity judgment circuit is arranged to judge a polarity of complementary PWM signals and accordingly generate a polarity indication value. The CIC filter is arranged to generate a filter output signal by averaging a plurality of polarity indication values. The DC offset judgment circuit is arranged to generate the DC offset detection result by comparing the filter output signal with a predetermined DC threshold.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03F 1/52 - Circuit arrangements for protecting such amplifiers
• H03F 3/38 - DC amplifiers with modulator at input and demodulator at outputModulators or demodulators specially adapted for use in such amplifiers

Abstract

A voltage converter comprising: a bootstrap circuit, comprising an output capacitor, an error amplifier, a charging control circuit and a charging circuit. The charging control circuit comprises: a detection circuit, configured to detect an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit, configured to clamp an output voltage of the error amplifier to a specific range based on the detection signal. The charging circuit is configured to generate a charging signal according the output voltage of the error amplifier to the bootstrap circuit, to charge the output capacitor.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03F 3/45 - Differential amplifiers
• H03K 5/08 - Shaping pulses by limiting, by thresholding, by slicing, i.e. combined limiting and thresholding
• H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

Abstract

An erase voltage compensation mechanism for group erase mode with bit line leakage detection comprises performing a block erase operation by applying an erase voltage. Continue block erasing until bit line leakage is detected upon which the erase voltage is latched and over-erase correction is performed. A compensation voltage value is calculated by finding the difference between an upper bound of a threshold voltage distribution and an erase verify point when the bit line leakage was detected. The latched erase voltage is increased by the compensation voltage to create a compensated voltage. A group erase operation is performed and the group address is incremented by 1 and the compensated voltage value is loaded. Then the group erase operation is performed on the next group. The address is incremented, the compensated voltage is loaded, and the group erase operation is performed until the group is the last group.

IPC Classes  ?

• G11C 16/20 - InitialisingData presetChip identification
• G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Abstract

A COT (constant on-time) buck converter includes a first transistor, a second transistor, a driver circuit, an inductor, a first resistor, a second resistor, a capacitor, a load, and a feedback loop circuit. The feedback loop circuit includes a first switch, a second switch, an error amplifier, a comparator, a frequency locked loop circuit, an inverter and a COT logic circuit. The COT buck converter is able to improve DC (direct-current) regulation efficiency and transient response time.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
• H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
• H02M 1/00 - Details of apparatus for conversion

Abstract

A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.

IPC Classes  ?

• G11C 8/06 - Address interface arrangements, e.g. address buffers
• G11C 29/38 - Response verification devices
• G06F 3/06 - Digital input from, or digital output to, record carriers

Goods & Services

Chips [integrated circuits], Semiconductors, Integrated circuits, Heat detector, Gas detector, Fire detector central control, Smoke siren, Smoke detector, Earthquake siren, Sensor, Transducer, Data processing apparatus, Computer firmware, Internet device, Microprocessors, Network signal repeater, Wireless base station, Transmitters of electronic signals, Signal transmitter, Network communication equipment, Network router, Network gateway, Controller apparatus. On-line information transmission, Communications by computer terminals, Providing access to databases, Providing access services to online network data, Streaming of data, Satellite locating signal transmission service, Geolocation services [telecommunications services], Providing telecommunication information; Communication information service; Providing information in the field of telecommunications. Processing of computer data; Computer software design; Consultancy in the design and development of computer hardware; Electronic data storage service; Software development in the framework of software publishing; Development of computer platforms; Computer programming services for data processing; Software engineering services for data processing; Research and development of new products for others; Technical project studies; Technical writing; Design of integrated circuits; Design of semiconductor chip; Electronic engineering consultancy; Telecommunication engineering technology consultancy; Telecommunications technology consultancy; Research in the field of telecommunications technology; Electrical engineering consultancy; Electrical engineering technology consultancy; Planning and design of communication system and equipment engineering.

Abstract

An electronic device is capable of determining a radio communications configuration. The electronic device includes a GPS module arranged for receiving an updated GPS coordinate. A controller is electronically coupled to the GPS module, and arranged for controlling the GPS module to receive the updated GPS coordinate and for determining the radio communications configuration based on the updated GPS coordinate received from the GPS module. A transmitter is electronically coupled to the controller and arranged for transmitting a message from the controller according to the determined radio communications configuration.

IPC Classes  ?

• H04W 4/029 - Location-based management or tracking services
• H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
• G01S 19/26 - Acquisition or tracking of signals transmitted by the system involving a sensor measurement for aiding acquisition or tracking
• H04W 4/021 - Services related to particular areas, e.g. point of interest [POI] services, venue services or geofences
• H04W 84/12 - WLAN [Wireless Local Area Networks]

Abstract

An input buffer circuit includes an input differential amplifier unit, a differential amplifier stage, and a buffer. The input differential amplifier unit has input terminals and at least one output terminal, wherein at least two of the input terminals of the input differential amplifier unit are configured to be capacitively coupled respectively so as to provide at least one pair of signal paths for a first input signal and a second input signal of a differential input signal. The differential amplifier stage, coupled to the input differential amplifier unit, has first and second differential input terminals, and a corresponding output terminal, wherein the first and second differential input terminals are capable of being coupled to the first input signal and the second input signal respectively. The buffer, coupled to the output terminal of the differential amplifier stage, is used for outputting an output single-ended signal.

IPC Classes  ?

• H03F 3/45 - Differential amplifiers

Abstract

A class-D amplifier configured to adjust at least one input signal to at least one output signal. The class-D amplifier comprises: a loop filter, configured to receive the input signal; a PWM circuit, configured to generate at least one PWM signal; a summing circuit, coupled between an output of the loop filter and an input of the PWM circuit; an output circuit operating at a supply voltage, configured to generate the output signal responding to the PWM signal; and a supply voltage filter, configured to monitor the supply voltage to generate a filtered signal to the summing circuit. The summing circuit is configured to sum the output of the loop filter and the filtered signal to adjust a common-mode level of the input of the PWM circuit.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• H03F 3/187 - Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
• H03F 3/45 - Differential amplifiers

Abstract

An over charge protection method applied to a voltage converter which can operate in a quaternary modulation mode (Q mode) or a ternary modulation mode (T mode). The over charge protection method comprises: (a) determining whether the voltage converter operates in the Q mode or the T mode; and (b) setting a current threshold of the voltage converter to a first over current threshold if the voltage converter operates in the T mode; and (c) setting the current threshold to a second over current threshold if the voltage converter operates in the Q mode, wherein the first current threshold is smaller than the second over current threshold.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03F 1/52 - Circuit arrangements for protecting such amplifiers
• H03F 3/38 - DC amplifiers with modulator at input and demodulator at outputModulators or demodulators specially adapted for use in such amplifiers

Abstract

An E-fuse circuit comprising: an E-fuse group, comprising a plurality of E-fuse sections, wherein each one of the E-fuse sections comprises a plurality of E-fuses; a multi-mode latch circuit, configured to receive an input signal to generate a first output signal in a burn in mode, and configured to receive an address to be compared to generate a second output signal in a normal mode; a first logic circuit group, configured to receive a first part of bits of the first output signal to generate a control signal in the burn in mode; and a second logic circuit group, configured to receive the control signal and a second part of bits of the first output signal to generate a selection signal in the burn in mode, to select which one of the E-fuse sections is activated.

IPC Classes  ?

• G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
• G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
• G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters

Abstract

A boost class-D amplifier includes a PWM modulator, a boost level controller coupled to the PWM modulator, a pre-driver coupled to the PWM modulator and the boost level controller, a system voltage source, an inductor coupled to the system voltage source, a first switch, a second switch, a third switch, a fourth switch, a first diode coupled between the third switch and a voltage ground, a second diode coupled between the fourth switch and the voltage ground, and a capacitor coupled between the first switch and the fourth switch. The PWM modulator is for receiving an input signal and generating a first modulated signal accordingly. The boost level controller is for receiving the first modulated signal and generating a second modulated signal accordingly. The pre-driver is for receiving the first modulated signal and the second modulated signal and generating control signals accordingly.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation

Abstract

A data first-in first-out (FIFO) circuit includes a register unit, a plurality of data multiplexers, and an output multiplexer. The register unit includes a plurality of decoders and a plurality of N registers. The decoders are used for outputting a plurality of decoded signals in response to a plurality of corresponding input control signals and at least one input enabling signal. The N registers are configured to receive input data in response to the corresponding decoded signals from the corresponding decoders. The data multiplexers each are coupled to M ones of the registers, wherein N and M are positive integers, N is equal to or greater than four, M is equal to or greater than two, and N is greater than M. The output multiplexer, coupled to the data multiplexers, is used for providing a corresponding output from the data multiplexers sequentially.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management

Abstract

A constant on-time controller (COT) includes: a voltage dividing circuit to generate a feedback voltage according to an output voltage of a buck regulator; a current ripple extracting circuit to sense a current from an inductor of a buck regulator, and generate an extracted ripple current having no DC component according to a sensed current; a one-shot on-timer to output a constant-on time control signal according to a regulator input voltage of the buck regulator and the output voltage; a comparing circuit to output a comparison result according to a reference voltage signal, the feedback voltage and the extracted ripple current; and a logic circuit to generate a control signal to the buck regulator according to the comparison result and the constant-on time control signal. The current ripple extracting circuit detects the DC component in the present cycle, and compares the detected DC component with the next cycle.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
• H02M 1/00 - Details of apparatus for conversion

Abstract

A power control circuit includes an alternating current (AC) power source, a rectifier and a valley-fill circuit. The AC power source is configured to receive an AC voltage. The rectifier is configured to convert the AC voltage into a rectified voltage. The valley-fill circuit includes: an inductor, having a first terminal coupled to the rectifier, and a second terminal; a first resistor, having a first terminal coupled to the second terminal of the inductor, and a second terminal; a diode, having a cathode coupled to the second terminal of the inductor, and an anode; and a first capacitor, having a first terminal coupled to the second terminal of the first resistor and the anode of the diode, and a second terminal coupled to ground.

IPC Classes  ?

• H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
• H05B 45/3725 - Switched mode power supply [SMPS]
• H05B 45/355 - Power factor correction [PFC]Reactive power compensation

Abstract

A synchronization circuit and a cascaded synchronization circuit for converting an asynchronous signal into at least one synchronous signal are provided. The synchronization circuit includes a signal control circuit, a flip-flop circuit, a clock enable circuit and a clock control circuit. The flip-flop circuit is coupled to the signal control circuit, the clock enable circuit is coupled to the signal control circuit and the flip-flop circuit, and the clock enable circuit is coupled to the signal control circuit and the flip-flop circuit. The signal control circuit and the clock control circuit can guarantee hold time and setup time is sufficient to allow the flip-flop circuit to output the synchronous signal without glitch regardless of the asynchronous signal.

IPC Classes  ?

• G06F 1/12 - Synchronisation of different clock signals
• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
• H04L 5/00 - Arrangements affording multiple use of the transmission path

Abstract

A memory device includes a plurality of memory blocks and each memory block includes a plurality of columns of memory cells. Each column of memory cells is coupled to a corresponding bit line. Upon completion of a power-up sequence, detect if a current leakage of corresponding columns in a group of memory blocks is greater than a predetermined level. If the current leakage of the corresponding columns in the group of memory blocks is greater than the predetermined level, perform an over-erasure correction on the corresponding columns.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 16/30 - Power supply circuits
• G11C 16/26 - Sensing or reading circuitsData output circuits

Abstract

A target row refresh method includes: providing first table having M entries each capable of storing information of target row address; providing second table having K entries respectively capable of storing information of different/identical candidate row addresses; determining whether an input address in an input address register matches address information recorded in the first table; when not match, determining whether to update information of a target row latch by using the input address in the input address register according to a sample policy so as to determine whether to compare the input address with address information recorded in the second table to determine a target row address; and performing a target row refresh operation to refresh a memory device's row(s) adjacent to a target row corresponding to the target row address.

IPC Classes  ?

• G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
• G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
• G11C 7/06 - Sense amplifiersAssociated circuits
• G06F 12/02 - Addressing or allocationRelocation
• G11C 11/409 - Read-write [R-W] circuits

Abstract

A pulse width modulation output stage incorporates a half bridge output stage, a gate control circuit, a detection circuit, and a control logic. The half bridge output stage has a first transistor and a second transistor connected in series between a power supply node and a ground node. The gate control circuit outputs a pulse width modulation signal to drive the first transistor and the second transistor. The detection circuit detects whether or not a glitch occurs in one of the gate voltages of the first and second transistor so as to generate a control code. The logic circuit varies the delay time of the pulse width modulation signal based on the control code.

IPC Classes  ?

• H03K 7/08 - Duration or width modulation

Abstract

A semiconductor memory device includes a memory bank of an open bit-line architecture and a word-line decoder. The memory bank is divided into a plurality of memory blocks in a bit-line direction, and each of the memory blocks includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells which are grouped into a plurality of memory sections including two edge memory sections and at least one non-edge memory section. The word-line decoder generates a plurality of word-line enabling signals based on a plurality of address signals and activates one of the word lines for each of the two edge memory sections of one of the memory blocks and one of the word lines for one of the at least one non-edge memory section of each of the other memory blocks concurrently in an active mode according to the word-line enabling signals.

IPC Classes  ?

• G11C 5/10 - Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting capacitors
• G11C 11/408 - Address circuits
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Abstract

An amplifier circuit with novel design is provided. The amplifier circuit includes an input stage, a resistor, an output stage, an intermediate stage and a gm circuit. The input stage is coupled to a first supply voltage, and is arranged to receive an input voltage and a feedback current. The resistor is coupled between the input voltage and the input stage. The output stage is coupled to a second supply voltage, and is arranged to provide an output voltage for driving a load. The intermediate stage is coupled between the input stage and the output stage, and includes a level shifter. The gm circuit is coupled to the input stage, and is arranged to compare the input voltage with a common mode voltage, and thereby generates a compensate current for the input stage.

IPC Classes  ?

• H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03F 3/45 - Differential amplifiers

Abstract

An E-fuse burning circuit comprising: a burning directing circuit, configured to receive first input data comprising first input address and burning directing data, to generate a burning directing signal according to the burning directing data; a ring address latch, configured to latch the first input address responding to a first clock signal, and configured to output second input address responding to the first clock signal; and a control signal generating circuit, configured to generate at least one stop signal to determine whether the data in the ring address latch is shifted or not. The ring address latch applies a first number of the stages when the burning directing signal indicates a row of the E-fuse circuit is to be burned and applies a second number of the stages when the burning directing signal indicates a column of the E-fuse circuit is to be burned.

IPC Classes  ?

• G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

An E-fuse circuit comprising: a ring address latch, configured to receive a first input address arranged in serial i bits responding to a first clock signal, and to output a second input address arranged in serial j bits responding to a second clock signal; a control signal generating circuit, configured to receive the second input address, and to decode the second input address to generate first control signals with m bits and second control signals with n bits, wherein the first control signals and the second control signals are transmitted in parallel, and m, n are factors of j; and an E-fuse group, comprising j fuses. If any one of the first control signals has a first logic value and any one of the second control signals has the logic value, a corresponding fuse the E-fuse group is burned.

IPC Classes  ?

• G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
• G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links

Abstract

A quaternary/ternary modulation selecting circuit of an amplifier includes: a signal generating circuit, a detecting circuit, and a selecting circuit. The signal generating circuit is arranged to generate a ternary signal and a quaternary signal. The detecting circuit coupled to the signal generating circuit is arranged to generate a mode selecting signal according to at least the ternary signal. The selecting circuit coupled to the signal generating circuit and the detecting circuit is arranged to select and output one of the ternary signal and the quaternary signal to an output stage of the amplifier according to the mode selecting signal.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
• H03F 3/187 - Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
• H03K 21/02 - Input circuits
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
• H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

Abstract

An erasing method used in a flash memory comprising at least one memory block divided into a plurality of memory sectors is illustrated. Whether the memory block or the memory sector corresponding to an address has at least one under-erased transistor memory cell according to a sector enable signal is verified, wherein the sector enable signal is determined according to whether the memory block has at least one over-erased transistor memory cell. The transistor memory cells of the memory block or the memory sector will be erased according to the sector enable signal if the memory block or the memory sector corresponding to the address that has the under-erased transistor memory cell.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits

Abstract

An oscillator includes a reference current generating circuit, a modulator circuit, and an oscillating circuit. The reference current generating circuit generates a first reference current. The modulator circuit generates a modulation current according to the first reference current and a feedback voltage, wherein the modulation current is negatively correlated with the feedback voltage. The oscillating circuit receives at least the modulation current, and generates an oscillating signal with an oscillating frequency according to at least the modulation current, wherein the oscillating frequency is varied according to the modulation current. The oscillator may be employed by a direct current (DC)-to-DC voltage converter.

IPC Classes  ?

• H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
• H03K 7/06 - Frequency or rate modulation, i.e. PFM or PRM
• H03K 3/36 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of semiconductors, not otherwise provided for

Abstract

A bootstrap circuit applied to a first transistor of a direct-current (DC) to DC converter includes a second transistor, a bootstrapping capacitor and a clamping circuit, wherein the bootstrapping capacitor has a first terminal and a second terminal, and the first terminal is coupled to a source terminal of a transistor, and the source terminal of the second transistor is coupled to the first transistor; and the clamping circuit is coupled between a gate terminal of the second transistor and the second terminal of the bootstrapping capacitor, and is arranged to maintain a voltage drop between the second terminal of the bootstrapping capacitor and the gate terminal of the second transistor. A drain terminal of the second transistor is coupled to a first reference voltage, and a maximum of a voltage level of the gate terminal of the first transistor is greater than the first reference voltage.

IPC Classes  ?

• G05F 1/10 - Regulating voltage or current
• H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
• H03K 5/12 - Shaping pulses by steepening leading or trailing edges
• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H03K 5/08 - Shaping pulses by limiting, by thresholding, by slicing, i.e. combined limiting and thresholding

Abstract

A memory auto repairing circuit including: a decoding circuit, a latch enable circuit and a first latch circuit, wherein the decoding circuit is arranged to compare a first input address with a plurality of fail addresses to generate a control signal; the latch enable circuit is arranged to selectively generate a first enable signal at least according to the control signal; and the first latch circuit is arranged to receive the first input address, and store the first input address when the first enable signal is received by the first latch circuit; wherein when the control signal indicates that the first input address is identical to one of the plurality of fail addresses, the enable signal is prevented from being transmitted from the latch enable circuit to the first latch circuit.

IPC Classes  ?

• G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
• G11C 8/10 - Decoders
• G11C 8/06 - Address interface arrangements, e.g. address buffers
• G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
• G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links