Abstract

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a flip-flop having a gated input circuit and a transmission gate. The first time delay circuit is configured to receive a first clock signal and to output a second clock signal. The second time delay circuit is configured to receive the second clock signal and to output a third clock signal. The transmission gate is controlled with the first clock signal and the second clock signal. The gated input circuit is controlled by the third clock signal. The first time delay circuit includes a first gate via-connector in direct contact with a first gate-conductor which intersects a first-type active region structure in a first area. The second time delay circuit includes a second gate via-connector in direct contact with a second gate-conductor which intersects a second-type active region structure in a second area.

IPC Classes  ?

• H03K 3/037 - Bistable circuits
• G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
• H03K 3/288 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
• H03K 3/289 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable of the primary-secondary type
• H03K 3/356 - Bistable circuits
• H03K 3/3562 - Bistable circuits of the primary-secondary type
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
• H10B 99/00 - Subject matter not provided for in other groups of this subclass
• H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
• H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes

Abstract

A method (of forming a semiconductor device) includes: forming a cell region including: forming active regions and source/drain (S/D) regions in the active regions resulting in at least: first ones of the active regions extending in a first direction; a first set of the first active regions being rectangular; a second one of the active regions having a T-shape including a stem extending in a perpendicular second direction and first and second arms extending perpendicularly from a same end of the stem; and a second set of corresponding ones of the second active region and the first active regions, members of the second set having aligned first ends defining a first reference line proximate and parallel to a first boundary of the cell region; and wherein, relative to the second direction, first and second members of the first set overlapping the stem of the second active region.

IPC Classes  ?

• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• G06F 1/12 - Synchronisation of different clock signals
• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates

Abstract

A semiconductor device includes a cell region configured as a functional circuit. The cell region includes active transistors which are arranged to fit within a rectangular area. One or more of the active transistors is configured correspondingly to receive data at a data-input node of the cell region and a clock at a timing-input node of the cell region, and one or more of the active transistors being configured to produce an output signal at an output node of the cell region. One or more capacitor-configured transistors is arranged within the rectangular area, a terminal of one or more of the capacitor-configured transistors being connected to a target node of the functional circuit

IPC Classes  ?

• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/33 - Design verification, e.g. functional simulation or model checking
• G06F 111/20 - Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• G06F 119/06 - Power analysis or power optimisation
• G06F 119/18 - Manufacturability analysis or optimisation for manufacturability

Abstract

A method includes forming a dummy gate structure over a semiconductor structure over a substrate. Gate spacers are formed on sidewalls of the dummy gate structure. The semiconductor structure is recessed to form recesses on opposite sides of the dummy gate structure. A channel portion of the semiconductor structure remains beneath the dummy gate structure. A first oxygen-removal process is performed to the channel portion, using hydrogen radicals, to remove oxygens in the channel portion. A second oxygen-removal process, using a hydrogen-containing gas mixture, is performed to remove an oxide layer formed on sidewalls of the channel portion. The hydrogen radicals used in the first oxygen-removal process have sizes smaller than the hydrogen-containing gas mixture used in the second oxygen-removal process. Source/drain structures are deposited in the recesses and connected to the channel portion. The dummy gate structure is replaced with a metal gate structure.

IPC Classes  ?

• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A scan flip-flop circuit includes first and second I/O nodes, a selection circuit coupled to the first and second I/O nodes and including first through third PMOS transistors arranged in parallel and first through third NMOS transistors arranged in parallel, each including a gate configured to receive a corresponding first through third signal, and an output terminal configured to output one of the first through third signals as a selected signal based on scan direction and scan enable signals, a flip-flop circuit including an input terminal coupled to the output terminal of the selection circuit and an output terminal configured to output an output signal based on the selected signal, first and second drivers coupled to the output terminal and configured to output the first signal to the first I/O node and the second signal to the second I/O node responsive to the selected signal and the scan direction signal.

IPC Classes  ?

• H03K 3/037 - Bistable circuits
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
• H03K 19/0948 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET using CMOS

Abstract

A method of fabricating a transistor includes: forming a dummy gate and gate spacers; forming an ILD layer alongside the gate spacers; forming a trench having a lower portion and an upper portion wider than the lower portion, forming the trench including: removing the dummy gate and part of the gate spacers; forming a gate structure in the trench; and forming a SAC layer in the trench on the gate structure, wherein: the gate structure has a lower portion and a wider upper portion, a first gate spacer has a first inner sidewall that faces a first side of the lower portion, and a second gate spacer has a second inner sidewall that faces a second side of the lower portion, the first inner sidewall being spaced from the second inner sidewall by a first distance, and the self-aligned contact layer is wider than the first distance.

IPC Classes  ?

• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H10D 64/01 - Manufacture or treatment

Abstract

A semiconductor device includes: a first array of memory cells; a second array of tracking cells, the second array being configured to emulate the first array; a first word line coupled to corresponding ones of the memory cells in a corresponding one of rows of the first array and to the tracking cells; a second word line configured to emulate the first word line; a first adjust circuit coupled to the first word line; and a second adjust circuit coupled to the second word line.

IPC Classes  ?

• G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• G11C 7/02 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
• G11C 7/14 - Dummy cell managementSense reference voltage generators

Abstract

A semiconductor device includes: a cell region including active regions in which components of transistors are formed that have Vt_low, Vt_std or Vt_high thresold voltages, the transistors being arranged to function as a scan-insertion D flip-flop (SDFQ) that includes a multiplexer and a D flip-flop (DFF); the DFF including a clock buffer, a primary latch and a secondary latch; the primary latch including a first sleepy inverter and a first non-sleepy (NS) inverter; the secondary latch including a second sleepy inverter and a second NS inverter; the clock buffer including third and fourth NS inverters; transistors which comprise at least one of the third NS inverter or the fourth NS inverter being Vt_low tranistors; transistors which comprise the first sleepy inverter are Vt_high transistors or transistors which comprise the second sleepy inverter are Vt_high transistors; and wherein transistors which comprise the multiplexer are Vt_std transistors.

IPC Classes  ?

• H03K 3/037 - Bistable circuits
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

A method of fabricating an IC includes: forming first and second arrays of active-region structures extending between first and second vertical zone-boundaries, the first vertical zone-boundary being a boundary of a first keep-out zone, and the second vertical zone-boundary being a boundary of a second keep-out zone; forming first-side boundary cells aligned with the first vertical zone-boundary, including: forming a first-side boundary cell that includes: a first ESD device region including a first ESD protection circuit; and a first pick-up region; and forming second-side boundary cells aligned with the second vertical zone-boundary, including: forming a second-side boundary cell that includes: a second ESD device region including a second ESD protection circuit.

IPC Classes  ?

• H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]

Abstract

A circuit includes a memory circuit, and a power management circuit having a latch circuit. The latch circuit, in response to a first state of a first management signal, controls supply of a first supply voltage to the memory circuit in accordance with a control signal. The latch circuit, in response to a second state of the first management signal, stores a state of the control signal, and controls supply of the first supply voltage in accordance with the stored state. The power management circuit, in response to a second management signal, disables at least one interface circuit in at least one of the power management circuit or the memory circuit. The at least one interface circuit interfaces between a first power domain of a first power supply voltage corresponding to the first supply voltage, and a second power domain of a different second power supply voltage.

IPC Classes  ?

• G11C 5/14 - Power supply arrangements
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only

Abstract

A device includes: first and second power rails; first and second active regions; a first source/drain (S/D) conductor, wherein: the first S/D conductor is conductively connected to the first active region and the first power rail, and is in a layer between the first active region and the first power rail; a second S/D conductor, wherein: the second S/D conductor is at a same level as the first S/D conductor, the second S/D conductor is conductively connected to the first active region and is spaced apart from the first power rail, and the first S/D conductor is wider than the second S/D conductor; and a first gate between the first S/D conductor and the second S/D conductor, wherein: the first gate, the first S/D conductor, and the second S/D conductor are components of a first transistor at the first active region.

IPC Classes  ?

• H10D 84/85 - Complementary IGFETs, e.g. CMOS
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A method of manufacturing an integrated circuit (IC) includes generating first and second active region shapes extending in a first direction, the second active region shape separated from the first active region shape in a second direction. The method includes generating first and second sets of gate structure shapes extending in the second direction and overlapping the first and second active region shapes. The method includes generating a first conductive shape and a second conductive shape extending in the first direction, the first conductive shape overlapping the first active region shape, and the second conductive shape overlapping the second active region shape. The method includes generating a third conductive shape, the third conductive shape extending in the second direction and overlapping the first conductive shape and the second conductive shape. The method includes generating a fourth conductive shape extending in the first direction and overlapping the third conductive shape.

IPC Classes  ?

• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A memory circuit includes a first and second inverter, a level shifter circuit, a memory cell configured to receive a word line signal, and a local input/output (LIO) circuit. The first inverter is coupled to a first voltage supply, and configured to generate a first input signal in response to a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured generate a first and second signal responsive to a first or second input signal. The second inverter is configured to generate the word line signal in response to the first signal. The level shifter circuit is configured to delay a leading edge of the word line signal in response to the first or second signal. An amount of delay of the leading edge of the word line signal is based on a voltage difference between the first and second supply voltage.

IPC Classes  ?

• G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
• G11C 11/4076 - Timing circuits
• G11C 11/408 - Address circuits

Abstract

A method includes identifying a cell in the layout diagram as a violated cell that fails to pass one or more design rules related to IR drops, and classifying a root cause of the violated cell with a root cause class. The method also includes determining a searching area for searching safe region candidates, and finding a selected cell for moving based upon the root cause class of the root cause. The method also includes dividing the searching area into multiple analysis regions; finding a safe region for moving the selected cell based on searching at least one of the multiple analysis regions in the searching area, and moving the selected cell to the safe region in response to a condition that the safe region is found within the searching area.

IPC Classes  ?

• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 119/06 - Power analysis or power optimisation

Abstract

An integrated circuit device includes a plurality of static random access memory (SRAM) cells, a first bit line, a capacitor, a write driver transistor, and a negative voltage generator circuit. The first bit line is coupled with a column of the SRAM cells, wherein the first bit line extends substantially along a first direction. The capacitor includes a first electrode and a second electrode spaced apart from the first electrode. The first electrode has at least one first metal line extending substantially along the first direction, and a length of the at least one first metal line is less than a length of the first bit line in a top view. The write driver transistor is coupled between the first bit line and the first electrode of the capacitor. The negative voltage generator circuit is coupled to the second electrode of the capacitor.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

A memory circuit includes a control circuit coupled to the word line driver circuit. The control circuit is configured to delay a leading or falling edge of a word line signal in response to at least a first clock signal. The control circuit includes a first clock circuit configured to generate a second clock signal in response to a first reset signal and a clock signal, and an adjustable delay circuit configured to adjust a delay between the second and third clock signal in response to the second clock signal and an enable signal. The third clock signal is a delayed version of the second clock signal. An amount of the delay between the second and third clock signal is based on a voltage difference between a first supply voltage having a first swing, and a second supply voltage having a second swing.

IPC Classes  ?

• G11C 11/418 - Address circuits

Abstract

A memory device is provided and includes a memory array, first to second latch circuits and a gating circuit. Read and write operations are triggered by first and second edges of an internal clock signal respectively. The first latch circuit generates a first output signal in response to an input signal and a first latch clock signal, a first edge of the first latch clock signal generated based on the first edge of the internal clock signal. The second latch circuit generates a second output signal in response to the first output signal and a second latch clock signal, a first edge of the second latch clock signal being between first and second edges of the first latch clock signal. The gating circuit generates, in response to the second output signal and a gating clock generated, a third output signal to the memory array.

IPC Classes  ?

• G06F 1/08 - Clock generators with changeable or programmable clock frequency
• G11C 16/24 - Bit-line control circuits
• G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells

Abstract

A method of testing an integrated circuit on a test circuit board includes performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design corresponding to the integrated circuit. The performing the simulation includes simultaneously performing a burn-in test of an integrated circuit and an automated test of the integrated circuit. The integrated circuit is coupled to the test circuit board. The burn-in test has a minimum burn-in temperature of the integrated circuit or a burn-in heat distribution across the integrated circuit. The simultaneously performing the burn-in test of the integrated circuit and the automated test of the integrated circuit includes configuring at least the set of circuit blocks or the first set of heaters as a first set of heat sources for the burn-in test of the integrated circuit thereby generating a first heat signature of the integrated circuit.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G01R 31/317 - Testing of digital circuits
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 119/08 - Thermal analysis or thermal optimisation

Abstract

A device is provided. The device includes multiple transistors, a first sense circuit, and a precharge circuit. The transistors are coupled to a tracking bit line and configured to generate a first tracking signal. The first sense circuit is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge and a falling edge of the first sense tracking signal, a precharge signal for precharging data lines.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits

Abstract

An integrated circuit includes a first active area of a first conductivity type being coupled to an input/output (I/O) pad; a second active area of a second conductivity type, different from the first conductivity type, being coupled to a first supply voltage terminal; a plurality of first gate structures extending in a first direction to pass through the first and second active areas; and a first well of the second conductivity type extending along the first direction. The first and second active areas extend along a second direction different from the first direction in the first well, and the first active area is aligned with the second active area along the first direction.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A semiconductor device includes: a substrate having a first conductivity-type; and a cell region including: a deep well having a second conductivity-type; first and second non-deep wells having the second conductivity-type in corresponding first and second portions of the substrate, the first and second portions of the substrate being in the deep well; and first through fourth transistor-regions, the first and second transistor-regions including transistors having the first conductivity-type, the first and second transistor-regions being correspondingly in the first and second non-deep wells, and the third and fourth transistor-regions including transistors having the second conductivity-type, the third and fourth transistor-regions being corresponding in third and fourth portions of the substrate, the third and fourth portions of the substrate being in the deep well; the first transistor-region being configured for a first power domain; and the second, third and fourth transistor-regions being configured for a second, different, power domain.

IPC Classes  ?

• H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
• H03K 3/356 - Bistable circuits
• H03K 19/003 - Modifications for increasing the reliability
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 89/10 - Integrated device layouts

Abstract

A memory device is provided, including at least one bit cell, a pair of transistors, and a voltage generation circuit. The voltage generation circuit is coupled to the negative voltage line and is configured to pull down a voltage of at least one of the pair of data lines to a negative voltage level through the negative voltage line. The voltage generation circuit includes a first capacitive unit, a second capacitive unit, and a switch circuit. The first capacitive unit includes a first capacitor. The second capacitive unit includes a second capacitor. The switch circuit is configured to connect the first capacitor, the second capacitor, or the combination thereof to the negative voltage line in response to a first kick signal and a second kick signal that are different from each other.

IPC Classes  ?

• G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• G11C 11/4094 - Bit-line management or control circuits
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Abstract

A system for designing a semiconductor device, the system including: a first module configured to receive code operable to execute a plurality of operations of a machine learning algorithm and identify, from among the plurality of operations, first operations and second operations that are faster than the first operations, based on a time required to complete each operation; and a second module coupled to the first module to receive information from the first module identifying the first operations, wherein: the second module is configured to define a neural network for executing the first operations; the second module is configured to map the neural network to a machine learning hardware configuration for executing the first operations; and the second module is configured to model the machine learning hardware configuration as one or more semiconductor chips that are useable to execute the first operations.

IPC Classes  ?

• G06F 30/39 - Circuit design at the physical level
• G06N 20/00 - Machine learning

Abstract

A semiconductor device includes a function circuit, an antenna circuit and a first isolation circuit. The function circuit is configured to receive a first reference voltage signal and a second reference voltage signal. The antenna circuit is configured to receive the first reference voltage signal to share charges with the function circuit. The first isolation circuit is disposed between the function circuit and the antenna circuit, and configured to receive the second reference voltage signal to isolate the function circuit and the antenna circuit from each other.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 23/66 - High-frequency adaptations
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Abstract

A memory circuit includes a first and second inverter, and a level shifter circuit. The first inverter is coupled to a first voltage supply, and configured to generate a first input signal in response to a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured generate a first and second signal responsive to a first or second input signal. The second inverter is configured to generate a word line signal in response to the first signal. The level shifter circuit is configured to delay a leading edge of the word line signal in response to the first or second signal. An amount of delay of the leading edge of the word line signal is based on a voltage difference between the first and second supply voltage. The first supply voltage has a first swing. The second supply voltage has a second swing.

IPC Classes  ?

• G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
• G11C 11/4076 - Timing circuits
• G11C 11/408 - Address circuits

Abstract

A memory macro includes a first memory array, a second memory array, a word line driver between the first memory array and the second memory array, and a control circuit adjacent to and coupled to the word line driver, and one of the word line driver or the control circuit comprises a through-silicon via (TSV) surrounded by a dielectric layer within the corresponding word line driver or control circuit.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• G11C 11/418 - Address circuits
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

An IC device includes first and second gate structures; first and second conductors overlying at least a portion of each of the first and second gate structures; a plurality of gate structures between the first and second gate structures; a conductive segment between the first and second conductors and overlying the plurality of gate structures; first and second pluralities of active areas between the first and second gate structures. The first and second pluralities of active areas are between the first and second conductors; a first portion of the plurality of gate structures, a first portion of the first plurality of active areas, and the second plurality of active areas are included in a functional circuit; and a second portion of the plurality of gate structures, a second portion of the first plurality of active areas, and the conductive segment are included in a decoupling capacitor or an antenna diode.

IPC Classes  ?

• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 119/06 - Power analysis or power optimisation

Abstract

A method of fabricating a semiconductor device includes forming a dummy gate and gate spacers; forming an interlayer dielectric layer; forming a trench having a lower portion and an upper portion that is wider than the lower portion; and forming a gate structure in the trench. The gate structure has an upper portion in the upper portion of the trench, and a lower portion in the lower portion of the trench. The upper portion of the gate structure is wider than the lower portion of the gate structure. A first gate spacer has a first inner sidewall facing the lower portion of the gate structure. A second gate spacer has a second inner sidewall facing the lower portion of the gate structure. The first inner sidewall is apart from the second inner sidewall by a first distance. The upper portion of the gate structure is wider than the first distance.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 29/66 - Types of semiconductor device

Abstract

A method of operating an IC includes receiving a power supply voltage at a first pickup structure and a reference voltage at a second pickup structure, using the first pickup structure to bias an n-well shared among a first set of more than two rows of IC devices, and using the second pickup structure to bias a p-well shared among a second set of more than two rows of the IC devices.

IPC Classes  ?

• H10D 89/10 - Integrated device layouts
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

An integrated circuit (IC) device includes at least one circuit having an input and an output, and a plurality of transistors electrically coupled with each other between the input and the output. The plurality of transistors includes a first transistor of a first type, and a second transistor of a second type different from the first type. The IC device further includes an extended contact structure over and in electrical contact with a source/drain of the first transistor and a source/drain of the second transistor, and a conductive pattern extending along and overlapping the extended contact structure. The output electrically couples the conductive pattern to the extended contact structure.

IPC Classes  ?

• H10D 89/10 - Integrated device layouts
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 119/12 - Timing analysis or timing optimisation
• H01L 23/528 - Layout of the interconnection structure
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

A circuit includes a memory circuit, and a power management circuit having a first circuit. The first circuit is configured to, in response to a first state of the first power management control signal and a first state of the second power management control signal, control supply of a first supply voltage to the memory circuit in accordance with a first power mode control signal. The first circuit is further configured to, in response to a second state of the first power management control signal, store a state of the first power mode control signal, and control supply of the first supply voltage to the memory circuit in accordance with the stored state of the first power mode control signal. The power management circuit is configured to, in response to a second state of the second power management control signal, disable a part of the first circuit.

IPC Classes  ?

• G11C 5/14 - Power supply arrangements
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only

Abstract

A voltage regulator includes a power supply voltage node, a power supply reference node, an output node, a plurality of phase circuits, and a control circuit. Each phase circuit of the plurality of phase circuits includes at least one p-type transistor coupled to the power supply voltage node, at least one n-type transistor coupled to the power supply reference node, and an inductor including a first terminal coupled exclusively to the at least one p-type transistor and the at least one n-type transistor, and a second terminal coupled to the output node. The control circuit is configured to, responsive to a power state signal, enable a predetermined number of phase circuits of the plurality of phase circuits, and the inductors of the plurality of phase circuits are an entirety of the inductors of the voltage regulator coupled to the output node and include a same inductor type.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control

Abstract

A method of making a semiconductor structure includes forming a first conductive line and a second conductive line in a first dielectric layer. The method further includes recessing the first conductive line, wherein a thickness of the second conductive line is greater than the recessed first conductive line. The method further includes forming a third conductive line in a second dielectric layer overlying the first dielectric layer, wherein the third conductive line extends above at least the second conductive line. Forming the third conductive line includes forming a via in the second dielectric layer and electrically connecting the second conductive line and the third conductive line, wherein a first portion of the via lands on a portion of the second conductive line, and a second portion of the via extends between the first conductive line and the second conductive line.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/528 - Layout of the interconnection structure

Abstract

An integrated circuit includes a Schmitt trigger circuit. The Schmitt trigger circuit includes a first, second, third and fourth transistor, a first and second feedback transistor, and a first and second circuit. The first transistor is connected between a first node and a first voltage supply having a first supply voltage. The fourth transistor is connected between the third transistor and a second voltage supply having a second supply voltage. The first circuit is connected to a second node, the first and second voltage supply, and configured to supply the second supply voltage to the second node in response to being enabled. The second feedback transistor is connected to a third node, and a fourth node. The second circuit is connected to the fourth node, the first and second voltage supply, and configured to supply the first supply voltage to the fourth node in response to being enabled.

IPC Classes  ?

• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]

Abstract

A method (of manufacturing a semiconductor device) includes migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, the migrating including: expanding a first version of the first netlist and a first precursor of the second netlist correspondingly to form a second version of the first netlist and a second precursor of the second netlist; before conducting (A) placement and routing (P&R) of a layout diagram corresponding to the second netlist or (B) a static timing analysis of the layout diagram; performing a logic equivalence check (LEC) between the second version of the first netlist and the second precursor of the second netlist, thereby identifying migration errors, and revising the second precursor of the second netlist to reduce the migration errors, thereby resulting in a third precursor of the second netlist.

IPC Classes  ?

• G06F 30/323 - Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
• G06F 30/3323 - Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/394 - Routing
• G06F 119/12 - Timing analysis or timing optimisation

Abstract

An integrated circuit includes a clocking transistor, a first enabling transistor coupled between the clocking transistor and a first node, and a second enabling transistor coupled between the clocking transistor and a second node. The integrated circuit also includes a branch-one transistor coupled between a first power supply and the first node, and a branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-one transistor is connected to the second node. The gate terminal of the branch-two transistor is connected to the first node. The clocking transistor, the first enabling transistor, and the second enabling transistor are first-type transistors. The branch-one transistor and the branch-two transistor are second-type transistors.

IPC Classes  ?

• H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
• G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 117/04 - Clock gating
• H03K 3/037 - Bistable circuits
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

A memory device includes a memory cell in a first power domain of a first power supply voltage, a bit line coupled to the memory cell, and a write assist circuit. The write assist circuit includes an input, an output electrically couplable to the bit line in a write operation of the memory cell, an input circuit electrically coupled to the input, and an output circuit electrically coupled between the input circuit and the output. The input circuit is in a second power domain of a second power supply voltage different from the first power supply voltage, and the output circuit is in the first power domain.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits

Abstract

An integrated circuit includes a first region including a first set of transistors that include a first set of active regions having a first threshold voltage, the first set of transistors in a first portion of a level shifter circuit, the first portion of the level shifter circuit being coupled to a first voltage supply. The integrated circuit further includes a second region adjacent to the first region. The second region includes a second set of transistors that include a second set of active regions having a second threshold voltage different from the first threshold voltage, and the second set of transistors being in a second portion of the level shifter circuit.

IPC Classes  ?

• H03K 3/037 - Bistable circuits
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only

Abstract

A memory circuit includes a control circuit configured to receive a clock signal including a clock cycle and output control signals based on the clock signal, an input circuit arrangement configured to, responsive to the control signals, pass a latched address to an output of the input circuit arrangement, the latched address including, during a first half of the clock cycle, a read address received at a first input port, and, during a second half of the clock cycle, a write address received at a second input port, an array of single-port memory cells, the memory circuit being configured to perform read and write operations during the respective first and second halves of the clock cycle, and a decoding circuit arrangement configured to, based on the latched address at the output, activate a row of memory cells of the array during each of the first and second clock cycle halves.

IPC Classes  ?

• G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
• G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• G11C 8/10 - Decoders
• G11C 11/418 - Address circuits
• G11C 11/419 - Read-write [R-W] circuits

Abstract

A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.

IPC Classes  ?

• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• G11C 8/10 - Decoders

Abstract

A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits
• G11C 11/418 - Address circuits
• H03K 3/037 - Bistable circuits

Abstract

A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits
• G11C 11/418 - Address circuits
• H03K 3/037 - Bistable circuits

Abstract

A scan flip-flop circuit includes first and second I/O nodes, a flip-flop circuit, a selection circuit configured to receive a scan direction signal and including input terminals coupled to the first and second I/O nodes and an output terminal coupled to an input terminal of the flip-flop circuit, and first and second drivers configured to receive the scan direction signal and a scan enable signal, each including an input terminal coupled to an output terminal of the flip-flop circuit and an output terminal coupled to a respective first or second input terminal of the selection circuit. Responsive to the scan direction and scan enable signals, one of the first driver is configured to output a first signal responsive to a second signal received at the second input terminal or the second driver is configured to output a third signal responsive to a fourth signal received at the first input terminal.

IPC Classes  ?

• H03K 3/037 - Bistable circuits
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
• H03K 19/0948 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET using CMOS

Abstract

A memory device includes: a first array of memory cells; a second array of tracking cells, the second array being configured to emulate the first array; a first word line coupled to corresponding ones of the memory cells in a corresponding one of rows of the first array and to the tracking cells; a second word line configured to emulate the first word line; a first adjust circuit coupled to the first word line; a second adjust circuit coupled to the second word line; and an adjust-timing circuit coupled to the second adjust circuit.

IPC Classes  ?

• G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• G11C 7/02 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
• G11C 7/14 - Dummy cell managementSense reference voltage generators

Abstract

A memory device, comprising: a first driving circuit configured to provide a first current signal to a first node according to a decoder signal; a second driving circuit configured to provide a second current signal to a second node according to the decoder signal; and a modulating circuit coupled to the first node and the second node, configured to transmit each of the first current signal and the second current signal to a reference voltage terminal. A method is also disclosed herein. A method is also disclosed herein.

IPC Classes  ?

• G11C 11/408 - Address circuits
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• G11C 11/4094 - Bit-line management or control circuits

Abstract

A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 5/14 - Power supply arrangements
• G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• G11C 8/10 - Decoders

Abstract

An IC structure includes first through third n-wells aligned along a first direction in a semiconductor substrate, wherein the first n-well is separated from each of the second and third n-wells by corresponding spaces, a first plurality of active areas, gate structures, and metal-like defined (MD) segments overlying and electrically connected to the active areas positioned in the first n-well, a first tap structure overlying and electrically connected to the second n-well, a second tap structure overlying and electrically connected to the third n-well, and a first metal segment extending in the first direction, overlying the first plurality of transistors, and electrically connected to each of the first and second tap structures.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/3953 - Routing detailed

Abstract

A memory device is provided, including at least one bit cell, a pair of transistors, and a voltage generation circuit. The voltage generation circuit is coupled to the negative voltage line and is configured to pull down a voltage of at least one of the pair of data lines to a negative voltage level through the negative voltage line. The voltage generation circuit includes a first capacitive unit, a second capacitive unit, and a switch circuit. The first capacitive unit includes a first capacitor. The second capacitive unit includes a second capacitor. The switch circuit is configured to connect the first capacitor, the second capacitor, or the combination thereof to the negative voltage line in response to a first kick signal and a second kick signal that are different from each other.

IPC Classes  ?

• G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• G11C 11/4094 - Bit-line management or control circuits
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Abstract

A memory circuit includes a control circuit coupled to the word line driver circuit. The control circuit is configured to delay a leading or falling edge of a word line signal in response to at least a first clock signal. The control circuit includes a first clock circuit configured to generate a second clock signal in response to a first reset signal and a clock signal, and an adjustable delay circuit configured to adjust a delay between the second and third clock signal in response to the second clock signal and an enable signal. The third clock signal is a delayed version of the second clock signal. An amount of the delay between the second and third clock signal is based on a voltage difference between a first supply voltage having a first swing, and a second supply voltage having a second swing.

IPC Classes  ?

• G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
• G11C 11/418 - Address circuits

Abstract

A memory device is provided, including at least one inverter, a transistor coupled between the at least one inverter and a bit line, and an assist circuit coupled to the bit line, configured to provide a negative voltage to the bit line, and configured to pull down a power supply voltage provided to the at least one inverter.

IPC Classes  ?

• G11C 11/4094 - Bit-line management or control circuits
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• H03K 19/017 - Modifications for accelerating switching in field-effect transistor circuits

Abstract

A coupling including a main body, a first hub at a first end of the main body and a second hub at a second end of the main body opposite the first end is provided. The first hub includes a first inner bore configured to receive a first shaft and a pair of aligned first and second through holes extending through opposite walls of the first hub. The first through hole and the second through hole are in optical communication with the first inner bore.

IPC Classes  ?

• F16D 3/72 - Yielding couplings, i.e. with means permitting movement between the connected parts during the drive with the coupling parts connected by one or more intermediate members with axially-spaced attachments to the coupling parts
• F16B 7/00 - Connections of rods or tubes, e.g. of non-circular section, mutually, including resilient connections
• F16D 3/74 - Yielding couplings, i.e. with means permitting movement between the connected parts during the drive with the coupling parts connected by one or more intermediate members with axially-spaced attachments to the coupling parts the intermediate member or members being made of rubber or other flexible material
• G01V 8/20 - Detecting, e.g. by using light barriers using multiple transmitters or receivers
• G05B 15/02 - Systems controlled by a computer electric
• G08B 5/36 - Visible signalling systems, e.g. personal calling systems, remote indication of seats occupied using electric transmissionVisible signalling systems, e.g. personal calling systems, remote indication of seats occupied using electromagnetic transmission using visible light sources
• G08B 21/18 - Status alarms

Abstract

A method (of manufacturing) includes forming transistor components connected as transistors resulting in: first to third transistor-component (TC) sets being a primary latch, a secondary latch and a clock buffer that comprise D flip-flop (DFF); the primary latch including a first sleepy inverter and a first non-sleepy (NS) inverter; the secondary latch including a second sleepy inverter and a second NS inverter; the clock buffer including third and fourth NS inverters; a first group of some but not all of the transistors having members with a standard threshold voltage (Vt_std members); a second group of some but not all of the transistors having members with a low threshold voltage; and transistors which comprise at least one of the first NS inverter or the second NS inverter being Vt_low members of the second group.

IPC Classes  ?

• H03K 3/037 - Bistable circuits
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

A coating system and a method for using such a system comprising a vessel, a flexible container within the vessel, and a coating apparatus. The flexible container includes an outlet port, wherein the flexible container is configured to contract in response to an increase in pressure within the vessel. The flexible container is configured to output a coating composition through the outlet port in response to contraction. The coating apparatus is configured to receive the coating composition from the outlet port and in some embodiments, deliver the coating composition to a wafer surface.

IPC Classes  ?

• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• B05B 12/08 - Arrangements for controlling deliveryArrangements for controlling the spray area responsive to condition of liquid or other fluent material discharged, of ambient medium or of target
• B05C 11/10 - Storage, supply or control of liquid or other fluent materialRecovery of excess liquid or other fluent material
• G03F 7/16 - Coating processesApparatus therefor
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

A method is provided, including following operations: receiving, by a static voltage drop (SIR) prediction circuitry, floorplan data of a floorplan layout of a semiconductor device; generating a first SIR result by a machine learning model based on the floorplan data; generating a first similarity value based on a comparison of the floorplan data with a plurality of training data; generating a second SIR result based on the first SIR result and a first compensation value, corresponding to the first similarity value, in a mapping table; and generating a bump assignment data to update the floorplan data based on a comparison between the second SIR result with a plurality of predetermined SIR values.

IPC Classes  ?

• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement

Abstract

A semiconductor device includes first active regions extending in a first direction and having a first number of fins; second active regions extending in the first direction and having a second number of fins, the second number of fins being less than the first number of fins; data transistors formed at least in part in the first active regions; and scan transistors formed at least in part in the second active regions. The data transistors and the scan transistors are included in a scan insertion D flip-flop (SDFQ) that includes a multiplexer serially connected at an internal node to a D flip-flop (FF), the multiplexer including the data transistors for selecting a data input signal, and including the scan transistors for selecting a scan input signal.

IPC Classes  ?

• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• H03K 3/353 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback

Abstract

A semiconductor device includes a connector layer; a dielectric layer over the connector layer; and a conductive element in the dielectric layer, the conductive element including: a first region having a first uniform width; a second region having a second uniform width, wherein the second uniform width is less than the first uniform width; and a shoulder between the first region and the second region, wherein an angle of the shoulder relative to a top surface of the connector layer is greater than 20 degrees and less than 70 degrees.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
• H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
• H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
• H01L 21/311 - Etching the insulating layers
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A method of performing a design rule check includes clustering at least one of a plurality of rules with overlapping operations from a plurality of operations or the plurality of operations with overlapping rules from the plurality of rules. The method further includes at least one of transforming at least one of the clustered plurality of operations into a first operation group or a second operation group, or transforming at least one of the clustered plurality of rules into a first rule group or a second rule group. The method even further includes at least one of assigning at least one of the first operation group to a first processor or the second operation group to a second processor, or assigning at least one of the first rule group to the first processor or the second rule group to the second processor.

IPC Classes  ?

• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Abstract

A non-transitory computer-readable storage medium is encoded with a set of instructions for designing a semiconductor device using electronic system level (ESL) modeling for machine learning applications that, when executed by at least one processor, cause the at least one processor to: retrieve a source code operable to execute a plurality of operations of a machine learning algorithm; classify a first group of the plurality of operations as slow group operations and classify a second group of the plurality of operations as fast group operations, based on a time required to complete each operation; define a neural network operable to execute the slow group operations; define a trained neural network configuration including a plurality of interconnected neurons operable to execute the slow group operations; and generate an ESL platform for evaluating a design of a semiconductor device based on the trained neural network configuration.

IPC Classes  ?

• G06F 30/39 - Circuit design at the physical level
• G06N 20/00 - Machine learning

Abstract

A method of forming a semiconductor device includes forming a first row of transistors extending in a first direction and including dummy transistors and active transistors. The first row includes, in a sequence from a first end to a second end, at least a first dummy group, a first delay cell, a second delay cell, and a second dummy group. The first dummy group is formed of one or more dummy transistors. The second dummy group is formed of one or more dummy transistors. The first delay cell is formed of active transistors configured as a basic inverter and a float-resistant inverter. The second delay cell is formed of active transistors configured as at least one inverter. The first row is free of dummy transistors between the first delay cell and the second delay cell.

IPC Classes  ?

• H03K 3/86 - Generating pulses by means of delay lines and not covered by the preceding subgroups
• H03K 3/037 - Bistable circuits
• H03K 3/356 - Bistable circuits

Abstract

A method of forming a semiconductor device structure includes forming a first resist structure over a hard mask. The method further includes patterning the first resist structure to form a trench therein. The method further includes performing a first hydrogen plasma treatment to the patterned first resist structure, wherein the first hydrogen plasma treatment is configured to smooth sidewalls of the trench. The method further includes patterning the hard mask using the patterned resist structure as an etch mask. The method further includes forming a second resist structure over the patterned hard mask. The method further includes patterning the second resist structure to form an opening therein. The method further includes performing a second hydrogen plasma treatment to the patterned second resist structure. The method further includes patterning the patterned hard mask using the patterned second resist structure as a second etch mask.

IPC Classes  ?

• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

An integrated circuit includes a control circuit and first to second voltage generation circuits. The control circuit is coupled between a first voltage terminal providing a first supply voltage and a first node coupled to a first capacitive unit. The first voltage generation circuit includes at least one first transistor that has a source terminal receiving a second supply voltage, a drain terminal coupled to a second node in contact with a second capacitive unit, and a gate terminal coupled to the first node. The second voltage generation circuit is coupled to the first voltage terminal and the first and second nodes. Firstly the control circuit turns on the at least one first transistor to adjust a voltage level of the second node to have the second supply voltage. The second voltage generation circuit adjusts a voltage level of the first node to have the first supply voltage.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
• H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices

Abstract

A device is provided. The device includes multiple transistors, a first sense circuit, and a precharge circuit. The transistors are coupled to a tracking bit line and configured to generate a first tracking signal. The first sense circuit is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge and a falling edge of the first sense tracking signal, a precharge signal for precharging data lines.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits

Abstract

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit. The second time delay circuit further includes a second gate-conductor and a second gate via-connector in direct contact with the second gate-conductor. The second gate-conductor intersects a first-type active region structure and a second-type active region structure in a second area, and wherein at least a portion of the second gate via-connector is atop the second-type active region structure.

IPC Classes  ?

• H03K 3/356 - Bistable circuits
• G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
• H03K 3/037 - Bistable circuits
• H03K 3/288 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
• H03K 3/289 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable of the primary-secondary type
• H03K 3/3562 - Bistable circuits of the primary-secondary type
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
• H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
• H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
• H10B 99/00 - Subject matter not provided for in other groups of this subclass

Abstract

A delay-enhanced inverter circuit (DE-inverter) includes: a non-delay-enhanced inverter circuit (NE-inverter) having an output at a first node and an input at a second node; and a capacitive device feedback-coupled between the first node and the second node. The capacitive device includes: a first positive-channel metal-oxide (PMOS) field-effect transistor (FET) (PFET) feedback-coupled between the first node and the second node, the first PFET having a capacitor-configuration; and a first negative-channel metal-oxide (NMOS) FET (NFET) feedback-coupled feedback-between the first node and the first reference voltage, the first NFET having a capacitor-configuration.

IPC Classes  ?

• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
• H03K 19/0948 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET using CMOS

Abstract

A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management

Abstract

An integrated circuit includes an input circuit coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal, and a level shifter circuit coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second or third input signal. The input circuit includes a first set of transistors having a first threshold voltage. The first set of transistors includes a first set of active regions extending in a first direction. The level shifter circuit includes a second set of transistors having a second threshold voltage. The second set of transistors includes a second set of active regions extending in the first direction.

IPC Classes  ?

• H03K 3/037 - Bistable circuits
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only

Abstract

A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.

IPC Classes  ?

• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/373 - Design optimisation
• G06F 30/394 - Routing
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Abstract

A method of testing an integrated circuit on a test circuit board includes performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design, and simultaneously performing a burn-in test of the integrated circuit and an automated test of the integrated circuit. The burn-in test has a minimum burn-in temperature of the integrated circuit or a burn-in heat distribution across the integrated circuit that includes a set of circuit blocks or a first set of heaters. The integrated circuit design corresponding to the integrated circuit. The performing the simulation includes determining a heat signature of the integrated circuit design from configured power information or location information for each circuit block of the set of circuit blocks or each heater of the set of heaters included in the integrated circuit design. The heat signature includes heat values distributed throughout the integrated circuit design.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G01R 31/317 - Testing of digital circuits
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 119/08 - Thermal analysis or thermal optimisation

Abstract

A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 21/8234 - MIS technology
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A scan flip-flop circuit includes a selection circuit including first and second input terminals coupled to first and second I/O nodes, a flip-flop circuit coupled to the selection circuit, a first driver coupled between the flip-flop circuit and the first I/O node, and a second driver coupled between the flip-flop circuit and the second I/O node. The selection circuit and drivers receive a scan direction signal. In response to a first logic level of the scan direction signal, the selection circuit responds to a first signal received at the first input terminal, and the second driver outputs a second signal responsive to a flip-flop circuit output signal. In response to a second logic level of the scan direction signal, the selection circuit responds to a third signal received at the second input terminal, and the first driver outputs a fourth signal responsive to the flip-flop circuit output signal.

IPC Classes  ?

• H03K 3/037 - Bistable circuits
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
• H03K 19/0948 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET using CMOS

Abstract

An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.

IPC Classes  ?

• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 11/418 - Address circuits
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

An integrated circuit (IC) device includes at least one circuit having an input and an output, and an output connector electrically coupled to the output. The circuit further includes a plurality of transistors electrically coupled with each other between the input and the output. The output is in a first metal layer. The output connector includes a first conductive pattern in the first metal layer, and a second conductive pattern in a second metal layer different from the first metal layer. The second conductive pattern electrically couples the output to the first conductive pattern.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• G06F 119/12 - Timing analysis or timing optimisation

Abstract

An integrated circuit includes a first terminal-conductor, a second terminal-conductor, and a gate-conductor between the first terminal-conductor and the second terminal-conductor. The first terminal-conductor intersects both an active-region structure and a power rail. The second terminal-conductor intersects the active-region structure without intersecting the power rail. The gate-conductor intersects the active-region structure and is adjacent to the first terminal-conductor and the second terminal-conductor. A first width of the first terminal-conductor is larger than a second width of the second terminal-conductor by a predetermined amount.

IPC Classes  ?

• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure

Abstract

A method of manufacturing an IC structure includes configuring each of an n-well and a p-well in a first IC die to have a first portion extending in a first direction and second and third portions extending from the first portion in a second direction perpendicular to the first direction, and forming IC devices including a first pickup structure electrically connected to the n-well and a second pickup structure electrically connected to the p-well. Forming the IC devices includes forming a PMOS transistor in the second or third portion of the n-well and forming an NMOS transistor in the second or third portion of the p-well.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Abstract

A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.

IPC Classes  ?

• G11C 11/408 - Address circuits
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• G11C 11/4094 - Bit-line management or control circuits

Abstract

A semiconductor device includes a first dummy group having a first set of dummy transistors; a first delay cell having a first set of active transistors; a second delay cell having a second set of active transistors; a second dummy group having a second set of dummy transistors; and relative to a first direction the first and second dummy groups and the first and second delay cells being arranged in a first sequence arranged as the first dummy group, the first delay cell, the second delay cell, and the second dummy group; and the first and second delay cells being free from having another dummy group therebetween.

IPC Classes  ?

• H03K 3/00 - Circuits for generating electric pulsesMonostable, bistable or multistable circuits
• H03K 3/037 - Bistable circuits
• H03K 3/356 - Bistable circuits
• H03K 3/86 - Generating pulses by means of delay lines and not covered by the preceding subgroups

Abstract

An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, and a branch-two transistor. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is connected to the first node. Each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor of a reduced threshold. Each of the branch-one transistor and the branch-two transistor is a second-type transistor of a default threshold.

IPC Classes  ?

• H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
• G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• H03K 3/037 - Bistable circuits
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• G06F 117/04 - Clock gating

Abstract

A semiconductor device includes: first and second input circuits in a central region and correspondingly configured to operate in a first voltage domain; first and second single bit level shifters (SBLSs) correspondingly in first and second regions at first and second sides of the central region relative to a first direction and electrically coupled correspondingly to the first and second input circuits, and correspondingly configured to operate in a second voltage domain; and a control circuit configured to toggle each of the first and second SBLSs between a normal state and a standby state when a control signal is received from the control circuit.

IPC Classes  ?

• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• H03K 3/356 - Bistable circuits

Abstract

A method of generating an integrated circuit (IC) layout diagram includes arranging a first portion of first through fourth pluralities of active regions and a plurality of gate regions of a cell as a functional circuit in a first portion of the cell, arranging a second portion of the first through fourth pluralities of active regions and the plurality of gate regions of the cell as a one of a decoupling capacitor or an antenna diode in a second portion of the cell, and storing an IC layout diagram of the cell in a storage device.

IPC Classes  ?

• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 119/06 - Power analysis or power optimisation

Abstract

A method includes receiving, in a first vessel, a flow of fluid from a second vessel, wherein the flow of fluid is generated by pressurizing a head space over the fluid in the second vessel; capturing the flow of fluid from the second vessel at an upper end of a de-bubbling slide in the first vessel; and directing the flow of fluid along a flow surface of de-bubbling slide to a lower portion of the first vessel, such that bubbles and dissolved gases in the fluid exit the fluid on the flow surface of the de-bubbling slide.

IPC Classes  ?

• B01D 19/00 - Degasification of liquids
• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor

Abstract

A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management

Abstract

A method of conditioning a polishing pad includes conditioning the polishing pad using a conditioner. The method includes detecting a roughness of the polishing pad following the conditioning. The method further includes tracking a number of iterations of the conditioning of the polishing pad. The method further includes outputting a signal for replacing the polishing pad in response to the number of iterations reaching an iteration limit. The method further includes repeating the conditioning in response to the detected roughness of the polishing pad being outside of a threshold roughness range and the number of iterations failing to reach the iteration limit.

IPC Classes  ?

• B24B 53/017 - Devices or means for dressing, cleaning or otherwise conditioning lapping tools
• B24B 37/20 - Lapping pads for working plane surfaces
• B24B 53/013 - Application of loose grinding agent as auxiliary tool during truing operation

Abstract

A semiconductor device includes: a cell region including active regions where components of transistors are formed; the cell region are arranged to function as a D flip-flop that includes a primary latch (having a first sleepy inverter and a first non-sleepy (NS) inverter), a secondary latch (having a second sleepy inverter and a second NS inverter), and a clock buffer (having third and fourth NS inverters). The transistors are grouped: a first group has a standard threshold voltage (Vt_std); a second group has a low threshold voltage (Vt_low); and an optional third group has a high threshold voltage (Vt_high). The transistors which comprise the first or second NS inverter have Vt_low. Alternatively, the transistors of the cell region are further arranged to function as a scan-insertion type of D flip-flop (SDFQ) that further includes a multiplexer; and the transistors of the multiplexer have Vt_low.

IPC Classes  ?

• H03K 3/037 - Bistable circuits
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.

IPC Classes  ?

• H10D 89/10 - Integrated device layouts
• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
• H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs

Abstract

An IC structure includes first and second gates, first and second source regions, a shared drain region, and an isolation region. The first gate has a first portion extending along a first direction and a second portion extending along a second direction. The second gate has a first portion extending along the first direction and a second portion extending along the second direction. The shared drain region extends from the first portion of the first gate to the first portion of the second gate. The first source region is spaced apart from the shared drain region by the first gate. The second source region is spaced apart from the shared drain region by the second gate. The isolation region is between the first portion of the first gate and the first portion of the second gate, and resembles a quadrilateral pattern bordering the shared drain region.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• H01L 21/762 - Dielectric regions

Abstract

A method includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group has a unique dominant feature among a plurality of features of the plurality of paths. The method further includes testing a path in a group and, when the path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram. The plurality of features includes a numerical feature having a numerical value, and a categorical feature having a non-numerical value. The non-numerical value is converted into a converted numerical value. The plurality of groups is created based on the numerical value of the numerical feature, and the converted numerical value of the categorical feature.

IPC Classes  ?

• G06F 30/327 - Logic synthesisBehaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
• G06F 30/333 - Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
• G06F 119/18 - Manufacturability analysis or optimisation for manufacturability

Abstract

A semiconductor device has a cell region including active regions that extend in a first direction and in which are formed components of transistors. The transistors of the cell region are arranged to function as a scan insertion D flip flop (SDFQ). The SDFQ includes a multiplexer serially connected at an internal node to a D flip-flop (FF). The transistors of the multiplexer include data transistors for selecting a data input signal, the data transistors having a first channel configuration with a first channel size, and scan transistors of the multiplexer for selecting a scan input signal, the scan transistors having a second channel configuration with a second channel size. The second channel size is smaller than the first channel size.

IPC Classes  ?

• G06F 7/50 - AddingSubtracting
• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• H03K 3/353 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement

Abstract

A circuit includes a series of a first latch circuit, selection circuit, second latch circuit, and pre-decoder. A control circuit, based on a clock signal, outputs control signals to the selection circuit and first and second latch circuits, and, to the pre-decoder, a pulse signal including a first pulse during a first portion of a clock period in response to a read enable signal having a first logical state, and a second pulse during a second portion of the clock period in response to a write enable signal having the first logical state. Based on the control signals, the selection circuit and first and second latch circuits output read and write addresses to the pre-decoder during the respective first and second clock period portions, and the pre-decoder outputs a partially decoded address in response to each of the read address and first pulse, and the write address and second pulse.

IPC Classes  ?

• G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
• G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• G11C 8/10 - Decoders
• G11C 11/418 - Address circuits
• G11C 11/419 - Read-write [R-W] circuits

Abstract

An integrated circuit includes a middle active-region structure between a group-one active-region structure and a group-two active-region structure. The integrated circuit also includes a main circuit, a group-one circuit, and a group-two circuit. The main circuit includes at least one boundary gate-conductor intersecting the middle active-region structure. The group-one circuit includes a group-one isolation structure separating the group-one active-region structure into a first part in the group-one circuit and a second part in a first adjacent circuit. The group-two circuit includes a group-two isolation structure separating the group-two active-region structure into a first part in the group-two circuit and a second part in a second adjacent circuit.

IPC Classes  ?

• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/30 - Circuit design
• G06F 119/18 - Manufacturability analysis or optimisation for manufacturability

Abstract

A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits
• G11C 11/418 - Address circuits
• H03K 3/037 - Bistable circuits

Abstract

A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

A method (of manufacturing a semiconductor device) includes: migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, at least the second netlist being stored on a non-transitory computer-readable medium, the migrating including: generating first versions correspondingly of the first and second netlists; abstracting selected components in the first version of the second netlist and correspondingly in the first version of the second netlist to form corresponding second versions of the second and first netlists; performing a logic equivalence check (LEC) between the second versions of the first and second netlists, thereby identifying migration errors; and revising the second version of the second netlist to reduce the migration errors, thereby resulting in a third version of the second netlist.

IPC Classes  ?

• G06F 30/323 - Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
• G06F 30/3323 - Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/394 - Routing
• G06F 119/12 - Timing analysis or timing optimisation

Abstract

A semiconductor device includes: a cell region including active regions that extend in a first direction and have components of corresponding transistors formed therein; a first majority of the active regions being rectangular; a first one of the active regions having a T-shape including a stem that extends in a second direction perpendicular to the first direction, and, relative to the first direction, first and second arms that extend from a same end of the stem and away from each other; and, relative to the first direction, a second majority of the active regions having aligned first ends defining a first reference line proximate and parallel to a first boundary of the cell region, and a third majority of the active regions having aligned second ends defining a second reference line proximate and parallel to a second boundary of the cell region.

IPC Classes  ?

• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• G06F 1/12 - Synchronisation of different clock signals
• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management

Abstract

In some embodiments, a method of generating a cell in a layout diagram includes: selecting a cell from a library of standard cells, components of the cell defining an active circuit; identifying a dummy device within the cell that is disconnected from the active circuit within the cell; and connecting the dummy device to a target node of the active circuit.

IPC Classes  ?

• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/33 - Design verification, e.g. functional simulation or model checking
• G06F 111/20 - Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• G06F 119/06 - Power analysis or power optimisation
• G06F 119/18 - Manufacturability analysis or optimisation for manufacturability

Abstract

A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 5/14 - Power supply arrangements
• G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• G11C 8/10 - Decoders

Abstract

An integrated circuit (IC) device includes first and second power rails extending in a first direction, a third power rail extending in the first direction between the first and second power rails, gate structures extending perpendicular to the first direction, each of two endmost gate structures extending continuously between endpoints underlying the first and second power rails, and first through fourth pluralities of active areas extending in the first direction between the endmost gate structures. Active areas of each of the first through fourth pluralities of active areas are aligned in the first direction, a first portion of the gate structures and first through fourth pluralities of active areas is configured as a functional circuit, and a second portion of the gate structures and first through fourth pluralities of active areas is configured as one of a decoupling capacitor or an antenna diode.

IPC Classes  ?

• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 119/06 - Power analysis or power optimisation

Abstract

An integrated circuit includes an array of first-type active-region structures and an array of second-type active-region structures extending in a first direction between a first vertical zone-boundary of a first keep-out zone and the second vertical zone-boundary of a second keep-out zone. The integrated circuit also includes an array of first-side boundary cells aligned with the first vertical zone-boundary and an array of second-side boundary cells aligned with the second vertical zone-boundary. In the array of first-side boundary cells, a first-side boundary cell has a first ESD protection circuit and a pick-up region. In the array of second-side boundary cells, a second-side boundary cell has a second ESD protection circuit.

IPC Classes  ?

• H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A voltage regulator includes a control circuit configured to output a plurality of enable signals, and a power stage including a plurality of phase circuits. Each phase circuit of the plurality of phase circuits includes a node, an inductor coupled between the node and an output node of the voltage regulator, a plurality of p-type transistors coupled between the node and a power supply node of the voltage regulator, and a plurality of n-type transistors coupled between the node and a reference node of the voltage regulator. Each phase circuit of the plurality of phase circuits is configured to, responsive to the plurality of enable signals, selectively couple the node to the power supply node through a first subset or all of the plurality of p-type transistors, and selectively couple the node to the reference node through a second subset or all of the plurality of n-type transistors.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control

Abstract

A semiconductor device includes a first conductivity-type substrate, and a cell region including: a second conductivity type deep well; first and second non-deep wells having the second conductivity-type, the first and second non-deep wells being in corresponding first and second portions of the substrate, the first and second portions of the substrate being in the deep well; and first, second, third and fourth transistor-regions. The first and second transistor-regions are correspondingly in the first and second non-deep wells and include first conductivity-type first transistors. The third and fourth transistor-regions are in the third and fourth portions of the substrate which are in the deep well, and include second transistors having the second conductivity-type. The first transistor-region is configured for a first power domain. The second, third and fourth transistor-regions are configured for a second power domain that is different than the first power domain.

IPC Classes  ?

• H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
• H03K 3/356 - Bistable circuits
• H03K 19/003 - Modifications for increasing the reliability
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 89/10 - Integrated device layouts

Abstract

A circuit includes an input circuit, a level shifter circuit and an output circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal. The level shifter circuit is coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second input signal or the third input signal. The level shifter circuit includes a header circuit coupled to a first node, and is configured to enable or disable the level shifter circuit responsive to the first enable signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and is configured to generate an output signal.

IPC Classes  ?

• H03K 3/037 - Bistable circuits
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only