|
2025
|
Invention
|
Method of testing an integrated circuit and testing system.
A method of testing an integrated ci... |
|
|
Invention
|
Memory structure with optimized latch clock design.
A memory device is provided and includes a m... |
|
|
Invention
|
Static random access memory with adaptive precharge signal generated in response to tracking oper... |
|
|
Invention
|
Memory circuit and method of operating same.
A memory circuit includes a control circuit coupled... |
|
|
Invention
|
Memory device and operating method thereof.
A memory device is provided, including at least one ... |
|
|
Invention
|
Semiconductor device with common deep n-well for different voltage domains and method of forming ... |
|
|
Invention
|
System and method for esl modeling of machine learning.
A system for designing a semiconductor d... |
|
|
Invention
|
Combined function ic device and method of fabricating the same.
An IC device includes first and ... |
|
|
Invention
|
Layout method and memory macro including through-silicon via.
A memory macro includes a first me... |
|
|
Invention
|
Method of operating a shared well integrated circuit.
A method of operating an IC includes recei... |
|
|
Invention
|
Integrated circuit device and method of manufacturing.
An integrated circuit (IC) device include... |
|
|
Invention
|
Voltage regulator circuit and method.
A voltage regulator includes a power supply voltage node, ... |
|
|
Invention
|
Semiconductor device having back end of line via to metal line margin improvement and method of m... |
|
|
Invention
|
Integrated circuit and method of manufacturing same.
An integrated circuit includes a Schmitt tr... |
|
|
Invention
|
Method and system for reducing migration errors.
A method (of manufacturing a semiconductor devi... |
|
|
Invention
|
Method of and apparatus for controlling clock signal.
An integrated circuit includes a clocking ... |
|
|
Invention
|
Level shifter circuit and method of operating the same.
An integrated circuit includes a first r... |
|
2024
|
Invention
|
Shared decoder circuit and method.
A memory circuit includes a control circuit configured to rec... |
|
|
Invention
|
Signal generator for controlling timing of signal in memory device.
A device includes a first me... |
|
|
Invention
|
Timing control circuit of memory device with tracking word line and tracking bit line.
A circuit... |
|
|
Invention
|
Bi-directional scan flip-flop circuit and method.
A scan flip-flop circuit includes first and se... |
|
|
Invention
|
Memory device and operating method thereof.
A memory device, comprising: a first driving circuit... |
|
|
Invention
|
Memory device.
A memory device includes a memory array, a first latch and a first logic element.... |
|
|
Invention
|
Coupling monitoring system.
A coupling including a main body, a first hub at a first end of the ... |
|
|
Invention
|
Methods of manufacturing flip-flop with transistors having different threshold voltages and semic... |
|
|
Invention
|
System, apparatus, and method for improving photoresist coating operations.
A coating system and... |
|
|
Invention
|
Multiplexer for sdfq having differently-sized scan and data transistors, semiconductor device inc... |
|
|
Invention
|
Semiconductor device.
A semiconductor device includes a connector layer; a dielectric layer over... |
|
|
Invention
|
System and method for esl modeling of machine learning. A non-transitory computer-readable storag... |
|
|
Invention
|
Trench etching process for photoresist line roughness improvement.
A method of forming a semicon... |
|
|
Invention
|
Method of forming semiconductor device including daisy-chained delay cells.
A method of forming ... |
|
|
Invention
|
Integrated circuit and an operation method thereof.
An integrated circuit includes a control cir... |
|
|
Invention
|
Integrated circuit device and method for fabricating the same.
An integrated circuit device incl... |
|
|
Invention
|
Integrated circuit with electrostatic discharge structure.
An integrated circuit includes a firs... |
|
|
Invention
|
Semiconductor device.
A semiconductor device includes a function circuit, an antenna circuit and... |
|
|
Invention
|
Memory circuit and method of operating same.
A memory circuit includes a first and second invert... |
|
|
Invention
|
Method for forming a timing circuit arrangements for flip-flops. An integrated circuit includes a... |
|
|
Invention
|
Method of fabricating transistor having expanded gate structure, and transistor fabricated thereb... |
|
|
Invention
|
Circuit and method for power management.
A circuit includes a memory circuit, and a power manage... |
|
2023
|
Invention
|
Memory device, write assist circuit, and method.
A memory device includes a memory cell in a fir... |
|
|
Invention
|
Memory device having tracking word line with adjust circuit, method of operating same and method ... |
|
|
Invention
|
Eco base cell structure, layout method, and system.
An IC structure includes first through third... |
|
|
Invention
|
Memory device and operating method thereof. A memory device is provided, including at least one b... |
|
|
Invention
|
Memory circuit and method of operating same. A memory circuit includes a control circuit coupled ... |
|
|
Invention
|
Memory device.
A memory device is provided, including at least one inverter, a transistor couple... |
|
|
Invention
|
Static voltage drop prediction system and method.
A method is provided, including following oper... |
|
|
Invention
|
System for physical verification runtime reduction and method of using same.
A method of perform... |
|
|
Invention
|
Semiconductor device iincluding delay-enhanced inverter circuit and method of forming same.
A de... |
