A virtualised PHY (V-PHY) Interface for the PCI Express protocol is provided to enable a first PIPE-compliant component located on a first circuit die to communicate with a second PIPE-compliant component located on a second circuit die, where the first and second circuit dies are communicatively coupled to one another via a die-to-die (D2D) interface. The V-PHY interface can enable this communication transparently so that neither the first component nor second component needs to have any knowledge of the D2D interface or indeed that they are communicating across dies.
Methods and systems are described for converting, using a first asynchronous ADC, an analog input signal to a digital output signal according to a first clock cycle, and outputting a done signal upon completion of the conversion, the first asynchronous ADC configured with a supply voltage large enough that the done signal is asserted prior to a next clock cycle with predetermined probability, generating, using a timing margin sensor comprising a programmable delay unit, a delayed done signal having a reduced timing margin, and measuring, using a dynamic voltage scaling controller, an error rate of the delayed done signal according to the next clock cycle, and adjusting the supply voltage provided to the first asynchronous ADC responsive to the measured error rate deviating from a target error rate by a predetermined threshold.
H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
H03M 1/50 - Analogue/digital converters with intermediate conversion to time interval
Methods and systems are described for obtaining a plurality of information bits, and responsively partitioning the obtained plurality of information bits into a plurality of subsets of information bits, generating a plurality of streams of forward error correction (FEC)-encoded bits using a plurality of FEC encoders receiving respective subsets of the plurality of subsets of information bits, providing the plurality of streams of FEC-encoded bits to a plurality of sub-channel encoders, each sub-channel encoder receiving a respective stream of FEC-encoded bits from a different FEC encoder of the plurality of FEC encoders for generating a set of codewords of a vector signaling code, and wherein sequential streams of FEC-encoded bits from a given FEC encoder are provided to different sub-channel encoders for each successively generated set of codewords, and transmitting the successively generated sets of codewords of the vector signaling code over a multi-wire bus.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/05 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
Methods and systems are described for mapping circuit configured to receive non-return-to-zero (NRZ) signals on one or more differential wire-pair interfaces, and to responsively map the NRZ signals as input signals to a plurality of forward sub-channels of an orthogonal differential vector signaling (ODVS) code, a set of line drivers, each line driver configured to receive a respective input from the mapping circuit and to provide an outbound signal on a respective output of a multi-wire interface according the plurality of forward sub-channels, and a multi-input comparator (MIC) configured to receive inbound signals from the multi-wire interface, the MIC configured to generate at least one output signal from the inbound signals based on a reverse sub-channel of the ODVS code, the reverse sub-channel corresponding to a balanced sub-channel that is mutually orthogonal to the plurality of forward sub-channels.
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
5.
MAPPING NON-RETURN-TO-ZERO TO ENSEMBLE NON-RETURN-TO-ZERO SIGNALING
Disclosed embodiments include systems and methods of operating systems comprising a first transceiver subsystem (102) connected to a second transceiver subsystem (104) via at least two four-wire groups (106), where the first transceiver subsystem is configured to convert between non-return-to-zero (NRZ) signals communicated via a first differential wire pair interface (122) and ensemble-NRZ (ENRZ) signals exchanged with the second transceiver subsystem via the at least two four-wire groups (106), and where the second transceiver subsystem is configured to convert between NRZ signals communicated via a second differential wire pair interface (136) ENRZ signals exchanged with the first transceiver subsystem via the at least two four-wire groups (106).
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
6.
TEST PATTERN VECTORS IN HOMOGENOUS MULTI-DIE PACKAGES
Connecting test equipment to an input pin of the MCM, transmitting pipeline delay configuration data for a first die-under-test (DUT) to configure a first die input pipeline register with a first delay value at a first die of the MCM, transmitting ATP data into a first die scan chain register in a predetermined number of clock cycles via the first delay value of the first die input pipeline register, configuring the first die to perform a scan chain test with the ATP datal, transmitting pipeline delay configuration data for a second DUT to configure the first die input pipeline register with a second delay value, transmitting the ATP data into a second die scan chain register in the predetermined number of clock cycles via the reconfigured first die input pipeline register and a die-to-die interconnect, and configuring the second die to perform a scan chain test with the ATP data.
Receiving, at an upstream pseudo-port of a first circuit die of a multi-die integrated circuit module (ICM), a plurality of serial data lanes associated with a PCIe data link, responsively generating respective deserialized lane-specific data words, providing the deserialized lane-specific data words for transmission via a downstream pseudo-port on the first circuit die of the multi-die ICM, the downstream pseudo-port having a PCIe data link to a first endpoint, responsive to a failure in the PCIe data link to the first endpoint, rerouting the deserialized lane-specific data words over an inter-die data interface using an inter-die adaptation layer protocol to a second circuit die of the multi-die ICM, receiving the deserialized lane-specific data words at the second circuit die from the inter-die data interface, and transmitting the deserialized lane-specific data words via a second downstream pseudo-port to a second endpoint via a second PCIe data link.
Methods and systems are described herein for exchanging retimer training status and state machine (RTSSM) status information between a plurality of circuit dies of a multi-chip module utilizing a ring bus configured to carry a multi-bit lane status signal using a plurality of time slots, the ring bus interconnecting the plurality of circuit dies into a ring of circuit dies, wherein each circuit die outputs stored aggregate RTSSM status information onto the ring bus to the next circuit die in the ring and stores the aggregate RTSSM status information from the preceding circuit die in the ring until each circuit die accrues the complete multi-die RTSSM status information for all of the circuit dies. Based on the complete multi-die RTSSM status information, each circuit die may synchronously execute state changes in the upstream and/or downstream RTSSMs on the circuit die.
Techniques for updating message definitions used by a PCIe component such as a retimer are described. The message definitions are provided within a firmware image that is checked for validity and authenticity during a firmware update process. This enables in-field updating of the message definitions in a secure manner, making it possible to securely expand or adjust the functionality offered by the component deployed in the field. In the case where the component is a retimer, the functionality can include delay buffer and/or lane routing settings that result in a reduced lane-to-lane skew. Techniques for in-band transmission of a data package such as a firmware update are also described.
A plurality of upstream pseudo-ports (PPs) of a first circuit die, each upstream PP having a connection to a respective one of at least two root complex devices, a plurality of downstream PPs of a second circuit die, each set of downstream PPs having connections to a respective one of at least two endpoints, an inter-die data interface between the first and second circuit dies having adaptation layer ports on each circuit die according to an adaptation layer protocol, lane routing logic in the first and second circuit dies configured to map at least one of the sets of upstream PPs and a corresponding set of downstream PPs to respective adaptation layer ports on the first and second circuit dies, and a processor on one of the first and second circuit dies for configuring the lane routing logic in both circuit dies.
A device control register is disclosed that stores a set of flags that set an access control level of an apparatus. The device control register includes a lock flag that controls access to the device control register itself, meaning that the device control register is self-referential as once locked the value of the lock flag cannot be changed until a cold reset is performed. The device control register can also include one or more interface flags that control bus leader access to a data bus of the apparatus and/or to functionality of the interface itself. The interface flag(s) is/are not accessible when the device control register is locked.
G06F 12/14 - Protection against unauthorised use of memory
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
A multi-chip module (MCM) is described herein which includes a number of components communicatively coupled by one or more busses (325, 625, 725, 725') and controlled by a processor (300). Some of these components require firmware to operate correctly. The firmware is typically loaded during an initialization process, called a "boot process". The system and methods described herein allow for updating of the firmware from time to time. Standards such as the Peripheral Component Interconnect Express (PCIe) standard typically place limits on boot time, e.g. a PCIe-compliant MCM may be required to be performing PCIe link training following boot after a certain time, e.g. 100ms or 120ms. Loading firmware during a boot process can take up a significant portion of this time, particularly in the case where multiple components require firmware to be loaded. Described herein is a technique that is capable of loading firmware to multiple MCM components in a time-efficient manner.
A multi-tile retimer is provided that includes a tile-to-tile bus that communicatively couples a leader tile and a follower tile. The multi-tile retimer implements one or more pairs of counters, where each counter in a pair is complementary to the other. Each counter increments based on detection of a particular tile-to-tile bus event, e.g. a read or write command, or data read. The value of one counter in the pair can be compared with the value of the other counter in the pair. A discrepancy in these values can indicate that a security breach may have occurred and/or that a communication error may have occurred on the tile-to-tile bus. Remedial action can be taken in response to such a discrepancy.
Receiving, at an upstream pseudo-port having physical layer circuits (PHYs) spread across at least two circuit dies of a multi-die integrated circuit module (ICM), a plurality of serial data lanes, and responsively generating respective deserialized lane-specific data words, selecting a first or a second downstream pseudo-port having PHYs spread across the at least two circuit dies of the ICM, the first and second downstream pseudo-ports having respective PCIe data links to first and second endpoints, respectively, storing the deserialized lane-specific data words for each serial data lane in corresponding PCS-mode FIFOs associated with the selected downstream pseudo-port, the corresponding PCS-mode FIFOs having output alignment across the plurality of serial data lanes received at the at least two circuit dies, and providing the deserialized lane-specific data words for transmission via the PHYs of the selected downstream pseudo-port.
Methods and systems are described for performing multi-lane alignment and rate adaptation between tiles (1304, 1302) in a multi¬ file package (1300), specifically exchanging alignment information (algn_found, rpcs_algn_ctl) across clock domains for different tiles (1304, 1302) based on a write tile clock (wr_tile_clk) generated from a local system clock (tx_clk) in a leader tile (1302), the write tile clock (wr_tile_clock) having a period equal to a common reference clock (refclk), the write tile clock (wr_tile_clock) corresponding to a pulse having a location within the period of the common reference clock (refclk) as determined by an active cycle of a counter.
Methods and systems are described for calculating lane-to-lane skew parameters from detected alignment symbols during a skew measurement mode of operation, detecting a command to switch from skew measurement mode to a transparent mode of operation, wherein each of the plurality of encoded data streams are routed to respective low-latency CDC FIFOs configured to store the encoded data streams using respective write clocks and to output encoded data streams based on corresponding read clocks, each read clock synchronized to a corresponding write clock, and adjusting a timing of a first encoded data stream relative to a second encoded data stream based on the set of lane-to-lane skew parameters generated in the PCS to reduce lane-to-lane skew.
Orthogonal differential vector signalling (ODVS) techniques are described. The ODVS encoding schemes described herein generate one sub-channel for each bit by multiplying each bit by a different row in a transmitter encoding matrix to produce a set of sub-channels. Each wire carries a signal that is a superposition of elements from all of the sub-channels in the set. The transmitter encoding matrix is selected such that its rows (i.e. sub-channels) are mutual orthogonal. This means that the receiver can decode the signals received from all wires in concert to reliably recover the original bits. The transmitter encoding matrix applies weights to each sub-channel of the set, with the absolute magnitude of the weights decreasing as the number of wires associated with the respective sub-channel increases.
Pre-scaled orthogonal differential vector signalling (ODVS) techniques are described. The ODVS encoding schemes described herein generate one sub-channel for each bit by multiplying each bit by a different row in a transmitter encoding matrix to produce a set of sub-channels. Each wire carries a signal that is a superposition of elements from all of the sub-channels in the set. The transmitter encoding matrix is selected such that its rows (i.e. sub-channels) are mutual orthogonal. This means that the receiver can decode the signals received from all wires in concert to reliably recover the original bits. The transmitter encoding matrix is a Hadamard matrix in some cases. This disclosure is particularly focussed on ODVS techniques that apply a scaling factor, termed a 'pre-scaler', to a weaker sub-channel or sub-channels within the set of sub-channels so as to boost that/those sub-channel(s) relative to the other sub-channels.
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
19.
LINE DRIVER IMPEDANCE CALIBRATION FOR MULTI-WIRE DATA BUS
Methods and systems are described for an output driver composed of complementary metal-oxide semiconductor (CMOS) devices, the output driver having a line driver control stage configured to selectively output a reference voltage or a first supply voltage at the control stage output node in response to a data signal, and a line driver output circuit configured to generate an output signal on a multi-wire bus, wherein the CMOS devices of the line driver output circuit are calibrated to have an on-resistance matched to a termination impedance via first and second supply voltages provided to the line driver control stage and the line driver output circuit, respectively.
Methods and systems are described for an output driver composed of complementary metal-oxide semiconductor (CMOS) devices, the output driver having a line driver control stage configured to selectively output a reference voltage or a first supply voltage at the control stage output node in response to a data signal, and a line driver output circuit configured to generate an output signal on a multi-wire bus, wherein the CMOS devices of the line driver output circuit are calibrated to have an on-resistance matched to a termination impedance via first and second supply voltages provided to the line driver control stage and the line driver output circuit, respectively.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
Pre-scaled orthogonal differential vector signalling (ODVS) techniques are described. The ODVS encoding schemes described herein generate one sub-channel for each bit by multiplying each bit by a different row in a transmitter encoding matrix to produce a set of sub-channels. Each wire carries a signal that is a superposition of elements from all of the sub-channels in the set. The transmitter encoding matrix is selected such that its rows (i.e. sub-channels) are mutual orthogonal. This means that the receiver can decode the signals received from all wires in concert to reliably recover the original bits. The transmitter encoding matrix is a Hadamard matrix in some cases. This disclosure is particularly focussed on ODVS techniques that apply a scaling factor, termed a ‘pre-scaler’, to a weaker sub-channel or sub-channels within the set of sub-channels so as to boost that/those sub-channel(s) relative to the other sub-channels.
Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
B41J 2/00 - Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
H03M 5/14 - Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
24.
Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation
Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H04L 7/00 - Arrangements for synchronising receiver with transmitter
25.
Clock data recovery with decision feedback equalization
Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
26.
VARIABLE GAIN AMPLIFIER WITH CROSS-COUPLED COMMON MODE REDUCTION
Methods and systems for receiving a differential input voltage signal at an input of a variable gain amplifier, and responsively generating an amplified differential output voltage signal on a pair of output nodes by driving a pair of load impedances connected to the pair of output nodes with an amplifier current according to the differential input voltage signal, enabling a cross-coupled differential pair connected in parallel to the pair of load impedances, the cross-coupled differential pair having drain inputs and cross-coupled gate inputs connected to the pair of output nodes to supplement a gain of the amplified differential voltage output voltage signal, and reducing a common mode voltage of the amplified differential output voltage signal by lowering the amplifier current driving the pair of load impedances via a bias control signal, the amplifier current lowered responsive to detecting the supplemented gain of the amplified differential output voltage signal.
Obtaining a bias control signal at a current source and responsively generating a fixed current, receiving a differential voltage input signal at corresponding differential input nodes of a plurality of differential amplifier stages connected to the current source, the plurality of differential amplifier stages comprising a primary amplifier stage and a set of supplemental amplifier stages, each of the plurality of differential amplifier stages having a pair of output nodes connected to common load impedances, generating an amplified differential voltage output signal on the pair of output nodes by directing the fixed current through the load impedances, and selectively connecting each supplemental amplifier stage in parallel to the primary amplifier stage via a corresponding gain control switch of a set of gain control switches connected to the primary amplifier stage and the plurality of supplemental amplifier stages to adjust an overall transconductance of the plurality of differential amplifier stages.
Methods are described for identifying and acting upon predetermined message patterns during reception of a data stream structured as USB message frames. A first embodiment performs pattern matching between received message bits and one or more predetermined sequences, identifying unscrambled ordered set messages. A second embodiment applies a descrambling operation and performs comparable pattern matching between descrambled received message bits and one or more additional predetermined sequences, identifying scrambled ordered set messages.
Methods and systems are described for generating a time-varying information signal at an output of a continuous time linear equalizer (CTLE), asynchronously sampling a data signal according to a sampling clock having a frequency less than a data rate of the data signal; generating corresponding pattern-verified samples for at least two data patterns, each of the at least two data patterns having a respective frequency content; determining corresponding frequency-specific voltage measurements associated with each of the at least two data patterns based on the corresponding pattern-verified samples of the at least two data patterns; and adjusting an equalization of the data signal based on a comparison of the corresponding frequency-specific voltage measurements.
Methods and systems are described for adjusting the sample timing of a data sampler operating in a data signal processing path having a decision threshold associated with a decision feedback equalization (DFE) correction factor. The vertical threshold and sample timing of a spare sampler are varied to measure a signal amplitude trajectory of a pattern-verified signal according to detection of the predetermined transitional data pattern, the locked sampling point then being adjusted based on the measured signal amplitude trajectory.
Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
32.
Horizontal centering of sampling point using vertical vernier
Methods and systems are described for measuring a vertical opening of a signal eye of a pulse amplitude modulated (PAM) signal received over a channel to determine a vertically-centered voltage decision threshold of a sampler receiving a sampling clock, determining channel-characteristic parameters indicative of a frequency response of the channel, determining a correctional vernier value from the channel-characteristic parameters, and generating a horizontally-centered voltage decision threshold that introduces a horizontal sampling offset in the sampling clock in a direction closer to a horizontal center of the signal eye by combining the vertically-centered voltage decision threshold and the correctional vernier value.
Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.
H04B 3/14 - Control of transmissionEqualising characterised by the equalising network used
H04L 25/08 - Modifications for reducing interferenceModifications for reducing effects due to line faults
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H01Q 13/24 - Non-resonant leaky-waveguide or transmission-line antennas Equivalent structures causing radiation along the transmission path of a guided wave constituted by a dielectric or ferromagnetic rod or pipe
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H04L 27/148 - Demodulator circuitsReceiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using filters, including PLL-type filters
Equalizing an input signal according to a receiver equalizer peaking circuit having a capacitor FET (CFET) providing a capacitive value and a resistor FET (RFET) providing a resistive value, generating a capacitor control voltage at a gate of the CFET using a capacitor controller DAC based on a first reference voltage, and a RFET control voltage at a gate of the RFET using a resistor controller DAC based on a second reference voltage, generating the first reference voltage using a replica input FET, the first reference voltage varying according to a threshold voltage (Vt) of an input FET, providing the first reference voltage to the capacitor controller DAC, generating the second reference voltage using a replica RFET, the second reference voltage varying with respect to the first reference voltage and a Vt of the replica of the RFET, and providing the second reference voltage to the resistor controller DAC.
H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage
H03F 3/16 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
H03G 3/30 - Automatic control in amplifiers having semiconductor devices
Methods and systems are described for generating early and late votes for a clock recovery system, each early or late vote associated with a detected transitional data pattern in a data stream, generating a first early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a first time interval, generating a second early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a second time interval, comparing the first and the second early-late vote measurements, and outputting a CDR-lock signal at least in part responsive to determining that the first and the second early-late vote measurements are within a predetermined threshold.
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
38.
Dynamic voltage scaling in hierarchical multitier regulator supply
Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.
Methods and systems are described for measuring a vertical opening of a signal eye of a pulse amplitude modulated (PAM) signal received over a channel to determine a vertically-centered voltage decision threshold of a sampler receiving a sampling clock, determining channel-characteristic parameters indicative of a frequency response of the channel, determining a correctional vernier value from the channel-characteristic parameters, and generating a horizontally-centered voltage decision threshold that introduces a horizontal sampling offset in the sampling clock in a direction closer to a horizontal center of the signal eye by combining the vertically-centered voltage decision threshold and the correctional vernier value.
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
40.
Continuous time linear equalization and bandwidth adaptation using peak detector
Methods and systems are described for asynchronously measuring an equalized information signal to obtain amplitude information, modifying frequency dependent parameters of a continuous-time linear equalization (CTLE) component of the signal path, determining a correlation between CTLE parameters and signal amplitude, and adjusting, responsive to the correlation, a continuous-time linear equalization (CTLE) code of a CTLE to adjust equalization of the equalized information signal.
Methods and systems are described for measuring a vertical opening of a signal eye of a pulse amplitude modulated (PAM) signal received over a channel to determine a vertically-centered voltage decision threshold of a sampler receiving a sampling clock, determining channel-characteristic parameters indicative of a frequency response of the channel, determining a correctional vernier value from the channel-characteristic parameters, and generating a horizontally-centered voltage decision threshold that introduces a horizontal sampling offset in the sampling clock in a direction closer to a horizontal center of the signal eye by combining the vertically-centered voltage decision threshold and the correctional vernier value.
Equalizing an input signal according to a receiver equalizer peaking circuit having a capacitor FET (CFET) providing a capacitive value and a resistor FET (RFET) providing a resistive value, generating a capacitor control voltage at a gate of the CFET using a capacitor controller DAC based on a first reference voltage, and a RFET control voltage at a gate of the RFET using a resistor controller DAC based on a second reference voltage, generating the first reference voltage using a replica input FET, the first reference voltage varying according to a threshold voltage (Vt) of an input FET, providing the first reference voltage to the capacitor controller DAC, generating the second reference voltage using a replica RFET, the second reference voltage varying with respect to the first reference voltage and a Vt of the replica of the RFET, and providing the second reference voltage to the resistor controller DAC.
Methods and systems are described for asynchronously measuring an equalized information signal to obtain amplitude information, modifying frequency dependent parameters of a continuous-time linear equalization (CTLE) component of the signal path, determining a correlation between CTLE parameters and signal amplitude, and adjusting, responsive to the correlation, a continuous-time linear equalization (CTLE) code of a CTLE to adjust equalization of the equalized information signal.
Methods and systems are described for generating a time-varying information signal at an output of a continuous time linear equalizer (CTLE), asynchronously sampling a data signal according to a sampling clock having a frequency less than a data rate of the data signal; generating corresponding pattern-verified samples for at least two data patterns, each of the at least two data patterns having a respective frequency content; determining corresponding frequency-specific voltage measurements associated with each of the at least two data patterns based on the corresponding pattern-verified samples of the at least two data patterns; and adjusting an equalization of the data signal based on a comparison of the corresponding frequency-specific voltage measurements.
Methods and systems are described for adjusting the sample timing of a data sampler operating in a data signal processing path having a decision threshold associated with a decision feedback equalization (DFE) correction factor. The vertical threshold and sample timing of a spare sampler are varied to measure a signal amplitude trajectory of a pattern-verified signal according to detection of the predetermined transitional data pattern, the locked sampling point then being adjusted based on the measured signal amplitude trajectory.
Methods and systems are described for adjusting the sample timing of a data sampler operating in a data signal processing path having a decision threshold associated with a decision feedback equalization (DFE) correction factor. The vertical threshold and sample timing of a spare sampler are varied to measure a signal amplitude trajectory of a pattern-verified signal according to detection of the predetermined transitional data pattern, the locked sampling point then being adjusted based on the measured signal amplitude trajectory.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
47.
Methods and systems for high bandwidth communications interface
A pair of ground planes arranged in parallel, a dielectric medium disposed in between the pair of ground planes, and a set of at least four signal conductors disposed in the dielectric medium, the set of at least four signal conductors having (i) a first pair of signal conductors arranged proximate to a first ground plane of the pair of ground planes and (ii) a second pair of signal conductors arranged proximate to a second ground plane of the pair of ground planes, each signal conductor of the set of at least four signal conductors configured to carry a respective signal corresponding to a symbol of a codeword of a vector signaling code.
H04L 25/08 - Modifications for reducing interferenceModifications for reducing effects due to line faults
G01R 31/3183 - Generation of test inputs, e.g. test vectors, patterns or sequences
H01L 29/768 - Charge-coupled devices with field effect produced by an insulated gate
H01Q 13/24 - Non-resonant leaky-waveguide or transmission-line antennas Equivalent structures causing radiation along the transmission path of a guided wave constituted by a dielectric or ferromagnetic rod or pipe
H01Q 13/28 - Non-resonant leaky-waveguide or transmission-line antennas Equivalent structures causing radiation along the transmission path of a guided wave comprising elements constituting electric discontinuities and spaced in direction of wave propagation, e.g. dielectric elements or conductive elements forming artificial dielectric
H01R 12/00 - Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocksCoupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structuresTerminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
H04L 5/02 - Channels characterised by the type of signal
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H03M 5/04 - Conversion to or from representation by pulses the pulses having two levels
H03M 5/16 - Conversion to or from representation by pulses the pulses having three levels
H03M 13/31 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining coding for error detection or correction and efficient use of the spectrum
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
48.
Interleaved forward error correction over multiple transport channels
Interleaved Forward Error Correction (FEC) encoded data from multiple FEC encoders for transport over a multi-channel physical transport medium, with cyclical rotation of the FEC encoded data bytes across transport channels in a given transmission interval as well as across time within each transport channel. A plurality of parallel FEC encoders are used to generate respective parallel FEC-encoded data streams, the outputs of which are then interleaved across a plurality of transport channels in a given transmission time interval, and, within each transport channel, the interleaved order varies over the time intervals.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H03M 13/05 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
H04L 25/08 - Modifications for reducing interferenceModifications for reducing effects due to line faults
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
49.
CONTINUOUS TIME LINEAR EQUALIZATION AND BANDWIDTH ADAPTATION USING ASYNCHRONOUS SAMPLING
Methods and systems are described for generating a time-varying information signal at an output of a continuous time linear equalizer (CTLE), asynchronously sampling a data signal according to a sampling clock having a frequency less than a data rate of the data signal; generating corresponding pattern-verified samples for at least two data patterns, each of the at least two data patterns having a respective frequency content; determining corresponding frequency-specific voltage measurements associated with each of the at least two data patterns based on the corresponding pattern-verified samples of the at least two data patterns; and adjusting an equalization of the data signal based on a comparison of the corresponding frequency-specific voltage measurements.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
50.
Skew detection and correction for orthogonal differential vector signaling codes
Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.
Methods and systems are described for generating early and late votes for a clock recovery system, each early or late vote associated with a detected transitional data pattern in a data stream, generating a first early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a first time interval, generating a second early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a second time interval, comparing the first and the second early-late vote measurements, and outputting a CDR-lock signal at least in part responsive to determining that the first and the second early-late vote measurements are within a predetermined threshold.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03L 7/10 - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
52.
Clock and data recovery lock detection circuit for verifying lock condition in presence of imbalanced early to late vote ratios
Methods and systems are described for generating early and late votes for a clock recovery system, each early or late vote associated with a detected transitional data pattern in a data stream, generating a first early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a first time interval, generating a second early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a second time interval, comparing the first and the second early-late vote measurements, and outputting a CDR-lock signal at least in part responsive to determining that the first and the second early-late vote measurements are within a predetermined threshold.
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
53.
Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation
Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H04L 7/00 - Arrangements for synchronising receiver with transmitter
Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
B41J 2/00 - Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
H03M 5/14 - Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
Equalizing an input signal according to a receiver equalizer peaking circuit having a capacitor FET (CFET) providing a capacitive value and a resistor FET (RFET) providing a resistive value, generating a capacitor control voltage at a gate of the CFET using a capacitor controller DAC based on a first reference voltage, and a RFET control voltage at a gate of the RFET using a resistor controller DAC based on a second reference voltage, generating the first reference voltage using a replica input FET, the first reference voltage varying according to a threshold voltage (Vt) of an input FET, providing the first reference voltage to the capacitor controller DAC, generating the second reference voltage using a replica RFET, the second reference voltage varying with respect to the first reference voltage and a Vt of the replica of the RFET, and providing the second reference voltage to the resistor controller DAC.
H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage
H03F 3/16 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
H03G 3/30 - Automatic control in amplifiers having semiconductor devices
Methods are described for identifying and acting upon predetermined message patterns during reception of a data stream structured as USB message frames. A first embodiment performs pattern matching between received message bits and one or more predetermined sequences, identifying unscrambled ordered set messages. A second embodiment applies a descrambling operation and performs comparable pattern matching between descrambled received message bits and one or more additional predetermined sequences, identifying scrambled ordered set messages.
Methods are described for identifying and acting upon predetermined message patterns during reception of a data stream structured as USB message frames. A first embodiment performs pattern matching between received message bits and one or more predetermined sequences, identifying unscrambled ordered set messages. A second embodiment applies a descrambling operation and performs comparable pattern matching between descrambled received message bits and one or more additional predetermined sequences, identifying scrambled ordered set messages.
Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.
H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
59.
Pipelined forward error correction for vector signaling code channel
Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
60.
Low latency combined clock data recovery logic network and charge pump circuit
Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current, and providing the output current to a local oscillator controller, the output current sourcing and sinking current to a capacitor through a resistive element to adjust an input voltage of a proportional control circuit relative to a voltage on the capacitor connected to the resistive element.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
62.
Continuous time linear equalization and bandwidth adaptation using peak detector
Methods and systems are described for asynchronously measuring an equalized information signal to obtain amplitude information, modifying frequency dependent parameters of a continuous-time linear equalization (CTLE) component of the signal path, determining a correlation between CTLE parameters and signal amplitude, and adjusting, responsive to the correlation, a continuous-time linear equalization (CTLE) code of a CTLE to adjust equalization of the equalized information signal.
Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/23 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
64.
Variable gain amplifier and sampler offset calibration without clock recovery
Methods and systems are described for generating a time-varying information signal at an output of a variable gain amplifier (VGA), sampling, using a sampler having a vertical decision threshold associated with a target signal amplitude, the time-varying information signal asynchronously to generate a sequence of decisions from varying sampling instants in sequential signaling intervals, the sequence of decisions comprising (i) positive decisions indicating the time-varying information signal is above the target signal amplitude and (ii) negative decisions indicating the time-varying information signal is below the target signal amplitude, accumulating a ratio of positive decisions to negative decisions, and generating a gain feedback control signal to adjust a gain setting of the VGA responsive to a mismatch of the accumulated ratio with respect to a target ratio.
Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H03K 5/26 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/00 - Automatic control of frequency or phaseSynchronisation
H03L 7/10 - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
66.
Error-tolerant forward error correction ordered set message decoder
Methods are described for identifying and acting upon predetermined message patterns during reception of a data stream structured as USB message frames. A first embodiment performs pattern matching between received message bits and one or more predetermined sequences, identifying unscrambled ordered set messages. A second embodiment applies a descrambling operation and performs comparable pattern matching between descrambled received message bits and one or more additional predetermined sequences, identifying scrambled ordered set messages.
Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
68.
Clock data recovery with decision feedback equalization
Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
69.
Data-driven phase detector element for phase locked loops
Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 25/493 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels by transition coding, i.e. the time-position or direction of a transition being encoded before transmission
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H04L 7/00 - Arrangements for synchronising receiver with transmitter
70.
Continuous time linear equalization and bandwidth adaptation using asynchronous sampling
Methods and systems are described for generating a time-varying information signal at an output of a continuous time linear equalizer (CTLE), asynchronously sampling a data signal according to a sampling clock having a frequency less than a data rate of the data signal; generating corresponding pattern-verified samples for at least two data patterns, each of the at least two data patterns having a respective frequency content; determining corresponding frequency-specific voltage measurements associated with each of the at least two data patterns based on the corresponding pattern-verified samples of the at least two data patterns; and adjusting an equalization of the data signal based on a comparison of the corresponding frequency-specific voltage measurements.
Methods and systems are described for receiving an input data voltage signal at a first data decision circuit of set of pipelined data decision circuits, receiving an aggregate decision feedback equalization (DFE) correction current signal from a first analog current summation bus, the aggregate DFE correction current signal comprising a plurality of DFE tap-weighted currents from respective other data decision circuits of the set of pipelined data decision circuits, determining a data output decision value based on the received input data voltage signal and the received aggregate DFE correction current signal, and generating at least one outbound DFE tap-weighted current on at least one other analog current summation bus connected to at least one other data decision circuit of the set of pipelined data decision circuits.
Dual mode T-switches driven by at least one low-impedance switch driver, to connect at least four wires of a multiwire bus to a multi-input comparator (MIC) of a plurality of MICs in a first mode of Orthogonal Vector Signaling operation, and in a full-duplex mode of operation, using the low-impedance switch driver to disable a corresponding subset of T-switches to selectively disconnect a pair of wires of the multiwire bus from the MIC while using low-impedance enable signal paths in the low-impedance switch drivers to shunt capacitively-coupled interfering outbound signals received at the MIC from the selectively disconnected pair of wires in the full-duplex mode of operation.
Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H04L 27/148 - Demodulator circuitsReceiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using filters, including PLL-type filters
Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 25/493 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels by transition coding, i.e. the time-position or direction of a transition being encoded before transmission
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H04L 7/00 - Arrangements for synchronising receiver with transmitter
76.
Dynamic integration time adjustment of a clocked data sampler using a static analog calibration circuit
Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.
Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.
H01Q 13/24 - Non-resonant leaky-waveguide or transmission-line antennas Equivalent structures causing radiation along the transmission path of a guided wave constituted by a dielectric or ferromagnetic rod or pipe
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H04L 25/08 - Modifications for reducing interferenceModifications for reducing effects due to line faults
H04B 3/14 - Control of transmissionEqualising characterised by the equalising network used
An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
79.
Multiple adjacent slicewise layout of voltage-controlled oscillator
Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.
H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
80.
Measurement and correction of multiphase clock duty cycle and skew
Methods and systems are described for generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal.
H03L 7/00 - Automatic control of frequency or phaseSynchronisation
H03K 5/156 - Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
81.
Dynamic voltage scaling in hierarchical multi-tier regulator supply
Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.
The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.
Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.
Methods and systems are described for generating a time-varying information signal at an output of a variable gain amplifier (VGA), sampling, using a sampler having a vertical decision threshold associated with a target signal amplitude, the time-varying information signal asynchronously to generate a sequence of decisions from varying sampling instants in sequential signaling intervals, the sequence of decisions comprising (i) positive decisions indicating the time-varying information signal is above the target signal amplitude and (ii) negative decisions indicating the time-varying information signal is below the target signal amplitude, accumulating a ratio of positive decisions to negative decisions, and generating a gain feedback control signal to adjust a gain setting of the VGA responsive to a mismatch of the accumulated ratio with respect to a target ratio.
Methods and systems are described for obtaining a plurality of BER-specific correction values by comparing a first set of BER values obtained by sampling, at a sampling instant near the center of a signaling interval, a non-DFE corrected received signal with a second set of BER values obtained by sampling a DFE-corrected received signal at the sampling instant. A set of eye-scope BER measurements are obtained, each eye-scope BER measurement having a sampling offset relative to the sampling instant, a voltage offset value representing a voltage offset applied to alter a decision threshold, and an eye-scope BER value. A set of DFE-adjusted eye-scope BER measurements are generated by using BER-specific correction values to adjust the voltage offset values of the eye-scope BER measurements.
Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
87.
Method for measuring and correcting multiwire skew
Methods and systems are described for sequentially obtaining a plurality of data streams, the plurality of data streams comprising a data stream in a current condition, a data stream in a skewed-forward condition, and a data stream in a skewed-backward condition, calculating, for each data stream in the plurality of data streams, a corresponding set of cost-function values by obtaining a corresponding set of eye measurements, the eye measurements obtained by adjusting a sampling threshold of a sampler generating a plurality of samples of the data stream, the plurality of samples comprising edge samples and data samples, wherein the data stream is sampled at a rate equal to twice a rate of the data stream and calculating the corresponding set of cost-function values based on the corresponding set of eye measurements, and generating a skew control signal based on a comparison of the sets of calculated cost-function values.
Methods and systems are described for sampling a data signal using a data sampler operating in a data signal processing path having a decision threshold associated with a decision feedback equalization (DFE) correction factor, measuring an eye opening of the data signal by adjusting a decision threshold of a spare sampler operating outside of the data signal processing path to determine a center-of-eye value for the decision threshold of the spare sampler, initializing the decision threshold of the spare sampler based on the center-of-eye value and the DFE correction factor, generating respective sets of phase-error signals for the spare sampler and the data sampler responsive to a detection of a predetermined data pattern, and updating the decision threshold of the data sampler based on an accumulation of differences in phase-error signals of the respective sets of phase-error signals.
Pre-charging two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets of nodes comprising a set of data signal nodes and a set of DFE correction nodes, in response to a sampling clock, generating a differential data voltage and an aggregate differential DFE correction signal, and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock.
A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
91.
Clock data recovery with decision feedback equalization
Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
92.
Passive multi-input comparator for orthogonal codes on a multi-wire bus
Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.
Methods and systems are described for obtaining a plurality of BER-specific correction values by comparing a first set of BER values obtained by sampling, at a sampling instant near the center of a signaling interval, a non-DFE corrected received signal with a second set of BER values obtained by sampling a DFE-corrected received signal at the sampling instant. A set of eye-scope BER measurements are obtained, each eye-scope BER measurement having a sampling offset relative to the sampling instant, a voltage offset value representing a voltage offset applied to alter a decision threshold, and an eye-scope BER value. A set of DFE-adjusted eye-scope BER measurements are generated by using BER-specific correction values to adjust the voltage offset values of the eye-scope BER measurements.
Methods and systems are described for obtaining a plurality of information bits, and responsively partitioning the obtained plurality of information bits into a plurality of subsets of information bits, generating a plurality of streams of forward error correction (FEC)-encoded bits using a plurality of FEC encoders receiving respective subsets of the plurality of subsets of information bits, providing the plurality of streams of FEC-encoded bits to a plurality of sub-channel encoders, each sub-channel encoder receiving a respective stream of FEC-encoded bits from a different FEC encoder of the plurality of FEC encoders for generating a set of codewords of a vector signaling code, and wherein sequential streams of FEC-encoded bits from a given FEC encoder are provided to different sub-channel encoders for each successively generated set of codewords, and transmitting the successively generated sets of codewords of the vector signaling code over a multi-wire bus.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H03M 13/05 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
H04L 25/08 - Modifications for reducing interferenceModifications for reducing effects due to line faults
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
Methods and systems are described for sampling a data signal using a data sampler operating in a data signal processing path having a decision threshold associated with a decision feedback equalization (DFE) correction factor, measuring an eye opening of the data signal by adjusting a decision threshold of a spare sampler operating outside of the data signal processing path to determine a center-of-eye value for the decision threshold of the spare sampler, initializing the decision threshold of the spare sampler based on the center-of-eye value and the DFE correction factor, generating respective sets of phase-error signals for the spare sampler and the data sampler responsive to a detection of a predetermined data pattern, and updating the decision threshold of the data sampler based on an accumulation of differences in phase-error signals of the respective sets of phase-error signals.
Methods and systems are described for selectively providing a signal path from a respective wire of a multi-wire bus to at least one corresponding data signal output node of at least one set of differential data signal output nodes using a respective switching element in a respective set of signal path circuits connected in parallel, and generating a set of discharge currents, each discharge current of the set of discharge currents generated through a respective resistive element in the respective set of signal path circuits to discharge a portion of a voltage pulse on the respective wire of the multi-wire bus to one or more metallic planes via a respective localized ESD protection circuit, the respective resistive element and the respective localized ESD protection circuit connected between the respective wire and the respective switching element.
Methods and systems are described for generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal.
H03K 5/12 - Shaping pulses by steepening leading or trailing edges
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
98.
VARIABLE GAIN AMPLIFIER AND SAMPLER OFFSET CALIBRATION WITHOUT CLOCK RECOVERY
Methods and systems are described for generating a time-varying information signal at an output of a variable gain amplifier (VGA), sampling, using a sampler having a vertical decision threshold associated with a target signal amplitude, the time-varying information signal asynchronously to generate a sequence of decisions from varying sampling instants in sequential signaling intervals, the sequence of decisions comprising (i) positive decisions indicating the time-varying information signal is above the target signal amplitude and (ii) negative decisions indicating the time-varying information signal is below the target signal amplitude, accumulating a ratio of positive decisions to negative decisions, and generating a gain feedback control signal to adjust a gain setting of the VGA responsive to a mismatch of the accumulated ratio with respect to a target ratio.
Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.
Methods and systems are described for selectively providing a signal path from a respective wire of a multi-wire bus to at least one corresponding data signal output node of at least one set of differential data signal output nodes using a respective switching element in a respective set of signal path circuits connected in parallel, and generating a set of discharge currents, each discharge current of the set of discharge currents generated through a respective resistive element in the respective set of signal path circuits to discharge a portion of a voltage pulse on the respective wire of the multi-wire bus to one or more metallic planes via a respective localized ESD protection circuit, the respective resistive element and the respective localized ESD protection circuit connected between the respective wire and the respective switching element.
patents
