A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes: a substrate; a first magnetic tunnel junction structure disposed over a portion of the substrate and including a first free layer; a first hard mask layer disposed over the first free layer; a second magnetic tunnel junction structure disposed over another portion of the substrate and including a second free layer having a thickness smaller than a thickness of the first free layer; a second hard mask layer disposed over the second free layer; and a doped layer interposed between the second free layer and the second hard mask layer and having conductivity.
Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a first structure including a first chip area and a first scribe lane area, a second structure provided on the first structure, a first alignment key disposed in the first scribe lane area, at least one first bonding pad provided between the first alignment key and the first chip area, the first bonding pad bordering an upper surface of the first structure, and a second bonding pad bordering a lower surface of the second structure to contact the at least one first bonding pad.
An image sensing device includes a substrate extending in a first direction and a second direction and including a first surface and a second surface; a plurality of unit pixel regions supported by the substrate to generate signal carriers through conversion of incident light; a plurality of circuit structures arranged to be spaced apart from each other in the first direction to generate a current in the substrate and capture the signal carriers carried by the current; a first isolation structure disposed between adjacent unit pixel regions in the substrate and extending vertically in a depth direction of the substrate while extending in the second direction; and a plurality of second isolation structures located on two opposite sides of the plurality of circuit structures in the second direction within the substrate, and arranged to extend obliquely in a depth direction in the substrate while extending in the first direction.
A method of manufacturing a semiconductor device may include forming a polishing stop layer on a substrate, forming a stack on the polishing stop layer, forming channel structures extending through the stack and the polishing stop layer and having different heights, polishing the substrate and the channel structures to expose the polishing stop layer, and removing the polishing stop layer.
A memory device includes a plurality of memory planes, each including a plurality of memory banks; one or more plane groups, each comprising at least two memory planes sharing at least one peripheral circuit; a plurality of compressing circuits, each connected to a corresponding memory bank and outputting compressed data by compressing data read from the corresponding memory bank; a plurality of merge circuits, each receiving compressed data and at least one output control signal corresponding to a merge group of a plurality of merge groups, each merge circuit outputting, in response to at least one output control signal, merged data obtained by merging compressed data corresponding to memory banks grouped in the merge group; and an output buffer circuit latching and outputting the merged data in response to at least one output control signal. The merge group comprises at least two memory banks in a same plane group.
A pellicle structure may include a membrane border and a pellicle membrane. The membrane border defines an open region. The membrane is in contact with the membrane border and extending over the open region. Thus, the membrane is capable of maintaining a thin film having a uniform thickness to prevent pattern errors.
Disclosed is an image sensor and an image processing system including the same, and the image sensor includes a first pixel pair arranged in a first row, and configured to generate, during a first single readout time, first and second pixel signals according to a first order, a second pixel pair arranged in the first row, and configured to generate, during the first single readout time, third and fourth pixel signals according to a second order which is different from the first order, and a row controller configured to control, during the first single readout time, the first pixel pair according to the first order and the second pixel pair according to the second order.
A method for fabricating a semiconductor device includes forming a cell mold including a dummy channel pattern and a plurality of mold layers over a lower structure; forming a horizontal conductive line that intersects with the dummy channel pattern; forming a dummy channel layer by trimming the dummy channel pattern; forming a data storage element that is coupled to a first side of the dummy channel layer; replacing the dummy channel layer with a channel layer; and forming a vertical conductive line that is coupled to a second side of the channel layer.
A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate; a lower portion of a first conductive pattern disposed over the substrate and extending in a second direction; a stacked structure disposed over the lower portion of the first conductive pattern and having a pillar shape, the stacked structure including an upper portion of the first conductive pattern, an oxide semiconductor channel, and a second conductive pattern; and a word line extending in a first direction intersecting the second direction and facing at least a portion of a sidewall of the oxide semiconductor channel with a gate insulating layer therebetween, wherein the first conductive pattern includes a first conductive metal oxide, and the lower portion of the first conductive pattern corresponds to a bit line, and the upper portion of the first conductive pattern corresponds to a drain electrode.
H10B 12/00 - Dynamic random access memory [DRAM] devices
10.
BUFFER CHIP, SEMICONDUCTOR PACKAGE INCLUDING BUFFER CHIP AND MEMORY CHIP, OPERATION METHOD OF BUFFER CHIP, AND OPERATION METHOD OF SEMICONDUCTOR PACKAGE
An operation method of a buffer chip may include receiving first control signals for setting a first memory chip; buffering the first control signals and transmitting the buffered signals to the first memory chip; storing a setting value of the first memory chip in response to the first control signals; receiving second control signals for setting a second memory chip; buffering the second control signals and transmitting the buffered second control signals to the second memory chip; storing a setting value of the second memory chip in response to the second control signals; receiving third control signals for applying the setting value of the first memory chip; buffering the third control signals and transmitting the buffered third control signals to the first memory chip; and applying the stored setting value of the first memory chip as a setting value of a buffer chip in response to the third control signals.
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
11.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device may include a first electrode, a second electrode, a variable resistance layer positioned between the first electrode and the second electrode and maintaining a phase before and after a program operation, a non-conductive sealing layer positioned between the first electrode and the variable resistance layer, and a nanostructure positioned inside the non-conductive sealing layer and spaced apart from the variable resistance layer.
Provided herein are a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a transistor, a cell array structure, a molded insulating structure including a first area disposed between the transistor and the cell array structure and overlapping with the transistor and a second area extending sideways from the first area, a pass gate disposed in the second area of the molded insulating structure, an active pillar penetrating the pass gate, and a pass gate insulating layer disposed between the active pillar and the pass gate.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
G11C 16/08 - Address circuitsDecodersWord-line control circuits
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
13.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a common conductive line extending in a first direction; a memory cell array including a plurality of horizontal layers stacked in the first direction while sharing the common conductive line; and a selector structure operatively coupled to the common conductive line, wherein the selector structure includes, a plurality of select transistors stacked in the first direction; and a selector commonly coupled to the select transistors.
A semiconductor device may include a gate structure including insulating layers and conductive layers alternately stacked, a channel layer passing through the gate structure, an insulating core disposed in the channel layer, and a capping layer including a capping pattern disposed in the channel layer and a capping liner disposed between the capping pattern and the insulating core and extending between the channel layer and the capping pattern, wherein the capping liner and the capping pattern may include impurities having different concentrations.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Embodiments of the present invention provide a semiconductor device capable of improving current leakage property and a method for fabricating the same. According to an embodiment of the present invention, a capacitor comprises: a lower electrode; a dielectric layer over the lower electrode; and an upper electrode over the dielectric layer, the upper electrode including a conductive carbon-containing layer, wherein a carbon content in the conductive carbon-containing layer is more than 5 at % and equal to or less than 10 at %.
A normalizer for performing normalization on floating-point data includes a search circuit configured to receive selected mantissa data and to output reference exponent data and shift data, the selected mantissa data being either mantissa data of the floating-point data or 2's complement data of the mantissa data, an exponent adder configured to output normalized exponent data by adding exponent data of the floating-point data and the reference exponent data, and a unidirectional mantissa shifter configured to output normalized mantissa data by performing a unidirectional shift on the selected mantissa data based on a value of the shift data.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.
A data storage device includes: a memory device including a plurality of first storage areas and a plurality of second storage areas, each of which stores a primary index corresponding to a primary key provided from a host and a primary value corresponding to the primary index, and a memory controller for controlling the memory device. The memory controller is configured to generate, according to a request from the host, the primary index including the primary key and address information of a target second storage area in which a primary value corresponding to the primary key is stored, among the plurality of second storage areas, generate, according to an additional request from the host, a secondary key corresponding to a secondary value including a portion of the primary value, and generate a secondary index including the secondary key and the address information of the target second storage area.
An external connection pad apparatus includes a first pad and a second pad. The first pad has a first surface area. The second pad has a second surface area larger than the first surface area.
Provided herein may be a memory controller. The memory controller may include a shared memory configured to store data, a hardware group configured to generate entry data including result data of an operation corresponding to a command, and output an interrupt signal generated in response to storage of the entry data, and a processor group configured to receive the entry data from the shared memory, wherein the processor group includes an interface converter configured to manage first index information of the entry data in response to the interrupt signal, and generate a first address for the entry data based on the first index information, and a data transmitter configured to receive, based on a first address, the entry data through a first interface using a data input/output scheme, and transfer the received entry data to a processor through a second interface using a fixed data input/output scheme.
A semiconductor device may include: a first gate structure; a second gate structure disposed over the first gate structure; and a channel structure including a first portion extending through the first gate structure, the first portion having a tapered cross section, a second portion having a tapered cross section, and a third portion connecting the first portion with the second portion, wherein the third portion has a vertical profile, and wherein the second portion and the third portion extends through the second gate structure.
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
H10B 41/23 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
22.
PELLICLE MEMBRANE, PELLICLE ASSEMBLY INCLUDING THE SAME AND METHOD OF MANUFACTURING THE PELLICLE ASSEMBLY
A pellicle assembly may include a pellicle membrane and a pellicle border. The pellicle membrane may include at least one recess and at least one opening. The at least one recess may extend from an upper surface or a lower surface of the pellicle membrane. The at least one opening may penetrate from the upper surface to the lower surface of the pellicle membrane. The pellicle border may support the pellicle membrane.
A memory controller includes a scrub control circuit configured to generate a scrub command for instructing a scrub operation; and an address generation circuit configured to generate a scrub address having an address sequence in which a first column bit group of a column address, a row address, and a second column bit group of the column address are sequentially allocated from a least significant bit (LSB) to a most significant bit (MSB), and change a value of the scrub address according to the scrub command.
A Peripheral Component Interconnect express (PCIe) device includes a Direct Memory Access (DMA) device including a plurality of functions; and a PCIe interface device for performing communication between a host and the DMA device. The PCIe interface device includes a reset operation controller for, when a plurality of reset signals are received from the host, grouping operations, which are the same as one another among reset operations respectively corresponding to the plurality of reset signals, determining a processing order of the reset operations, and performing the reset operations according to the processing order.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
25.
IMAGE SIGNAL PROCESSOR AND IMAGE SIGNAL PROCESSING METHOD
An image signal processor capable of processing image signals and an image signal processing method for the same are disclosed. The image signal processor includes a remosaic processor configured to by perform remosaic processing on an input image to generate a converted image, a noise-amount estimator configured to estimate an amount of noise of the converted image based on preset noise-amount parameters and the input image, a noise-reduction-degree determiner configured to determine a degree of noise reduction and generate noise-reduction-degree information, and a noise suppression processor configured to generate an output image in which the degree of noise reduction is controlled based on the noise-reduction-degree information.
An image sensing device includes a semiconductor substrate; unit pixels supported by the semiconductor substrate to detect light incident to the unit pixels and to convert detected light into pixel signal, and an inter-pixel isolation structure disposed between adjacent unit pixels to physically isolate the adjacent unit pixel from each other. Each unit pixel includes photoelectric conversion elements, an inner-pixel isolation structure disposed between adjacent photoelectric conversion elements within the unit pixel and at least one overflow path configured to interconnect the photoelectric conversion elements within the unit pixel, and wherein each unit pixel is shaped in a triangular shape when viewed in a plane.
An image sensing device includes a semiconductor substrate, a first pixel region, and a second gate. The semiconductor substrate includes a first pixel region configured to include at least one first photoelectric conversion region and at least one first floating diffusion region, a second pixel region located adjacent to the first pixel region in a first direction and configured to include at least one second photoelectric conversion region and at least one second floating diffusion region, and a first inter-pixel isolation structure disposed between the first pixel region and the second pixel region. The first gate disposed over the semiconductor substrate extends to overlap the first pixel region, the first inter-pixel isolation structure, and the second pixel region. The second gate disposed at one side of the first gate on the semiconductor substrate extends to overlap the first pixel region, the first inter-pixel isolation structure, and the second pixel region.
Disclosed is an image processor and an image processing system including the same. The image processor includes an analyzer configured to generate quantified characteristic values of noise reflected in a captured image based on image values corresponding to the captured image, and a discriminator configured to determine whether the noise has occurred in the captured image based on the characteristic values.
Disclosed is an interface circuit and a semiconductor device including the same. The interface circuit may include a data pad, a first driving circuit connected between the data pad and a first supply node, and configured to adjust a first resistance value applied between the data pad and the first supply node according to termination modes and selectively drive the data pad with a first supply voltage, and a first tuning circuit connected between the first supply node and a first voltage supply terminal, and configured to tune the first resistance value according to the termination modes.
An image sensing device includes a counter configured to generate first count data by counting pulses corresponding to photocharges, a shift register configured to store second count data corresponding to upper digits of the first count data, and an adder configured to sum the second count data and an overflow value indicating whether the first count data has overflowed.
A method for fabricating a semiconductor device includes: forming an isolation layer that defines a plurality of active regions over a substrate; forming a bit line stack over the substrate; forming a main hard mask layer over the bit line stack; forming a plurality of first sacrificial mask layers over the main hard mask layer; forming a plurality of second sacrificial mask layers overlapping with both side ends of the first sacrificial mask layers over the first sacrificial mask layers; forming a main hard mask layer pattern by using the first and second sacrificial mask layers as barriers and etching the main hard mask layer; and forming a bit line structure by using the main hard mask layer pattern as a barrier and etching the bit line stack.
A memory device includes an open memory block and control circuitry. The open memory block includes at least one first page having an erased state. The control circuitry is configured to perform a read operation for a page included in the open memory block, and apply a weight determined based on a ratio of the at least one first page in the open memory block to calculate a read count subject to the read operation.
INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY (Republic of Korea)
Inventor
Kang, In Ku
Min, Kyung Hoon
Hong, Sung In
Song, Yun Heub
Sim, Jae Min
Song, Ji Ho
Abstract
A method of programming a three-dimensional semiconductor memory device includes applying a first word line programming voltage to a selected word line among the word lines, floating unselected word lines among the word lines, and applying a back-gate pass voltage to the back-gate electrode; applying a first word line verification voltage to the selected word line, applying a word line pass voltage to the unselected word lines, and applying a first back-gate verification voltage to the back-gate electrode; applying a second word line programming voltage to the selected word line, floating the unselected word lines, and applying the back-gate pass voltage to the back-gate electrode; and applying a second word line verification voltage to the selected word line, applying the word line pass voltage to the unselected word lines, and applying a second back-gate verification voltage to the back-gate electrode.
A memory controller includes a command/address generation module; and a row-hammer tracking module configured to track a row-hammer address based on an active command and an address for a target bank and a target row indicated by the active command, the active command and the address being received from the command/address generation module, wherein the row-hammer tracking module includes: a plurality of storage devices each including fields corresponding to banks, each of the fields storing candidate addresses and access counting values for the candidate addresses; and at least one search controller configured to sequentially search, according to a clock, fields of the plurality of storage devices corresponding to the target bank when the active command is input, and search, during one clock, fields of the plurality of storage devices corresponding to different banks based on active commands indicating the different banks.
A memory device including: a first stack structure including conductive layers stacked along a first direction, the first stack structure having a stepped structure defined by end portions of the conductive layers; contact plugs respectively connected to the conductive layers, the contact plugs extending along the first direction, the contact plugs extending to the inside of the first stack structure; and dummy layers located between the contact plugs.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
36.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating a semiconductor device includes forming a stack body including a plurality of recess target layers over a lower structure; forming sacrificial isolation openings in the stack body; forming sacrificial isolation layers in the sacrificial isolation openings; forming sacrificial vertical openings having bottom surfaces disposed at a lower level than bottom surfaces of the sacrificial isolation openings in the stack body between the sacrificial isolation layers; forming preliminary horizontal layers by recessing the recess target layers through the sacrificial vertical openings; forming sacrificial pillar structures that fill the sacrificial vertical openings; forming cell isolation openings by removing the sacrificial isolation layers; forming horizontal layers by trimming the preliminary horizontal layers through the cell isolation openings; and forming cell isolation layers that fill the cell isolation openings.
A memory device includes: a plurality of memory cells; a peripheral circuit for performing a program operation of storing data in the plurality of memory cells; and a program operation control circuit for, in the program operation, controlling the peripheral circuit to perform a foggy program operation of increasing a threshold voltage of the plurality of memory cells to a threshold voltage corresponding to any one state among an erase state and first to sixth foggy program states, and perform a fine program operation of increasing the threshold voltage of the plurality of memory cells to any one state among the erase state and first to fifteenth fine program states.
A semiconductor device includes a semiconductor substrate formed to include a first active region and a second active region, first and second dielectric layer disposed over the first and second active regions, first and second gate electrode disposed over the first and second dielectric layers, respectively; and wherein the first and second active region have different impurity doping types from each other, and fluorine concentration of the first dielectric layer is higher than fluorine concentration of the second dielectric layer.
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Embodiments of the present disclosure relate to a monitoring circuit and a semiconductor device, and particularly, to a monitoring circuit including an oscillation circuit configured to generate an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level and a counter configured to count the number of rises or the number of falls of the oscillation signal, and a semiconductor device including the monitoring circuit.
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
H01L 21/66 - Testing or measuring during manufacture or treatment
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
40.
SEMICONDUCTOR DEVICE CONFIGURED TO STORE PARITY DATA AND METHOD OF OPERATING THE SEMICONDUCTOR DEVICE
A semiconductor device includes a memory cell array and a plurality of read and write circuits. The memory cell array includes a plurality of planes. Any one of the read and write circuits generates parity data based on data sequentially received from a controller through a channel.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
An image signal processor includes a bit extension processor configured to generate extension data by expanding, by a first number of bits, a number of bits of input data including a Bayer image and a white image, and an output circuit configured to adjust, upon receiving the extension data, the first number of bits to a second number of bits, to generate output data.
G06T 3/4038 - Image mosaicing, e.g. composing plane images from plane sub-images
G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries
42.
READOUT CIRCUIT AND IMAGE SENSING DEVICE INCLUDING THE SAME
A readout circuit and an image sensing device including the same are disclosed. The readout circuit includes a ramp signal generator configured to generate a ramp signal having first noise, a sampling circuit configured to generate a pixel sampling signal having second noise by sampling a pixel signal, and a conversion circuit configured to compare the ramp signal with the pixel sampling signal and offset the first noise and the second noise based on the comparison result.
There is provided a semiconductor memory device. The semiconductor memory device includes a first peripheral circuit structure, a cell array structure, a mold insulating structure disposed between the first peripheral circuit structure and the cell array structure, and a second peripheral circuit structure disposed in the mold insulating structure and including a pass transistor.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
G11C 16/08 - Address circuitsDecodersWord-line control circuits
44.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first stack structure, a plurality of first slits passing through the first stack structure in a vertical direction and extending in a first horizontal direction orthogonal to the vertical direction, a first source line layer contacting an a top portion of the first stack structure, a second source line layer directly contacting the first source line layer, a second stack structure contacting the second source line layer and overlapping with the first stack structure in the vertical direction, and a plurality of second slits passing through the second stack structure in the vertical direction and extending in a second horizontal direction orthogonal to the vertical direction.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
45.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device may include a stack including a chip region and a guard region surrounding the chip region, contact structures positioned in the chip region, and a chip guard structure positioned in the guard region and including first protrusions protruding by a first width and second protrusions protruding by a second width greater than the first width.
A semiconductor device may include a bit line extending in a third direction, a plurality of active layers extending in a first direction and contacting the bit line, a plurality of word lines extending in a second direction and each disposed at an top surface or bottom surface of each of the plurality of active layers, a plurality of capacitors contacting the plurality of active layers, and a contact formed in at least one active layer disposed at the uppermost part of the bit line, among the plurality of active layers. The bit line and the contact may be electrically connected or separated by using, as a control line, a word line disposed in the top surface or bottom surface of the at least one active layer, among the plurality of word lines.
A memory device includes a first peripheral circuit having first page buffers is functionally divided into a cell region and a connection region. A first memory cell array positioned on the first peripheral circuit includes first bit lines that are electrically connected to the first page buffers. A second memory cell array positioned on the first memory cell array includes second bit lines, which are electrically connected to the first bit lines, respectively. The first peripheral circuit is able to make use of both memory arrays using connections between the two memory arrays.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
A string filter device may include an input buffer group and a string comparator group. The input buffer group may store a plurality of string group data segments. Each of the plurality of string group data segments has a first size and includes a plurality of string data having a variable size. The string comparator group may extract a plurality of different sub-string group data segments having a second size among the plurality of string group data segments, and compare, in parallel, each of the plurality of sub-string group data segments with query data, using a plurality of string comparators.
There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first gate stack structure and a second gate stack structure, disposed on a substrate; and a slit disposed between the first gate stack structure and the second gate stack structure to electrically isolate the first gate stack structure and the second gate stack structure from each other.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
A storage device may input a program command requesting to program target data into the memory, input the target data into a memory, and input the program confirmation command into the memory after inputting the program command and the target data into the memory. In this case, the program confirmation command may include information about a cell type of memory cells to be programmed with target data among a plurality of memory cells.
An operation method of a memory may include receiving an active command and an active address; determining whether a row corresponding to the active address and a row corresponding to a target row address are able to be substantially simultaneously activated; activating the row corresponding to the active address; and activating the row corresponding to the target row address in response to determining that the row corresponding to the active address and the row corresponding to the target row address are able to be substantially simultaneously activated.
A semiconductor device includes a memory cell array and a peripheral circuit. The memory cell array is coupled to a plurality of word lines and a plurality of bit lines. The peripheral circuit performs a deep-erase verification operation to determine whether a target memory cell has a threshold voltage that is lower than a first negative reference voltage by applying a second negative reference voltage that is lower than the first negative reference voltage to the target memory cell.
A fail data augmentation device may input a plurality of fail data units to a data augmentation model, obtain a plurality of augmented fail data units outputted from the data augmentation model, and delete one or more of the augmented fail data units. The plurality of fail data units and the plurality of augmented fail data units includes a first parameter indicating one of a plurality of banks included in a random access memory, a second parameter indicating one of a plurality of matrices included in the bank corresponding to the first parameter, and a third parameter indicating one of a plurality of hex units included in the matrix corresponding to the second parameter respectively.
A semiconductor device includes a bit line; a plurality of first semiconductor pillars disposed over the bit line; a plurality of first cell contact plugs disposed between the first semiconductor pillars; a plurality of second semiconductor pillars coupled to the first cell contact plugs; a plurality of second cell contact plugs disposed between the second semiconductor pillars and coupled to the first semiconductor pillars; and a plurality of capacitors respectively coupled to the second semiconductor pillars and the second cell contact plugs.
A semiconductor device may include a color filter array, an optical synapse array including a plurality of light passage paths transferring light incident through the color filter array with independently controlled transmissivities, and an optical-to-digital conversion circuit converting the transferred light through the plurality of light passage paths into digital data.
An electronic device includes a phase detection circuit configured to detect a difference between the phases of a reference clock and a feedback clock and a phase-locked signal generation circuit configured to generate a phase-locked signal based on the results of the detection of the difference between the phases of the reference clock and the feedback clock. The phase-locked signal generation circuit is configured to generate the phase-locked signal when the difference between the phases of the reference clock and the feedback clock is equal to or smaller than a first phase difference after the start of an initial operation and configured to stop the generation of the phase-locked signal when the difference between the phases of the reference clock and the feedback clock is equal to or greater than a second phase difference, which is greater than the first phase difference, after outputting the phase-locked signal.
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
57.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
A semiconductor device may include: a first conductive line extending in a first direction; a second conductive line extending in a second direction intersecting the first direction; a memory cell located between the first conductive line and the second conductive line in a third direction that is intersecting to the first and second directions; and a liner pattern located over a sidewall of the memory cell and including a first portion and a second portion, the first portion including halide impurities at a first concentration, the second portion including halide impurities at a second concentration that is lower than the first concentration.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
A method for fabricating a semiconductor device includes forming a stack body by sequentially forming a first layer, a second layer, a third layer, a fourth layer, and a fifth layer over a lower structure; forming an opening in the stack body; forming a capping layer that exposes an edge of the third layer by horizontally recessing the second layer and the fourth layer from the opening; forming a liner structure on the capping layer and an edge of the third layer; forming a sacrificial liner material over the liner structure; recessing the sacrificial liner material and the liner structure to expose an edge of the third layer; forming a third layer pattern by recessing an exposed edge of the third layer; and forming a data storage element that is coupled to the third layer pattern.
A semiconductor apparatus includes a data alignment circuit and a data pattern control circuit. The data alignment circuit aligns data input through each of a plurality of data input/output pads to generate a plurality of alignment data. The data pattern control circuit generates a plurality of preliminary write data by copying some bits of a first alignment data among the plurality of alignment data to a plurality of input paths coupled to data input/output pads other than a first data input/output pad among the plurality of data input/output pads, and changes a pattern of the plurality of preliminary write data according to remaining bits of the first alignment data to generate a plurality of write data.
An image sensing device comprising, a latch array including, a first latch group, a second latch group, a first latch controller generates a first latch control signal to control the first latch group, and a second latch controller generates a second latch control signal to control the second latch group, wherein a second edge of the second latch control signal occurs after a first edge of the first latch control signal.
A storage device may transmit a command set to a memory, set a plurality of flag bits based on transmission status of a plurality of commands included in the command set, respectively, and determine whether an error occurred in the process of transmitting the command set to the memory based on the plurality of flag bits. Each of the plurality of flag bits has a first value or a second value, and the command set includes a reset command, a command set start command, and a command set end command.
A semiconductor device may include: a first conductive line; a second conductive line located over the first conductive line, wherein the first conductive line and the second conductive line extend in different directions, intersecting each other; a variable resistance pattern located between the first conductive line and the second conductive line; a first electrode pattern located between the first conductive line and the variable resistance pattern; a first resistivity barrier pattern located between the first conductive line and the first electrode pattern; and a first diffusion barrier pattern located between the first resistivity barrier pattern and the first electrode pattern.
An embodiment of the disclosed technology provides a semiconductor package including: a substrate; a first chip and a second chip stacked on the substrate, each of the first chip and the second chip including a slice command/address reception pad, a slice command/address transmission pad, a slice data pad, an input buffer connected to the slice command/address reception pad, an output buffer connected to the slice command/address transmission pad and an input/output buffer connected to the slice data pad; a first connection member connecting the slice command/address transmission pad of the first chip to the slice command/address reception pad of the second chip; and a second connection member connecting the slice data pad of the first chip to the slice data pad of the second chip.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
An image sensing device includes a plurality of unit pixels. A first unit pixel of the plurality of unit pixels includes first to fourth sub-pixels arranged in a 2×2 matrix, an isolation structure including first and second portions, the first portion formed to surround the first unit pixel, the second portion disposed between adjacent sub-pixels among the first sub-pixel to the fourth sub-pixel, a first junction region formed to surround a first transistor region and disposed across the first sub-pixel and the second sub-pixel along a first side of the first unit pixel, and a second junction region formed to surround a second transistor region and disposed across the third sub-pixel and the fourth sub-pixel along a second side parallel to the first side. The length of the first side is equal to the length of a third side of the first unit pixel perpendicular to the first side.
A semiconductor memory device includes a plurality of memory blocks and a contact region. Each of the plurality of memory blocks includes a plurality of memory cells. The contact region is formed between the plurality of memory blocks. The semiconductor memory device uses a first memory block that is not adjacent to the contact region and a second memory block adjacent to the contact region among the plurality of memory blocks differently.
A semiconductor device may include: a first substrate structure including: a first substrate; a first word line, a first bit line, a second bit line, a second word line, a third word line, a third bit line, a fourth bit line, and a fourth word line that are sequentially arranged over the first substrate in a vertical direction; and first, second, third, and fourth memory cells, the first memory cell being disposed between the first word line and the first bit line, the second memory cell being disposed between the second word line and the second bit line, the third memory cell being disposed between the third word line and the third bit line, and the fourth memory cell being disposed between the fourth word line and the fourth bit line; and a second substrate structure disposed over the first substrate structure and including a second substrate.
A semiconductor package includes a substrate; a first chip and a second chip stacked on the substrate, each including a first pad, a cell region, a first level serializer-deserializer connected to the first pad, a second level serializer-deserializer connected between the first level serializer-deserializer and the cell region and a second pad that is connected to a node between the first level serializer-deserializer and the second level serializer-deserializer; and a first connection member connecting the second pad of the first chip to the second pad of the second chip.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
68.
STORAGE DEVICE, METHOD OF OPERATING THE SAME, AND COMPUTING SYSTEM INCLUDING THE STORAGE DEVICE
Storage devices, methods of operating storage devices, and computing systems including storage devices are disclosed. In an embodiment, a storage device may include a plurality of memory devices and a memory controller for controlling the plurality of memory devices to process a request of a host in accessing plurality of memory devices, wherein the memory controller is configured to allocate the plurality of memory devices to a plurality of functions, allocate a plurality of request slots allowed to process the request per unit time for each of the plurality of functions, determine idle request slots other than active request slots being used to process the request among the plurality of request slots allocated to each of the plurality of functions, and control an internal operation of the plurality of memory devices based on at least one target function including the idle request slots among the plurality of functions.
G06F 3/06 - Digital input from, or digital output to, record carriers
69.
THIN WAFER, METHOD OF MANUFACTURING THE THIN WAFER, STACK TYPE SEMICONDUCTOR DEVICE INCLUDING THE THIN WAFER AND METHOD OF MANUFACTURING THE STACK TYPE SEMICONDUCTOR DEVICE
In an embodiment, a wafer may include a substrate including a first surface and a second surface opposite to each other, a polishing stop layer formed in a selected portion of the substrate, the polishing stop layer including one or more insulation trenches each filled with an insulation material and having a depth corresponding to a thickness of the substrate, and a device layer supported by the substrate and structured to include a plurality of conductive patterns configured to electrically connect different circuit elements in the substrate.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
A semiconductor apparatus includes a frequency control circuit and an internal clock generation circuit. The frequency control circuit generates a frequency information signal based on a command address signal, and generates a frequency control signal by comparing the frequency information signal with a frequency setting signal. The internal clock generation circuit generates an internal clock signal from a system clock signal based on the frequency control signal.
G06F 1/12 - Synchronisation of different clock signals
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/191 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference
In an embodiment of the disclosed technology, a storage device starts in advance loading map data before outputting a signal corresponding to a read buffer command of a host device, encodes map data using a plurality of map load areas and a plurality of encoding areas, and provides encoded map data to the host device.
A method of manufacturing a semiconductor device including the array of conductive patterns is presented. The semiconductor device may include first conductive patterns disposed over an insulating layer over a semiconductor substrate, a second conductive pattern disposed to extend lengthwise to the side of the first conductive patterns, and third conductive patterns connected to the first conductive patterns and the second conductive pattern. The third conductive patterns may be storage nodes of a capacitor.
Memory devices and operating methods are disclosed. In an embodiment, a memory device may include a memory cell array including a plurality of memory cells, each of the plurality of memory cells configured to store a data value corresponding to read data to be read out through a plurality of conductive lines, and a read circuit connected to the plurality of conductive to generate the read data corresponding to the data value stored in a selected memory cell among the plurality of memory cells based on or according to whether there is a change in a cell current flowing through the selected memory cell during a single read period.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
74.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a lower structure; a plurality of horizontal conductive layers oriented in a direction parallel to a surface of the lower structure; a plurality of reservoir capacitors commonly coupled to first-side ends of the horizontal conductive layers, wherein each of the plurality of the reservoir capacitors is vertically stacked over the lower structure, and includes a cylindrical storage node; and a vertical conductive line commonly coupled to second-side ends opposite to first-side ends of the horizontal conductive layers, extending in a direction perpendicular or substantially perpendicular to the surface of the lower structure, and including a plurality of electrode portions, each electrode portion being symmetrical with the cylindrical storage node of a corresponding reservoir capacitor.
A memory device may include memory banks comprised of memory blocks; data compressing circuits connected to memory blocks and first merge circuits. A second merge circuit receives output from the first merge circuits. A delay detecting circuit generates delay control signals by comparing the output control signals. A compensating circuit calibrates the output control signals, based on the delay control signal. An output buffer circuit latches the second merged data and outputs the second merged data, based on at least a portion of the output control signals.
According to an embodiment of the present disclosure, a memory device includes a memory cell array including a plurality of planes; a charge pump configured to generate an operating voltage used for an operation on each of the plurality of planes according to a first clock signal having a first cycle; page buffers each configured to store pass data representing whether an operation of each of the plurality of planes has been completed; and an operation control circuit configured to, based on a number of the pass data received from the page buffers, control the charge pump to generate the operating voltage according to a second clock signal having a second cycle that is longer than the first cycle.
The present technology includes a memory device and a method of manufacturing the memory device. The memory device includes a memory block in which first and second connection regions and a cell region between the first and second connection regions are designated, a word line included in the memory block, a first drain selection line included in the memory block and positioned on the word line, a first drain contact contacting the first drain selection line of the first connection region, a second drain contact contacting the first drain selection line of the second connection region, and a first drain voltage supply line commonly contacting the first and second drain contacts.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/08 - Address circuitsDecodersWord-line control circuits
A semiconductor wafer analyzing device and semiconductor wafer analyzing system are disclosed that provide estimated analysis values of unit areas that are not measured in a target wafer. The device and system calculate estimated analysis values based on measured analysis values of unit areas in a basic wafer and measured analysis values of some unit areas in the target wafer.
A semiconductor device may include a first support including a first inclined surface, a first gate structure including first insulating layers and first conductive layers alternately stacked along the first inclined surface, a second support positioned over or on the first support and including a second inclined surface, a second gate structure including second insulating layers and second conductive layers alternately stacked along the second inclined surface, a first contact plug extending through the second gate structure and connected to at least one first conductive layer among the first conductive layers, and a second contact plug disposed over or on the second gate structure and connected to at least one second conductive layer among the second conductive layers.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
80.
IMAGE SIGNAL PROCESSOR AND IMAGE SIGNAL PROCESSING METHOD
An image signal processor capable of processing image signals and an image signal processing method for the same are disclosed. The image signal processor includes a first determiner configured to determine whether a target kernel including a target pixel corresponds to a corner pattern, a second determiner configured to determine a corner pattern group corresponding to the target kernel when the target kernel corresponds to the corner pattern, a third determiner configured to determine a target corner pattern corresponding to the target kernel from among a plurality of corner patterns of a corner pattern group corresponding to the target kernel, and a pixel interpolator configured to interpolate the target pixel using pixel data of a pixel corresponding to the target corner pattern.
A storage device may receive provisioning information, which is setting information for a provisioning operation that sets a plurality of zones on a memory, from a host, and set a first zone in which cold data requested to be written by the host is stored, among the plurality of zones based on write booster type included in the provisioning information. The storage device may set the first zone in a first memory area if the write booster type is a first type, and set the first zone in a second memory area if the write booster type is a second type.
A method for fabricating a semiconductor device includes: forming preliminary horizontal layers vertically stacked over a lower structure in a first direction and extending horizontally in a second direction crossing the first direction; forming trimming target layers that surround each of the preliminary horizontal layers; forming horizontal layers by trimming the preliminary horizontal layers in a third direction crossing the second direction; forming trimmed target layers by trimming the trimming target layers in the third direction; and replacing the trimmed target layers with conductive layers.
A storage device includes: a memory device; and a memory controller configured to receive, from an external device having an external memory, a write command for storing data in the memory device and address information of an area in the external memory that corresponds to the write command, and acquire write data from the external device based on the address information. The memory controller may be further configured to store the write data in the memory device in response to the write command. The memory controller may be further configured to acquire a portion of the write data from the external memory upon a failure of storage of the portion of the write data in the memory device, and provide a response to the write command to the external device after completing storing of the write data in the memory device.
An image sensing device includes a first sampling circuit suitable for sampling a reference ramp signal as a ramp signal; a switching circuit suitable for sequentially outputting first and second pixel signals to a common node based on first and second control signals; a second sampling circuit suitable for sampling the first and second pixel signals, which are sequentially outputted through the common node, as a measurement signal; a comparison circuit suitable for comparing the ramp signal with the measurement signal and generating a comparison signal corresponding to a comparison result; and a count circuit suitable for generating a count signal, which corresponds to a voltage level of the measurement signal, based on the comparison signal and a clock signal.
G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
H04N 13/207 - Image signal generators using stereoscopic image cameras using a single 2D image sensor
H04N 13/218 - Image signal generators using stereoscopic image cameras using a single 2D image sensor using spatial multiplexing
H04N 25/40 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
H04N 25/581 - Control of the dynamic range involving two or more exposures acquired simultaneously
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/705 - Pixels for depth measurement, e.g. RGBZ
An image sensing device includes a first sampling circuit suitable for sampling a reference ramp signal as a ramp signal; a switching circuit suitable for sequentially outputting first and second pixel signals to a common node based on first and second control signals; a second sampling circuit suitable for sampling the first and second pixel signals, which are sequentially outputted through the common node, as a measurement signal; a comparison circuit suitable for comparing the ramp signal with the measurement signal and generating a comparison signal corresponding to a comparison result; and a count circuit suitable for generating a count signal, which corresponds to a voltage level of the measurement signal, based on the comparison signal and a clock signal.
G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
H04N 13/207 - Image signal generators using stereoscopic image cameras using a single 2D image sensor
H04N 13/218 - Image signal generators using stereoscopic image cameras using a single 2D image sensor using spatial multiplexing
H04N 25/40 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
H04N 25/581 - Control of the dynamic range involving two or more exposures acquired simultaneously
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/705 - Pixels for depth measurement, e.g. RGBZ
A clock distribution network includes an input control circuit and a clock tree. The input control circuit is configured to generate a control input clock signal based on an input clock signal and a low power mode signal. The clock tree is configured to generate an output clock signal by buffering the control input clock signal. When the low power mode signal is enabled, the input control circuit is configured to change a DC level of the control input clock signal.
An image sensor includes a pixel array including pixels and a controller configured to control the pixels to produce a plurality of images. The image sensor also includes a defect detector configured to determine a target image based on an average green pixel value and a gain value related to a light exposure time among the images, and detect an adaptive static defective pixel, which is a defective pixel with a fixed location based on pixel values included in the target image.
A memory device includes: a plurality of memory planes each including a plurality of memory banks, the plurality of memory planes being grouped into memory planes; a plurality of compressing circuits respectively connected to the plurality of memory banks, the plurality of compressing circuits outputting compressed data by respectively compressing data read from the plurality of memory; a plurality of first merge circuits receiving the compressed data and output control signals corresponding to at least a portion of the memory banks, the plurality of first merge circuits outputting first merged data obtained by merging compressed data corresponding to memory banks grouped as a first merge group; a second merge circuit outputting second merged data obtained by merging first merged data generated from memory banks included in the same plane group; and an output buffer circuit outputting the second merged data, based on at least a portion of the output control signals.
A semiconductor device may include a gate structure including gate lines extending in a first direction; a first source pattern located on the gate structure; second source patterns located on the first source pattern and extending in a second direction intersecting the first direction; and channel structures extending through the gate structure and protruding into the first source pattern.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
90.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
A semiconductor device may include: a capacitor including a first source electrode, a second source electrode connected in common to a plurality of second access lines, each of the second access lines spaced apart from one another and located on different layers, and a first channel structure located on the first source electrode and penetrating through the plurality of second access lines; and at least one cell string located between a source line and a first access line, the at least one cell string including a second channel structure penetrating through the plurality of second access lines, the plurality of second access lines electrically separated from each other.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
91.
MEMORY CONFIGURED TO PERFORM A CHANNEL PRECHARGE OPERATION AND METHOD OF OPERATING THE MEMORY
A memory includes a cell string including a first select transistor, cell transistors, and a second select transistor and a row circuit configured to drive a first select line for controlling the first select transistor, a second select line for controlling the second select transistor and word lines for controlling the cell transistors. The row circuit differently performs a discharge operation of the first select line according to a position in the cell string of a program target cell transistor.
A clock doubler includes a first differential gate and a second differential gate. The first differential gate generates an output clock signal from a first clock signal, a first complementary clock signal, a second clock signal, and a second complementary clock signal and adjusts a duty cycle of the output clock signal based on a first bias control signal. The second differential gate generates a complementary output clock signal from the first clock signal, the first complementary clock signal, the second clock signal, and the second complementary clock signal and adjusts a duty cycle of the complementary output clock signal based on a second bias control signal.
A semiconductor device may include a plurality of active regions delimited on a substrate. A plurality of bit line structures crossing over the plurality of the active regions may be provided. A plurality of storage node contacts may be disposed between the plurality of the bit line structures. A plug isolation pattern may be disposed between the plurality of the storage node contacts. The plug isolation pattern may include an isolation insulating layer between the plurality of the storage node contacts; and a tapered dielectric layer between the isolation insulating layer and the plurality of the storage node contacts.
IUCF-HYU (Industry-University Cooperation Foundation Hanyang University) (Republic of Korea)
Inventor
Park, Young Wook
Shin, Wang-Chul
Kim, Sung Jun
Abstract
Disclosed are semiconductor devices, three-dimensional memory devices, and manufacturing methods thereof. A disclosed semiconductor device is a semiconductor device including a transistor, and the transistor may comprise a polycrystalline layer in which crystal grains are vertically oriented, a channel layer in contact with a side surface of the polycrystalline layer and having a structure in which crystal grains are vertically oriented, a source and a drain provided on a first portion and a second portion of the channel layer, respectively, and a gate for controlling an electrical characteristic of the channel layer. The polycrystalline layer may have a discontinuous structure between the source and the drain, the channel layer may have a continuous structure between the source and the drain, and grain boundaries of the channel layer may be arranged in a direction non-parallel to a channel length direction between the source and the drain.
A semiconductor memory device includes a semiconductor substrate including an upper surface extending in a horizontal direction, a source structure including a trench extending in the horizontal direction, the source structure disposed above the semiconductor substrate, a metal structure in the trench of the source structure and connecting the source structure to the semiconductor substrate, and memory cell strings disposed on both sides of the trench and connected to the source structure.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
96.
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
There are provided a semiconductor memory device and a manufacturing method of the semiconductor including: a plurality of source channels penetrating a source select line; a gate stack structure overlapping with the source select line; a connection pattern disposed between the source select line and the gate stack structure, the connection pattern being commonly connected to the plurality of source channels; and a plurality of vertical channels penetrating the gate stack structure, the plurality of vertical channels being commonly connected to the connection pattern.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
97.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE
The present disclosure relates to a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a word line, a first select line on the word line, a second select line on the first select line, a first upper contact extending to be in contact with a first surface of the first select line, and a second upper contact extending through the second select line to be in contact with a second surface of the first select line, wherein the first surface and the second surface of the first select line are on opposites sides of each other.
G11C 8/14 - Word line organisationWord line lay-out
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
98.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a substrate with a complementary metal oxide semiconductor (CMOS) circuit; a gate stacked body with interlayer insulating layers and conductive patterns that are alternately stacked on the substrate in a vertical direction; a plurality of channel structures passing through the gate stacked body, each with a first end that protrudes above the gate stacked body; and a plurality of conductive layers disposed over the gate stacked body. Each of the plurality of conductive layers is in contact with the first end of at least one of the plurality of channel structures.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
99.
SEMICONDUCTOR DEVICE FOR PERFORMING DATA ALIGNMENT OPERATION
A semiconductor device includes an alignment data generation circuit aligning first and second latch data generated from a first group of input data in synchronization with a first internal strobe signal, outputting the aligned first and second latch data as first alignment data, aligning a first and second latch data generated from a second group of the input data in synchronization with a second internal strobe signal, and outputting the aligned first and second latch data as second alignment data. The semiconductor device includes a write data generation circuit generating first and second write data from the first and second alignment data in synchronization with a latch clock after the start of a first operation mode and generating the first and second write data from the first alignment data in synchronization with the latch clock after the start of a second operation mode.
Korea Advanced Institute of Science and Technology (Republic of Korea)
Inventor
Kim, Joo Young
Kim, Dong Hyuk
Kim, Jae Young
Han, Wok Tak
Choi, Hae Rang
Kwon, Yong Kee
Won, Jong Soon
Abstract
A multilevel processing in memory (PIM) includes a processor in which an optimal operator installed at several layers of memory, an accelerator type circuit for processing an irregular operation, and a scheduler for processing an irregular operation have been installed. The multilevel processing in memory includes a memory module including at least one rank in which a computation operation and a data storage operation are performed in response to a control command from a memory controller. The memory module, the rank, a PIM command scheduler included in the rank, a bank group processing unit, and a bank group constitute a plurality of layers, respectively.
