The present technology provides an external data storage device comprising: a memory module including a plurality of semiconductor chips suitable for storing data received from an external device; a case including a plurality of surfaces surrounding the memory module; and a case stand suitable for supporting the case in an approximately vertical direction on a ground.
A stacked memory device includes a plurality of core dies stacked over a base die, and a power supply wire stacked over the plurality of core dies. Each of the plurality of core dies includes a core connection circuit including a core interconnection and a through via set, and an isolated connection circuit that is isolated from the core connection circuit and transmits a power supply voltage.
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
An operating method of a memory device includes receiving a first read command, providing a read voltage to a first memory cell based on the first read command, determining whether the first memory cell is in a set state, and providing a backward pulse to the first memory cell that has been determined to be in the set state.
A single memory package includes: a substrate; and a memory chip and a buffer chip that are integrated over the substrate, wherein the memory chip includes an interface modulator embedded therein, and the interface modulator is a serializing modulator including a multi-level amplitude modulator.
A storage device compares a first error bit number of a first word line included in a first weak word line group of a target memory block during a first period with a preset first reference value, compares the difference between a second error bit number of a second word line included in a strong word line group of the target memory block and the first reference value with a preset second reference value, sets a movement range of data of the target memory block on the basis of a result of comparing the difference with the second reference value, and moves the data to a preset space, whereby it is possible to efficiently perform a refresh operation on a memory block.
SK Hynix NAND Product Solutions Corp. (dba Solidigm) (USA)
SK hynix Inc. (République de Corée)
Inventeur(s)
Zhang, Ming
Wakchaure, Yogesh
Wang, Xiaolei
Chen, Lei
Kathawala, Gulzar
Park, Heejoung
Cho, Wanik
Abrégé
A method comprises applying a first reference drive voltage to a wordline of memory cells to generate a respective first resulting voltage level from each respective cell in the wordline, and storing in memory a first respective logic value indicated by the respective first resulting voltage level for each memory cell. The method further comprises applying a second reference drive voltage to the wordline of memory cells to generate a respective second resulting voltage level from each respective cell in the wordline while detecting a pattern of logic values stored in the memory in parallel. The memory is modified based on a second respective logic value indicated by the respective second resulting voltage level, and at least one of the first reference drive voltage and the second reference drive voltage is modified based on the detected pattern data.
G11C 16/28 - Circuits de détection ou de lectureCircuits de sortie de données utilisant des cellules de détection différentielle ou des cellules de référence, p. ex. des cellules factices
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
A memory device includes a stack including a plurality of electrode layers and a plurality of interlayer insulating layers that are vertically alternately stacked; a cell plug vertically penetrating the stack; a source plate disposed on the stack and connected to the cell plug; a contact vertically penetrating the stack and connected to one of the plurality of electrode layers; and a pass transistor disposed on the stack, and including a semiconductor pillar that is connected to the contact, a gate insulating layer that surrounds an outer wall of the semiconductor pillar and a gate electrode that surrounds an outer wall of the gate insulating layer.
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
A semiconductor device includes a line; a source structure on the line; a stack structure on the source structure; a first slit structure penetrating the stack structure; a second slit structure penetrating the stack structure; and a contact plug adjacent to the first slit structure in a first direction. The first slit structure and the second slit structure may be spaced apart from each other by a first distance in a second direction that is perpendicular to the first direction. The contact plug penetrates the source structure, the contact plug being electrically connected to the lower line. The first slit structure and the contact plug may be spaced apart from each other by a second distance in the first direction, and the second distance may be longer than the first distance.
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
A method for calculating carbon emissions of semiconductor products and a computing device using the same are disclosed, and more particularly, a method for indicating the environmental impact of a semiconductor product (DRAM, NAND, SSD, HBM, etc.) as a quantitative number using a unique product code thereof, and converting it into carbon emissions equivalents, thereby evaluating the carbon emissions.
A semiconductor device according to another embodiment of the present disclosure may include a substrate including a channel region, a gate dielectric structure disposed over the channel region, a gate electrode disposed over the gate dielectric structure, and a barrier dielectric layer disposed between the channel region and the gate dielectric structure or between the gate dielectric structure and the gate electrode. The capacitor dielectric structure may include a ferroelectric layer and a dielectric layer. The barrier dielectric layer may include a ferroelectric material.
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
11.
PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM PERFORMING LOW POWER MANAGEMENT AND METHOD OF OPERATING THE SAME
The present technology relates to an electronic device. A computing system may include a host and a peripheral component interconnect express (PCIe) device connected the host through a link. The host comprises a host memory and a storage device driver. The host memory may store information on a first target command to be executed in the PCIe device. The storage device driver may provide the first target command to the host memory and a notification message indicating that the first target command is stored in the host memory to the PCIe device. The PCIe device may request the host memory to register an address of the host memory in which a second target command to be executed in the PCIe device is stored through a preset protocol.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 1/3296 - Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
12.
STORAGE DEVICE, HOST DEVICE, AND ELECTRONIC DEVICE FOR SHARED MEMORY AREA ACCESS
A storage device includes a memory device and a memory controller configured to provide conversion data obtained by converting data received from an external host to the memory device. The memory controller receives, from the external host, a command including information on a specific position in the external host and performs data input or output for the specific position based on the information.
A memory device, and a method of manufacturing the memory device, includes first and second vertical structures spaced apart from each other and a connection structure contacting bottoms of the first and second vertical structures. The memory device also includes a first gate layer disposed between the first and second vertical structures and a second gate layer enclosing the first and second vertical structures and the connection structure. The memory device further includes a global line disposed on the first vertical structure and a local line disposed on the second vertical structure.
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
14.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
A semiconductor device including: a gate structure including stacked gate lines; an insulating core located in the gate structure and including a first long axis and a first short axis; a memory layer surrounding the insulating core; first channel pattern and a second channel pattern located facing each other along the first long axis, wherein the first channel pattern and the second channel pattern are located between the insulating core and the memory layer; and a capping layer located between the first channel pattern and the second channel pattern.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/30 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire
A semiconductor device includes a first gate stack and a second gate stack disposed on a substrate. The first gate stack includes a first lower gate insulating layer. The second gate stack includes a second lower gate insulating layer. The first lower gate insulating layer includes silicon oxide with a first dipole material. The second lower gate insulating layer includes silicon oxide with a second dipole material. The first dipole material and the second dipole material are different from each other.
H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
16.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a gate structure including a cell region and a contact region, a slit structure configured to extend in a first direction through the gate structure, first channel structures disposed in the cell region of the gate structure, and second channel structures disposed in the cell region of the gate structure and disposed to be more adjacent to the contact region of the gate structure than the first channel structures. In a second direction that intersects the first direction, the first channel structures may be spaced apart from the slit structure by a first distance, and the second channel structures may be spaced apart from the slit structure at a second distance.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
Present invention relates to a semiconductor memory device. A semiconductor memory device according to the present invention may comprise: a memory cell array including a plurality of memory cells over a substrate, the plurality of memory cells repeatedly arranged in horizontal direction and a vertical direction, the horizontal direction parallel to a surface of the substrate, the vertical direction perpendicular to the surface of the substrate, a bit line coupled to the memory cells arranged in the vertical direction, and a word line coupled to the memory cells arranged in the horizontal direction, wherein each of the memory cells comprises a capacitor comprising a storage node and a plate node, and the plate nodes of the capacitors are coupled to each other in the vertical direction and are spaced apart from each other in the horizontal direction.
A memory device includes a memory block including strings, each including first memory cells coupled between a first dummy cell and a second dummy cell and second memory cells coupled between third dummy cell and fourth dummy cell, and a peripheral circuit performing a normal program operation on first and second memory cells, or a soft program operation on first to fourth dummy cells, wherein the peripheral circuit is configured to, perform a soft program operation on the fourth dummy cell which is farthest from an area to which the precharge voltage is applied and perform a normal program operation on second memory cells, wherein the precharge voltage is applied to the area during the normal program operation, and wherein the area is adjacent to the first dummy cells.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
19.
DATA CODING DEVICE, MEMORY CONTROLLER, AND STORAGE DEVICE
A data coding device may include a raw data storage configured to store raw data of which the total number of bits is 2N, a previous data storage configured to store previous data output before the raw data, a counter configured to count the number of reference data bits included in the raw data, and a data output circuit configured to invert and output the raw data according to a comparison result with the previous data when the number of reference data bits included in the raw data is N, and invert and output the raw data according to the number of reference data bits included in the raw data when the number of reference data bits included in the raw data is not N.
A slurry reuse system includes a slurry collection part that selectively collects high-concentration waste slurry included in waste slurry discharged after a CMP process, a fine particle separation part that separates fine particles by applying high-frequency sound waves to abrasive particles of the collected high-concentration waste slurry, an abrasive particle uniformity part that operates simultaneously with the fine particle separation part and that has electrodes inserted into both ends of the waste slurry, secures the uniformity of the shape and size of the abrasive particles, and removes impurities by applying an electric field, a slurry mixing part that mixes slurry subjected to processes of the fine particle separation part and the abrasive particle uniformity part, a filter part that extracts abrasive particles, chemicals, and DI water from the mixed slurry, and an abrasive particle and chemical remixing part that re-mixes the extracted abrasive particles and high-concentration chemicals.
Method for power mode management of an interconnection protocol in an electronic device and an electronic device configured to communicate with another electronic device using an interconnection protocol are provided. The method comprises a plurality of steps as follows. A power mode for a forward link is determined by the electronic device, based on version information of the interconnection protocol of another electronic device, wherein the version information of the interconnection protocol of the another electronic device is obtained in a first stage of link initialization. The electronic device operates in the power mode for the forward link for a second stage of the link initialization following the first stage of the link initialization.
A memory device includes a plurality of non-volatile memory cells connected to word lines and bit lines. The memory device includes a plurality of buffer circuits coupled to the memory cell array. The plurality of buffer circuits are configured to, in a deep neural network computing operation, store values read from selected memory cells of the memory cell array, and perform multiplication operations using the stored values and corresponding input data values.
KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY (République de Corée)
Inventeur(s)
Lee, Seungjun
Jang, Junhyeok
Jung, Myoungsoo
Abrégé
A data storage device includes an address estimating circuit configured to generate a start logical address and a request size corresponding to the start logical address from an input logical address corresponding to a write request; an address allocating circuit configured to allocate a target physical address corresponding to the input logical address by using the start logical address, the request size, and the input logical address; and a read queue storing a read command to be provided to a memory device, wherein the address estimating circuit estimates the start logical address considering a probability of the start logical address coexisting in the read queue with the input logical address.
A memory device includes a refresh latch configured to generate a first aggressive address by latching an address input with a refresh management command; a detection circuit configured to sequentially store the first aggressive address as a plurality of first candidate addresses, and generate a detection signal according to a number of duplicated addresses among the plurality of the first candidate addresses; an address sampling circuit configured to generate a second aggressive address by collecting information on rows subjected to a row-hammer attack; and an output control circuit configured to output, as a target address, the first aggressive address or the second aggressive address according to the refresh management command and the detection signal.
G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
G06F 21/56 - Détection ou gestion de programmes malveillants, p. ex. dispositions anti-virus
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p. ex. les mémoires adressables directement
A system includes a first device including a first transmitter and a first receiver, and a second device including a second transmitter and a second receiver and configured to communicate with the first device. The two devices perform a first equalization operation by performing a first phase in which the first receiver performs a signal tuning operation on the second transmitter, a second phase in which the second receiver performs a signal tuning operation on the first transmitter, and one or more other phases. The first, second, and other phases may constitute all the phases of the first equalization operation, and some of the other phases may precede the first and second phases. In response to detection of an error after the first equalization operation, the two devices may perform a second equalization operation by performing the first phase, the second phase, or both, but not performing the other phases.
A semiconductor device may include: a first gate structure; a second gate structure disposed over the first gate structure; and a channel structure including a first portion extending through the first gate structure, the first portion having a tapered cross section, a second portion having a tapered cross section, and a third portion connecting the first portion with the second portion, wherein the third portion has a vertical profile, and wherein the second portion and the third portion extends through the second gate structure.
H10B 41/30 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire
H10B 41/23 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés
A memory controller according to the present disclosure may be configured to receive a trim command from a host, the trim command instructing to read range data corresponding to a plurality of logical block address ranges, and to sequentially invalidate mapping information corresponding to the plurality of logical block address ranges based on priority information included in the range data.
According to one embodiment, a magnetic memory device includes first and second lower wiring lines, each extending along a first direction, first and second upper wiring lines, each extending along a second direction, a first memory cell between the first lower and first upper wiring line, a second memory cell between the first lower and second upper wiring line, and a third memory cell between the second lower and first upper wiring line, and each of the first, second, and third memory cells includes a structure in which a magnetoresistance effect element and a switching element are stacked in a third direction, the magnetoresistance effect element includes main body and a sidewall, and the sidewall included in the first and second memory cells are spaced apart from each other along the first direction.
A memory system includes a cache memory storing a data symbol and a parity symbol, and a main memory storing the data symbol. A controller generates a first virtual tag symbol including tag information used to identify a location where the data symbol is stored in the main memory, and generates a second virtual tag symbol including tag information indicating where a cache hit of the data symbol is expected in the cache memory, based on an access address received from a host. An ECC engine performs encoding on the data symbol and a first virtual tag symbol, generates the parity symbol based on the encoding, performs decoding on the second virtual tag symbol, and the data symbol and the parity symbol read from the cache memory, and checks an error in the data symbol and an error in the second virtual tag symbol based on the decoding.
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
30.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
A semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked with each other in a first direction, a source layer, and a channel layer passing through the stacked structure and being in contact with the source layer. The channel layer includes a first region and a second region, and the first region is disposed between the source layer and the second region, and a first thickness of the first region is greater than a second thickness of the second region.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
A memory device includes a plurality of memory cells coupled to each of a plurality of word lines, a peripheral circuit configured to perform a first sensing operation on first memory cells, among the plurality of memory cells, coupled to a selected word line among the plurality of memory cells by applying different voltages to the selected word line and unselected word lines, and control logic configured to control the peripheral circuit to perform an operation including applying voltages to the plurality of word lines, in which the control logic determines, based on a magnitude of a first sensing voltage applied to the selected word line during the first sensing operation, a first equalizing time period during which an equalizing voltage is applied to the plurality of word lines after the first sensing operation.
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
32.
PRECURSOR FOR FORMING LOW DIELECTRIC CONSTANT SILICON-CONTAINING THIN FILM AND METHOD FOR FORMING LOW DIELECTRIC CONSTANT SILICON-CONTAINING THIN FILM USING SAME
The present invention relates to: a precursor for forming a low dielectric constant silicon-containing thin film, the precursor containing a silicon-containing compound represented by chemical formula 1 or chemical formula 2; and a method for forming a thin film using the precursor. The precursor for forming a low dielectric constant silicon-containing thin film forms a low dielectric constant silicon-containing thin film having a dielectric constant of 2.2-3.6. The precursor is a liquid at room temperature and thus easy to store and handle, and has high reactivity and thus can easily form a high-quality silicon-containing thin film at an excellent growth rate.
A semiconductor device includes: a source structure comprising a cell area and an edge area; a stack located on the edge area of the source structure; a gate structure located on the cell area of the source structure; a channel structure connected to the cell area of the source structure by extending through the gate structure; and a read-only memory area.
There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a first etch stop layer; a source layer on the first etch stop layer; a second etch stop layer on the source layer; a stack structure on the second etch stop layer; and a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer. A material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.
The present disclosure includes a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a stack including a plurality of conductive layers stacked to be spaced apart in a first direction, an opening in the stack extending in the first direction and having an elliptical shape in a plan view, and a first channel pattern and a second channel pattern spaced apart from each other in a second direction toward which a major axis of the elliptical shape faces in the opening, the first channel pattern and the second channel pattern extending in the first direction. Each of the first channel pattern and the second channel pattern includes a central portion overlapping with the major axis of the elliptical shape and bent portions extending away from the central portion.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
36.
DATA STORAGE DEVICE, DATA STORAGE SYSTEM AND COMPUTING SYSTEM FOR SNAPSHOT OPERATIONS
In an embodiment of the disclosed technology, a data storage device includes at least one memory device including a plurality of memory regions configured to store data, a first controller configured to allocate the plurality of memory regions according to a memory allocation request of one or more host devices, and a second controller configured to: generate, in response to a snapshot request of a first host device among the one or more host devices, snapshot data corresponding to at least part of the data stored in at least part of the plurality of memory regions allocated to the first host device; and store the snapshot data into an auxiliary storage device coupled to the second controller.
A storage device includes a memory device and a controller. The memory device includes a plurality of memory regions. The controller is configured to perform a test operation on a target memory region among the memory regions when it is impossible to determine a second program standby time amount by which a second program operation remains as not performed on the target memory region after a first program operation is performed on the target memory region, and configured to control, according to a result of the test operation, the memory device to perform an adjusted second program operation on the target memory region.
G11C 29/12 - Dispositions intégrées pour les tests, p. ex. auto-test intégré [BIST]
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
38.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE
A semiconductor device may include: a plurality of word lines; a select line; a channel layer extending into the select line through the word lines; a floating gate surrounding sidewalls of the channel layer between the channel layer and the select line; and a charge trap layer including a first and a second portion, wherein the first portion surrounds the sidewalls of the channel layer between the channel layer and the word lines and the second portion surrounds the floating gate between the channel layer and the select line.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
39.
BUFFER CIRCUIT, AND SEMICONDUCTOR APPARATUS CAPABLE OF ADJUSTING A CLOCK RECEIVER AND/OR CHANGING A CLOCK PATH ACCORDING TO FREQUENCY INFORMATION
A semiconductor apparatus includes a frequency control circuit and an internal clock generation circuit. The frequency control circuit generates a frequency information signal based on a command address signal, and generates a frequency control signal by comparing the frequency information signal with a frequency setting signal. The internal clock generation circuit generates an internal clock signal from a system clock signal based on the frequency control signal.
G06F 1/12 - Synchronisation des différents signaux d'horloge
G06F 1/324 - Économie d’énergie caractérisée par l'action entreprise par réduction de la fréquence d’horloge
H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
H03L 7/191 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle une différence de temps étant utilisée pour verrouiller la boucle, le compteur entre des nombres fixes ou le diviseur de fréquence divisant par un nombre fixe utilisant au moins deux signaux différents à partir du diviseur de fréquence ou du compteur pour déterminer la différence de temps
A data processing system may include a storage unit and a controller in communication with the storage unit and configured to program write data to a first area as at least one of the plurality of storage areas with priority over a second area as at least one of the plurality of storage areas and transfer data of the first area to the second area. The controller is further configured to adjust a size of the first area based on 1) a number of times saturated by the write data for the first area, a saturation occurring due to a size of the write data written to the first area being greater than a certain size and 2) an overflow size of the write data corresponding to a difference between the size of the write data and the certain size.
A memory device includes a control signal generation circuit configured to generate a control signal at a voltage level corresponding to a current temperature in each operation period, among a plurality of operation periods, of a program operation, and a bit line control circuit configured to charge a bit line in response to the control signal.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
G11C 16/24 - Circuits de commande de lignes de bits
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
42.
SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF
A semiconductor package according to embodiments of the present disclosure may include a base chip; a first redistribution layer disposed on the base chip; a first bump disposed on the first redistribution layer; a plurality of core chips stacked upon each other; a second redistribution layer disposed below the plurality of the core chips; a plurality of bonding wires disposed under the plurality of core chips, and respectively connecting the plurality of core chips and the second redistribution layer; a molding layer disposed on the second redistribution layer, and disposed to cover the plurality of core chips and surround the plurality of bonding wires; and a second bump disposed under the second redistribution layer and bonded onto the first bump.
A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of strings coupled between a bit line and a source line and each of the plurality of strings comprises a drain selection transistor coupled to a corresponding drain selection line, memory cells coupled to a plurality of word lines, and a source selection transistor coupled to a corresponding source selection line. The peripheral circuit is configured to apply a subthreshold gate voltage to a particular source selection line coupled to an unselected string among the plurality of strings, while applying a turn-off voltage to a particular drain selection line coupled to the unselected string, during at least a portion of a read interval in which a read pass voltage is applied to unselected word lines among the plurality of word lines.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
44.
Bit-Flipping Algorithm for Binary Asymmetric Channels
A method and associated memory system for reading data from a memory. The method decodes with a memory controller the data read from the memory using symmetric bit-flip (BF) decoding and asymmetric bit BF decoding; iterates the symmetric BF decoding; during the iterating of the symmetric BF decoding, determines an asymmetric ratio of a) a number of errors in flipping from “0” to “1” to b) a number of errors in flipping from “1” to “0”; and compares the asymmetric ratio to an asymmetric ratio threshold in order to determine whether to continue the iterating of the symmetric BF decoding or to switch to the asymmetric BF decoding.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
45.
MEMORY DEVICES CONFIGURED TO PERFORM A REFRESH OPERATION AND METHOD OF PERFORMING A REFRESH OPERATION WITH A MEMORY DEVICE
A memory device includes an address arithmetic circuit configured to generate a redundancy switching signal when a normal word line connected to a normal cell is designated as a target word line and a redundancy word line connected to a redundancy cell is designated as an adjacent word line so that a smart refresh operation is performed. The memory device also includes a redundancy control circuit configured to generate a redundancy activation signal based on the redundancy switching signal.
A memory device includes a base die configured to output a temperature code signal after the start of a self-refresh operation. The memory device also includes a core die. The core die is configured to generate a refresh code signal that is set as a gray code based on the temperature code signal. The core die is further configured to perform the self-refresh operation based on a refresh pulse signal having a generation cycle adjusted based on a combination of logic levels of the refresh code signal. The core die is additionally configured to adjust the generation cycle of the refresh pulse signal by latching the refresh code signal in synchronization with the refresh pulse signal.
Embodiments of the present disclosure configures data structure information corresponding to map data representing mapping relationships between logical addresses by a host device and physical addresses of a memory in a binary search tree structure, and manages and searches for the map data on the basis of the data structure information, thereby reducing the time required for searching for the map data and thus improving the operational performance of a storage device including the memory that processes a command from the host device.
According to embodiments of the present disclosure, a memory device may include a landing pad disposed on the substrate and located in the cell region, a lower electrode in contact with an upper surface of the landing pad, an upper electrode on the lower electrode, a dielectric layer between the lower electrode and the upper electrode, a conductive layer located in the peripheral region and disposed in the same layer as the landing pad, a first contact structure including a first contact plug portion in contact with an upper surface of the conductive layer, and a first contact wiring portion that extends continuously from the first contact plug portion with a width greater than a width of the first contact plug portion, and a first wiring layer disposed on the first contact structure and having a same width as the first contact wiring portion.
A memory device includes memory cells and a peripheral circuit. The memory cells are coupled to a plurality of word lines. The peripheral circuit is configured to, in a first interval, while a program voltage is applied to a selected word line among the plurality of word lines, apply a pre-program pass voltage to one or more adjacent word lines adjacent to the selected word line in a first sub-interval included in the first interval, and discharge the one or more adjacent word lines in a second sub-interval included in the first interval, and in a second interval, apply a program pass voltage to the one or more adjacent word lines while the program voltage is applied to the selected word line.
A storage device includes a memory device including a plurality of memory blocks, and a controller. The controller is configured to allocate one or more of the plurality of memory blocks to each of a plurality of zone regions, determine, as victim memory blocks, one or more memory blocks having remaining spaces, sizes of which each exceed a threshold size, among memory blocks allocated to closed zone regions among the plurality of zone regions, a remaining space representing an empty space in which no data is stored, and merge at least one or more of the victim memory blocks into a target memory block. The plurality of zone regions respectively correspond to logical address groups received from an external host device.
A multiplication-accumulation (MAC) includes a multiply-accumulate circuit configured to receive weight data and vector data, and to generate and output maximum exponent data and exponent data of multiply-accumulate data. The multiply-accumulate circuit includes a multiplication circuit that performs a multiplication operation on the weight data and the vector data to output sign data, modified exponent data, and mantissa data of each of multiplication data, a pre-processing circuit that separates each of the exponent data of the multiplication data to generate exponent upper data and exponent lower data, and performs exponent pre-processing using the exponent upper data and mantissa pre-processing using the exponent lower data to output maximum exponent upper data and pre-processed mantissa data, and an adder tree that adds the pre-processed mantissa data to generate and output mantissa data of the multiply-accumulate data.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p. ex. la justification, le changement d'échelle, la normalisation
52.
MEMORY DEVICE GENERATING VOLTAGE RESPONSIVE TO TEMPERATURE AND METHOD OF OPERATING THE SAME
A memory device includes a memory cell array including a plurality of memory cells, a temperature sensor configured to measure an internal temperature and generate a temperature compensation code corresponding to the internal temperature, a voltage control circuit configured to generate a conversion temperature code converted from the temperature compensation code, and a voltage generation circuit configured to output a compensation voltage obtained by compensating for a level of a voltage used in an operation on the memory cell array responsive to the conversion temperature code. The temperature sensor and the voltage control circuit are may be located at different positions relative to the memory cell array.
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
A method of manufacturing a semiconductor memory device may include alternately stacking a first insulation layer and a second insulation layer to form a stacked structure. Slits may be formed at the stacked structure to divide the stack structure into a plurality of memory blocks. A preliminary bridge may be simultaneously formed in each of the slits to partially connect memory blocks of the stacked structure with each other. The memory block and the second insulation layer of the preliminary bridge exposed through the slit may be selectively removed to form a space. A conductive layer for a word line may be formed in the space of the memory block and the preliminary bridge. The conductive layer for the word line remaining in the space of the preliminary bridge may form an insulation bridge.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
54.
MEMORY CONTROLLER AND STORAGE DEVICE INCLUDING THE SAME
A memory controller that includes a buffer memory configured to store user data and a write command corresponding to a write request received from a host, a processor configured to control a memory device to perform a write operation, and a host interface configured to determine an active range based on mapping information of the memory device, determine the throttle trigger value based on the active range, determine a base latency based on a write ratio of the write command to commands received from the host, and determine a delay time of a write completion response based on the throttle trigger value and the base latency, delay the write completion response according to the delay time, and transmit the delayed write completion response to the host.
A data storage system includes a controller comprising pipelined multiple processors. The controller is configured to: generate plural instructions having dependency based on a command, input from an external device, for controlling at least one storage device to perform an operation corresponding to the command; allocate the plural instructions to the pipelined multiple processors in stages; and reallocate, when a number of second instructions allocated to a second processor of the pipelined multiple processors becomes a first threshold or greater, at least one of the second instructions to a first processor of the multiple processors.
A semiconductor device according to an embodiment of the present disclosure may include: a stack structure including a plurality of first conductive patterns and a plurality of dielectric layers, which are alternately stacked, the stack structure having a stepped structure such that any one of the first conductive patterns further protrudes than the first conductive pattern positioned immediately above it; a plurality of second conductive patterns which are respectively formed over protrusions of the first conductive patterns; a plurality of contact plugs which overlap the plurality of second conductive patterns, respectively, and pass through the overlapping second conductive patterns and the stack structure; and a sealing layer pattern which is interposed between the first conductive patterns and the contact plugs and separates the first conductive patterns from the contact plugs.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
57.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
A semiconductor device including a first block word line, and a first channel layer located in the first block word line. the semiconductor device including a source pad connected to the first channel layer and located on the first block word line, and a first drain pad connected to the first channel layer and located on the first block word line. The semiconductor device including a global word line connected to the source pad, and a first local word line connected to the first drain pad.
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
58.
STORAGE DEVICE STORING ARTIFICIAL INTELLIGENCE MODEL, AND OPERATING METHOD THEREOF
A storage device may include a memory configured to store a plurality of data units, each data unit including at least one of parameters of an artificial intelligence model; and a controller configured to externally receive structure information on the artificial intelligence model, determine the plurality of data units based on the structure information, and determine whether to cache each of the plurality of data units in a cache.
Disclosed are a semiconductor device capable of increasing the upper area of an active region, and a method for fabricating the semiconductor device. The semiconductor device includes: a substrate including an isolation layer and a plurality of active regions that are defined by the isolation layer; a trench disposed in the substrate to cross the isolation layer and the plurality of active regions in a first direction; a semiconductor layer disposed on inner sidewalls and a bottom surface of the trench in each of the plurality of active regions; a buried gate structure disposed in the trench including the semiconductor layer.
A memory device according to an embodiment of the present disclosure includes a plurality of memory cells; a plurality of page buffers storing data in the plurality of memory cells or reading data from the plurality of memory cells; a plurality of bit lines connected between the plurality of memory cells and the plurality of page buffers; and a cyclic redundancy check unit including a collection unit collecting bit line data loaded on the plurality of bit lines and a calculation unit performing a cyclic redundancy check (CRC) on the collected bit line data.
UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY (République de Corée)
Inventeur(s)
Lee, Min Yung
Jeon, Woojin
Kim, Yewon
Abrégé
A method for forming a thin film structure may include providing a TiN member, forming a MoO2 thin film on the TiN member by using a first ALD (atomic layer deposition) process using ozone (O3) as a reactant, and forming a TiO2 thin film having a rutile crystal structure on the MoO2 thin film by using a second ALD process. The MoO2 thin film may have a thickness of about 10 nm or less. A TiO2 element layer may be further formed between the TiN member and the MoO2 thin film. The TiO2 element layer may have a nanodot array shape or a continuous layer structure. The TiO2 thin film may have a dielectric constant of 100 or more. The method of manufacturing a capacitor may further include forming a conductive material layer on the TiO2 thin film.
A semiconductor device may include: first semiconductor structure including a page buffer, a first peripheral circuit, a bit line located on the page buffer, a stack located on the bit line and the stack including a) a step structure, b) a source structure located on the stack, and channel structures extending through the stack; and a second semiconductor structure bonded to the first semiconductor structure and the second semiconductor structure including a) a second peripheral circuit located to face the source structure and b) pass transistors located to face the step structure.
A storage device may include a memory and a controller. The memory may include a plurality of memory units. The controller may transmit a read command for a target memory unit among the plurality of memory units to the memory, read a state value from the memory after transmitting the read command to the memory, and determine that all bits of data stored in the target memory unit are 1 when the state value is a first value, and determine that all bits of the data stored in the target memory unit are 0 when the state value is a second value.
Data storage systems are disclosed. In some implementations, a data storage device includes a controller coupled to a plurality of memory devices to control memory operations of the plurality of memory devices, and including M communication lanes, and an interface device configured to include N communication lanes to be connected to a host device that includes N communication lanes and to the M communication lanes of the controller, wherein the interface device includes a connector configured to connect the N communication lanes of the host device to the N communication lanes of the interface device, and a selector configured to, in response to a host port type identification signal received from the host device, selectively activate M communication lanes of the interface device, out of the N communication lanes of the interface device, to transmit or receive the data to or from the M communication lanes of the controller.
A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
H03M 13/37 - Méthodes ou techniques de décodage non spécifiques à un type particulier de codage prévu dans les groupes
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
66.
POLY(PHTHALALDEHYDE) DERIVATIVES, COMPOSITIONS INCLUDING THE SAME, AND PATTERN FORMATION METHODS
A photoresist composition including a first polymer including a first repeating unit derived from a compound of Formula (1); a second polymer including a first repeating unit comprising an acid-labile group, a base-labile group, a base soluble group, or a combination thereof, wherein the first repeating unit of the second polymer is derived from a monomer comprising an ethylenically unsaturated polymerizable double bond; a photoacid generator; and a solvent,
A photoresist composition including a first polymer including a first repeating unit derived from a compound of Formula (1); a second polymer including a first repeating unit comprising an acid-labile group, a base-labile group, a base soluble group, or a combination thereof, wherein the first repeating unit of the second polymer is derived from a monomer comprising an ethylenically unsaturated polymerizable double bond; a photoacid generator; and a solvent,
A photoresist composition including a first polymer including a first repeating unit derived from a compound of Formula (1); a second polymer including a first repeating unit comprising an acid-labile group, a base-labile group, a base soluble group, or a combination thereof, wherein the first repeating unit of the second polymer is derived from a monomer comprising an ethylenically unsaturated polymerizable double bond; a photoacid generator; and a solvent,
wherein, in Formula (1), each R1 is a non-hydrogen substituent, each R1 optionally further includes one or more divalent linking groups as part of their structure, wherein each of the one or more divalent linking groups is independently substituted or unsubstituted, two adjacent R1 optionally form a ring together, wherein the ring is substituted or unsubstituted, and a is an integer from 1 to 4.
A semiconductor package includes a substrate on which a first substrate pad array and a second substrate pad array are formed; and a plurality of semiconductor dies each including a first die pad array and a second die pad array, the plurality of semiconductor dies stacked on the substrate in a stack. A first semiconductor die of the plurality of semiconductor dies is stacked such that the first die pad array and the second die pad array of the first semiconductor die face the first substrate pad array and the second substrate pad array, respectively, and the semiconductor dies, except for the first semiconductor die, are stacked in an orientation opposite to an orientation of the first semiconductor die.
A semiconductor apparatus includes a clock distribution network, wherein a clock receiving circuit receives a first data clock signal and a second data clock signal to generate a first internal clock signal pair and a second internal clock signal pair. A first clock distribution path provides the first internal clock signal pair to a data receiving circuit, and the data receiving circuit divides the first internal clock signal pair to generate a plurality of write clock signals. A second clock distribution path divides the second internal clock signal pair to generate a plurality of read clock signals and provides the plurality of read clock signals to a data output circuit.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 8/18 - Circuits de synchronisation ou d'horlogeGénération ou gestion de signaux de commande d'adresse, p. ex. pour des signaux d'échantillonnage d'adresse de ligne [RAS] ou d'échantillonnage d'adresse de colonne [CAS]
A semiconductor apparatus includes a calibration control circuit, a first data input and output block, and a second data input and output block. The calibration control circuit generates a main clock signal and a calibration control signal for an offset calibration operation. The first data input and output block adjusts the offset of the first data input and output block based on the main clock signal, the calibration control signal, and a reference voltage. The second data input and output block adjusts the offset of the second data input and output block based on the main clock signal, the calibration control signal, and the reference voltage.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
70.
BUFFER CHIP, SEMICONDUCTOR PACKAGE INCLUDING BUFFER CHIP AND MEMORY CHIP, AND MEMORY MODULE
A buffer chip includes: an external control signal interface configured to receive control signals transmitted from a memory controller; an internal control signal interface configured to transmit the control signals to a plurality of memory chips; an external data interface configured to transmit and receive (transmit/receive) data to and from (to/from) the memory controller; an internal data interface configured to transmit/receive the data to/from the plurality of memory chips; and a loopback circuit configured to be activated in a loopback mode to receive the control signals transmitted by the internal control signal interface, and transmits the control signals to the external data interface.
A semiconductor package may include: a package substrate including a plurality of terminals for communication with a memory controller and a plurality of bonding pads for communication inside a package; a buffer chip located on the package substrate; a plurality of memory chips stacked on the buffer chip; and a plurality of wires connecting the plurality of bonding pads and the plurality of memory chips. The buffer chip may communicate with the memory controller through the plurality of terminals of the package substrate, and the plurality of memory chips may communicate with the buffer chip through the plurality of wires and the plurality of bonding pads of the package substrate.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
A memory device, and a method of manufacturing the same, includes a first select line including a first cell area, a second select line including a second cell area disposed in a first direction from the first cell area, a first separation pattern extending in a second direction intersecting the first direction between the first cell area and the second cell area, second separation patterns extending from both ends of the first separation pattern in the first direction and a third direction opposite the first direction, respectively, and a third separation pattern extending from at least one of the second separation patterns in the second direction, and disposed in a direction opposite the first separation pattern with respect to the at least one second separation pattern.
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
73.
MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME
Provided herein are a memory controller and a method of operating the same. The memory controller may include a background condition storage and a background controller. The background condition storage may be configured to store a trigger condition for each background operation for a memory device in each of a non-charging mode and a charging mode associated with a battery for the memory controller. The background controller may be configured to change the trigger condition from a non-charging condition to a charging condition depending on charging information indicating whether the battery for the memory controller is in a charging state. The trigger condition is mitigated in the charging condition compared to the non-charging condition.
A semiconductor device includes a first row line, a first column line positioned on the first row line, a first memory cell positioned between the first row and first column lines and included in a first current path, a third row line, a third column line positioned on the third row line, a third memory cell positioned between the third row and third column lines and included in a third current path longer than the first current path, first contact plugs including first and third ones electrically connected to the first and third row lines, respectively, second contact plugs including first and third ones electrically connected to the first and third column lines, respectively, a first barrier pattern positioned between the first one of the first contact plugs and the first row line, and a second barrier pattern positioned between the first barrier pattern and the first row line.
According to an embodiment of the disclosed technology, a storage device is provided. The storage device comprises a first memory device configured to store data, a second memory device including a first cache memory configured to store mapping information between physical data addresses and logical data addresses of the stored data and a second cache memory configured to store segments of the mapping information, and a memory controller in communication with the first memory device and the second memory device and configured to update the mapping information in response to a write request received from an external host device, in which the memory controller is configured to allocate a first region among regions of the second cache memory for the mapping information in response to determining that a size of a workload corresponding to the write request is less than or equal to a first threshold value.
A semiconductor system includes a first semiconductor apparatus and a second semiconductor apparatus. The first semiconductor apparatus provides the second semiconductor apparatus with a chip enable signal and a command address signal set, and the second semiconductor apparatus performs an internal operation based on the chip enable signal and the command address signal set. The first semiconductor apparatus provides the second semiconductor apparatus with a selection chip enable command, and the second semiconductor apparatus transmits data to the first semiconductor apparatus or receives the data from the first memory device after receiving the selection chip enable command.
Seoul National University R&DB Foundation (République de Corée)
Inventeur(s)
Park, Sung Ho
Abrégé
A memory device includes a cell array including a NAND string comprising a plurality of memory cells whose control gates are connected to a plurality of word lines, and a plurality of drain selection switches connected between the plurality of memory cells and a bit line and controlled by a plurality of drain selection lines; and a control circuit configured to control a erase operation for erasing a selected memory cell. During the first erase operation, the control circuit sets a voltage applied to the first bit line and a voltage applied to a first one of the plurality of first drain selection lines so as to generate GIDL current at a first one of the plurality of first drain selection switches, and sets voltage applied to another one of the drain selection lines to be lower than the voltage of the first one of the drain selection lines.
A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.
Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
A memory device includes a plurality of core dies stacked over a base die. Each of the plurality of core dies includes a first channel region including a first repeater that receives and amplifies first fuse data stored in a fuse data storage circuit during a boot-up operation. Each of the plurality of core dies also includes a second channel region including a second repeater that receives and amplifies second fuse data stored in the fuse data storage circuit during the boot-up operation.
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
81.
APPARATUS AND OPERATION METHOD FOR PERFORMING A READ OPERATION IN A MEMORY DEVICE
A memory system includes a memory device and a controller. The memory device is configured to store data corresponding to a data input/output command. The controller is configured to receive, from an external device, the data input/output command and a notification of Slack Space Recycling (SSR) corresponding to the data input/output command, and control, based on the notification, a buffer for processing data and metadata corresponding to the data input/output command.
An image sensing device is provided to comprise: pixels supported by a substrate, wherein the pixels includes a first pixel including: a first sub pixel including a first pixel area, and a portion of a second non-pixel area; second sub pixels, each including a second pixel area, another portion of the second non-pixel area, and a first non-pixel area; photoelectric conversion elements respectively placed in the first and second sub pixels and configured to detect a photon reflected from a target object and generate a pixel signal corresponding to the detected photon; a grid structure including first and second grids placed in the first and second non-pixel areas, respectively, wherein the substrate includes a first recess in the first non-pixel area and the substrate includes a second recess in the second non-pixel area, and a depth of the first recess is greater than a depth of the second recess.
H04N 25/773 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des convertisseurs A/N, V/T, V/F, I/T ou I/F comprenant des circuits de comptage de photons, p. ex. des diodes de détection de photons uniques [SPD] ou des diodes à avalanche de photons uniques [SPAD]
G01S 7/481 - Caractéristiques de structure, p. ex. agencements d'éléments optiques
G01S 7/4861 - Circuits pour la détection, d'échantillonnage, d'intégration ou de lecture des circuits
G01S 7/4865 - Mesure du temps de retard, p. ex. mesure du temps de vol ou de l'heure d'arrivée ou détermination de la position exacte d'un pic
G01S 17/894 - Imagerie 3D avec mesure simultanée du temps de vol sur une matrice 2D de pixels récepteurs, p. ex. caméras à temps de vol ou lidar flash
H04N 25/78 - Circuits de lecture pour capteurs adressés, p. ex. amplificateurs de sortie ou convertisseurs A/N
H10F 39/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément couvert par le groupe , p. ex. détecteurs de rayonnement comportant une matrice de photodiodes
In an embodiment, a display device includes a substrate including pixel regions for a plurality of sub-pixels configured to emit light in response to an electric signal, wherein the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel; a first reflective electrode disposed on the substrate in the first sub-pixel; a first insulating layer disposed on the first reflective electrode; a second reflective electrode disposed on the first insulating layer in the second sub-pixel; a second insulating layer disposed on the second reflective electrode; and a third reflective electrode disposed on the second insulating layer in the third sub-pixel, in which a thickness of the first reflective electrode is greater than a thickness of the second reflective electrode and a thickness of the third reflective electrode.
A memory device includes a base chip and a core chip that are stacked through a signal path. The base chip and the core chip drive the signal path after the start of a scan operation and detect a connection fail of the signal path based on a logic level at which an internal node that is connected to the signal path is driven. The base chip adjusts timing at which the logic level of the internal node is latched.
A storage device includes a shared memory and a memory controller. The shared memory stores first data received from a first computing node and second data received from a second computing node. The memory controller performs an instruction on the first data and the second data, stores third data, which is a result of performing the instruction, in the shared memory, and transmits the third data to the first computing node and the second computing node.
A semiconductor device includes: row lines extending along a first direction; column lines extending along a second direction that intersects the first direction; memory cells located between the row lines and the column lines and including variable resistance layers; and a first gap-fill insulating layer including a first portion located between an adjacent pair of the row lines in the second direction and a second portion located between an adjacent pair of the memory cells in the second direction. The first portion has a first nitrogen concentration, and the second portion has a second nitrogen concentration higher than the first nitrogen concentration.
In a method of manufacturing a magnetic memory device, a temporary shift cancel layer including X metal atoms and Y metal atoms as free atoms may be formed. A magnetic tunnel junction layer may be formed on the temporary shift cancel layer. The magnetic tunnel junction layer and the temporary shift cancel layer may be etched to form a magnetic tunnel junction pattern and a temporary shift cancel pattern. The Y metal atoms redeposited between the magnetic tunnel junction pattern and the temporary shift cancel pattern may be oxidized to form metal oxide. The Y metal atoms of the temporary shift cancel pattern may be substituted with Z metal atoms to form a shift cancel pattern. The Y metal atoms may have higher oxidizing than the Z metal atoms. The Z metal atoms may have a higher reduction potential than the Y metal atoms.
A hub device is provided. The hub device includes a first memory, a second memory, and a hub controller. The first memory is configured to store queue setting information for setting a plurality of software queues corresponding to a plurality of processors, and to store doorbell information generated based on the queue setting information and indicating statuses of the plurality of software queues. The second memory is configured to store tag information triggering operations of the plurality of processors. The hub controller is configured to select a target processor from the plurality of processors upon request of a host, select a target queue from at least one software queue corresponding to the target processor, and support communication between the host and the target processor using the target queue.
A data processing system includes a host; a first memory device communicating with the host via an interface; and a second memory device communicating with the first memory device via the interface, storing data used in a memory-intensive computation, and performing the memory-intensive computation instead of the first memory device.
A storage device includes a target group of non-volatile memory cells and a peripheral circuit. Each of the non-volatile memory cells stores multiple data bits. The peripheral circuit includes page buffers coupled to the respective memory cells. The peripheral circuit performs a normal program operation on the target group, and performs, according to data loaded on the page buffers, a corrective program operation on one or more selected memory cells that are supposed to have threshold voltages corresponding to one or more predetermined program states within the target group.
A system for processing failure information for storage devices includes: a preprocessor configured to process test failure information to generate text, categorical and numerical features, the test failure information associated with test failures for a storage device; an embedding vector generator configured to generate an embedding vector based on the text features; a features concatenator configured to concatenate the embedding vector and the categorical and numerical features, and generate concatenated features as a training dataset; and a classifier configured to classify the training dataset, and generate prediction information indicating probabilities for each category identifying features to change for a reduction in the test failures in the storage device.
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
G06F 40/216 - Analyse syntaxique utilisant des méthodes statistiques
92.
SEMICONDUCTOR DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS, SEMICONDUCTOR PACKAGE HAVING SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device is provided including a first semiconductor chip including a first substrate, a first circuit layer disposed on the first substrate and a first chip pad disposed on the first circuit layer; a second semiconductor chip bonded onto the first semiconductor chip, and including a second substrate, a second circuit layer disposed under the second substrate and a second chip pad disposed under the second circuit layer; and a through electrode penetrating the first semiconductor chip and the second semiconductor chip, and connected to the first chip pad and the second chip pad.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
A power management circuit includes a voltage conversion circuit, a multi-mode control circuit, and a drive control circuit. The voltage conversion circuit generates an operating voltage according to an input voltage and a plurality of drive control signals. The multi-mode control circuit divides the operating voltage to generate a feedback voltage, generates an operating voltage detection signal according to the feedback voltage and a first reference voltage, varies a frequency of a ramp voltage to match one of a plurality of operation modes selected according to the operating voltage detection signal and a second reference voltage, and generates a comparison signal according to the operating voltage detection signal and the ramp voltage. The drive control circuit generates the plurality of drive control signals according to the comparison signal.
H02M 1/088 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques pour la commande simultanée de dispositifs à semi-conducteurs connectés en série ou en parallèle
H02M 1/00 - Détails d'appareils pour transformation
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
A semiconductor device including a substrate; an insulating layer disposed on the substrate, and including an outer boundary; a passivation layer disposed on the insulating layer, and including an inner boundary that is located inward of the outer boundary; a dummy pattern layer having a lower surface that forms the same plane with the lower surface of the passivation layer, overlapping at least a part of a region disposed between the outer and inner boundaries, and having a side surface that is located inward of the inner boundary; and a redistribution pattern layer disposed on the dummy pattern layer.
A semiconductor device includes a stack including first insulating layers and second insulating layers that are alternately stacked; channel structures extending through the stack; and gate lines disposed between the channel structures and the first insulating layers and including annular portions respectively surrounding the channel structures and line portions connecting the annular portions to each other.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
96.
APPARATUS AND AN OPERATION METHOD FOR PERFORMING A READ OPERATION IN A MEMORY DEVICE
A memory system includes a memory device including a plurality of data storage areas and a controller. The controller is configured to distribute and store a plurality of first data in a first range among the plurality of data storage areas, generate a first parity corresponding to the plurality of first data, read the plurality of first data from the first range before distributing and storing a plurality of second data in a second range spaced apart from the first range by a preset distance, perform a verification operation based on the first parity, and overwrite a second parity, corresponding to the plurality of second data in a location where the first parity is stored, based on a verification result.
A memory device includes a base chip configured to generate a plurality of division clocks each having a first frequency by dividing the frequencies of an even read signal and an odd read signal generated based on a read command, configured to generate first and second output strobe signals each having a second frequency by synthesizing the plurality of division clocks, and configured to output the first and second output strobe signals through signal paths, and a core chip vertically stacked on the base chip and configured to output data to the base chip in synchronization with the first and second output strobe signals.
A semiconductor device according to embodiments of the present disclosure may include a substrate including a chip region and a scribe lane region disposed around the chip region, the scribe lane region including an inner boundary that abuts the chip region and an outer boundary that is spaced apart from the inner boundary; alignment patterns disposed in the scribe lane region on the substrate, spaced apart from each other in a direction in which the outer boundary extends, and disposed spaced apart from the outer boundary; and cutting guide patterns located in the scribe lane region on the substrate, overlapping with at least some of the alignment patterns, and disposed in a direction that intersects the alignment patterns.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p. ex. marques de repérage, schémas de test
Image sensing devices including pixel isolation structures are disclosed. In an embodiment, an image sensing device includes a first pixel and a second pixel. The first pixel includes a first photoelectric conversion region configured to generate electrical signals in response to detecting light of a first wavelength range, and a first pixel isolation structure that surrounds the first photoelectric conversion region and has a first width. The second pixel includes a second photoelectric conversion region configured to generate electrical signals in response to detecting light of the first wavelength range, and a second pixel isolation structure that surrounds the second photoelectric conversion region and has a second width smaller than the first width.
H10F 39/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément couvert par le groupe , p. ex. détecteurs de rayonnement comportant une matrice de photodiodes
100.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a word-line structure extending into a semiconductor layer to a first depth, and additionally extending in a first direction, an active region extending in a diagonal direction with respect to the first direction in the semiconductor layer, and overlapping with the word-line structure, a bit-line pad region overlapping with one end of the active region and contacting one side of the word-line structure, and extending into the semiconductor layer to a second depth that is shallower than the first depth, and a storage-node pad region overlapping with another end of the active region and contacting another side of the word-line structure, the storage-node pad region being spaced apart from the bit-line pad region in the diagonal direction and extending into the semiconductor layer to a third depth that is shallower than the first depth.
