Abstract

A fabrication method for increasing bottom gate oxide thickness of a power transistor and trench gate structure formed by using the same are provided. A power transistor is provided, and a gate oxide layer is deposited along its trench. Two polysilicon sidewalls are formed and covering thereon. A barrier layer is provided on a side surface of each polysilicon sidewall. And wet etching process is used to remove the gate oxide layer underneath such that a vacancy is formed at the bottom of the trench. By oxidizing the polysilicon sidewalls, a thick oxide layer is formed and filling the vacancy. The disclosed barrier layer is used for avoiding the polysilicon sidewalls from lateral oxidation such that the process method is under better process control. By employing the present invention, it is advantageous of increasing bottom gate oxide thickness, reducing trench corner curvature as well as parasitic gate-drain capacitance.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

The present inventive concept discloses a method for fabrication of a semiconductor structure, and an apparatus for fabrication of the semiconductor structure according to the method. The method comprises: providing a semiconductor structure which includes a plurality of first layers and a plurality of second layers, wherein each of the first layers lies parallelly on each of the second layers and the first layer comprises a first material and the second layer comprises a second material; performing a first etching process by irradiating neutral beam in a first direction onto a surface of the semiconductor structure to form a plurality of fin structures with sidewall surfaces of the first material and the second material; and performing a second etching process onto the sidewall surfaces to remove the second layers and form a plurality of voids, wherein the second etching process has an etching selectivity between the first material and the second material.

IPC Classes  ?

• H01L 21/3065 - Plasma etchingReactive-ion etching
• H01J 37/32 - Gas-filled discharge tubes
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

A method is provided for planning a movement path for a non-fixed end of a robotic arm. A mixed reality (MR) device is used to capture hand images of a user to obtain multiple target coordinate sets in an MR coordinate system. A computer device is used to convert the target coordinate sets into multiple path coordinate sets in a robot base coordinate system, and controls the non-fixed end of a robotic arm to move along a movement path as indicated by the path coordinate sets. A camera device is used to capture images of a base that the robotic arm is fixed to for conversion of the target coordinate sets into the path coordinate sets.

IPC Classes  ?

• B25J 9/16 - Programme controls
• B25J 13/08 - Controls for manipulators by means of sensing devices, e.g. viewing or touching devices

Abstract

A semiconductor device includes a first transistor, a second transistor above the first transistor, and an isolation structure. The first transistor includes a first semiconductor channel layer, a first gate structure wrapping around the first semiconductor channel layer, and first source/drain epitaxy structures on opposite ends of the first semiconductor channel layer. The second transistor includes a second semiconductor channel layer, a second gate structure wrapping around the second semiconductor channel layer, and second source/drain epitaxy structures on opposite ends of the second semiconductor channel layer. The isolation structure electrically isolates the first gate structure from the second gate structure, wherein in a top view the isolation structure is adjacent to the second gate structure, and wherein in a first cross-sectional view, the isolation structure wraps around the first semiconductor channel layer.

IPC Classes  ?

• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 21/762 - Dielectric regions
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

Provided is acid-base controlled nano-bending lassos to manipulate photo-switching units in [1]rotaxanes, which contain sequentially bonded a macrocyclic moiety including a cyclic polyether moiety, a photochromic photo-switching moiety, a first station moiety including a secondary ammonium group, a linear moiety, a second station moiety being capable of forming multiple hydrogen bonding with the macrocyclic moiety, and an aggregation-induced emission stopper moiety. Under the base condition (in the loosened lasso form), the photochromic photo-switching moiety can perform a ring-closing reaction upon ultraviolet light exposure, and a ring-opening reaction can occur when exposed to visible light. However, the mentioned photo-switchable ring-closing and ring-opening reactions cannot proceed under the acidic condition (in the tightened lasso form). A linear moiety is bonded to the first station moiety and passes through the macrocyclic moiety. The photo-switching moiety and the stopper moiety are located on both sides of the macrocyclic moiety.

IPC Classes  ?

• C07D 409/14 - Heterocyclic compounds containing two or more hetero rings, at least one ring having sulfur atoms as the only ring hetero atoms containing three or more hetero rings
• A61K 9/107 - Emulsions
• A61K 41/00 - Medicinal preparations obtained by treating materials with wave energy or particle radiation

Abstract

A passive optofluidic device capable of making a microfluidic fluid flow downward to a test zone via an entrance at one side of a three-dimensional microfluidic structure, and then rise upward to a bridge passage by means of a capillary action provided by an uplink microfluidic passage on the other side of the three-dimensional microfluidic structure, and then flow downward to a waste holding tank through the bridge passage, thereby enabling the microfluidic fluid to flow through the test zone to undergo an optical detection without the need of electrical energy and an infusion pump.

IPC Classes  ?

• B01L 3/00 - Containers or dishes for laboratory use, e.g. laboratory glasswareDroppers

Abstract

A high-sensitivity hapten detection method capable of deriving a real time hapten concentration by using a SPR device, in which different concentrations of a hapten in a sample solution result in different reflected light intensities on the SPR device, and by mapping a reflected light intensity, via a lookup table, to a corresponding concentration, a detection result of the concentration of the hapten in the sample solution can be instantly provided.

IPC Classes  ?

• G01N 33/53 - ImmunoassayBiospecific binding assayMaterials therefor
• G01N 33/553 - Metal or metal coated

Abstract

Provided is a method for inhibiting vascular aging in a subject in need thereof by administering a pharmaceutical composition including a CCL4 antagonist. The CCL4 antagonist inhibits vascular aging by reducing a CCL4 level, inhibiting a binding activity of CCL4 with a receptor thereof, or a combination thereof.

IPC Classes  ?

• C07K 16/24 - Immunoglobulins, e.g. monoclonal or polyclonal antibodies against material from animals or humans against cytokines, lymphokines or interferons
• A61P 9/14 - VasoprotectivesAntihaemorrhoidalsDrugs for varicose therapyCapillary stabilisers

Abstract

Provided is a method for treating or preventing skin aging or skin inflammation in an individual in need thereof, which includes administering an effective amount of a pharmaceutical composition to the individual. The pharmaceutical composition includes a CCL4 antagonist and/or a pharmaceutically acceptable salt thereof and a pharmaceutically acceptable carrier thereof. Also provided is a method for increasing a content of collagen in an individual in need thereof, which includes administering an effective amount of a cosmetic composition to the individual.

IPC Classes  ?

• C07K 16/24 - Immunoglobulins, e.g. monoclonal or polyclonal antibodies against material from animals or humans against cytokines, lymphokines or interferons
• A61K 8/64 - ProteinsPeptidesDerivatives or degradation products thereof
• A61K 39/00 - Medicinal preparations containing antigens or antibodies
• A61P 17/02 - Drugs for dermatological disorders for treating wounds, ulcers, burns, scars, keloids, or the like
• A61P 29/00 - Non-central analgesic, antipyretic or antiinflammatory agents, e.g. antirheumatic agentsNon-steroidal antiinflammatory drugs [NSAID]
• A61Q 19/08 - Anti-ageing preparations

Abstract

A system for information security management over 5G open architecture infrastructures, in which a controlled 5G open architecture system connected to the 5G open architecture central management system and performs data transmission. A 5G virtualized infrastructure information security monitoring system, arranged in the 5G open architecture central management system, selects the 5G open architecture central management system, the controlled 5G open architecture system, an intelligent controller management platform, or the 5G virtualized infrastructure information security monitoring system as a scanning target for monitoring. The 5G virtualized infrastructure information security monitoring system includes multiple types of information security risk models and scans the scanning target based on the usage restrictions of one of the multiple types of information security risk models, thereby generating an information security risk result. The 5G virtualized infrastructure information security monitoring system provides an analytical recommendation based on the information security risk result.

IPC Classes  ?

• H04W 12/67 - Risk-dependent, e.g. selecting a security level depending on risk profiles
• H04L 41/16 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using machine learning or artificial intelligence
• H04W 24/08 - Testing using real traffic

Abstract

A method for the fabrication of p-type Ga2O3 by phosphorus ion implantation, wherein the method comprises: growing gallium oxide epilayer having a predetermined thickness on a substrate by controlling a growth temperature and a growth pressure; and implanting phosphorus ions on the gallium oxide epilayer by providing the phosphorus ion with a predetermined energy, wherein the phosphorus ions were implanted with a predetermined doses and with a predetermined incident angle.

IPC Classes  ?

• C30B 31/22 - Doping by irradiation with electromagnetic waves or by particle radiation by ion-implantation
• C30B 25/16 - Controlling or regulating
• C30B 29/16 - Oxides
• C30B 33/02 - Heat treatment

Abstract

A heat sink includes a thermally conductive base. The thermally conductive base has a first surface, a second surface, a guiding surface and an accommodating recess. The second surface faces away from the first surface. The guiding surface are connected to the first surface and the second surface. The guiding surface is not perpendicular to the first surface and the second surface. The accommodating recess is located at the first surface. The thermally conductive base has an inner bottom surface and an inner annular side surface which surround and form the accommodating recess. The inner annular side surface is connected to the inner bottom surface. The accommodating recess accommodates a heat source. The inner bottom surface is thermally coupled to the heat source.

IPC Classes  ?

• H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

Abstract

A sperm sorting device includes a foundation unit and a channel unit. The foundation unit includes a foundation wall, a surrounding wall extending from a periphery of the foundation wall, and a plurality of column portions. The channel unit has an inner bordering wall, a base plate surrounded by and connected to the inner bordering wall and having first and second surfaces, and a plurality of channel holes. The column portions of the foundation unit respectively extend through the channel holes. A distance between a summit surface of each of the column portions and the foundation wall is not smaller than a distance between the second surface and the foundation wall. Each of the channel holes has a selection space that is not occupied by the respective one of the column portions and that gradually reduces in size in a direction from the foundation wall to the base plate.

IPC Classes  ?

• G01N 15/149 - Optical investigation techniques, e.g. flow cytometry specially adapted for sorting particles, e.g. by their size or optical properties

Abstract

A dual gate high electron mobility transistor (HEMT) includes a substrate, a channel layer above the substrate, a source electrode, a drain electrode, a first gate electrode, and a second gate electrode. The source electrode and the drain electrode are respectively electrically coupled to the channel layer and are respectively above the channel layer. The first gate electrode and the second gate electrode are respectively electrically coupled to the channel layer and are respectively above the channel layer. The first gate electrode is located between the source electrode and the drain electrode. The second gate electrode is located between the source electrode and the first gate electrode. The second gate electrode is biased with a DC voltage.

IPC Classes  ?

• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device

Abstract

A transistor includes a field effect transistor, a surface modification layer, and a cell detection layer. The field effect transistor includes a source region, a drain region, a channel region, a gate dielectric layer, and a gate. The drain region is spaced apart from the source region in a first direction. The channel extends in the first direction and is disposed between the source region and the drain region. The gate dielectric layer is disposed below the channel region. The gate is disposed below the gate dielectric layer. The surface modification layer is disposed on the channel region. The cell detection layer is disposed on the surface modification layer and includes a plurality of antibodies, wherein the antibodies are configured to identify cell surface antigens, and the cell detection layer is configured to capture cells identified by the antibodies.

IPC Classes  ?

• G01N 27/414 - Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
• B01L 3/00 - Containers or dishes for laboratory use, e.g. laboratory glasswareDroppers
• G01N 33/68 - Chemical analysis of biological material, e.g. blood, urineTesting involving biospecific ligand binding methodsImmunological testing involving proteins, peptides or amino acids

Abstract

Provided are a composition and a method for preventing thrombogenesis. The composition includes a conjugate of heparin and a viral capsid protein, wherein the heparin is covalently bonded with the viral capsid protein.

IPC Classes  ?

• A61K 47/69 - Medicinal preparations characterised by the non-active ingredients used, e.g. carriers or inert additivesTargeting or modifying agents chemically bound to the active ingredient the non-active ingredient being chemically bound to the active ingredient, e.g. polymer-drug conjugates the conjugate being characterised by physical or galenical forms, e.g. emulsion, particle, inclusion complex, stent or kit
• A61K 47/64 - Drug-peptide, drug-protein or drug-polyamino acid conjugates, i.e. the modifying agent being a peptide, protein or polyamino acid which is covalently bonded or complexed to a therapeutically active agent
• A61P 7/02 - Antithrombotic agentsAnticoagulantsPlatelet aggregation inhibitors

Abstract

A device includes a first transistor, a second transistor, an interlayer dielectric (ILD) layer, and a backside gate rail. The first and second transistors are arranged along a first direction in a top view. The first transistor includes a first channel layer, a gate structure surrounding the first channel layer, a first source/drain epitaxial structure and a second source/drain epitaxial structure connected to the first channel layer. The second transistor includes a second channel layer, the gate structure surrounding the second channel layer, a third source/drain epitaxial structure and a fourth source/drain epitaxial structure connected to the second channel layer. A portion of the ILD layer is sandwiched between the first and third source/drain epitaxial structures. The backside gate rail is under the ILD layer and is electrically connected to the gate structure. The portion of the ILD layer is directly above the backside gate rail.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

The present inventive concept discloses a method of bonding two pieces of semiconductor materials, which comprises: providing the two pieces of semiconductor materials each having a surface that is suitable for molecular bonding; and activating at least one surface monolayer of one of the two pieces of semiconductor materials by irradiating neutral beam onto the surface(s) being activated while controlling activation parameters of the neutral beam to provide kinetic energy to the pieces sufficient to create an activated region of controlled thickness beneath the surface(s) being activated.

IPC Classes  ?

• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

Provided is a method for improving would healing, including administering an effective amount of a chemokine C-C motif ligand 7 (CCL7) antagonist to a subject in need thereof to inhibit CCL7 activity.

IPC Classes  ?

• C07K 16/24 - Immunoglobulins, e.g. monoclonal or polyclonal antibodies against material from animals or humans against cytokines, lymphokines or interferons
• A61K 31/713 - Double-stranded nucleic acids or oligonucleotides
• A61P 17/02 - Drugs for dermatological disorders for treating wounds, ulcers, burns, scars, keloids, or the like
• C12N 15/113 - Non-coding nucleic acids modulating the expression of genes, e.g. antisense oligonucleotides

Abstract

A method includes following steps. A first transistor is formed on a substrate. A first dielectric layer is formed over the first transistor. A first trench is formed in the first dielectric layer. An amorphous semiconductor layer is deposited in the first trench and over the first dielectric layer. The amorphous semiconductor layer is crystallized into a crystalline semiconductor layer. A second transistor is formed over the crystalline semiconductor layer.

IPC Classes  ?

• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

A method for manufacturing a high electron mobility transistor (HEMT), which comprises the following steps: providing a substrate, wherein a semiconductor layer is formed on the substrate, and a source electrode and a drain electrode are formed on the semiconductor layer; forming a passivation layer on the source electrode and the drain electrode; etching the passivation layer to form a through hole between the source electrode and the drain electrode, wherein a region of the semiconductor layer is exposed through the through hole; forming a photoresist layer on the passivation layer, wherein a first sub-region of the region of the semiconductor layer is covered by the photoresist layer, and a second sub-region of the region of the semiconductor layer is not covered by the photoresist layer; forming a metal layer on the second sub-region to form a gate electrode; and removing the passivation layer.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

Abstract

Provided are compositions and methods of use of a pharmaceutical composition in the manufacture of a medicament for preventing or treating a diabetic kidney disease, the pharmaceutical composition including a chemokine C-C motif ligand 7 (CCL7) antagonist and/or a pharmaceutically acceptable salt thereof and a pharmaceutically acceptable carrier. The medicament can prevent or treat diabetic kidney disease by protecting tubular epithelial cells, reducing glomerular hypertrophy, glomerulosclerosis, and fibrosis. The present disclosure also provides a method for preventing or treating a diabetic kidney disease in a subject in need thereof, including administering an effective amount of a CCL7 antagonist and/or a pharmaceutically acceptable salt thereof to the subject to inhibit an activity of CCL7.

IPC Classes  ?

• C12N 15/113 - Non-coding nucleic acids modulating the expression of genes, e.g. antisense oligonucleotides
• A61P 13/12 - Drugs for disorders of the urinary system of the kidneys
• C07K 16/24 - Immunoglobulins, e.g. monoclonal or polyclonal antibodies against material from animals or humans against cytokines, lymphokines or interferons
• C07K 16/28 - Immunoglobulins, e.g. monoclonal or polyclonal antibodies against material from animals or humans against receptors, cell surface antigens or cell surface determinants

Abstract

A device includes a substrate, a semiconductor layer and a ferroelectric layer. The semiconductor layer is over the substrate. The semiconductor layer is a single crystal silicon layer or a single crystal germanium layer. The ferroelectric layer is over the semiconductor layer. The ferroelectric layer is in physical contact with the semiconductor layer and has an orthorhombic phase.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/51 - Insulating materials associated therewith
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A nanomaterial composition for magnetic field-induced electrical stimulation of cells includes a piezoelectric nanoparticle and a magnetic nanodisc. The piezoelectric nanoparticle is conjugated to a first molecule of a specific binding molecule pair and is coated with a cell-binding molecule. The magnetic nanodisc is conjugated to a second molecule of the specific binding molecule pair and is attached to the piezoelectric nanoparticle through bonding of the second molecule and the first molecule. The magnetic nanodisc converts a magnetic energy into a mechanical energy in the presence of an external magnetic field, and the mechanical energy is then applied to the piezoelectric nanoparticle that is in contact with the cells via the cell-binding molecule, such that the piezoelectric nanoparticle converts the mechanical energy into an electrical energy, so as to electrically stimulate the cells. A method for magnetic field-induced electrical stimulation of cells in a subject is also provided.

IPC Classes  ?

• A61K 49/18 - Nuclear magnetic resonance [NMR] contrast preparationsMagnetic resonance imaging [MRI] contrast preparations characterised by a special physical form, e.g. emulsions, microcapsules, liposomes
• A61N 1/36 - Applying electric currents by contact electrodes alternating or intermittent currents for stimulation, e.g. heart pace-makers

Abstract

Provided is an insufflation needle assembly with remote visual functionality. The insufflation needle assembly includes a needle having an outer tubular sharp-ended cannula and an inner hollow blunt-ended cannula with a side opening near its blunt end, an optic fiber removably disposed in the inner hollow blunt-ended cannula, a driving mechanism coupled to the optic fiber and configured to rotate the optic fiber around its longitudinal axis, and an optical coherence tomography imaging system. Also provided is a method for insufflating a body cavity in a subject in need thereof by using the insufflation needle assembly for a visual-guided procedure to insufflate the body cavity.

IPC Classes  ?

• A61B 17/34 - TrocarsPuncturing needles
• A61B 1/015 - Control of fluid supply or evacuation
• A61B 1/05 - Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopesIlluminating arrangements therefor combined with photographic or television appliances characterised by the image sensor, e.g. camera, being in the distal end portion
• A61B 1/07 - Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopesIlluminating arrangements therefor with illuminating arrangements using light-conductive means, e.g. optical fibres
• A61B 10/04 - Endoscopic instruments, e.g. catheter-type instruments
• A61B 90/00 - Instruments, implements or accessories specially adapted for surgery or diagnosis and not covered by any of the groups , e.g. for luxation treatment or for protecting wound edges

Abstract

A power device threshold voltage measurement circuit and its operation method thereof are provided. The measurement circuit includes a switch component, a device under test, a common source capacitor and a decoupling capacitor. The switch component and the device under test forms a half bridge circuit and the common source capacitor is in series connected at the source of the device under test. The device under test is connected as a lower switch of the half bridge circuit and the decoupling capacitor is connected between the device under test and the common source capacitor. By applying an OFF-state stress mode and a measurement mode successively afterwards, a threshold voltage of the device under test is obtained. And the present invention is beneficial to achieving in shorter pulse width, faster measuring speed and inexpensive measuring equipment, and can thus be widely applied to group III-N based power devices.

IPC Classes  ?

• G01R 31/12 - Testing dielectric strength or breakdown voltage
• G01R 31/26 - Testing of individual semiconductor devices

Abstract

A method includes forming a first pull-up transistor and a first pass-gate transistor over a substrate at a first level height, the first pull-up and first pass-gate transistors being of a dual port static random access memory (SRAM) cell; forming a first pull-down transistor and a second pass-gate transistor of the dual port SRAM cell over the substrate at a second level height; forming a second pull-down transistor and a third pass-gate transistor of the dual port SRAM cell over the substrate at a third level height; forming a second pull-up transistor and a fourth pass-gate transistor of the dual port SRAM cell over the substrate at a fourth level height.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

The present invention is related to a use of prochlorperazine (PCP), or analog thereof for treating a cancer in a subject by influencing membrane proteins and receptors and inducing alterations in the expressions of the surface marker on cancer cells and their derived extracellular vesicles. The invention method offers a novel approach for the treatment and diagnosis of cancer and metastasis. Specific surface markers serve as a potential candidate for cancer-associated extracellular vesicles (EVs) and have applications in diagnosis, prognosis, and therapeutic targeting.

IPC Classes  ?

• G01N 33/574 - ImmunoassayBiospecific binding assayMaterials therefor for cancer
• A61K 31/4178 - 1,3-Diazoles not condensed and containing further heterocyclic rings, e.g. pilocarpine, nitrofurantoin

Abstract

A system for navigating a virtual environment using seated walking-in-place footstep locomotion includes a virtual reality device, a first sensing device, and a second sensing device. The first sensing device senses the first footstep locomotion of one of feet of a user seated in a physical environment to generate and transmit a first stepping signal to the virtual reality device. The second sensing device senses the second footstep locomotion of another of the feet of the user seated in the physical environment to generate and transmit a second stepping signal to the virtual reality device. The virtual reality device navigates the virtual environment in a virtual locomotion mode based on a combination of the first stepping signal and the second stepping signal.

IPC Classes  ?

• G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer

Abstract

An optical system includes a pancake lens assembly and a varifocal lens device. The varifocal lens device is coupled to the pancake lens assembly in a way that an optical axis of the varifocal lens device is in alignment with an optical axis of the pancake lens assembly, thereby permitting the optical system to have an adjustable focal length.

IPC Classes  ?

• G02F 1/1335 - Structural association of cells with optical devices, e.g. polarisers or reflectors
• G02B 3/14 - Fluid-filled or evacuated lenses of variable focal length
• G02F 1/13363 - Birefringent elements, e.g. for optical compensation

Abstract

The present invention is related to a use of prochlorperazine (PCP), or analog thereof for treating a cancer in a subject by influencing membrane proteins and receptors and inducing alterations in the expressions of the surface marker on cancer cells and their derived extracellular vesicles. The invention method offers a novel approach for the treatment and diagnosis of cancer and metastasis. Specific surface markers serve as a potential candidate for cancer-associated extracellular vesicles (EVs) and have applications in diagnosis, prognosis, and therapeutic targeting.

IPC Classes  ?

• A61K 31/517 - PyrimidinesHydrogenated pyrimidines, e.g. trimethoprim ortho- or peri-condensed with carbocyclic ring systems, e.g. quinazoline, perimidine
• A61K 31/519 - PyrimidinesHydrogenated pyrimidines, e.g. trimethoprim ortho- or peri-condensed with heterocyclic rings
• A61K 31/537 - Heterocyclic compounds having nitrogen as a ring hetero atom, e.g. guanethidine or rifamycins having six-membered rings with at least one nitrogen and at least one oxygen as the ring hetero atoms, e.g. 1,2-oxazines spiro-condensed or forming part of bridged ring systems
• A61P 35/00 - Antineoplastic agents
• A61P 35/04 - Antineoplastic agents specific for metastasis

Abstract

A blood physiological parameter sensing device includes a housing, a flow channel structure, a control unit and a sensing unit. The flow channel structure is disposed in the housing and forms a channel for a liquid to be measured to pass. The control unit is disposed in the housing. The sensing unit is disposed in the housing, is electrically connected to the control unit, and has a sensing end. The sensing end passes through the flow channel structure, is configured in the channel, and has an electrochemical sensing material. The electrochemical sensing material is used to exchange electrons with the blood physiological parameter in the liquid to be measured to produce redox reactions to generate current or voltage change parameters. The sensing unit transmits the current or voltage change parameters to the control unit, which obtains a blood physiological parameter concentration value to achieve instantaneous and continuous monitor the patients.

IPC Classes  ?

• A61B 5/1468 - Measuring characteristics of blood in vivo, e.g. gas concentration or pH-value using chemical or electrochemical methods, e.g. by polarographic means
• A61B 5/00 - Measuring for diagnostic purposes Identification of persons

Abstract

An early classification method with multiple-objectives optimization is provided. The method includes: dividing time series data into multiple snippets; input a snippet into a first machine learning model to obtain a spatial feature vector; calculating, by a recurrent neural network, a current spatiotemporal feature vector according to the spatial feature vector and a previous spatiotemporal feature vector; determining whether to perform early classification according to the spatiotemporal feature vector; if determined not to perform the early classification, processing a subsequent snippet; if determined to perform the early classification, input the spatiotemporal feature vector into a second machine learning model to calculate a predicted label of the time series data. Accordingly, multiple-objectives optimization is achieved.

IPC Classes  ?

• G06N 3/08 - Learning methods

Abstract

A method includes forming a first conductive feature over a first semiconductor structure; forming a first dielectric layer over the first conductive feature and the first semiconductor structure; removing a portion of the first dielectric layer to expose a top surface of the first conductive feature; forming a second conductive feature over a second semiconductor structure, wherein the first and second conductive features comprise nanotwinned copper; forming a second dielectric layer over the second conductive feature and the second semiconductor structure, wherein the second dielectric layer comprises a same material as the first dielectric layer; removing a portion of the second dielectric layer to expose a top surface of the second conductive feature; and performing a hybrid bonding process to bond the first dielectric layer to the second dielectric layer and bond the first conductive feature to the second conductive feature.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A fused ring acceptor material includes a structure of following formula (I). A fused ring acceptor material includes a structure of following formula (I). A fused ring acceptor material includes a structure of following formula (I). formula (I), where R1 is a C1-C24 alkyl, a phenyl, a phenyl derivative, a furyl, a furyl derivative, a thienyl, a thienyl derivative, a selenophene or a selenophene derivative; B is A fused ring acceptor material includes a structure of following formula (I). formula (I), where R1 is a C1-C24 alkyl, a phenyl, a phenyl derivative, a furyl, a furyl derivative, a thienyl, a thienyl derivative, a selenophene or a selenophene derivative; B is A fused ring acceptor material includes a structure of following formula (I). formula (I), where R1 is a C1-C24 alkyl, a phenyl, a phenyl derivative, a furyl, a furyl derivative, a thienyl, a thienyl derivative, a selenophene or a selenophene derivative; B is R2 is a C1-C24 alkyl, a phenyl, a phenyl derivative, a thienyl or a thienyl derivative; D is A fused ring acceptor material includes a structure of following formula (I). formula (I), where R1 is a C1-C24 alkyl, a phenyl, a phenyl derivative, a furyl, a furyl derivative, a thienyl, a thienyl derivative, a selenophene or a selenophene derivative; B is R2 is a C1-C24 alkyl, a phenyl, a phenyl derivative, a thienyl or a thienyl derivative; D is A fused ring acceptor material includes a structure of following formula (I). formula (I), where R1 is a C1-C24 alkyl, a phenyl, a phenyl derivative, a furyl, a furyl derivative, a thienyl, a thienyl derivative, a selenophene or a selenophene derivative; B is R2 is a C1-C24 alkyl, a phenyl, a phenyl derivative, a thienyl or a thienyl derivative; D is R3 is a hydrogen atom, a halogen, a C1-C24 alkyl or a C1-C24 alkoxy; and A1 is A fused ring acceptor material includes a structure of following formula (I). formula (I), where R1 is a C1-C24 alkyl, a phenyl, a phenyl derivative, a furyl, a furyl derivative, a thienyl, a thienyl derivative, a selenophene or a selenophene derivative; B is R2 is a C1-C24 alkyl, a phenyl, a phenyl derivative, a thienyl or a thienyl derivative; D is R3 is a hydrogen atom, a halogen, a C1-C24 alkyl or a C1-C24 alkoxy; and A1 is

IPC Classes  ?

• H10K 85/60 - Organic compounds having low molecular weight
• C07D 495/22 - Heterocyclic compounds containing in the condensed system at least one hetero ring having sulfur atoms as the only ring hetero atoms in which the condensed system contains four or more hetero rings
• H10K 30/20 - Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising organic-organic junctions, e.g. donor-acceptor junctions

Abstract

Provided is a method for preventing or treating a peripheral arterial disease (PAD) in a subject in need thereof, including administering an effective amount of a chemokine C-C motif ligand 7 (CCL7) antagonist to the subject to inhibit CCL7 activity.

IPC Classes  ?

• C07K 16/24 - Immunoglobulins, e.g. monoclonal or polyclonal antibodies against material from animals or humans against cytokines, lymphokines or interferons
• A61K 9/00 - Medicinal preparations characterised by special physical form
• A61P 9/10 - Drugs for disorders of the cardiovascular system for treating ischaemic or atherosclerotic diseases, e.g. antianginal drugs, coronary vasodilators, drugs for myocardial infarction, retinopathy, cerebrovascula insufficiency, renal arteriosclerosis

Abstract

A device includes a carbon nanotube having a channel region and dopant-free source/drain regions at opposite sides of the channel region, a first metal oxide layer interfacing a first one of the dopant-free source/drain regions of the carbon nanotube, a second metal oxide layer interfacing a second one of the dopant-free source/drain regions of the carbon nanotube and a gate structure over the channel region of the carbon nanotube, and laterally between the first metal oxide layer and the second metal oxide layer.

IPC Classes  ?

• H10K 10/84 - Ohmic electrodes, e.g. source or drain electrodes
• H10K 10/46 - Field-effect transistors, e.g. organic thin-film transistors [OTFT]

Abstract

The present invention is related to a method and pharmaceutical composition for treating a cartilage damage in a subject (including a human or an animal), particularly osteoarthritis (OA), using extracellular vesicles (EVs) with SOX9 gene, called as “EV-SOX9”. The EV-SOX9 is obtained by encapsulating the SOX9 mRNA or the mRNA of its upstream and downstream gene in EVs, naïve EVs with high expression level of SOX9 mRNA or its upstream and downstream gene from different cell sources, or MSC-derived EV-SOX9, which is obtained by transferring the SOX9 gene or its upstream and downstream gene into a multipotent cell and collecting EVs.

IPC Classes  ?

• A61K 48/00 - Medicinal preparations containing genetic material which is inserted into cells of the living body to treat genetic diseasesGene therapy
• A61K 9/00 - Medicinal preparations characterised by special physical form
• A61K 9/50 - Microcapsules
• A61K 38/39 - Connective tissue peptides, e.g. collagen, elastin, laminin, fibronectin, vitronectin, cold insoluble globulin [CIG]
• A61K 45/06 - Mixtures of active ingredients without chemical characterisation, e.g. antiphlogistics and cardiaca
• A61P 19/02 - Drugs for skeletal disorders for joint disorders, e.g. arthritis, arthrosis
• C12N 15/88 - Introduction of foreign genetic material using processes not otherwise provided for, e.g. co-transformation using microencapsulation, e.g. using liposome vesicle

Abstract

A method includes following steps. A dielectric layer is formed over a substrate. A transition metal-containing layer is deposited on the dielectric layer. The transition metal-containing layer is patterned into a plurality of transition metal-containing pieces. The transition metal-containing pieces are sulfurized or selenized to form a plurality of semiconductor seeds. Semiconductor films are grown from semiconductor seeds. Transistors are formed on the semiconductor films.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/8234 - MIS technology
• H01L 23/528 - Layout of the interconnection structure
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Abstract

A method includes forming a first conductive feature and a second conductive feature over a first substrate, wherein the first and second conductive features comprise nano-twinned copper; and depositing a first metal cap layer over the first conductive feature and a second metal cap layer over the second conductive feature, wherein the first metal cap layer is spaced apart from the second metal cap layer in a cross-sectional view.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An integrated circuit structure includes a substrate, a bottom nanostructure transistor, and a top nanostructure transistor. The bottom nanostructure transistor is over the substrate and includes a first channel layer, a first gate structure, and first source/drain epitaxial structures. The first gate structure wraps around the first channel layer. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The top nanostructure transistor is over the bottom nanostructure transistor and includes a second channel layer, a second gate structure, and second source/drain epitaxial structures. The second channel layer is over the first channel layer. The second gate structure wraps around the second channel layer. A bottom surface of the second gate structure is substantially coplanar with a bottom surface of the first gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

Various embodiments include stacked transistors and methods of forming stacked transistors. In an embodiment, a device includes: a first nanostructure; a second nanostructure above the first nanostructure; a first gate structure extending along a top surface and a bottom surface of the first nanostructure; and a second gate structure extending along a top surface and a bottom surface of the second nanostructure. The first gate structure is disposed at a first side of the first nanostructure and a first side of the second nanostructure. The second gate structure is disposed at a second side of the first nanostructure and a second side of the second nanostructure. The second side of the first nanostructure is opposite the first side of the first nanostructure. The second side of the second nanostructure opposite the first side of the second nanostructure.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 21/8234 - MIS technology
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A method includes following steps. A single-crystalline two-dimensional (2D) semiconductor layer is formed over a substrate. A single-crystalline 2D material layer is epitaxially grown on the single-crystalline 2D semiconductor layer. The single-crystalline 2D material layer is lattice-matched with the single-crystalline 2D semiconductor layer. A semiconductor device is over the single-crystalline 2D semiconductor layer.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• C30B 25/18 - Epitaxial-layer growth characterised by the substrate
• C30B 29/40 - AIIIBV compounds
• H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes

Abstract

An expanded spinal fusion cage is provided and includes: an outer frame; a sliding block set with a middle sliding block located within the outer frame, and the middle sliding block is located between two outer sliding blocks; a screw rod penetrating through and combined with the outer frame, and the screw rod is screwed with the middle sliding block, so that the middle sliding block is moved in translation in the outer frame and simultaneously expands the two outer sliding blocks by rotating the screw rod; two curved surface elements located outside the outer frame and combined with the two outer sliding blocks respectively, each of the curved surface elements has a wing plate; and two vertebral arch screws penetrating through and combined with the two wing plates.

IPC Classes  ?

• A61F 2/44 - Joints for the spine, e.g. vertebrae, spinal discs
• A61F 2/30 - Joints

Abstract

An IC structure includes a first transistor, an interconnect structure, a dielectric layer, a polysilicon fin, and a second transistor. The first transistor is over a substrate. The interconnect structure is over the first transistor. The dielectric layer is over the interconnect structure. The polysilicon fin includes a first portion laterally extending over the dielectric layer, and a second portion extending through the dielectric layer to a metal material within the interconnect structure. The second transistor is formed on the first portion of the polysilicon fin.

IPC Classes  ?

• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
• H01L 21/8234 - MIS technology
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

An epitaxial structure includes a substrate and a dielectric layer. The dielectric layer is on the substrate. The substrate comprises a single crystal metal or a single crystal 2D material. The dielectric layer is in physical contact with the substrate. The dielectric layer comprises a non-perovskite structure with defined grain orientation with ferroelectric (FE) phase or antiferroelectric (AFE) phase.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/51 - Insulating materials associated therewith

Abstract

The present disclosure in various embodiments provides a method. In some embodiments of the present disclosure, the method includes forming a transition metal dichalcogenide layer on a substrate; and performing an ion bombardment process on the transition metal dichalcogenide layer, performing an annealing process on the transition metal dichalcogenide layer.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The present disclosure provides a container network communication method, which includes steps as follows. An encapsulation based on a tunneling protocol is performed on a first packet with a destination network address indicating a second pod by a first tunnel endpoint of a first SDN switch, so as to obtain a first tunnel packet; the first tunnel packet is sent from the first SDN switch to the second SDN switch, and then performing a decapsulation based on the tunneling protocol on the first tunnel packet by a second tunnel endpoint of the second SDN switch, so that the second pod obtains a data of the first packet.

IPC Classes  ?

• H04L 45/76 - Routing in software-defined topologies, e.g. routing between virtual machines
• H04L 12/46 - Interconnection of networks

Abstract

A method for path planning of a robot arm in a dynamic environment includes steps as follows. During an operation of the robot arm in a three-dimensional environment, a state of an obstacle is obtained in real time, and when a collision danger occurs, the robot arm is allowed to dodge the obstacle. In the collision danger, a partial path of the robot arm is re-planned based on a hybrid RRT, so that the robot arm avoids dynamic and static obstacles in an environment and then returns to an original path for continuing operation.

IPC Classes  ?

• B25J 9/16 - Programme controls

Abstract

A robot and method for autonomously moving and grasping objects are provided. The robot includes a robotic arm for grasping a target object; a mobile platform for moving the robotic arm to the target object's location; a semantic navigation system for navigating the mobile platform to the target object's location; a first camera for shooting the external environment during navigation; a second camera for obtaining relative images of the environment for the robotic arm; an object recognition and pose estimation system for performing semantic segmentation and pose estimation of the target object; an automatic docking coordination controller for obtaining the best mobile grasping path and pose for the robotic arm and the mobile platform; a mobile grasping controller for controlling the movement of the robotic arm through the object recognition and pose estimation system; and a mobile platform controller for controlling the motion of the robot.

IPC Classes  ?

• B25J 9/16 - Programme controls

Abstract

In an automated detection system for acute ischemic stroke, a preprocessor performs registration on a whole-brain image and a standard-brain spatial template to extract individual brain region masks from the whole-brain image. A deep learning encoder performs feature extraction on the whole-brain image and the individual brain region masks, thereby converting the whole-brain image into 2D whole-brain slice images. A first processor maps the individual brain masks onto the whole-brain slice images for registration, thereby generating sets of brain region slice images. A second processor computes the stroke-related weight values of the slice images of each of the sets of brain region slice images and sums the weight values to obtain the characteristic value of each brain region. A disparity-aware classifier determines whether any brain region has acute ischemic stroke according to the characteristic value of each brain region.

IPC Classes  ?

• G06T 7/00 - Image analysis
• G06T 7/11 - Region-based segmentation
• G06T 7/174 - SegmentationEdge detection involving the use of two or more images
• G06V 10/24 - Aligning, centring, orientation detection or correction of the image
• G06V 10/42 - Global feature extraction by analysis of the whole pattern, e.g. using frequency domain transformations or autocorrelation
• G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
• G16H 30/40 - ICT specially adapted for the handling or processing of medical images for processing medical images, e.g. editing
• G16H 50/20 - ICT specially adapted for medical diagnosis, medical simulation or medical data miningICT specially adapted for detecting, monitoring or modelling epidemics or pandemics for computer-aided diagnosis, e.g. based on medical expert systems

Abstract

The invention provides a system for detecting obstacle state and an operating method thereof, comprising an image capturing module, a semantic segmentation module, a feature extraction module, an object detection module, and a distance table calibration module. The invention is delivered a semantic segmentation information to a model for processing self-learning, and selected an output of an original image size, for a carrier of an attention mechanism.

IPC Classes  ?

• G06V 20/58 - Recognition of moving objects or obstacles, e.g. vehicles or pedestriansRecognition of traffic objects, e.g. traffic signs, traffic lights or roads
• G06T 7/50 - Depth or shape recovery
• G06V 10/26 - Segmentation of patterns in the image fieldCutting or merging of image elements to establish the pattern region, e.g. clustering-based techniquesDetection of occlusion
• G06V 10/40 - Extraction of image or video features
• G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
• G06V 10/77 - Processing image or video features in feature spacesArrangements for image or video recognition or understanding using pattern recognition or machine learning using data integration or data reduction, e.g. principal component analysis [PCA] or independent component analysis [ICA] or self-organising maps [SOM]Blind source separation
• G06V 10/774 - Generating sets of training patternsBootstrap methods, e.g. bagging or boosting

Abstract

The present disclosure relates to a device structure for sensing infrared light. The device structure includes a substrate, a first metal electrode, a second metal electrode, and a semiconductor layer. The first metal electrode and the second metal electrode are located on the substrate. The semiconductor layer is located on the substrate, in which the semiconductor layer is located between the first metal electrode and the second metal electrode and above the first metal electrode and the second metal electrode. The semiconductor layer directly contacts the first metal electrode and the second metal electrode.

IPC Classes  ?

• H01L 31/101 - Devices sensitive to infrared, visible or ultraviolet radiation
• H01L 31/0224 - Electrodes

Abstract

A system of generating data from diffusion-weighted images for pre-processing and a method thereof are disclosed. In the system, a processing parameter set including diffusion information is acquired; after a raw diffusion-weighted image including data images and image information is acquired, the image information is interpreted to set image processing data of the raw diffusion-weighted image, and non-deformation correction and deformation correction are performed on the raw diffusion-weighted image to generate a pre-processed diffusion-weighted image based on the processing parameter set and the image processing data. Therefore, the image processing data can be automatically set based on the raw diffusion-weighted image, to achieve the effect of lowering difficulty for analyzing DWI and saving setup time of image processing data.

IPC Classes  ?

• G06T 11/00 - 2D [Two Dimensional] image generation
• G06T 5/00 - Image enhancement or restoration
• G06T 7/00 - Image analysis
• G06T 7/30 - Determination of transform parameters for the alignment of images, i.e. image registration

Abstract

This disclosure provides method of manufacturing pharmaceutical composition for treating cancer, which provides great cell yield via not performing negative selection on CD3−CD19−CD14−. By administration of the pharmaceutical composition, cancer cells in a subject may be effectively inhibited via cell-mediated immunity.

IPC Classes  ?

• C12N 5/0783 - T cellsNK cellsProgenitors of T or NK cells
• A61P 35/00 - Antineoplastic agents

Abstract

A differential channel circuit structure is disclosed. The differential channel circuit structure comprises a first differential circuit including a differential channel and a termination circuit. The differential channel has a differential mode impedance and a common mode impedance, and includes a first end and a second end, each capable of processing at least a first differential signal and a first common mode signal. The termination circuit includes a third end and a fourth end connected to the first end and the second end of the differential channel respectively, so as to simultaneously match the differential mode impedance and the common mode impedance of the differential channel.

IPC Classes  ?

• H04L 25/02 - Baseband systems Details

Abstract

Multifunctional nanoparticles incorporate an ERS inducer (p97 inhibitors) and immunotherapeutics (immune-modulating miR or aptamer plus immunoadjuvants) to address the poor aqueous solubility and toxicity associated with p97 inhibitors and immunotherapeutics while also enhancing the immune activation of these therapeutics. The nanoformulation offers several advantages, such as pH-sensitivity, self-detachable coating, active targeting, and intracellular localization in tumors, and has the potential to overcome the limitations of systemic administration, such as the degradation of nucleic acid therapeutics and toxicities associated with ERS inducer.

IPC Classes  ?

• A61K 47/69 - Medicinal preparations characterised by the non-active ingredients used, e.g. carriers or inert additivesTargeting or modifying agents chemically bound to the active ingredient the non-active ingredient being chemically bound to the active ingredient, e.g. polymer-drug conjugates the conjugate being characterised by physical or galenical forms, e.g. emulsion, particle, inclusion complex, stent or kit
• A61K 45/06 - Mixtures of active ingredients without chemical characterisation, e.g. antiphlogistics and cardiaca
• A61K 47/54 - Medicinal preparations characterised by the non-active ingredients used, e.g. carriers or inert additivesTargeting or modifying agents chemically bound to the active ingredient the non-active ingredient being chemically bound to the active ingredient, e.g. polymer-drug conjugates the non-active ingredient being a modifying agent the modifying agent being an organic compound
• A61K 47/66 - Medicinal preparations characterised by the non-active ingredients used, e.g. carriers or inert additivesTargeting or modifying agents chemically bound to the active ingredient the non-active ingredient being chemically bound to the active ingredient, e.g. polymer-drug conjugates the non-active ingredient being a modifying agent the modifying agent being a protein, peptide or polyamino acid the modifying agent being a pre-targeting system involving a peptide or protein for targeting specific cells
• A61P 35/00 - Antineoplastic agents

Abstract

The path planning system projects a plurality of path distance point clouds to a path image to generate a path and distance point composition image, and then input the path and distance point composition image to a deep learning model and a probabilistic graphical model to obtain a path segmentation image. The path planning system obtains an adjacent lane point cloud and a main lane point cloud. The path planning system clusters the adjacent lane point cloud and the main lane point cloud, calculates an adjacent lane cluster center and a main lane cluster center, and transforms a LIDAR coordinates of the adjacent lane cluster center and the main lane cluster center to a car coordinate. The path planning system obtains a changing path and a main path by smoothing the car coordinate, and selects the changing path or the main path as a driving path according to obstacle information.

IPC Classes  ?

• B60W 60/00 - Drive control systems specially adapted for autonomous road vehicles
• B60W 30/08 - Predicting or avoiding probable or impending collision
• B60W 30/12 - Lane keeping
• B60W 30/18 - Propelling the vehicle
• B60W 40/06 - Road conditions
• G01S 17/86 - Combinations of lidar systems with systems other than lidar, radar or sonar, e.g. with direction finders
• G01S 17/89 - Lidar systems, specially adapted for specific applications for mapping or imaging
• G01S 17/931 - Lidar systems, specially adapted for specific applications for anti-collision purposes of land vehicles
• G06V 10/762 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using clustering, e.g. of similar faces in social networks
• G06V 10/84 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using probabilistic graphical models from image or video features, e.g. Markov models or Bayesian networks
• G06V 20/56 - Context or environment of the image exterior to a vehicle by using sensors mounted on the vehicle
• G06V 20/58 - Recognition of moving objects or obstacles, e.g. vehicles or pedestriansRecognition of traffic objects, e.g. traffic signs, traffic lights or roads

Abstract

A method includes forming a sacrificial multi-layer stack including first, second, and third sacrificial layers stacked in a vertical direction on a substrate; removing the first sacrificial layer to form a first space; depositing a first dielectric layer and a first electrode material in the first space; removing the second sacrificial layer to form a second space; depositing a second dielectric layer and a second electrode material in the second space; removing the third sacrificial layer to form a third space; depositing a third dielectric layer and a third electrode material in the third space.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A prediction model training method comprises following steps. A plurality of valid electrocardiograms is filtered from a plurality of electrocardiograms according to an elimination rule. A plurality of training features corresponding to the valid electrocardiograms is generated according to a training category set. A prediction model is trained according to the valid electrocardiograms, the training features, and a plurality of episode data corresponding to the valid electrocardiograms. The prediction model is configured to predict whether the atrial high rate episode state will last more than a time threshold according to an untested electrocardiogram in the atrial high rate episode state.

IPC Classes  ?

• G06N 5/022 - Knowledge engineeringKnowledge acquisition

Abstract

A prediction model training method includes the following steps. A first model is trained according to first electrocardiograms, wherein the first model includes a feature extraction layer, and the feature extraction layer is configured to extract features corresponding to an electrocardiogram. First feature information corresponding to second electrocardiograms is extracted according to the second electrocardiograms and the feature extraction layer of the first model. A second model is trained according to the first feature information, gender information corresponding to the second electrocardiograms, and age information corresponding to the second electrocardiograms.

IPC Classes  ?

• G16H 50/30 - ICT specially adapted for medical diagnosis, medical simulation or medical data miningICT specially adapted for detecting, monitoring or modelling epidemics or pandemics for calculating health indicesICT specially adapted for medical diagnosis, medical simulation or medical data miningICT specially adapted for detecting, monitoring or modelling epidemics or pandemics for individual health risk assessment
• A61B 5/35 - Detecting specific parameters of the electrocardiograph cycle by template matching
• G06N 20/00 - Machine learning

Abstract

An electrical connection includes a first driving substrate, a first adhesive layer, a first bonding pad a first bonding pad and a second bonding pad. The first driving substrate includes a first substrate and a first dielectric layer on the first substrate. The first adhesive layer is at a sidewall of the first dielectric layer of the first driving substrate. The first bonding pad is on the first substrate of the first driving substrate and in contact with the first adhesive layer, and the first bonding pad includes a plurality of grains, the grains are connected with each other, the grains include [111]-oriented copper grains, and a maximum width of the first bonding pad is equal to or less than 8 microns. The second bonding pad is on the first bonding pad.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A high electron mobility transistor includes a growth substrate, a lattice matching layer, an back-barrier layer, an electron blocking layer, a channel layer, an active layer, a source, a gate, and a drain. The lattice matching layer and the back-barrier layer are formed on the growth substrate. The back-barrier layer includes GaN doped with C. The electron blocking layer is formed on the back-barrier layer. The electron blocking layer includes AlGaN, wherein the doping percent of Al atoms of the AlGaN is 3˜5% and the doping percent of Ga atoms of the AlGaN is 95˜97%. The electron blocking layer has a thickness of 2˜5 nm. The channel layer and the active layer are formed on the electron blocking layer. The source, the gate, and the drain are formed on the active layer.

IPC Classes  ?

• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
• H01L 29/15 - Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

Abstract

A high electron mobility transistor and a method for fabricating the same is disclosed. Firstly, a lattice matching layer, a channel layer, and an AlGaN layer are sequentially formed on a growth substrate. The AlGaN layer includes a first area, a second area, and a third area, wherein the second area is located between the first area and the third area. Then, an insulation block is formed on the second area of the AlGaN layer and two GaN blocks are respectively formed on the first area and the third area of the AlGaN layer. Two InAlGaN blocks are respectively formed on the GaN blocks and the insulation block is removed. Finally, a gate is formed to interfere the second area of the AlGaN layer and a source and a drain are respectively formed on the InAlGaN blocks.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

Abstract

A method for manufacturing a transparent thin film transistor-based photosensitive device includes preparing a semiconductor substrate unit including a gate electrode layer, forming a gate insulator layer by depositing a high dielectric constant material using plasma-assisted atomic layer deposition to cover the gate electrode layer, forming a sensing channel layer made of an indium oxide-based material on the gate insulator layer in a position corresponding to the gate electrode layer by sputtering and doping nitrogen into the sensing channel layer, and forming a source electrode and a drain electrode on two opposite end portions of the sensing channel layer, respectively.

IPC Classes  ?

• H01L 31/113 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect photo- transistor being of the conductor-insulator- semiconductor type, e.g. metal- insulator-semiconductor field-effect transistor
• H01L 31/032 - Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups
• H01L 31/20 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor material

Abstract

A nano-twinned copper foil is provided, which comprises: plural twinned grains, wherein at least part of the plural twinned grains are formed by stacking plural nano-twins along a [111] crystal axis. The nano-twinned copper foil has a first surface and a second surface opposite to the first surface, and 80% or more of areas of the first surface and the second surface respectively exposes (111) planes of the nano-twins. In addition, the present invention further provides a method for manufacturing the aforesaid nano-twinned copper foil, an electronic element comprising the same, and a method for manufacturing the electronic element.

IPC Classes  ?

• C25D 1/04 - WiresStripsFoils
• C25D 3/38 - ElectroplatingBaths therefor from solutions of copper
• C25D 7/06 - WiresStripsFoils

Abstract

An image sensor chip with depth information is provided. The image sensor chip includes an SPAD array, a time-to-digital converter module, a storage circuit, and a data processing circuit. The SPAD array includes a plurality of image sensor units, and each of the image sensor units includes a plurality of SPAD units and a decision circuit, wherein each of the SPAD units outputs a photon detection result within a scan period, and the decision circuit generates an image-sensing signal based on the photon detection results. The time-to-digital converter module generates a plurality of first time data in response to the image-sensing signals. The storage circuit stores the first time data temporarily. The data processing unit reads the first time data from the storage circuit and generates a plurality of second time data in response to the first time data.

IPC Classes  ?

• H04N 25/773 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]
• G04F 10/00 - Apparatus for measuring unknown time intervals by electric means
• H04N 25/779 - Circuitry for scanning or addressing the pixel array

Abstract

Provided is a method for preventing and treating brain tumor, especially refractory brain tumor, glioblastoma multiforme (GBM), or refractory GBM in a subject in need thereof, including administering to the subject with an effective amount of an immunomodulatory protein of Ganoderma, a recombinant thereof, or a fungal immunomodulatory protein of a similar structure.

IPC Classes  ?

• A61K 38/16 - Peptides having more than 20 amino acidsGastrinsSomatostatinsMelanotropinsDerivatives thereof
• A61K 31/495 - Heterocyclic compounds having nitrogen as a ring hetero atom, e.g. guanethidine or rifamycins having six-membered rings with two nitrogen atoms as the only ring hetero atoms, e.g. piperazine
• A61K 36/074 - Ganoderma
• A61K 38/08 - Peptides having 5 to 11 amino acids
• A61P 25/00 - Drugs for disorders of the nervous system
• A61P 35/00 - Antineoplastic agents

Abstract

The present disclosure relates to an electrical signal sensing composition. The electrical signal sensing composition includes an oxidoreductase and an amphiphilic molecule. The amphiphilic molecule includes alkyl sulfuric acid, alkyl sulfate, alkyl sulfonic acid, alkyl sulfonate, alkyl ammonium, alkyl ammonium salt, alkyl phosphoric acid, alkyl phosphate, alkyl carboxylic acid, alkyl carboxylate, alkylboronic acid, alkylborate, or combinations thereof.

IPC Classes  ?

• G01N 27/327 - Biochemical electrodes

Abstract

A method for inhibiting the metastasis of triple-negative breast cancer, which includes administering to a subject in need thereof a pharmaceutical composition containing rosoxacin or a pharmaceutically acceptable salt thereof.

IPC Classes  ?

• A61K 31/4709 - Non-condensed quinolines containing further heterocyclic rings
• A61P 35/04 - Antineoplastic agents specific for metastasis

Abstract

A MOCVD method for growing an InAlGaN/GaN heterostructure comprises steps: sequentially growing a nitride nucleation layer, a GaN buffer layer, an InAlGaN barrier layer on a substrate; using a precursor gas containing silane to in-situ grow a SiNx protective layer on the InAlGaN barrier layer at a temperature of 950-1000° C. in the same reaction chamber. Thereby is achieved a SiNx/InAlGaN/GaN heterostructure having an ultrathin barrier layer, which is suitable to fabricate HEMT elements. The present invention needn't take sample out of the reaction chamber and thus can prevent the heterostructure from oxidation and damage.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

Provided is a non-natural polypeptide including a fragment of major histocompatibility complex class I (MHC I). Also provided are a method for inhibiting combination between SARS-COV-2 and a cell of a subject and a method for preventing or treating SARS-COV-2 infection in a subject in need thereof, including contacting the cell or administering to the subject with the non-natural polypeptide.

IPC Classes  ?

• C07K 14/74 - Major histocompatibility complex [MHC]

Abstract

The system includes: an ultrasound imaging probe located in the center of the ultrasound probe device; an ultrasound stimulation probe located around the center of the ultrasound probe device, and two independent piezoelectric elements with a slight frequency difference can focused ultrasound and applied to the same target area, and fixed on a specific position of the abdomen with a touch fastener to generate an acoustic field that changes the intensity of the acoustic field with time: Stimulate the area of the inflammatory bowel in the abdomen through this acoustic field: to suppress the inflammatory bowel disease and the brain inflammation through the gut-brain axis.

IPC Classes  ?

• A61B 90/00 - Instruments, implements or accessories specially adapted for surgery or diagnosis and not covered by any of the groups , e.g. for luxation treatment or for protecting wound edges
• A61N 7/00 - Ultrasound therapy

Abstract

An early assistive diagnosis system of ADHD provides a test to the subject and uses a brain-computer interface (BCI) to detect the electroencephalography (EEG) signals of subject. A host receives the EEG signals, captures the features associated with ADHD heterogeneities, obtains feature EEG signals, and classifies the subject as typical development or ADHD, then uses the EEG feature signals to train a predicted index score range for the heterogeneities of ADHD. The test scores of a new subject is tested, it is compared whether the scores fall within the predicted index score range to determine the ADHD heterogeneity types to which the new subject belongs. Thus, the present invention uses attention tests for ADHD in combination with EEG signals to assess symptoms of a subject, further predicts the potential aptitude of a subject for ADHD and provides objective assistive diagnosis to physicians.

IPC Classes  ?

• A61B 5/16 - Devices for psychotechnicsTesting reaction times
• A61B 5/00 - Measuring for diagnostic purposes Identification of persons
• A61B 5/291 - Bioelectric electrodes therefor specially adapted for particular uses for electroencephalography [EEG]
• A61B 5/372 - Analysis of electroencephalograms
• A61B 5/378 - Visual stimuli
• A61B 5/38 - Acoustic or auditory stimuli

Abstract

A GaN transistor is provided, which comprises: a substrate; a GaN layer disposed on the substrate; a barrier layer disposed on the GaN layer; a source electrode disposed on the barrier layer; a drain electrode disposed on the barrier layer; a composite dielectric layer disposed on the barrier layer and comprising a first seed layer and a La-doped HZO layer, wherein the first seed layer comprises ZrO2; and a gate electrode disposed on the composite dielectric layer.

IPC Classes  ?

• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/51 - Insulating materials associated therewith
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

An electrically tunable liquid crystal lens includes a carrier substrate, a common electrode layer disposed on the carrier substrate, a liquid crystal unit, a patterned electrode layer, a terminal electrode layer, a dielectric insulating layer, and a cover. The liquid crystal unit is disposed on the common electrode layer opposite to the carrier substrate, and includes a plurality of liquid crystal molecules. The patterned electrode layer is disposed on the liquid crystal unit opposite to the common electrode layer, and has a plurality of aperture patterns located within a projection of the liquid crystal unit on the patterned electrode layer. The terminal electrode layer is disposed on the patterned electrode layer opposite to the liquid crystal unit. The dielectric insulating layer is disposed between the patterned electrode layer and the terminal electrode layer. The cover is disposed on the terminal electrode layer opposite to the dielectric insulating layer.

IPC Classes  ?

• G02F 1/29 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the position or the direction of light beams, i.e. deflection

Abstract

A multi-bit analog multiplication and accumulation circuit system, which includes: a plurality of analog multiplication circuits, first to fourth accumulation lines, and a binary place value combiner. Each of the analog multiplication circuits performs multiplications on four-bit input data and four-bit weight data, wherein each of the analog multiplication circuits includes four capacitor and switch arrays for performing multiplications on one bit of the four-bit input data and the four-bit weight data. Each of the accumulation lines outputs an accumulation of multiplications performed by each capacitor switch array of each analog multiplication circuit on one bit of the four-bit input data and the four-bit weight data. The binary place value combiner sums up the accumulated result outputted from the accumulation line with corresponding binary place value.

IPC Classes  ?

• G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
• G06F 7/50 - AddingSubtracting
• G06F 7/523 - Multiplying only
• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Abstract

Ganoderma, a recombinant thereof, or a fungal immunomodulatory protein of a similar structure. Also provided is a method for preventing or treating an EBV-associated cancer.

IPC Classes  ?

• C07K 14/00 - Peptides having more than 20 amino acidsGastrinsSomatostatinsMelanotropinsDerivatives thereof
• A61P 31/20 - Antivirals for DNA viruses
• A61P 35/00 - Antineoplastic agents
• C07K 14/375 - Peptides having more than 20 amino acidsGastrinsSomatostatinsMelanotropinsDerivatives thereof from fungi from Basidiomycetes

Abstract

The present disclosure provides a method for treating and/or ameliorating a lung injury or inflammation in the lung, and/or promoting polarization of macrophages in a subject in need thereof, wherein the method comprises administering microRNA-7704 (miR-7704) or a composition comprising miR-7704 to the subject.

IPC Classes  ?

• C12N 15/113 - Non-coding nucleic acids modulating the expression of genes, e.g. antisense oligonucleotides
• A61P 11/00 - Drugs for disorders of the respiratory system
• C12N 5/0775 - Mesenchymal stem cellsAdipose-tissue derived stem cells

Abstract

A method is to be implemented by a computing device that stores a risk assessment model, and includes steps of: obtaining an entry of target physiological data and target magnetic resonance imaging (MRI) images of a brain of a subject with mild cognition impairment (MCI); obtaining, based on the target MRI images, voxel values respectively of primitive voxels that are related to grey matter of the brain of the subject; selecting, from among the primitive voxels, any primitive voxel satisfying a filtering criterion as a selected voxel; calculating an average of the voxel value(s) respectively of the selected voxel(s) to obtain an average target voxel value; and obtaining a probability of the subject developing Alzheimer's disease within a predetermined time period by feeding the average target voxel value and the entry of target physiological data into the risk assessment model.

IPC Classes  ?

• A61B 5/00 - Measuring for diagnostic purposes Identification of persons
• G06T 7/00 - Image analysis

Abstract

The present disclosure provides a radar object recognition method, which includes steps as follows. The radar image generation is performed on radar data to generate a radar image; the radar image is inputted into an object recognition model, so that the object recognition model outputs a recognition result; the post-process is performed on the recognition result to eliminate recognition errors from the recognition result.

IPC Classes  ?

• G01S 7/41 - Details of systems according to groups , , of systems according to group using analysis of echo signal for target characterisationTarget signatureTarget cross-section
• G06T 5/00 - Image enhancement or restoration
• G06V 10/32 - Normalisation of the pattern dimensions
• G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects

Abstract

A memory array for computing-in-memory (CIM) is disclosed. The memory array for CIM includes a bit cell array, at least one word line and at least one bit line. The bit cell array has a plurality of bit cells, wherein each bit cell is operated at an operating voltage. The at least one word line is electrically connected to the bit cell array, wherein the at least one word line is associated with a first parameter. The at least one bit line is electrically connected to the bit cell array, wherein the bit cells extend along a specific direction, each the at least one bit line has an electrical parameter associated therewith, each the bit cell is associated with a second parameter, a first quantity of the plurality of bit cells of the bit cell array extends along the specific direction, and the memory array determines how an expansion associated with at least one of the first parameter and the second parameter is according to the specific direction.

IPC Classes  ?

• G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using elements simulating biological cells, e.g. neuron
• G11C 11/408 - Address circuits
• G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines

Abstract

A semiconductor device includes a substrate, a channel layer, a first barrier layer, a source/drain contact, and a gate layer. The channel layer is on the substrate. The first barrier layer is on the channel layer and the thickness of the first barrier layer is less than 6 nm. The source/drain contact is on the first barrier layer and is directly contact with the first barrier layer. The gate layer is over the first barrier layer.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

Abstract

Provided is a method for preventing or treating a liver disease, including administering a therapeutically effective amount of pharmaceutical composition to a subject in need, and the pharmaceutical composition includes the isothiocyanate structural modified compound and a pharmaceutically acceptable carrier thereof.

IPC Classes  ?

• A61K 31/26 - Cyanate or isocyanate estersThiocyanate or isothiocyanate esters
• A61K 45/06 - Mixtures of active ingredients without chemical characterisation, e.g. antiphlogistics and cardiaca
• A61P 1/16 - Drugs for disorders of the alimentary tract or the digestive system for liver or gallbladder disorders, e.g. hepatoprotective agents, cholagogues, litholytics
• A61P 35/00 - Antineoplastic agents

Abstract

The present invention demonstrated a Cre-loxP based cofilin-1 transgenic animal model to address the pathophysiological role of over-expressed cofilin-1 on systemic development.

IPC Classes  ?

• A01K 67/027 - New or modified breeds of vertebrates

Abstract

A group III-N based semiconductor 3D integrated circuit that directly stacks a thin-film transistor on a group III-N based transistor is provided. Since the group III-N based semiconductor 3D integrated circuit integrates the group III-N based transistor and the thin-film transistor without performing a packaging process, the group III-N based semiconductor 3D integrated circuit can reduce the packaging cost and have better circuit performance and reliability.

IPC Classes  ?

• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
• H01L 29/786 - Thin-film transistors

Abstract

A method for determining a road type includes measuring, for a preset period, a magnetic field of an environment in which an electronic device is located to obtain a plurality of magnetic field values, calculating an absolute value of a difference between every two adjacent magnetic field values among the magnetic field values sorted in chronological order, calculating an average of the absolute values related to the magnetic field values to serve as a variation value for the environment, determining whether the variation value is smaller than a predetermined threshold value, determining that the environment is a surface road when the determination result is affirmative, and determining that the environment is a non-surface road when the determination result is negative.

IPC Classes  ?

• G01R 33/00 - Arrangements or instruments for measuring magnetic variables
• B60W 40/06 - Road conditions

Abstract

A laser device for photocoagulation surgery is disclosed, wherein the laser device includes a multi-wavelength laser source having a first direction and a second direction different from the first direction. The laser device includes a positioning light source, a first laser light source, a first lens, a second laser light source, a second lens, a third laser light source, a third lens, a fourth laser light source and a fourth lens. The positioning light source configured to project a positioning visible light along the first direction, wherein the positioning visible light has a specific wavelength being about 635 nm. The first laser light source configured to project a first laser light having a first wavelength along the second direction. The first lens disposed in a main optical path of the positioning visible light, and configured to receive the first laser light and reflect the first laser light along the first direction.

IPC Classes  ?

• A61B 18/22 - Surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body by applying electromagnetic radiation, e.g. microwaves using laser the beam being directed along or through a flexible conduit, e.g. an optical fibreHand-pieces therefor

Abstract

A gate fabrication method of an UMOSFET and a trench gate structure formed thereof are provided, comprising providing a transistor structure and a lithography process is employed to define a trench region. A gate oxide layer is deposited along the trench and two polysilicon sidewalls having a spacing there in between are formed afterwards. A wet etching is used to remove the gate oxide layer underneath the polysilicon sidewalls such that a vacancy is formed at the trench bottom. By oxidizing the polysilicon sidewalls, a thick oxide layer is formed, enfolding periphery of the polysilicon sidewalls and filling the vacancy. The spacing can be alternatively retained between the polysilicon sidewalls covered with the thick oxide layer, such that the trench can be alternatively filled. The present invention is effective in increasing oxide thickness of the gate bottom, reducing the trench corner curvature as well as the feedback capacitance.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A process method for fabricating a three-dimensional source contact structure is provided, which is applicable to form a step-like three-dimensional source contact structure in a MOSFET of a power device. The proposed method sequentially adopts a lithography process and a shallow trench process to form a metal contact window. And a lateral etching process, or spacers which will be removed eventually, can be alternatively provided for increasing horizontal surface contact when depositing a source contact metal. Meanwhile, a longitudinal surface exposed by the shallow trench process is also beneficial to increase vertical contact when depositing the source contact metal. As a result, a step-like three-dimensional source contact structure can be formed by employing the present invention. It is believed that the present invention achieves in reducing cell pitch effectively and can be widely applied to various power devices having MOSFET structure thereof.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/3065 - Plasma etchingReactive-ion etching
• H01L 29/66 - Types of semiconductor device

Abstract

A three-dimensional source contact structure and fabrication process method thereof are provided. A lithography process and shallow trench process are sequentially performed to form a metal contact window in a power device. A source heavily doped area is divided by the metal contact window into a first and second heavily doped region. A lateral etching process is applied to an inter-layer dielectric to form a first and a second dielectric layer, each of which is in a trapezoid shape. Meanwhile, a first and a second metal-source surface contact regions are exposed. A longitudinal surface exposed by the shallow trench process is beneficial to increase vertical contact when depositing a source contact metal, thereby a step-like three-dimensional source contact structure can be formed. The present invention achieves in reducing cell pitch effectively and can be widely applied to various power devices having MOSFET structure thereof.

IPC Classes  ?

• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
• H01L 29/40 - Electrodes
• H01L 29/45 - Ohmic electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A three-dimensional source contact structure and its fabrication process method thereof are applicable to a power device, in which an inter-layer dielectric is deposited thereon. A lithography process is applied for forming a first and second dielectric layer. A spacer is respectively provided on opposite sidewalls of the first and second dielectric layer. And a shallow trench process is sequentially performed along the opposite surfaces of the spacers. The spacers are removed after the shallow trench process is complete for exposing a first and a second metal-source surface contact region. The present invention achieves in increasing horizontal surface contact and longitudinal vertical contact when depositing a source contact metal, thereby a step-like three-dimensional source contact structure can be formed. By employing the present invention, it enhances to reduce cell pitch effectively and can be widely applied to various power devices having MOSFET structure thereof.

IPC Classes  ?

• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
• H01L 29/40 - Electrodes
• H01L 29/45 - Ohmic electrodes
• H01L 29/66 - Types of semiconductor device

Abstract

A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.

IPC Classes  ?

• H01L 27/11597 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by three-dimensional arrangements, e.g. cells on different height levels
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 27/11587 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the top-view layout
• H01L 27/1159 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the memory core region
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A semiconductor device includes a first contact layer, a second contact layer, an active layer, a photonic crystal layer, a passivation layer, a first electrode and a second electrode. The first contact layer has a first surface and a second surface opposite to each other. Microstructures are located on the second surface. The second contact layer is located below the first surface. The active layer is located between the first contact layer and the second contact layer. The photonic crystal layer is located between the active layer and the second contact layer. The passivation layer is located on the second contact layer. The first electrode is located on the passivation layer and is electrically connected the first surface of the first contact layer. The second electrode is located on the passivation layer and is electrically connected to the second contact layer.

IPC Classes  ?

• H01S 5/042 - Electrical excitation
• H01S 5/028 - Coatings
• H01S 5/11 - Comprising a photonic bandgap structure

Abstract

The present invention relates to a lithium metal powder, a preparing method thereof, and an electrode including the same, wherein the method for preparing the lithium metal powder includes: providing a lithium metal material and a ultrasonication solution; mixing the lithium metal material and the ultrasonication solution to form a mixed solution; and ultrasonically vibrating the mixed solution to form a lithium metal powder, wherein the lithium metal powder is covered by a protective layer, and the aforementioned protective layer includes a protective layer material, wherein the protective layer material includes a sulfide, fluoride, or nitride, or a combination thereof.

IPC Classes  ?

• C22B 3/22 - Treatment or purification of solutions, e.g. obtained by leaching by physical processes, e.g. by filtration, by magnetic means
• B22F 9/04 - Making metallic powder or suspensions thereofApparatus or devices specially adapted therefor using physical processes starting from solid material, e.g. by crushing, grinding or milling
• C22B 26/12 - Obtaining lithium

Abstract

A device comprises a first semiconductor layer, a dielectric layer, a second semiconductor layer, and a gate structure. The first semiconductor layer is over a substrate. The first semiconductor layer comprises a first channel region and first source/drain regions on opposite sides of the first channel region. The dielectric layer is over the first semiconductor layer. The second semiconductor layer is over the dielectric layer. The second semiconductor layer comprises a second channel region and second source/drain regions on opposite sides of the second channel region. The gate structure comprises a first portion extending in the dielectric layer, a second portion wrapping around the first channel region of the first semiconductor layer, and a third portion wrapping around the second channel region of the second semiconductor layer.

IPC Classes  ?

• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

Curved surface measurement device comprises a plurality of vector sensors, each comprising: a main body and a vector device connected thereto. The vector device comprises a linear extension, with an end provided with a connector for connecting with the main body of another vector sensor; a sensing chip to sense the vector of gravity; a wireless communication circuit to transmit to the external a sensing value of the sensing chip. Computing device calculates the vector value of the end of the linear extension relative to the gravity, the result of which is a plurality of point representing a curve in the space. Method for preparation of the vector device is disclosed.

IPC Classes  ?

• G01B 7/28 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring contours or curvatures

Abstract

A robotic surgical system includes a surgical robot holding a surgical instrument, a wearable device worn by a person, a camera for capturing images, and a computer device. The camera captures images of a base marker, and a dynamic reference frame disposed on an affected part of a patient. The computer device calculates a plurality of conversion relationships among different coordinate systems, and controls the surgical robot to move the surgical instrument according to a pre-planned surgical path and based on the conversion relationships. Furthermore, the computer device transmits data of a 3D model and the pre-planned surgical path to the wearable device, such that the wearable device is configured to present the 3D model in combination with the pre-planned surgical path as an AR image based on the conversion relationships.

IPC Classes  ?

• A61B 34/10 - Computer-aided planning, simulation or modelling of surgical operations
• A61B 34/00 - Computer-aided surgeryManipulators or robots specially adapted for use in surgery
• A61B 34/20 - Surgical navigation systemsDevices for tracking or guiding surgical instruments, e.g. for frameless stereotaxis
• A61B 34/30 - Surgical robots
• A61B 90/00 - Instruments, implements or accessories specially adapted for surgery or diagnosis and not covered by any of the groups , e.g. for luxation treatment or for protecting wound edges
• A61B 90/50 - Supports for surgical instruments, e.g. articulated arms

Abstract

A power amplifier includes an amplifying circuit, a feedback circuit and a grounding capacitor. The amplifier circuit includes at least a first transistor and a second transistor. A control terminal of the first transistor is configured to receive an input signal, a first terminal of the second transistor is coupled to the first transistor, and a second terminal of the second transistor is configured to generate an output signal. The feedback circuit is coupled to the control terminal of the first transistor and the second terminal of the second transistor. The ground capacitor is configured to couple the control terminal of the second transistor to ground. When a frequency of the input signal is between a first band and a second band, an amplification gain of the output signal relative to the input signal is substantially the same.

IPC Classes  ?

• H04B 1/04 - Circuits
• H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission

Abstract

A biomarker includes acrolein-protein conjugate (Acr-PC). An assay kit includes an antibody capable of binding to the biomarker for diagnosing nephropathy, monitoring the progression of nephropathy, or assessing the therapeutic response of nephropathy. The antibody includes a heavy chain having the amino acid sequence of SEQ ID NO:1 and a light chain having the amino acid sequence of SEQ ID NO:2.

IPC Classes  ?

• C07K 16/18 - Immunoglobulins, e.g. monoclonal or polyclonal antibodies against material from animals or humans
• G01N 33/68 - Chemical analysis of biological material, e.g. blood, urineTesting involving biospecific ligand binding methodsImmunological testing involving proteins, peptides or amino acids