40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Custom manufacture of semiconductors and integrated circuits; custom manufacture of semiconductors in the field of semiconductor wafer bonding; custom manufacture of semiconductors in the field of semiconductor die bonding; Wafer-level packaging of semiconductors Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits; Custom design, engineering and testing for new product development of semiconductors and integrated circuits in the fields of semiconductor wafer bonding, semiconductor die bonding, and wafer-level packaging of semiconductors; technology consultation services regarding semiconductors and integrated circuits in the fields of semiconductor wafer bonding, semiconductor die bonding, and wafer-level packaging of semiconductors
The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Custom manufacture of semiconductors and integrated circuits. Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits.
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Custom manufacture of semiconductors and integrated circuits Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits
The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
09 - Scientific and electric apparatus and instruments
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
(1) Semiconductors, processed semiconductor wafers, and integrated circuits (1) Custom manufacture of semiconductors and integrated circuits
(2) Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits
09 - Scientific and electric apparatus and instruments
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Semiconductors, processed semiconductor wafers, and integrated circuits. Custom manufacture of semiconductors and integrated circuits. Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits.
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Custom manufacture of semiconductors and integrated circuits Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits
09 - Scientific and electric apparatus and instruments
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
(1) Semiconductors, processed semi-conductor wafers, and integrated circuits (1) Custom manufacture of semiconductors and integrated circuits
(2) Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits
09 - Scientific and electric apparatus and instruments
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Semiconductors, processed semi-conductor wafers, and integrated circuits. Custom manufacture of semiconductors and integrated circuits. Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits.
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Custom manufacture of semiconductors and integrated circuits Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits
09 - Scientific and electric apparatus and instruments
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
(1) Semiconductors, processed semi-conductor wafers, and integrated circuits (1) Custom manufacture of semiconductors and integrated circuits
(2) Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits
09 - Scientific and electric apparatus and instruments
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Semiconductors, processed semiconductor wafers, and integrated circuits. Custom manufacture of semiconductors and integrated circuits. Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits.
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Custom manufacture of semiconductors and integrated circuits Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits
The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
The present disclosure relates to semiconductor structures and, more particularly, to dual thickness fuse structures and methods of manufacture. The structure includes a continuous wiring structure on a single wiring level and composed of conductive material having a fuse portion and a thicker wiring structure.
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts
The present disclosure relates to a structure which includes a first metal layer patterned as a mandrel, a dielectric spacer on the first metal layer, and a second metal layer on the dielectric spacer.
A method of fabricating a semiconductor device structure comprising depositing a layer of material on a dielectric stack and patterning the layer of material to form a hard mask, depositing a metal layer covering the hard mask to form a metal hard mask, forming vias in the dielectric stack using the metal hard mask, removing the metal hard mask, and forming trenches in the dielectric stack using the hard mask, wherein the hard mask and the metal hard mask are used to define a line end structure separating the trenches.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
28.
Forming replacement low-k spacer in tight pitch fin field effect transistors
A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
29.
Dual metal-insulator-semiconductor contact structure and formulation method
A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
An ROV hot-stab device (100) comprising a hot stab body (102) having a flow bore (102A) that is adapted to receive a fluid, a housing (104) that is operatively coupled to the hot stab body (102), and at least one fluid inlet/outlet (104A/104B) defined in the housing (104). The device (100) also includes an isolation valve (103) that is at least partially positioned within the housing (104) wherein the isolation valve (103) is adapted to, when actuated, establish fluid communication between the bore (102A) of the hot stab body (102) and the at least one fluid inlet/outlet (104A/104B) and at least one sensor (114) positioned at least partially within the housing (104) wherein the sensor (114) is adapted to sense a parameter of the fluid.
A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.
One illustrative integrated circuit (IC) product disclosed herein includes an MRAM cell, the MRAM cell having an outer perimeter, wherein the MRAM cell comprises a bottom electrode, a top electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the IC product also includes an insulating material positioned around the outer perimeter of the MRAM cell and a conductive sidewall spacer comprised of a metal-containing shielding material positioned around the outer perimeter of the MRAM cell, wherein the insulating material is positioned between the conductive sidewall spacer and the MRAM cell.
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
H01L 23/552 - Protection against radiation, e.g. light
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
36.
Methods of shielding an embedded MRAM array on an integrated circuit product comprising CMOS based transistors
One illustrative method disclosed herein includes forming an MRAM memory array and a plurality of peripheral circuits for an integrated circuit product above a semiconductor substrate, forming a patterned layer of a metal-containing shielding material above the substrate, the patterned layer of metal-containing shielding material covering the MRAM memory array while leaving an area above the plurality of peripheral circuits exposed, and, with the patterned layer of metal-containing shielding material in position, performing a silicon dangling bond passivation anneal process on the integrated circuit product.
H01L 21/30 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
H01L 43/12 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , , or
H01L 29/267 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups , , , , in different semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Interanational Business Machines Corporation (USA)
GLOBALFOUNDRIES Inc. (Cayman Islands)
Inventor
Chi, Cheng
Xie, Ruilong
Abstract
A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided, in one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers In a dielectric; forming gate trenches by selectively rernoving the dielectric from: regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.
Devices are formed to have inner layers that have electronic devices, and an outer passivation layer. A patterned conductor is formed on a first surface of the inner layers, and through conductors (that extend through interior insulator layers) are positioned to electrically connect the patterned conductor to the electronic devices. The patterned conductor includes a pattern of connected linear sections that are parallel to the first surface of the inner layers. The linear sections of the patterned conductor meet at conductor corners, and at least one of the conductor corners of the patterned conductor includes a chamfer side that terminates at the linear sections. Further, the chamfer side is not perfectly diagonal, but instead forms unequal angles with the linear sections that intersect to form the corner.
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
41.
Trench silicide contacts with high selectivity process
A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.
H01L 21/283 - Deposition of conductive or insulating materials for electrodes
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
42.
FinFETs with air-gap spacers and methods for forming the same
Fin field effect transistors (FinFETs) include air-gaps between adjacent metal contacts and/or between metal contacts and the transistor gate. The air-gaps are formed during non-conformal deposition of an isolation dielectric in conjunction with a metal-first process to form the conductive structures.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
The disclosure relates to integrated circuit (IC) structures and fabrication techniques. Methods according to the disclosure can include: providing a precursor structure including: a first inter-metal dielectric (IMD); a barrier dielectric positioned on the first IMD; forming an insulator on the barrier dielectric of the precursor structure, wherein an upper surface of the insulator includes a first trench and a second trench laterally separated from the first trench; forming an alignment marker over the precursor structure by filling the first trench with a first refractory metal film; forming a first metal-insulator-metal (MIM) electrode by filling the second trench with the first refractory metal film; recessing the insulator without exposing an upper surface of the barrier dielectric; forming a MIM dielectric layer on the insulator; and forming a second MIM electrode on the MIM dielectric layer, such that the second MIM electrode overlies a portion of the first MIM electrode.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
44.
Gate cut with high selectivity to preserve interlevel dielectric layer
A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
Forming a semiconductor structure includes forming a dummy gate stack on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack. The dummy gate stack is partially recessed. The sacrificial spacer is etched down to the partially recessed dummy gate stack. Remaining portions of the sacrificial spacer are etched leaving gaps on sides of a remaining portion of the dummy gate stack. A first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the remaining portions of the dummy gate stack and extending vertically along a sidewall of a dummy gate cavity. The first and second low-k spacer portions are etched. A poly pull process is performed on the remaining portions of the dummy gate stack. A replacement metal gate (RMG) structure is formed with the first low-k spacer portion and the second low-k spacer portion.
A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.
H01L 21/283 - Deposition of conductive or insulating materials for electrodes
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
48.
Trench silicide contacts with high selectivity process
A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.
H01L 21/283 - Deposition of conductive or insulating materials for electrodes
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
49.
Unmerged epitaxial process for FinFET devices with aggressive fin pitch scaling
Semiconductor devices and methods for making the same includes conformally forming a first spacer on multiple fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched fins to fill the fin cavity.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
50.
METHOD OF SIMULTANEOUS LITHOGRAPHY AND ETCH CORRECTION FLOW
A method of mask correction where two independent process models are analyzed and co-optimized simultaneously. In the method, a first lithographic process model simulation is run on a computer system that results in generating a first mask size in a first process window. Simultaneously, a second hard mask open etch process model simulation is run resulting in generating a second mask size in a second process window. Each first lithographic process model and second hard mask open etch process model simulations are analyzed in a single iterative loop and a common process window (PW) optimized between lithography and etch is obtained such that said first mask size and second mask size are centered between said common PW. Further, an etch model form is generated that accounts for differences in an etched pattern due to variation in three-dimensional photoresist profile, the model form including both optical and density terms that directly relate to an optical image.
G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Custom manufacture of semiconductors and integrated circuits; manufacturing consultation services in the field of semiconductor fabrication Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits
52.
A SYSTEM AND METHOD FOR ACTIVE POWER FACTOR CORRECTION AND CURRENT REGULATION IN LED CIRCUIT
The present invention discloses a system and method for active power factor correction and current regulation in led circuit. The system (100) used in the LED driver circuit performs active PFC and current regulation through the dynamic input current wave shaping by limiting peak currents. The dynamic wave 5 shaping scheme is realized through hardware and firmware and is used to strike an optimal balance between current accuracy, Power factor, THD and peak inductor currents. The system (100) is versatile enough to improve PF and current accuracy in LED circuits and indimmers circuits.
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
53.
DYNAMIC BLEED SYSTEM AND METHOD FOR DYNAMIC LOADING OF A DIMMER USING EVENT DRIVEN ARCHITECTURE
The present invention discloses a dynamic bleed system and method for dynamic loading of a dimmer using event driven architecture for LED applications. An integrated event driven LED driver architecture is used to perform dynamic loading (bleed) of triac dimmer to effectively operate in low power LED applications. The bleeder circuit dynamically loads the dimmer when instantaneous cycle by cycle power falls below a specified value and shuts the bleed path when the power is above a specified value. This threshold is programmable with hysteresis and the loading pattern is programmable as well.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
54.
A SYSTEM AND METHOD TO REGULATE PRIMARY SIDE CURRENT USING AN EVENT DRIVEN ARCHITECTURE IN LED CIRCUIT
The present invention discloses a system and method to regulate primary side current using an event driven architecture in led circuit. The system (100) performs a primary side regulation (PSR) of isolated or non-isolated LED driver topology such as fly back system. The primary side peak voltage/current is regulated to achieve desired secondary side currents without the need of additional external components. The architecture combines firmware and hardware to realize PSR. The method (200) may effectively combine input wave shaping (Active PFC), dimming and PSR to achieve accurate secondary side currents. The method (200) corrects the Peak Regulation Voltage/current (PRV) of primary loop to meet desired half cycle reference voltage/current, which in turn achieves the desired secondary loop current in led circuit.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A method includes receiving cardiac data and determining a cardiac index based upon the cardiac data; determining an increased risk of death associated with epilepsy if the indices are extreme, issuing a warning of the increased risk of death and logging information related to the increased risk of death. A second method comprises receiving at least one of arousal data, responsiveness data or awareness data and determining an arousal index, a responsiveness index or an awareness index, where the indices are based on arousal data, responsiveness data or awareness data respectively; determining an increased risk of death related to epilepsy if indices are extreme values, issuing a warning of the increased risk of death and logging information related to the increased risk of death. A non-transitory computer readable program storage device encoded with instructions that, when executed by a computer, perform a method is also provided.
A61N 1/36 - Applying electric currents by contact electrodes alternating or intermittent currents for stimulation, e.g. heart pace-makers
A61N 1/365 - Heart stimulators controlled by a physiological parameter, e.g. by heart potential
A61B 5/0452 - Detecting specific parameters of the electrocardiograph cycle
A61B 5/16 - Devices for psychotechnicsTesting reaction times
G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)
A61N 1/372 - Arrangements in connection with the implantation of stimulators
Embodiments of the present invention relate to time delayed release of previously distributed digital content. In one embodiment, a method of and computer program product for low-bandwidth time-embargoed content disclosure are provided. A first cryptographic key is received. Encrypted content is received, encoded in a computer readable medium. A correction value is received. A predetermined function is applied to the first cryptographic key and the correction value to determine a second cryptographic key. The second cryptographic key is applied to the encrypted content to obtain decrypted content.
In a method for utilizing social networking services of a user to perform online retail services, a processor retrieves a set of contacts, wherein the set of contacts includes a first group of contacts of a first networking service and a second group of contacts of a second networking service, wherein each contact in the set of contacts has a corresponding link to information about that contact. A processor receives a request for an action to be executed, wherein the request includes gifting information, wherein the gifting information specifies a required relationship between the user and the one or more contact of the set of contacts. A processor determines the one or more contacts that have the required relationship with the user, as specified by the gifting information. A processor causes the action to be executed based on the determined one or more contacts.
A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFETfins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followd by an anneal to drive in both dopants.
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
09 - Scientific and electric apparatus and instruments
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Semiconductors, processed wafers, and integrated circuits. Custom manufacture of semiconductors and integrated circuits. Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits.
09 - Scientific and electric apparatus and instruments
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Semiconductors, processed wafers, and integrated circuits. Custom manufacture of semiconductors and integrated circuits. Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits.
A CMOS device that includes an nFET portion, a pFET portion and an interlayer dielectric between the nFET portion and pFET portion. The nFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer in direct physical contact with the barrier layer and a gate metal filling the remainder of the recess. The pFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer on the barrier layer, a third titanium nitride layer in direct physical contact with the second titanium nitride layer and a gate metal filling the remainder of the recess.
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
A method, computer program product, and system is provided for community based mobile device profiling. In an implementation, a method may include receiving, via a first mobile device, a wireless signal associated with a second mobile device. The method may also include determining an identity of a user associated with the second mobile device. The method may further include establishing at least one setting of the first mobile device based upon, at least in part, a mobile device profile associated with the first mobile device and the identity of the user associated with the second mobile device.
THREE-DIMENSIONAL PROCESSING SYSTEM HAVING MULTIPLE CACHES THAT CAN BE PARTITIONED, CONJOINED, AND MANAGED ACCORDING TO MORE THAN ONE SET OF RULES AND/OR CONFIGURATIONS
Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein one or more chip layers include processor cores that share cache hierarchies over multiple chip layers. The caches can be partitioned, conjoined, and managed according to various sets of rules and configurations.
Identifying a vehicle involved in a hit-and-run accident may comprise generating a damage signature associated with a first vehicle that is left behind with collision damage in a hit-and-run accident. A reverse event signature may be generated that indicates a position of impact and severity of damage associated with a second vehicle involved in the hit-and-run accident that fled a scene of the hit-and-run accident. The generating of the reverse event signature may be based on reverse engineering the damage signature associated with the first vehicle.
A method for providing a matrix material between a bonded pair of substrates with a homogeneous distribution of anisotropic filler particles is provided. Functionalized anisotropic filler particles are mixed uniformly with a matrix material to form a homogenous mixture. A bonded assembly of a first substrate and a second substrate with an array of electrical interconnect structures is placed within a vacuum environment. The homogenous mixture of the matrix material and the anisotropic filler particles is dispensed around the array of electrical interconnect structures. A gas is abruptly introduced into the vacuum environment to induce an implosion of the homogenous mixture. The implosion causes the homogenous mixture to fill the cavity between the first and second substrates without causing agglomeration of the anisotropic filler particles. The mixture filling the space between the first and second substrates has a homogenous distribution of the anisotropic filler particles.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/58 - Mounting semiconductor devices on supports
H01L 21/603 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
H01L 21/4763 - Deposition of non-insulating-, e.g. conductive-, resistive-, layers on insulating layersAfter-treatment of these layers
B29C 70/72 - Encapsulating inserts having non-encapsulated projections, e.g. extremities or terminal portions of electrical components
67.
Pooling entropy to facilitate mobile device-based true random number generation
A mobile device operating system pools any available entropy. The resulting entropy pool is stored in device memory. When storing entropy in memory, preferably memory addresses are randomly allocated to prevent an attacker from capturing entropy that might have already been used to create a random number. The stored entropy pool provides a readily-available entropy source for any entropy required by the operating system or device applications. Then, when a cryptographic application requests a true random number, the operating system checks to determine whether the pool has available entropy and, if so, a portion of the entropy is provided to enable generation (e.g., by a TRNG) of a true random number that, in turn, may then be used for some cryptographic operation. After providing the entropy, the operating system clears the address locations that were used to provide it so that another entity cannot re-use the entropy.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
G06F 7/58 - Random or pseudo-random number generators
68.
POLICY ENFORCEMENT USING NATURAL LANGUAGE PROCESSING
A term of use policy document defines permissible actions that may be implemented by a user using a computing device. A natural language processing (NLP)-based question and answer (Q&A) system is trained to understand the policy document. The device includes a management application that interacts with the Q&A system to identify a policy violation. When the user performs an action on the device, the application converts that action into an NLP query directed to the Q&A system to determine whether the action constitutes a violation. The query may be accompanied by metadata associated with the user, the device or its state. Upon receipt of the query and any associated metadata, the Q&A system determines if the user action is compliant with the policy and returns a response. Based on the response, the user's computing device may take an enforcement action, e.g., restricting or disabling functionality, or issuing a warning.
A method for semiconductor fabrication includes providing (404) channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed (406) for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.
ALD of HfxA1yCz films using hafnium chloride (HfC14) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfC14 pulse time allows for control of the A1 % incorporation in the HfxA1yCz film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfxA1yCz work function layer coupled with ALD deposited HfO2 high-k gate dielectric layers was quantified to be mid-gap at ~4.6 eV. Thus, HfxA1yCz is a promising metal gate work function material allowing for the tuning of device threshold voltages (Vth) for anticipated multi-Vth integrated circuit (IC) devices.
C23C 16/04 - Coating on selected surface areas, e.g. using masks
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
An approach for polishing-based hard mask removal during FinFET device formation is provided. In a typical embodiment, an initial device will be provided with a set of fins (e.g., silicon (Si)), a set of fin caps (e.g., silicon nitride (SiN)), and an oxide layer. A post-oxide planarizing and thinning polishing will first be performed (e.g., using a Silica-based slurry) to thin/reduce the oxide layer. A stop-on-nitride polishing will then be performed (e.g., using a Ceria-based slurry) to reduce the oxide layer to a top surface of the fin caps. Still yet, a stop-on-silicon polishing will be performed (e.g., using a Ceria-based slurry) to remove the set of fin caps and to reduce the oxide layer to a top surface to the set of fins.
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
Provided are methods of High Productivity Combinatorial testing of semiconductor substrates, each including multiple site isolated regions. Each site isolated region includes a titanium nitride structure as well as a hafnium oxide structure and/or a polysilicon structure. Each site isolated region is exposed to an etching solution that includes sulfuric acid, hydrogen peroxide, and hydrogen fluoride. The composition of the etching solution and/or etching conditions are varied among the site isolated regions to study effects of this variation on the etching selectivity of titanium nitride relative to hafnium oxide and/or polysilicon and on the etching rates. The concentration of sulfuric acid and/or hydrogen peroxide in the etching solution may be less than 7 % by volume each, while the concentration of hydrogen fluoride may be between 50 ppm and 200 ppm. In some embodiments, the temperature of the etching solution is maintained at between about 40C and 60C.
Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.
Embodiments include semiconductor-on-insulator (SOI) substrates having SOI layers strained by oxidation of the base substrate layer and methods of forming the same. The method may include forming a strained channel region in a semiconductor-on-insulator (SOI) substrate including a buried insulator (BOX) layer above a base substrate layer and a SOI layer above the BOX layer by first etching the SOI layer and the BOX layer to form a first isolation recess region and a second isolation recess region. A portion of the SOI layer between the first isolation recess region and the second isolation recess region defines a channel region in the SOI layer. A portion of the base substrate layer below the first isolation recess region and below the second isolation recess region may then be oxidized to form a first oxide region and a second oxide region, respectively, that apply compressive strain to the channel region.
An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A method for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure.
A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.
Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.
A self-aligned source/drain contact formation process without spacer or cap loss is described. Embodiments include providing two gate stacks, each having spacers on opposite sides, and an interlayer dielectric (ILD) over the two gate stacks and in a space therebetween, forming a vertical contact opening within the ILD between the two gate stacks, and laterally removing ILD between the two gate stacks from the vertical contact opening toward the spacers, to form a contact hole.
An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.
This application is directed to a semiconductor device with an oversized local contact as a Faraday shield, and methods of making such a semiconductor device. One illustrative device disclosed herein includes a transistor comprising a gate electrode and a source region, a source region conductor that is conductively coupled to the source region, a Faraday shield positioned above the source region conductor and the gate electrode and a first portion of a first primary metallization layer for an integrated circuit device positioned above and electrically coupled to the Faraday shield.
Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.
When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing the final work function metal, for instance a titanium nitride material in P-channel transistors, only preserving a well-defined bottom layer.
The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Embodiments of the invention provide a multi-step cleaning process, comprising exposing the substrate to a nitric acid solution after a first anneal, followed by an aqua regia solution after a second anneal. The substrate can be optionally exposed to a hydrochloric acid solution afterward to completely remove any remaining platinum residues.
Lithographic limitations on gate and induced channel length in MOSFETS are avoided by forming non-planar MOSFETS in a cavity extending into a semiconductor substrate. The gate insulator and channel region lie proximate a cavity sidewall having angle α preferably about ≧90 degrees with respect to the semiconductor surface. The channel length depends on the bottom depth of the cavity and the depth from the surface of a source or drain region adjacent the cavity. The corresponding drain or source lies at the cavity bottom. The cavity sidewall extends therebetween. Neither depth is lithographic dependent. Very short channels can be consistently formed, providing improved performance and manufacturing yield. Source, drain and gate connections are brought to the same surface so that complex circuits can be readily constructed. The source and drain regions are preferably formed epitaxially and strain inducing materials can be used therein to improve channel carrier mobility.
Correction of reticle defects, such as EUV reticle defects, is accomplished with a second exposure. Embodiments include obtaining a reticle with a first pattern corresponding to a design for a wafer pattern, detecting dark defects and/or design/OPC weak spots in the first pattern, exposing a resist covered wafer using the reticle, and exposing the wafer using a second reticle with a second pattern or a second image field with openings corresponding to the dark defects, with a repair pattern on the reticle or on another reticle, or with a programmed e-beam or laser writer.
Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts to active areas. A fill layer is deposited and planarized to expose the dummy gates and the dummy gates are removed. A mask is formed having an opening overlying a portion of the channel region from which the dummy gate was removed and a portion of an adjacent metal silicide contact. The fill layer and a portion of the sidewall spacers exposed through the mask opening are etched to expose a portion of the adjacent metal silicide contact. A gate electrode material is deposited overlying the channel region and exposed metal silicide contact and is planarized to form a gate electrode and a gate-to-metal silicide contact interconnect.
Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.
Methods are provided for fabricating integrated circuit systems that include forming integrated circuits in and on a semiconductor substrate. Via holes are etched into a front surface of the semiconductor substrate and are filled with a conductive material. A carrier wafer having a layer of adhesive thereon is provided and an imprinted pattern is formed in the layer of adhesive. The front surface of the semiconductor substrate is bonded to the carrier wafer with the patterned layer of adhesive. A portion of a back surface of the semiconductor substrate is removed to expose a portion of the conductive material and the thinned back surface is attached to a second substrate. The semiconductor substrate is then de-bonded from the carrier wafer.
Disclosed herein are various methods of forming metal-containing insulating material regions on a metal layer of a gate structure of a semiconductor device. In one example, the method includes forming a gate structure of a transistor, the gate structure comprising at least a first metal layer, and forming a first metal-containing insulating material region in the first metal layer by performing a gas cluster ion beam process using to implant gas molecules into the first metal layer.
One illustrative method disclosed herein includes forming first and second FinFET devices in and above a first region and a second region of a semiconducting substrate, respectively, performing a first ion implantation process through a patterned mask layer to implant nitrogen into the second region, removing the patterned mask layer, performing a second ion implantation process to implant oxygen atoms into both the first and second regions, performing a heating process to form a layer of insulating material at least in the first region and performing at least one etching process to define at least one first fin in the first region and to define at least one second fin in the second region, the second fin being taller than the first fin.
A DRAM cell and method for storing information in a dynamic random access memory using an electrostatic actuator beam to make an electrical connection between a storage capacitor and a bit line.
G11C 11/24 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using capacitors
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
93.
Integrated circuit system with reduced polysilicon residue and method of manufacture thereof
A method of manufacturing an integrated circuit system includes: providing a substrate; forming a polysilicon layer over the substrate; forming an anti-reflective coating layer over the polysilicon layer; etching an anti-reflective coating pattern into the anti-reflective coating layer leaving an anti-reflective coating residue over the polysilicon layer; and etching the anti-reflective coating residue with an etchant gas mixture comprising hydrogen bromide, chlorine, and oxygen to remove the anti-reflective coating residue for mitigating the formation of a polysilicon protrusion.
Apparatus for providing semiconductor device with an analysis module to receive device information, a G-function processor producing an ordered relationship representation corresponding to an optimization parameter specification, and a power cell optimizer to produce an optimization parameter from the ordered relationship representation. A method for designing a semiconductor device includes receiving an optimization target specification; receiving an optimization parameter specification corresponding to an optimization parameter; receiving a the target parameter; receiving a G-function corresponding to an ordered relationship representation; optimizing the optimization parameter specification as a function of the predetermined G-function; and producing at least one optimized geometric layout parameter (GLP) by the optimizing, wherein the at least one GLP corresponds to an optimized power cell.
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
(1) Custom manufacture of semiconductors and integrated circuits; custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits.
96.
Method, system and apparatus for automated termination of a therapy for an epileptic event upon a determination of effects of a therapy
A method comprising detecting an epileptic event in a patient; applying an electrical therapy to a first target area in at least one of a brain region or a cranial nerve of said patient in response to said detecting; receiving a body signal responsive to the electrical therapy, wherein said body signal is selected from an autonomic signal, a neurologic signal, a metabolic signal, an endocrine signal, or a tissue stress marker signal; determining whether said body signal indicates that said electrical therapy has an efficacious effect; and terminating the application of said electrical therapy if the response indicates that the electrical therapy has an efficacious effect. An apparatus capable of performing the method. A non-transitive, computer-readable storage device for storing data that when executed by a processor, perform the method.
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Custom manufacture of semiconductors and integrated circuits. Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits.
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Custom manufacture of semiconductors and integrated circuits Custom design, engineering and testing for new product development of semiconductors and integrated circuits; technology consultation services regarding semiconductors and integrated circuits
99.
Implant damage control by in-situ C doping during sige epitaxy for device applications
Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.
