An optoelectronic device includes an optical gain medium having a first end and a second end and configured to amplify laser radiation within a gain band, a laser cavity containing the optical gain medium and including a first reflector disposed at the first end of the optical gain medium and a second reflector disposed at the second end of the gain medium and including an interferometer having a tunable reflectance band. The optoelectronic device further includes a controller configured to tune the reflectance band of the interferometer so as to modify a spectrum of the laser radiation emitted from the gain medium through the first reflector.
A system includes a controller configured to receive a cellular configuration data and a network traffic data. The cellular configuration data is associated with a plurality of cells within a wireless network. The system includes an on-chip shared memory configured based on the cellular configuration data into a plurality of memory bank groups. Each memory bank group includes a number of memory banks. A first subset of memory bank groups is associated with an uplink slot. A second subset of memory bank groups is associated with a downlink slot. The first subset of memory bank groups associated with the uplink slot is clocked off in response to the network traffic data being associated with a downlink slot. The second subset of memory bank groups associated with the downlink slot is clocked off in response to the network traffic data being associated with an uplink slot.
An unshielded data connection is disposed on a first surface of a printed circuitry board having a major plane. The unshielded data connection is disposed within an imaginary plane, perpendicular to the surface of the printed circuit board, that includes the unshielded data connection as a line segment within the imaginary plane. A symmetrical arrangement of one or more ground connections is disposed around the unshielded data connection. The arrangement is symmetrical with respect to the imaginary plane.
An electronic device package, consisting of a planar package substrate defining a package footprint. The package also includes one or more micro-devices surface mounted on and configured to electrically couple to the package substrate via an array of surface mount terminals. A vapor chamber lid overlays the one or more micro-devices and the vapor chamber lid has planar dimensions that are smaller than the package footprint.
H01L 23/427 - Cooling by change of state, e.g. use of heat pipes
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/552 - Protection against radiation, e.g. light
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
5.
POWER REDUCTION IN PROCESSING PHYSICAL LAYER OF A WIRELESS SYSTEM
A system includes a controller that receives a data for a slot and processes the data in a first power mode and assign jobs associated with the data to one or more accelerators or one or more DSP cores. A scheduler receives the jobs assigned by the controller and schedules the jobs for execution by the at least one or more hardware accelerators and the one or more DSP cores. An event manager manages power modes for the controller. The controller transitions from the first power mode to a second power mode after the controller completes the processing of the data associated with the slot. The second power mode is a lower power mode in comparison to the first power mode when the controller is processing the data. The event manager transitions the controller from the second power mode to the first power mode in response to a triggering event.
A new approach is proposed that contemplates system and method to support multiple error detection and/or correction mechanisms via flexible on-chip memory (OCM) configurations. Here, an OCM includes a plurality of memory banks, wherein each of the plurality of memory banks includes a plurality of memory instances. Under the proposed approach, a first subset of the plurality of memory banks are configured to support a first type of error detection and/or correction mechanism while a second subset of the plurality of memory banks are configured to support a second type of error detection and/or correction mechanism. Moreover, a subset of memory instances within one or more of the plurality of memory banks are configured to store data and extra code words at the same time in order to efficiently support a specific type of error detection and/or correction mechanism.
A network switch, for use in an Ethernet network in a vehicle, includes multiple ports, a switch unit, a peripheral bus, multiple DMA engines and a mapping engine. The ports connect to the Ethernet network. The switch unit forwards packets s among the ports. The peripheral bus connects to a host that runs host applications. The DMA engines transfer packets from the host applications via the peripheral bus to the switch unit. The mapping engine constructs a mapping that maps between (i) bus functions of the peripheral bus that are assigned to the host applications, and (ii) respective ones of the DMA engines, and configures the switch unit, in accordance with the mapping, to permit forwarding of a packet sent from a host application only upon verifying that a DMA engine that transferred the packet is mapped to the bus function assigned to the host application.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 21/85 - Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
8.
Adaptive analog equalization in ADC-based receiver
An analog-to-digital converter-based serial receiver configured to tune analog equalization settings for link training is described. An analog signal from a transmitter is received and the receiver applies initial analog equalization settings. The receiver then converts the equalized analog signal into a digital signal. The receiver then measures frequency content of the analog signal and saturation at the analog-to-digital converter and determines updated analog equalization settings.
An optical transmitter includes a DAC, a timing circuit, and circuitry. The DAC includes switches configured to convert digital data into analog data that is modulated into an optical signal for transmission over an optical fiber. The timing circuit is configured to generate timing signals to control the switches of the DAC. The circuitry is configured to control an output data rate of the DAC by biasing the switches based on a logical combination of the digital data and the timing signals. An optical transmitter includes DACs and a driver. The DACs are configured to receive digital data at a first data rate and to output currents at a second data rate that is greater than the first data rate. The driver is configured to receive a combined current comprising the currents output by the DACs and to generate an output signal that is proportional to the combined current.
An access point (AP) device transmits a first downlink transmission via a first WLAN communication channel having a first radio frequency (RF) bandwidth, and transmits a second downlink transmission via a second WLAN communication channel having a second RF bandwidth. The second downlink transmission including a trigger frame configured to prompt one or more client stations to transmit one or more respective acknowledgments of one or more packets transmitted by the AP device via the first WLAN communication channel. The AP device receives one or more uplink transmissions from the one or more respective client stations. The one or more uplink transmissions from the one or more respective client stations are received via the second WLAN communication channel. The one or more uplink transmissions via the second WLAN communication channel overlap in time with the first downlink transmission via the first WLAN communication channel.
A switch device is configured to communicate with a plurality of hosts and a solid state drive (SSD). The plurality of hosts includes a first host and a second host. The switch device receives a first memory access command from the SSD, the first memory access command including an indication of the first host to indicate the first memory access command is intended for the first host. The switch device uses the indication of the first host in the first memory access command to route the first memory access command to the first host. The switch device removes the indication of the first host from the first memory access command prior to sending the first memory access command to the first host via a peripheral computer interface express (PCIe) interface of the switch device.
09 - Scientific and electric apparatus and instruments
Goods & Services
(1) Data processors used in computers, security sub-systems networking equipment, namely, hardware accelerators, offload engines, crypto chips and other networking equipment, namely, routers, switches, load-balances, web-servers, firewalls, virtual private network gateways and other computer equipment, namely, servers and work stations
13.
Meeting performance and temperature requirements in electronic circuits
An Integrated Circuit (IC) includes an electronic circuit and a controller. The electronic circuit is designed to operate at temperatures above a specified minimal temperature. The IC has a controllable operational parameter that affects a performance measure of the electronic circuit and an amount of heat produced by the electronic circuit. The controller is configured to control the operational parameter so as to meet both requirements concurrently: (i) exceeding a specified minimal performance level of the performance measure, and (ii) a local temperature of the electronic circuit exceeding the specified minimal temperature.
A new approach is proposed that contemplates system and method to support security enhancement for a hardware security module (HSM) using artificial intelligence (AI). Specifically, one or more AI models are trained with datasets of the HSM to establish a pattern of normal/typical behaviors for each of a plurality of applications requesting services of the HSM. While the HSM is running, an AI security module running on the HSM is configured to continuously monitor and analyze service requests from the plurality of applications to the HSM using the one or more trained AI models to identify security breaches/threats. If the AI models detect an anomaly or a deviation from its normal pattern of behaviors, the AI security module marks the application as a potential security threat and stops the HSM from performing a cryptographic operation requested by the application.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
A network interface device operates in a normal operating mode in which the network interface device continually receives transmission symbols via a communication link. The network interface device determines that the network interface device is to transition to a low power mode, and in response transitions receiver circuitry to the low power mode. During a transition time period corresponding to determining that that the network interface device is to transition to the low power mode, the network interface device ignores signals received via the communication link.
An interface in a communications system includes a physical layer transceiver (PHY) for coupling to a wireline channel medium, and for coupling to a functional device via a single-ended cable. The PHY is an integrated circuit (IC) device having first and second differential input/output (I/O) conductors for coupling to the functional device, an impedance element configured to terminate a first one of the differential I/O conductors to a system ground, a second one of the differential I/O conductors being coupled to the single-ended cable, and a common-mode filter coupled to both of the differential I/O conductors. The PHY may further include a printed circuit board (PCB), with the IC device being mounted on the PCB, the first and second differential I/O conductors being signal traces on the PCB. The single-ended cable may be a coaxial cable.
The present disclosure describes apparatuses and methods for adaptive cache management for a storage media system. In aspects, an adaptive cache manager obtains telemetry information relating to access of a cache memory and access of storage media of a storage media system. Based on the telemetry information, the adaptive cache manager determines a cache policy for the cache memory and applies the cache policy to the cache memory to modify a caching scheme or a prefetching scheme for the data of the cache memory. In some cases, the adaptive cache manager receives caching parameters from an application or user of a host system and uses these parameters when determining the cache policy. By so doing, the adaptive cache manager may dynamically alter the caching and prefetch activities of the cache memory to improve efficiency of the cache memory.
A first integrated circuit (IC) chip of a communication device includes a first communication interface that receives a first portion of an input data signal, a first forward error correction (FEC) decoder circuit that generates first error information regarding the first codeword symbols in the first portion of the input data signal, a second communication interface, and a first statistics generator circuit that generates error statistics information using a) the first error information and b) second error information received via the second communication interface. A second IC chip includes a third communication interface that receives a second portion of the input data signal, a second FEC decoder circuit that generates the second error information, the second error information regarding second codeword symbols in the second portion of the input data signal, and iii) a fourth communication interface that sends the second error information to the second communication interface.
A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs a first delayed signal. A second delay line outputs a second delayed signal. A phase detector compares the first and second delayed signals and outputs a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay. A reset circuit resets the first and second signal delay lines in response to the comparison signal, and a clock controller outputs a command to adjust a clock frequency or engage in other mitigation measures based on the comparison signal.
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
G01R 25/00 - Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
H03L 7/00 - Automatic control of frequency or phaseSynchronisation
20.
Methods and apparatus for combining received uplink transmissions
Methods and apparatus for combining received uplink transmissions. In an embodiment, a process for providing wireless data via a communication network is able to determine a type of 5G orthogonal frequency-division multiplexing (OFDM) in accordance with resource elements (REs) of each symbol and configuration parameters. After removing reference signals from the REs to generate a stream of data, demapped data and signal to interference noise radio (SINR) information are generated in accordance with the stream of data. The process is further capable of categorizing REs via an RE identifier to generate RE information including categorizations of REs.
A method for increasing accuracy of a timing protocol packet includes receiving, at a buffer of a first node, for transmission onto a transmission medium, at least one timing protocol packet among a plurality of packets, detecting that a delay-inducing phenomenon affecting a timestamp to be applied to a timing protocol packet will occur within a temporal interval, and in response to detecting that the delay-inducing phenomenon will occur within the temporal interval, preventing, during the temporal interval, application of the timestamp to the timing protocol packet and preventing transmission of the timing protocol packet onto the transmission medium until the delay-inducing phenomenon has elapsed.
A hardware security module system, method and device including one or more security meshes that cover portions of a circuit board including the encryption/decryption component for determining if an unwanted physical access of the circuit board is occurring and disabling or erasing the hardware security module to prevent the unauthorized access of encryption data.
Techniques as described herein may be implemented to support selecting a transmission path in a multi-path network link. In an embodiment, respective cumulative data carrying capacities for selected network paths in a group of network paths defining a multipath group used to forward network packets from a first network node to a second network node are computed. A cumulative capacity comparison value for a received network packet in a flow of network packets is computed based at least in part on a hash value used to distinguish the flow from other flows of network packets. A specific network path is selected from amongst the network paths of the multi-path group, over which to forward the received network packet from the first network node towards the second network node, based on comparing the cumulative capacity comparison value with at least a subset of the cumulative data carrying capacities.
A first integrated circuit (IC) chip of a communication device includes a first communication interface that receives a first portion of an input data signal, a first forward error correction (FEC) decoder circuit that generates first error information regarding the first codeword symbols in the first portion of the input data signal, a second communication interface, and a first statistics generator circuit that generates error statistics information using a) the first error information and b) second error information received via the second communication interface. A second IC chip includes a third communication interface that receives a second portion of the input data signal, a second FEC decoder circuit that generates the second error information, the second error information regarding second codeword symbols in the second portion of the input data signal, and iii) a fourth communication interface that sends the second error information to the second communication interface.
Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.
A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.
H03L 7/16 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
A new approach is proposed that contemplates system and method to support a new network architecture for secure AI computing based on one or more secure, multi-core (SMC) data processing units (DPUs). Each of the SMC DPUs includes a gateway that ensures a secure interface and operating environment for the SMC DPU through encryption. Each of the SMC DPUs may further include a microprocessor core, one or more general purpose processing units (XPU cores) and/or customized processing units (CXPU cores), and a communications interface (COMM I/F) to external memories and other processing units. In some embodiments, a secure AI cloud cluster is constructed using multiple SMC DPUs along with one or more of switches, memories, separate XPUs, and high-speed interconnects (including optical interconnects) to ensure protection of client data for cloud-based AI services.
A transmission driver for serial communication includes first multiplexing circuitry configured to partially serialize a data group into data subgroups based on an in-phase clock, and to delay a quadrature clock corresponding to the in-phase clock. The delay is based on latency of the partial serialization. The transmission driver also includes second multiplexing circuitry having a source-series terminated (SST) driver configured to serialize the data subgroups into a serial data stream based on the delayed quadrature clock. The first multiplexing circuitry may be configured to partially serialize the data group into the data subgroups by arranging a four-bit data group into a pair of two-bit data groups, and the second multiplexing circuitry may be configured to serialize the data subgroups into the serial data stream by arranging the pair of two-bit data groups into the serial data stream.
A communication device includes a convolutional interleaver and an encoder. The convolutional interleaver is configured to receive first codewords encoded using a first error-correcting code. The first codewords include symbols. The convolutional interleaver is configured to distribute the symbols from the first codewords into a second codeword to improve robustness to burst errors. The distribution of the symbols is performed by way of interleaving symbols from different first codewords into the second codeword. The encoder is configured to encode the second codeword using a second error-correcting code, which is different from the first error-correcting code, by appending error-correcting bits to the second codeword.
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
A first communication device determines, based on information included in a first packet received from a second communication device, i) an overall frequency bandwidth of an operating channel of a WLAN and ii) one or more punctured sub-channels for the operating channel. The first communication device transmits, via a plurality sub-channels included in the operating channel of the WLAN, the plurality of sub-channels not including any of the one or more punctured sub-channels, a second packet that includes an RTS frame to initiate a TXOP of the first communication device. The first communication device receives, via a subset of the plurality of sub-channels, a third packet that includes a CTS frame, determines that the subset of sub-channels is reserved for the transmit opportunity TXOP initiated by the first communication device, and transmit a fourth packet to the second communication device during the TXOP via the subset of sub-channels.
A new approach is proposed that contemplates system and method to support a new network architecture for secure AI computing based on one or more secure, multi-core (SMC) data processing units (DPUs). Each of the SMC DPUs includes a gateway that ensures a secure interface and operating environment for the SMC DPU through encryption. Each of the SMC DPUs may further include a microprocessor core, one or more general purpose processing units (XPU cores) and/or customized processing units (CXPU cores), and a communications interface (COMM I/F) to external memories and other processing units. In some embodiments, a secure AI cloud cluster is constructed using multiple SMC DPUs along with one or more of switches, memories, separate XPUs, and high-speed interconnects (including optical interconnects) to ensure protection of client data for cloud-based AI services.
Managing patching of write-limited memory with a hardware security module (HSM) comprising a plurality of one-time programmable (OTP) memory blocks where each OTP memory block is associated with a respective identification value, comprises: receiving, from a patching entity, a patch management request, the patch management request comprising a first identification value associated with an OTP memory block of the plurality of OTP memory blocks of the HSM, an identity token, a cryptographic key, and a signature object; comparing, by the HSM, the identity token and the cryptographic key to a respective identity token and a respective cryptographic key stored in the HSM; verifying, by the HSM, the signature object of the patch management request; configuring a patch code; and installing the patch code in the write-limited memory.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
Techniques as described herein may be implemented to support selecting a transmission path in a multi-path network link. In an embodiment, respective cumulative data carrying capacities for selected network paths in a group of network paths defining a multi-path group used to forward network packets from a first network node to a second network node are computed. A cumulative capacity comparison value for a received network packet in a flow of network packets is computed based at least in part on a hash value used to distinguish the flow from other flows of network packets. A specific network path is selected from amongst the network paths of the multi-path group, over which to forward the received network packet from the first network node towards the second network node, based on comparing the cumulative capacity comparison value with at least a subset of the cumulative data carrying capacities.
An optical transmitter includes a first encoder, a first interleaver, a second encoder, a mapper, a second interleaver, and a frame generator. The first encoder is configured to encode data using a staircase code to generate first codewords. The first interleaver is configured to interleave the first codewords using convolutional interleaving to spread a transmission order of the first codewords. The second encoder is configured to encode the interleaved first codewords using a second code to generate second codewords. The mapper is configured to map the second codewords to transmit symbols. The second interleaver is configured to interleave the transmit symbols to distribute the transmit symbols between pilot symbols. The frame generator is configured to generate a transmit frame including the interleaved transmit symbols and the pilot symbols.
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
H03M 13/19 - Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
35.
System and method for SRAM less electronic device bootup using cache
A new approach is proposed to support SRAM less bootup of an electronic device. A portion of a cache unit of a processor is utilized as a SRAM to maintain data to be accessed via read and/or write operations for bootup of the electronic device. First, the portion of the cache unit is mapped to a region of a memory, which has not been initialized. The processor reads data from a non-modifiable storage to be used for the bootup process of the electronic device and writes the data into the portion of the cache unit serving as the SRAM. To prevent having to read or write to the uninitialized memory, any read operation to the memory region returns a specific value and any write operation to the memory region is dropped. The processor then accesses the data stored in the portion of the cache unit to bootup the electronic device.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
36.
Method and system for memory management within machine learning inference engine
A method includes receiving a machine learning (ML) network model in high-level code; generating an internal representation (IR), the IR is mapped to components in a multi-processing tile device; determining whether a first processing tile with a first on-chip memory (OCM) has a same dimension for an input/output tensor data as a second processing tile with a second OCM performing a same primitive function based on the IR; allocating a same memory address range within the first and the second OCM for the same primitive function if the first processing tile has the same dimension for the input/output tensor data as the second processing tile for the same primitive function; linking the memory address range of the first OCM to the memory address range of the second OCM to form a grouped memory space within the first and the second OCM respectively; and compiling low-level instructions based on the linking.
A printed circuit board (PCB) is provided herein, including signal and ground pads on a surface of the PCB. The signal pads are grouped into differential signal pad pairs, where each differential signal pad pair has a midpoint located halfway between the centers of the signal pads of the differential signal pad pair. A first differential signal pad pair is positioned on a first line, which intersects with both centers of the signal pads of the first differential signal pad pair. A second differential signal pad pair is positioned on a second line, which intersects with the centers of the signal pads of the second differential signal pad pair, parallel to the first line. Additionally, at least one ground pad is positioned along a line drawn from a midpoint of the first differential signal pad pair and a midpoint of the second differential signal pad pair.
Link data is stored in a distributed link descriptor memory (“DLDM”) including memory instances storing protocol data unit (“PDU”) link descriptors (“PLDs”) or cell link descriptors (“CLDs”). Responsive to receiving a request for buffering a current transfer data unit (“TDU”) in a current PDU, a current PLD is accessed in a first memory instance in the DLDM. It is determined whether any data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD. If no data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD, a current CLD is accessed in a second memory instance in the plurality of memory instances of the same DLDM. Current address information in connection with the current TDU is stored in an address data field within the current CLD.
New and advanced computing tools and operations require increasingly large amounts of memory and computing power. Disclosed herein are novel apparatus and methods the provide a scalable, modular, and adaptable design that enables any desired configured of additional nodes to be connected to and used to host computing nodes. The design does not require changes to the hardware, software, or protocols of the host computing nodes which can view the additional nodes as a unitary source of supplemental compute and memory. The disclosed design includes the connection of additional nodes in a peer-to-peer topology that enables a chain interconnected of multiple additional nodes share a single connection to a host node. This avoids the limitations imposed by individual node space and configurations on the amount of compute and memory that can be provided to host nodes.
A system and corresponding method perform large memory transaction (LMT) stores. The system comprises a processor associated with a data-processing width and a processor accelerator. The processor accelerator performs a LMT store of a data set to a coprocessor in response to an instruction from the processor targeting the coprocessor. The data set corresponds to the instruction. The LMT store includes storing data from the data set, atomically, to the coprocessor based on a LMT line (LMTLINE). The LMTLINE is wider than the data-processing width. The processor accelerator sends, to the processor, a response to the instruction. The response is based on completion of the LMT store of the data set in its entirety. The processor accelerator enables the processor to perform useful work in parallel with the LMT store, thereby improving processing performance of the processor.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
42.
Reconfigurable optical receiver for use with multiple modulation techniques
In an optical receiver apparatus for use with multiple optical modulation techniques, a photodiode circuit is configured to process optical signals corresponding to multiple optical modulation techniques, including a first modulation technique and a second modulation technique different from the first modulation technique. The photodiode circuit includes: a first photodiode configured to receive a first optical signal corresponding to a first modulation technique, and a multiple-input second photodiode coupled in series with the first photodiode. The multiple-input second photodiode is configured to receive i) a second optical signal corresponding to the first modulation technique, and ii) a third optical signal corresponding to the second modulation technique. An input of a transimpedance amplifier is coupled to the first photodiode and the second photodiode via a node between the first photodiode and the second photodiode.
Methods and apparatus for beamforming in MIMO systems are disclosed. In an embodiment, a method is provided that includes associating a plurality of signal-to-noise ratio (SNR) ranges with a plurality of precoding schemes, respectively, identifying groups of user equipment (UE) that have SNRs within each SNR range, and configuring downlink transmissions to each group of UE to use a precoding scheme associated with the SNR range of that group.
A circuit and corresponding method perform resource arbitration. The circuit comprises a pending arbiter (PA) that outputs a PA selection for accessing a resource. The PA selection is based on PA input. The PA input represents respective pending-state of requesters of the resource. The circuit further comprises a valid arbiter (VA) that outputs a VA selection for accessing the resource. The VA selection is based on VA input. The VA input represents respective valid-state of the requesters. The circuit performs a validity check on the PA selection output. The circuit outputs a final selection for accessing the resource by selecting, based on the validity check performed, the PA selection output or VA selection output. The circuit addresses arbitration fairness issues that may result when multiple requesters are arbitrating to be selected for access to a shared resource and such requesters require a credit (token) to be eligible for arbitration.
A data channel on an integrated circuit device includes a non-linear equalizer having as inputs digitized samples of signals on the data channel, decoding circuitry configured to determine from outputs of the non-linear equalizer a respective value of each of the signals, and adaptation circuitry configured to adapt parameters of the non-linear equalizer based on respective ones of the value. The non-linear equalizer includes a non-linear filter portion, and a front-end filter portion configured to reduce numbers of the inputs from the digitized samples. The non-linear equalizer may be a neural network equalizer, such as a multi-layer perceptron neural network equalizer, a reduced complexity multi-layer perceptron neural network equalizer, or a radial-basis function neural network equalizer. Alternatively, the non-linear equalizer may include a linear filter and a non-linear activation function, which may be a hyperbolic tangent function.
An electro-optical modulator includes a substrate and an optical waveguide including an electro-optical thin film disposed on the substrate. The optical waveguide has an input end coupled to receive an optical signal and an output end opposite the input end. First and second electrodes are disposed on the substrate along opposite sides of the waveguide. A differential driver has first and second differential outputs coupled to apply a differential electrical signal between the first and second electrodes to modulate a polarization of the optical signal propagating in the waveguide.
G02F 1/035 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect in an optical waveguide structure
An optical communication system includes an optical waveguide and a photodetector (PD). The optical waveguide is arranged to receive and guide an optical signal. The PD is configured to receive the optical signal from the optical waveguide and to convert the optical signal into an electrical signal. The PD includes a stack of layers including at least (i) first layers (68, 72, 76) including two or more semiconductor layers forming a reverse-biased semiconductor junction configured to produce the electrical signal in response to the optical signal impinging thereon, and (ii) second layers (64, 68) forming a capacitance component that is connected in series with the reverse-biased semiconductor junction. The PD further includes a first electrode (80) and a second electrode (84), configured to (i) apply one or more voltages that reverse-bias the reverse-biased semiconductor junction and (ii) output the electrical signal.
H10F 30/223 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PIN barrier
H10F 77/122 - Active materials comprising only Group IV materials
An electro-optical modulator (100) includes a substrate (104) and an optical waveguide (106) including an electro-optical thin film (102) disposed on the substrate. The optical waveguide has an input end (105) coupled to receive an optical signal and an output end (109) opposite the input end. First and second electrodes (108, 110) are disposed on the substrate along opposite sides of the waveguide. A differential driver (124) has first and second differential outputs (126, 128) coupled to apply a differential electrical signal between the first and second electrodes to modulate a polarization of the optical signal propagating in the waveguide.
G02F 1/035 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect in an optical waveguide structure
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
49.
Packaging electronic device with liquid thermal interface material
An electronic device includes (i) an integrated circuit (IC) die mounted on a substrate, (ii) a lid having first and second surfaces facing one another, and one or more openings formed through the lid between the first and second surfaces, the lid being disposed over at least the IC die to form a space between the IC die and the first surface of the lid, the one or more openings are configured to enable transference of fluids through the lid, (iii) a liquid thermal interface material (TIM) filling the space and being formulated to conduct heat from the IC die to the lid, and (iv) a stopper structure extended from the first surface of the lid, the stopper structure includes one or more sidewalls configured to contain the liquid TIM at least in the space between the IC die and the first surface of the lid.
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/24 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel, at the normal operating temperature of the device
H01L 23/373 - Cooling facilitated by selection of materials for the device
50.
SIMULTANEOUS BIDIRECTIONAL SIGNALING IN THROUGH-SILICON VIAS
A signal transmitter transmits a signal onto the bidirectional transmission medium of the TSV. A boost circuit is available to supplement the signal as needed. Calibration circuitry periodically activates, at an interval of time, a signal driver of the signal transmitter to transmit a test signal on the bidirectional transmission medium of the TSV. The calibration circuitry then compares a level of the test signal to a range, with different levels within the range corresponding to different logic levels. If the level of the test signal is outside an expected range, a boost circuit is activated to bring the level of the test signal into the expected range.
An interface device distributes data from a plurality of input data streams to a smaller number first data streams, and periodically inserts a set of alignment markers (AMs) into the first data streams. After using the AMs, the interface device removes the AMs and reinserts the AMs at particular positions. A forward error correction (FEC) encoder encodes data corresponding to the first data stream to generate FEC codewords and distributes data from the FEC codewords to multiple outputs streams. Within the output streams, the AMs are located at FEC codeword boundaries and bits of a first AM, among the set of AMs, are spread across multiple outputs stream. A single output data stream is generated based on the multiple output streams of the FEC encoder.
An optical communication system includes an optical waveguide and a photodetector (PD). The optical waveguide is arranged to receive and guide an optical signal. The PD is configured to receive the optical signal from the optical waveguide and to convert the optical signal into an electrical signal. The PD includes a stack of layers including at least (i) first layers including two or more semiconductor layers forming a reverse-biased semiconductor junction configured to produce the electrical signal in response to the optical signal impinging thereon, and (ii) second layers forming a capacitance component that in is connected with series the reverse-biased semiconductor junction. The PD further includes a first electrode and a second electrode, configured to (i) apply one or more voltages that reverse-bias the reverse-biased semiconductor junction and (ii) output the electrical signal.
H01L 31/109 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN heterojunction type
A multi-lane integrated circuit transceiver device includes first and second integrated circuit dies having respective first and second pluralities of transmit block/receive block pairs. Each respective transmit block and each respective receive block in the first plurality of block pairs on the first die and the second plurality of block pairs on the second die includes respective digital clock generation circuitry. The device further includes digital clock distribution circuitry to distribute a digital clock signal output by one respective receive block, in one of the first and second pluralities of block pairs, to the transmit blocks in both of the pluralities of block pairs, for use as a baseline clock by the respective digital clock generation circuitry in each of the transmit blocks in both of the pluralities of block pairs. Where each plurality includes N block pairs, the two dies together form a single 2N-lane device.
H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
54.
METHOD AND APPARATUS FOR QUIETING TRANSMISSIONS IN A COMMUNICATION NETWORK
A coordinator communication device in a communication network determines that a time period is to begin during which only the coordinator communication device will have opportunities to transmit. The time period includes a plurality of time cycles, each time cycle i) beginning with the coordinator communication device transmitting a beacon signal and ii) including a transmit opportunity that follows the beacon signal. The transmit opportunity is for the coordinator communication device. The coordinator communication device transmits one or more signals to follower communication devices in the communication network to prompt the follower communication devices to refrain from transmitting during the time period. During one or more transmit opportunities of the time period, the coordinator communication device transmits one or more time-sensitive packets.
H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
An electronic device (11) includes (i) an integrated circuit (IC) die (22) mounted on a substrate (25), (ii) a lid (33) having first and second surfaces (32, 34) facing one another, and one or more openings (66) formed through the lid between the first and second surfaces, the lid being disposed over the IC die to form a space (23) between the IC die and the first surface (32) of the lid, the one or more openings configured to enable transference of fluids through the lid, (iii) a liquid thermal interface material (TIM) (44) filling the space and formulated to conduct heat from the IC die to the lid, and (iv) a stopper structure (54) extended from the first surface of the lid, the stopper structure includes sidewalls (55) configured to contain the liquid TIM at least in the space between the IC die and first surface of the lid.
H01L 23/04 - ContainersSeals characterised by the shape
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
56.
Mitigating process problems in hybrid bonding of vertical die stacking
An electronic device includes a first integrated circuit (IC) die and a second IC die. The second IC die is mounted on the first IC die. The first IC die includes (i) a first dielectric layer having a first dielectric surface, and (ii) a first pad having a first footprint and a first pad surface, the first pad being electrically conductive and being at least partially embedded in the first dielectric layer. The second IC die includes (i) a second dielectric layer having a second dielectric surface at least partially facing the first dielectric surface, and (ii) a second pad, which is electrically conductive and is at least partially embedded in the second dielectric layer. The second pad has a second footprint, smaller than the first footprint, and a second pad surface electrically coupled to the first pad surface.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
57.
SIGNAL TRACE TRANSITION FOR HIGH DATA RATE APPLICATIONS
Systems, methods, and apparatus are described herein for maintaining high signal integrity and high bandwidth in data transmissions between an integrated circuit package and a PCB. The integrated circuit package has multiple layers. Signal pins for connecting the integrated circuit package, both physically and electrically, to the PCB are located at a first layer. A signal trace is coupled to each signal pin. The signal trace bifurcates into two branches and couples to a given signal pin at the distal end of each branch.
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
An interface device distributes data from a plurality of input data streams to a smaller number first data streams, and periodically inserts a set of alignment markers (AMs) into the first data streams. After using the AMs, the interface device removes the AMs and reinserts the AMs at particular positions. A forward error correction (FEC) encoder encodes data corresponding to the first data stream to generate FEC codewords and distributes data from the FEC codewords to multiple outputs streams. Within the output streams, the AMs are located at FEC codeword boundaries and bits of a first AM, among the set of AMs, are spread across multiple outputs stream. A single output data stream is generated based on the multiple output streams of the FEC encoder.
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H03M 5/14 - Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
H03M 9/00 - Parallel/series conversion or vice versa
H04L 7/00 - Arrangements for synchronising receiver with transmitter
A memory device includes a plurality of memory cells. Each memory cell stores a plurality of signal levels representing a plurality of values corresponding to a respective plurality of bits, bits in corresponding respective positions of significance across the plurality of memory cells constituting respective memory pages of the memory device. The memory device also includes decoding circuitry to decode each bit value of one of the respective memory pages using bit values read from at least one other one of the respective memory pages, adjacent to the one of the respective memory pages. The plurality of signal levels may represent the plurality of values according to a Gray code. The decoding circuitry may be configured to compare each signal level to a set of voltage thresholds, and to decode a subset of the plurality of signal levels using fewer than all voltage thresholds in the set of voltage thresholds.
A memory array circuit routes packet data to a destination within the array. The memory array includes memory devices arranged in a plurality of rows and columns, as well as passthrough channels connecting non-adjacent memory devices. Each of the memory devices includes a memory configured to store packet data, and a packet router configured to interface with at least one adjacent memory device of the memory array. The packet router determines a destination address for a packet, and, based on the destination address, selectively forwards the packet to a non-adjacent memory device via a passthrough channel of the plurality of passthrough channels. A memory interface routes the packet from a source to the memory array, and selectively forwarding the packet to one of the plurality of memory devices based on the destination address.
A machine learning (ML) hardware includes a first data format conversion block configured to receive data generated by an application source in a first data format. The first data format conversion block is configured to convert the received data from the first data format into a second data format. The first data format is different from the second data format. The ML hardware includes a plurality of processing units configured to perform one or more ML operations on the data in the second data format to generate a processed data. The ML hardware includes a second data format conversion block configured to convert the processed data to a third data format. The ML hardware further includes a transmitting component configured to output the processed data in the third data format to a memory component for use by an application destination.
A coordinator communication device in a communication network determines that a time period is to begin during which only the coordinator communication device will have opportunities to transmit. The time period includes a plurality of time cycles, each time cycle i) beginning with the coordinator communication device transmitting a beacon signal and ii) including a transmit opportunity that follows the beacon signal. The transmit opportunity is for the coordinator communication device. The coordinator communication device transmits one or more signals to follower communication devices in the communication network to prompt the follower communication devices to refrain from transmitting during the time period. During one or more transmit opportunities of the time period, the coordinator communication device transmits one or more time-sensitive packets.
An input signal is sampled at a current sampling phase by a sampler device of a receiver device. The sampled input signal is equalized by an adaptive equalizer of the receiver device. One or more parameters of the adaptive equalizer are adapted, based on the equalized input signal, under one or more adaptation constraints. Phase gradient information indicative of an offset of the current sampling phase from an optimal sampling phase is determined, and the one or more adaptation constraints of the adaptive equalizer are updated based on the phase gradient information to move the current sampling phase towards the optimal sampling phase.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
64.
Reliable electronic fuse based storage using error correction coding
An apparatus for reliable fuse-based storage in an Integrated Circuit (IC) includes a plurality of electronic fuses and processing logic. The electronic fuses store (i) data bits, (ii) parity bits that were generated from the data bits in accordance with an Error Correction Code (ECC) scheme, and (iii) access information required for accessing the data bits and the parity bits. The processing logic receives a read command for reading given data bits from the electronic fuses, based on the read command retrieves access information specifying given electronic fuses storing the given data bits and given parity bits associated with the given data bits, using the access information reads the given data bits and the given parity bits from the given electronic fuses, applies the ECC scheme to the given data bits and the given parity bits, using the ECC module to generate corrected data bits, and outputs the corrected data bits.
A circuit and corresponding method employ directional link (DL) credit pools. The circuit comprises the DL credit pools and transmit (TX) port logic. The DL credit pools are associated with neighboring node (NBN) TX ports of a NBN on a chip. The NBN is coupled to a node on the chip via the circuit. The node includes the circuit. The TX port logic admits a received packet to the circuit based on routing information in the received packet and produces a TX packet by updating the routing information, in the received packet admitted, to indicate a NBN TX port of the NBN TX ports. The TX port logic transmits the TX packet produced to the NBN based on a DL credit pool of the DL credit pools that is associated with the NBN TX port indicated. Use of the DL credit pool mitigates head-of-line blocking under bursty traffic conditions.
An optical communication device includes a laser, a transmitter (Tx), a receiver (Rx) and a device controller. The laser is configured to generate an optical carrier. The transmitter is configured to generate an optical Tx signal using the optical carrier and to transmit the optical Tx signal to a peer optical communication device. The receiver is configured to receive an optical Rx signal from the peer optical communication device, and to down-convert the optical Rx signal using the optical carrier. The device controller is configured to adjust a frequency of the laser to reduce a Carrier Frequency Offset (CFO) between the received optical Rx signal and the optical carrier generated by the laser, including conditionally applying to a frequency of the laser a series of frequency hops in accordance with a defined dithering sequence.
A system and corresponding method queue work within a virtualized scheduler based on in-unit accounting (IUA) of in-unit entries (IUEs). The system comprises an IUA resource and arbiter. The IUA resource stores, in association with an IUA identifier, an IUA count and threshold. The IUA count represents a global count of work-queue entries (WQEs) that are associated with the IUA identifier and occupy respective IUEs of an IUE resource. The IUA threshold limits the global count. The arbiter retrieves the IUA count and threshold from the IUA resource based on the IUA identifier and controls, as a function of the IUA count and threshold, whether a given WQE from a given scheduling group, assigned to the IUA identifier, is moved into the IUE resource to be queued for scheduling. The IUA count and threshold prevent group(s) assigned to the IUA identifier from using more than an allocated amount of IUEs.
An Ethernet Physical Layer (PHY) device includes a link interface and a transceiver. The link interface is configured to connect to a full-duplex wired Ethernet link. The transceiver is configured to receive first Ethernet signals carrying first data at a first data rate over the Ethernet link in a first direction, the first Ethernet signals occupying a first frequency band, and to transmit second Ethernet signals carrying second data at a second data rate different from the first data rate, over the Ethernet link in a second direction that is opposite the first direction, the second Ethernet signals occupying a second frequency band that is different from f the first frequency band.
H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex
H04B 3/23 - Reducing echo effects or singingOpening or closing transmitting pathConditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
H04L 7/04 - Speed or phase control by synchronisation signals
69.
System and Method for Neural Network-Based Autonomous Driving
A system and corresponding method for autonomous driving of a vehicle are provided. The system comprises at least one neural network (NN) that generates at least one output for controlling the autonomous driving. The system further comprises a main data path that routes bulk sensor data to the at least one NN and a low-latency data path with reduced latency relative to the main data path. The low-latency data path routes limited sensor data to the at least one NN which, in turn, employs the limited sensor data to improve performance of the at least one NN's processing of the bulk sensor data for generating the at least one output. Improving performance of the at least one NN's processing of the bulk sensor data enables the system to, for example, identify a safety hazard sooner, enabling the autonomous driving to divert the vehicle and avoid contact with the safety hazard.
A first communication device performs a handshaking procedure with a second communication device, the handshaking procedure associated with transitioning from an active mode to a low power mode. The first communication device transmits data and/or idle symbols to the second communication device i) after completion of the handshake procedure, and ii) at least until the earlier of a) a time period expiring, and b) determining that the second communication device quieted a transmitter of the second communication device. The first communication device transitions to the low power mode in connection with the handshaking procedure.
Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In one embodiment, a system for processing network data from a wireless communications network includes a vector pipeline, a programmable mixed radix engine, and a job scheduler. The vector pipeline is configured to scale, stage, and multiply twiddle factor to vector data from a mega-job. The programmable mixed radix engine is configurable for computing jobs bundled in the mega-job in accordance with a DFT of a particular point size. The job scheduler is operable to bundle multiple discrete Fourier transform (DFT) jobs having a substantially same point size into the mega-job after obtaining the DFT jobs.
Two pointers are initialized. The first pointer is incremented every M cycles of a monitored clock and the second pointer is incremented every N cycles of a reference clock, where M and N are determined from a frequency relationship between the clocks. If the positions of the pointers are determined to differ by more than a drift threshold, an error is detected and corrective action may be taken.
Data read from a storage medium is first processed through a first data path including a first decoder configured to decode data output from at least one first finite impulse response (FIR) filter and first FIR adaptation circuitry configured to adjust a first FIR coefficient for the at least one first FIR filter. The data is then processed through a second data path, which includes at least one second FIR filter and second FIR adaptation circuitry configured to adjust a second FIR coefficient to reach an FIR coefficient that achieves a target minimum number of errors. The second FIR adaptation circuitry is configured to reach the FIR coefficient that achieves the target minimum number of errors faster than the first FIR adaptation circuitry. A second decoder in the second data path is configured to decode data output by the at least one second FIR filter.
A circuit and corresponding method enable mining for digital currency in a blockchain network. The circuit comprises a controller and at least one partial hash engine that (i) implements a hash function, partially, to compute a partial hash digest of a final hash digest for a block header of a block candidate and (ii) generates a notification based on determining that the partial hash digest satisfies a criterion. The controller includes a complete hash engine that implements the hash function, completely. In response to the notification generated, the controller activates the complete hash engine to compute, in its entirety, the final hash digest for the block header, effectuating a decision for submission of the block candidate with the block header to the blockchain network for mining the digital currency. Power savings and reduction in area are achieved relative to multiple hash engines that compute the entire final hash digest.
G06Q 20/40 - Authorisation, e.g. identification of payer or payee, verification of customer or shop credentialsReview and approval of payers, e.g. check of credit lines or negative lists
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
H04L 9/00 - Arrangements for secret or secure communicationsNetwork security protocols
An optoelectronic device includes a gain medium having first and second ends and configured to amplify laser radiation within a gain band having a peak at a given wavelength. A laser cavity, containing the gain medium, includes a first reflector disposed on a first side of the gain medium and a second reflector disposed on a second side of the gain medium, opposite the first side. The second reflector has a reflectance as a function of wavelength that is tunable so as to reduce a reflectance of the second reflector at the peak of the gain band, thereby broadening a spectrum of the laser radiation emitted from the gain medium through the second reflector.
H01S 5/10 - Construction or shape of the optical resonator
H01S 3/105 - Controlling the intensity, frequency, phase, polarisation or direction of the emitted radiation, e.g. switching, gating, modulating or demodulating by controlling the mutual position or the reflecting properties of the reflectors of the cavity
Hardware circuitry of a network device in a communication network collects telemetry data generated by the network device, the telemetry data providing information regarding operational status of at least one of i) the network device, and ii) one or more network links connected to the network device. The hardware circuitry generates packets that include respective sets of the telemetry data collected by the hardware circuitry. The packets are addressed to a remote network device in, or communicatively coupled to, the communication network. The hardware circuitry prompts the network device to transmit the packets to the remote network device.
An integrated circuit (IC) chip includes a first memory that stores first information, and a second memory that stores second information that it to be protected from unauthorized access. Communication interface circuitry gives a processor external to the IC chip read access and/or write access to components of the IC chip. Embedded hardware security circuitry selectively provides the processor external to the IC chip with secure access to the second memory. Interconnect circuitry i) selectively grants the processor unsecured access to the first memory via the communication interface circuitry, ii) selectively grants the processor access to the embedded hardware security, and iii) limits access to the second memory.
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
G06F 21/85 - Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
78.
System and Method for Payment Hardware System Module (HSM) Integration
A system and corresponding method integrate a payment application and at least one payment hardware system module (HSM). The system comprises a payment system interface (PSI) interposed between a payment application and at least one payment hardware system module (HSM). The PSI implements a standard, payment HSM application programming interface (API) that is payment HSM vendor-agnostic. The PSI enables communication between the payment application and the at least one payment HSM based on the standard, payment HSM API implemented. Since the standard, HSM payment API is payment HSM vendor-agnostic, development effort otherwise expended to develop a connector for each vendor payment HSM integration is avoided.
G06Q 20/34 - Payment architectures, schemes or protocols characterised by the use of specific devices using cards, e.g. integrated circuit [IC] cards or magnetic cards
79.
MULTI-BANK MEMORY THAT SUPPORTS MULTIPLE READS AND MULTIPLE WRITES PER CYCLE
In a memory system having a plurality of memory banks, a plurality of memory access requests having a first priority level and a plurality of memory access requests having a second priority level different are received. A set of first memory banks executes the multiple memory access requests having the first priority level during a first clock cycle. The memory system determines one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle. In response to determining the one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle, the one or more second memory banks execute one or more memory access requests having the second priority level during the first clock cycle.
Hardware circuitry of a network device in a communication network collects telemetry data generated by the network device, the telemetry data providing information regarding operational status of at least one of i) the network device, and ii) one or more network links connected to the network device. The hardware circuitry generates packets that include respective sets of the telemetry data collected by the hardware circuitry. The packets are addressed to a remote network device in, or communicatively coupled to, the communication network. The hardware circuitry prompts the network device to transmit the packets to the remote network device.
H04L 43/0817 - Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning
81.
MULTI-BANK MEMORY THAT SUPPORTS MULTIPLE READS AND MULTIPLE WRITES PER CYCLE
In a memory system having a plurality of memory banks, a plurality of memory access requests having a first priority level and a plurality of memory access requests having a second priority level different are received. A set of first memory banks executes the multiple memory access requests having the first priority level during a first clock cycle. The memory system determines one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle. In response to determining the one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle, the one or more second memory banks execute one or more memory access requests having the second priority level during the first clock cycle.
A method of reading data from a rotating magnetic storage medium, having at least one read head, includes storing respective digitized data samples from each respective read head of the at least one read head in a respective timing buffer, determining a zero-phase start phase angle from a preamble of the digitized data samples, feeding forward the zero-phase start phase angle to an interpolator, selecting an interpolation filter based on the fed-forward zero-phase start phase angle, releasing the respective digitized data from the respective timing buffer after a duration sufficient for completion of the determining, the feeding forward and the selecting, and interpolating samples of the digitized data released from the respective timing buffer.
A first photonics integrated circuit (PIC) chip originates from a PIC wafer. The first PIC chip includes a substrate, and one or more optical communication components fabricated on the substrate. Optical testing components are also fabricated on the substrate. The optical testing components are configured to, prior to die singulation of the PIC wafer, transfer light to a second PIC chip on the PIC wafer for testing one or more operational attributes of optical components disposed on the second PIC chip Prior to die singulation of the PIC wafer, the second PIC chip was adjacent to the first PIC chip on the PIC wafer.
An integrated circuit (IC) chip includes a first memory that stores first information, and a second memory that stores second information that it to be protected from unauthorized access. Communication interface circuitry gives a processor external to the IC chip read access and/or write access to components of the IC chip. Embedded hardware security circuitry selectively provides the processor external to the IC chip with secure access to the second memory. Interconnect circuitry i) selectively grants the processor unsecured access to the first memory via the communication interface circuitry, ii) selectively grants the processor access to the embedded hardware security, and iii) limits access to the second memory.
A network device provides a search key corresponding to a packet to a TCAM. The TCAM determines that the search key matches one or more search patterns stored in the TCAM. The network device selects one search pattern among the one or more search patterns at least by analyzing respective priority information associated with the one or more search patterns. The respective priority information indicates one or more respective priority levels that are independent from one or more physical locations of the one or more search patterns within the TCAM. In connection with selecting the one search pattern, the network device determines one or more actions to be performed on the packet by the network device, the one or more actions corresponding to the selected one search pattern.
A method for writing data to a magnetic data storage medium includes detecting whether the duration, before occurrence of a data transition, of data to be written exceeds a predetermined threshold, and, when the duration, before the occurrence of the data transition, of the data to be written exceeds the predetermined threshold, writing the data by applying an initial pulse and then maintaining a steady-state write current for a defined interval, and when the duration, before the occurrence of the data transition, of the data to be written is at most equal to the predetermined threshold, writing the data by applying the initial pulse without applying a steady-state write current before the data transition. The predetermined threshold may be determined by size of a magnetic bubble formed when writing a single bit to the magnetic data storage medium. A subsequent pulse may be applied following the defined interval.
A method for digital timing recovery from oversampled analog signals includes computing filter coefficients for digitized samples of the oversampled analog signals based on an oversampling factor of the oversampled analog signals, using the filter coefficients in a rotation filter to compensate for the oversampling factor in the digitized samples of the oversampled analog signals, deriving a starting phase and magnitude from the compensated digitized samples of the oversampled analog signals, and using the starting phase and magnitude in a timing recovery loop to recover a clock from the compensated digitized samples of the oversampled analog signals. The rotation filter may include a plurality of taps, and the circuitry may be configured to compute respective sets of coefficients for respective taps. Each set of coefficients may be dependent on another set of coefficients, or the coefficients may be approximate with each set of approximate coefficients being independent.
A method for fabricating an electronic device having two or more stacked integrated circuit (IC) dies, the method includes, disposing a first IC die on a substrate. A registration error of the first IC die between (i) a first intended position of the first IC die on the substrate, and (ii) a first actual position of the first IC die on the substrate, is determined. A second IC die is stacked on the first IC die, and at least part of the registration error of the first IC die is compensated for by shifting the second IC die, from a second intended position to a second actual position.
A network device, for use in an automotive network, includes a semiconductor die, network-device circuitry and an on-chip traffic monitor. The network-device circuitry is disposed on the die and is configured to transfer traffic of the automotive network. The on-chip traffic monitor is disposed on the die and is configured to monitor the traffic traversing the network-device circuitry from one or more sources in the automotive network to one or more destinations in the automotive network, and to detect a performance degradation in the network-device circuitry by analyzing the monitored traffic.
A silicon photonics communications device, configured for fastening thereto a fitting of an optical fiber cable, includes an integrated circuit structure having optical transducers thereon and having a first surface, and a fastening block having a bonding area of a block surface bonded to the first surface and having a cantilevered arm having a cantilever surface parallel to the first surface. The cantilever surface is configured for bonding to the fitting at a cantilever area at least as large as the bonding area, and is spaced away from the block surface by a step distance to accommodate alignment of the fitting to the optical transducers. Where the optical transducers are on a second surface perpendicular to the first surface, the arm extends beyond the second surface, and holds an end face of the fitting, at which ends of optical fibers are exposed, adjacent to the optical transducers.
A network device (18), for use in an automotive network (20), includes a semiconductor die, network-device circuitry and an on-chip traffic monitor (76). The network-device circuitry is disposed on the die and is configured to transfer traffic of the automotive network. The on-chip traffic monitor is disposed on the die and is configured to monitor the traffic traversing the network-device circuitry from one or more sources in the automotive network to one or more destinations in the automotive network, and to detect a performance degradation in the network-device circuitry by analyzing the monitored traffic.
A method for cancelling, from servo signals read in a read channel while a write channel is active, interference caused by write signals in the write channel, includes generating a predicted channel response signal from the write signals in a data clock domain, resampling the generated predicted channel response signal using a clock in the data clock domain having a rate corresponding to a servo clock from a servo clock domain, transferring the resampled predicted channel response signal from the data clock domain to the servo clock domain and aligning phase of the transferred resampled predicted channel response signal with phase of the servo clock, determining a domain-boundary-crossing delay incurred in the transferring, based on the domain-boundary-crossing delay, synchronizing the phase-aligned transferred resampled predicted channel response signal with the servo signals, and subtracting the synchronized phase-aligned transferred resampled predicted channel response signal from the servo signals.
A storage system including a plurality of HDDs, a cooling system, and a system controller is provided. Each of the plurality of HDDs includes a disk, a write head configured to write data to the disk, a microphone, an HDD controller configured to process a signal from the microphone determine noise detected by the microphone, and a housing that houses the disk, the write head, the microphone, and the HDD controller. The cooling system is configured to cool the plurality of the HDDs. The system controller is configured to receive data corresponding to the determined noise detected by the microphones of each of the plurality of HDD, and control a cooling level of the cooling system based on the received data and acoustic noise information associated with each of the plurality of HDDs. A method for operating the storage system is also provided.
A method of testing an integrated circuit device includes detecting a number of integrated clock gates (ICGs) in the device. Each ICG can stop clock propagation in a respective branch of a clock tree of the device. For each detected ICG, an ICG fanout (a number of digital inputs that the output of each ICG can feed) is compared with a threshold number of registers. When the ICG fanout is greater than the threshold number, it is determined whether a function-enable path of an existing ICG is timing-critical. When the function-enable path of the existing ICG is timing-critical, an additional ICG and a test point are inserted into the device as a clock input to the existing ICG. When the function-enable path of the existing ICG is not timing-critical, a test point and an AND-gate may be inserted in that function-enable path.
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
95.
System and method for generating multiple platform-dependent instruction sets from single hardware specification
A new approach of systems and methods to support automatic generation of multiple platform-dependent instruction sets from a single specification of an integrated circuit (IC). First, a specification compiler accepts as input a first instruction set of a plurality of first instructions in a specification format, wherein the first instruction set defines a design pattern of one or more specifications and/or requirements of the IC and is independent of any implementation or platform of the IC. The design tool then converts the first instruction set into a second instruction set of a plurality of second instructions in an intermediate format. A language compiler then accepts and compiles the second instruction set into a plurality of third instruction sets, wherein each of the plurality of third instruction sets comprises a plurality of third instructions in a specific language for a specific platform targeting a specific implementation or application of the IC.
An optical transceiver includes a silicon photonics substrate and multiple devices. The devices are configured to process optical signals propagating to and from the optical transceiver, and to perform at least one of an optical-to-electrical conversion of received optical signals to incoming electric signals and an electrical-to-optical conversion of outgoing electric signals to transmitted optical signals. The devices are each fabricated to include respectively a package substrate configured according to one of multiple different package substrate mounting technologies. Each package substrate among the multiple devices is mounted on the silicon photonics substrate according to mounting requirements of the respective package substrate mounting technology of that package substrate. At least two of the package substrates are mounted according to the mounting requirements of different package substrate mounting technologies.
B60G 15/02 - Resilient suspensions characterised by arrangement, location, or type of combined spring and vibration- damper, e.g. telescopic type having mechanical spring
B60G 21/05 - Interconnection systems for two or more resiliently-suspended wheels, e.g. for stabilising a vehicle body with respect to acceleration, deceleration or centrifugal forces permanently interconnected mechanically between wheels on the same axle but on different sides of the vehicle, i.e. the left and right wheel suspensions being interconnected
G02B 6/42 - Coupling light guides with opto-electronic elements
G02F 1/313 - Digital deflection devices in an optical waveguide structure
H01S 5/02 - Structural details or components not essential to laser action
H01S 5/0234 - Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
H01S 5/12 - Construction or shape of the optical resonator the resonator having a periodic structure, e.g. in distributed feedback [DFB] lasers
97.
Automotive data processing system with efficient generation and exporting of metadata
An automotive data processing system includes a storage subsystem and a processor. The storage subsystem is disposed in a vehicle and is configured to store at least data produced by one or more data sources of the vehicle. The processor is installed in a vehicle and is configured to apply, to the data stored in the storage subsystem or that is en route to be stored in the storage subsystem, at least one model that identifies one or more specified features-of-interest in the data, so as to generate metadata that tags occurrences of the specified features-of-interest in the stored data, and to export at least part of the metadata to an external system that is external to the vehicle.
G07C 5/08 - Registering or indicating performance data other than driving, working, idle, or waiting time, with or without registering driving, working, idle, or waiting time
A method for operation of a first communication device in a wireless local area network (WLAN) communication channel, having a plurality of component channels, between the first communication device and a second communication device is described. A first physical layer (PHY) protocol data unit (PPDU) and a second PPDU, distinct from the first PPDU, are generated. The first PPDU and second PPDU are transmitted simultaneously to the second communication device over the WLAN communication channel, including: transmitting the first PPDU via a first component channel within a first radio frequency (RF) channel segment that occupies a first frequency bandwidth, and transmitting the second PPDU via a second component channel within a second RF channel segment that occupies a second frequency bandwidth that does not overlap the first frequency bandwidth segment, and is separated from the first frequency bandwidth segment by a frequency gap.
A network device comprises a receive processor configured to generate respective packet descriptors that include i) respective header information extracted from headers of packets received via a plurality of network interfaces, the packets also including trailers, and ii) respective trailer information extracted from the trailers of the packets. A packet processor is configured to process the header information and the trailer information in the packet descriptors to determine actions to be performed on the packets, including determining network interfaces via which at least some packets are to be transmitted by the network device. A transmit processor is configured to transmit the at least some packets via the plurality of network interfaces in accordance with the determining of network interfaces by the packet processor.
A network device obtains measurement data for one or more device attributes or environmental factors, and compares the measurement data to respective ranges specified for the device attributes or the environmental factors. Different ranges for the device attributes or the environmental factors are associated with different operating regions (OREs) classified for the device. The operating state of the network device corresponds to a first ORE of the different OREs, and various tasks performed by the device in the operating state are based on configurations specified by the first ORE. Based on comparing the measurement data, the network device identifies a second ORE that includes ranges for the device attributes or the environmental factors that match the measurement data. The network device transitions the operating state to correspond to the second ORE, and adjusting the tasks performed by the device according to configurations specified by the second ORE.
