A Mach-Zehnder modulator (MZM) includes a waveguide arrangement, an electrode structure, an input, and an output. The waveguide arrangement has a first waveguide arm and a second waveguide arm arranged in parallel. The first and second waveguide arms have a length of less than 2 millimeters. The electrode structure is associated with the waveguide arrangement and has a differential impedance of at least 100 ohms. The input splits an input optical signal into a first optical signal portion propagating through the first waveguide arm and a second optical signal portion propagating through the second waveguide arm. The output combines the first optical signal portion from the first waveguide arm and the second optical signal portion from the second waveguide arm into an output optical signal.
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
2.
Hardware Acceleration for Fragment Reassembly and Checksums
A method of reassembling a set of packet fragments comprises receiving, with a hardware-based input processing handler, a plurality of packet fragments, and associating, with a hardware-based hash content addressable memory (CAM), two or more of the plurality of packet fragments as components of a complete packet. The method further comprises excising, with a hardware-based reassembly engine, one or more headers from the two or more of the plurality of packet fragments to produce excised packet fragments, and combining, with the hardware-based reassembly engine, the excised packet fragments to form a reassembled complete packet. The method may further comprise determining a partial checksum for each packet fragment payload and storing the partial checksum in memory. The method may further comprise combining the partial checksums determined for each packet fragment payload to form a complete checksum that is appended to the complete packet payload.
H04W 28/06 - Optimising, e.g. header compression, information sizing
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
3.
ARTIFICIAL INTELLIGENCE ASSISTANT MODULE ASSOCIATED WITH TRACKING AN ELECTRONIC DATA
A method includes receiving a user entered data associated with tracking/generating an electronic data destined for an electronic tracking system, wherein the user entered data is provided through a graphical user interface (GUI) with a plurality of fields and includes a description associated with the electronic data. The method also includes receiving a user specific data and a historical data associated with the electronic tracking system. The method further includes executing a code associated with an artificial intelligence (AI) module to process the user entered data and based on the user specific data and the historical data to generate a plurality of recommendations associated with a subset of fields of the plurality of fields.
A SERDES includes a transmitter configured to output a differential signal that is subject to common-mode noise, where the differential signal includes a digital signal and an inverted digital signal. The detector circuitry is configured to derive an amplified and biased common-mode signal from the differential signal, and the transmitter is further configured to tune the digital signal responsively to feedback based on the amplified and biased common-mode signal to reduce electromagnetic interference of the common-mode noise. Such a SERDES may include feedback circuitry which configured to receive the amplified and biased common-mode signal and to convert the amplified and biased common-mode signal into a feedback signal, and the transmitter may be further configured to receive the feedback signal for tuning the digital signal based on the feedback signal.
The present disclosure describes apparatuses and methods for adaptive frame alignment for a receiver. In some aspects, an adaptive frame aligner detects a failure by a decoder to decode a frame of symbols that are stored in a buffer. In response to the failure to decode, the adaptive frame aligner alters a pointer of the buffer to realign the symbols of a subsequent frame. The decoder can then attempt to decode the realigned symbols of the subsequent frame to provide decoded data of the subsequent frame. If the decoding attempt fails, the adaptive frame aligner can alter the pointer again to provide a different realignment of the symbols of another subsequent frame and may repeat this process until the decoder is able to decode the realigned symbols of a frame. By so doing, the adaptive frame aligner may enable the decoder to decoder the frame without retraining a data link.
An integrated circuit (IC) is manufactured and is mounted in an IC package. A processor of a measurement system determines a reference value of a physical layer (PHY) parameter at a second test point on a test fixture based on one or more model values, specified by an Ethernet communication standard, corresponding to a first test point on the test fixture corresponding to a contact on the IC package and one or more measured test fixture parameters characterizing a channel connecting the first test point to the second test point on the test fixture. The processor then determines whether the PHY parameter at the first test point on the IC package complies with the Ethernet communication standard based on i) the reference value of the PHY parameter and ii) a measured value of the PHY parameter obtained from a measurement of the PHY parameter at the second test point.
A method of facilitating insertion of a device into, or removal of a device from, a bus architecture of a computer system while the computer system is operational, comprises configuring a first function of a device of the computer system as a control function to control insertion and removal of at least one additional function from the bus architecture, and sending, by the device of the computer system to a host driver of a host computer, a binding command to bind the control function to the host driver. The method may further comprise configuring the at least one additional function for insertion into the bus architecture, sending, by the control function to the host driver, a request to insert the at least one additional function into the bus architecture, and enabling, by the host driver, the at least one additional function in response to the request.
A method for assembling and mounting a stacked substrate package includes: a) mounting a build-up substrate to a base substrate, the build-up substrate including interconnections between surfaces of the build-up substrate, and the base substrate including interconnections between surfaces of the base substrate; b) mounting the base substrate to a rigid carrier; and c) mounting an integrated circuit to the build-up substrate, where, during a), b), and c), the build-up substrate, the base substrate and the integrated circuit are stacked to provide a substrate stack, where i) a) is performed before at least one of b) and c), ii) c) is performed before at least one of a) and b), or iii) b) is performed before a) and c), and c) is performed before a).
A method for testing a semiconductor assembly (11) includes: in a three-dimensional (3D) multi-die assembly with a first die (12) and a second die (14) coupled by hybrid bond pad interconnects (22), operating a mission-mode datapath (20a, 20b) between the dies using bidirectional general purpose input output (GPIO) pads configured for a first signal direction in mission mode. In test mode, at least a subset of the GPIO pads operate in a second signal direction different from the first signal direction to form at least one on-die loopback path (33a, 33b, 38a, 38b, 41, 42). Test data is injected into the mission-mode datapath at an injection (circuit and) point (27, 28, 62) not on a critical timing path for mission-mode operation of the mission-mode datapath. Received test data is monitored through the on-die loopback path to detect at least one interconnect defect (9) associated with the hybrid bond pad interconnects.
A glass optical interposer assembly (11, 90) includes: (i) a glass pane (14), (ii) one or more optical waveguides (16) embedded within the glass pane (14), (iii) a plurality of optical transceiver integrated circuits (22) positioned within the glass pane (14), (iv) circuit switching logic (18) embedded within the glass pane (14) and coupled to the one or more optical waveguides (16), and (v) a plurality of electrical integrated circuits (30), which are individually packaged and are coupled to the glass pane (14), the one or more optical waveguides (16) are configured to provide optical communication pathways between the plurality of electrical integrated circuits (30) through the plurality of optical transceiver integrated circuits (22) as selectively enabled by the circuit switching logic (18).
G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/42 - Coupling light guides with opto-electronic elements
G02B 6/35 - Optical coupling means having switching means
11.
System and method for hardware-based register protection mechanism
A new approach is proposed to support hardware-based protection for registers of an electronic device. Sources requesting access to the registers are categorized into a set of internal sources that can be trusted and a set of external sources that are untrusted. The registers are classified into a set of internal registers allowed to be accessed by the internal resources only, a set of read-only external registers that can be read by the external resources in addition to accessed by the internal resources, and a set of read/write external registers that can be read and written by both the internal and the external resources. Each access request by a source to the registers includes the source type, wherein access request is granted or denied based on the matching between the source bits in the access request and the register classification bits of the one or more registers to be accessed.
Examples described herein include clock gating logic to gate a clock signal from the memory controller when the memory controller interface is idle. The clock gating logic may ungate the clock signal for a duration when it detects that the memory controller has received a memory access request. The duration that the clock is ungated for may be based on timing parameters obtained from the memory controller, such as latency values and/or other timing parameters. Gating the clock signal when the memory controller’s interface with a requester is idle may result in significant power savings in the memory subsystem.
An interposer system, method and device including an interposer including a redistribution layer having a plurality of conductive pathways and passive electrical components positioned within the redistribution layer, wherein the redistribution layer electrically couples electrical devices with the passive components and/or a substrate.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
A phase interpolator (PI) for clock and data recovery (CDR) in a high-speed receiver implements nonlinearity mitigation. The PI interpolates between adjacent phase-shifted clock signals based on digital PI-codes to generate a sampling clock. To reduce phase nonlinearity at high frequencies, the PI applies zone-based dynamic biasing to phase interpolation elements. A bias generator selects and applies one or more bias values to PI unit cells based on a phase zone corresponding to the PI-code. The applied bias adjusts operating characteristics of the interpolation elements, such as bias current or transconductance, to reduce differential nonlinearity and integrated nonlinearity across the PI phase range. In some embodiments, PI unit cells are arranged in groups that receive independently selectable dynamic or fixed biases. The architecture improves phase linearity and timing alignment with low area and power overhead.
A glass optical interposer assembly includes: (i) a glass pane, (ii) one or more optical waveguides embedded within the glass pane, (iii) a plurality of optical transceiver integrated circuits positioned within the glass pane, (iv) circuit switching logic embedded within the glass pane and coupled to the one or more optical waveguides, and (v) a plurality of electrical integrated circuits, which are individually packaged and are coupled to the glass pane, the one or more optical waveguides are configured to provide optical communication pathways between the plurality of electrical integrated circuits through the plurality of optical transceiver integrated circuits as selectively enabled by the circuit switching logic.
A glass optical interposer assembly includes: (i) a glass pane having one or more optical waveguides embedded therein, (ii) a compute die coupled to the glass pane, (iii) a plurality of high bandwidth memory (HBM) components coupled to the glass pane and arranged around the compute die, and (iv) a plurality of optical transceiver integrated circuits embedded within the glass pane and positioned at a depth having a Z dimension offset relative to respective ones of the compute die and the plurality of HBM components, the one or more optical waveguides provide optical communication pathways between the compute die and the plurality of HBM components through the plurality of optical transceiver integrated circuits.
A ferrule-to-ferrule retaining clip for applying axial compression forces on a laser ferrule and an optical fiber ferrule of a pluggable optical transceiver module includes: a bulk end configured to hold a strain relief tube of an optical fiber and abut the optical fiber ferrule; joints; a center member connected to the joints and configured to hold the laser ferrule and the optical fiber ferrule; locking members extending from the joints axially and configured to apply pressure against the laser ferrule; and side members extending axially from the bulk end to the joints, where the side members are convex shaped and configured to i) spread apart the locking members when compressed, and ii) cause the bulk end and the locking members to apply an axial compression force against the laser ferrule and the optical fiber ferrule when not compressed.
Tunable distributed oscillators (DOs) with flexible electrical length and associated systems, components, and devices are disclosed. In one aspect, a DO may include a plurality of DO units coupled in series. An individual DO unit includes a transmission-line segment having first and second ends and a middle portion between the first end and the second end. The DO unit further includes a first oscillator coupled with the first end, a second oscillator coupled with the second end, a first inductive matching circuit coupled between the first oscillator and the middle portion, and a second inductive matching circuit coupled between the second oscillator and the middle portion. By tuning the inductance or effective reactance of the first and second inductive matching circuits, the phase response of the DO unit may be adjusted so that the effective electrical length of the transmission-line segment is shortened relative to its physical length.
H03B 5/18 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance
H03B 5/08 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
A method of selecting a foundational building block model from a trained dataset of foundational building block models may comprise performing a semantic similarity search of the trained dataset, based on a user specification, to produce a set of foundational building block model candidates. The specification may be conveyed to the trained dataset through an initial prompt. The method may further comprise combining the initial prompt from the user with the set of foundational building block model candidates to produce an augmented prompt, submitting the augmented prompt to a primary large language model (LLM), and receiving, from the primary LLM, a prioritized categorization of the final set of foundational building block candidates generated based, at least in part, on the specification from the user. The method may further comprise performing a multi-stage reranking of the set of foundational building block model candidates using a Bi-encoder followed by a Cross-encoder.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
A method for testing a semiconductor assembly includes: in a three-dimensional (3D) multi-die assembly with a first die and a second die coupled by hybrid bond pad interconnects, operating a mission-mode datapath between the dies using bidirectional general purpose input output (GPIO) pads configured for a first signal direction in mission mode. In test mode, at least a subset of the GPIO pads operate in a second signal direction different from the first signal direction to form at least one on-die loopback path. Test data is injected into the mission-mode datapath at an injection point not on a critical timing path for mission-mode operation of the mission-mode datapath. Received test data is monitored through the on-die loopback path to detect at least one interconnect defect associated with the hybrid bond pad interconnects.
An optoelectronic device includes a first reflector and a second reflector, which define an optical path on a substrate. A gain medium is disposed on the optical path between the first and second reflectors and configured to amplify laser radiation within a given gain band. A comb filter is disposed on the optical path between the first and second reflectors and configured to pass a set of distinct wavelength sub-bands within the gain band, the set of distinct wavelength sub-bands defining a comb. A bandpass filter is disposed on the optical path between the first and second reflectors in series with the comb filter. The bandpass filter has a passband encompassing a subset of the wavelength sub-bands in the comb.
H01S 3/10 - Controlling the intensity, frequency, phase, polarisation or direction of the emitted radiation, e.g. switching, gating, modulating or demodulating
H01S 5/50 - Amplifier structures not provided for in groups
H01S 5/30 - Structure or shape of the active regionMaterials used for the active region
A receiver circuit is disclosed. The receiver circuit includes an input circuit configured to receive a data stream defined by a plurality of input symbols. Ones of the input symbols are encoded with M-bit values. A transcoder transcodes the input symbols in the data stream encoded with M-bit values to a stream of transcoded symbols. Ones of the transcoded symbols are encoded with N-bit values, where N
Lidar apparatus includes a light source having a source frequency, an electrical signal generator configured to generate a digitally-coded electrical signal, a modulator configured to impress the digitally-coded signal onto a light beam emitted by the light source, and to convert the digitally-coded output beam of the light source into a multi-dimensional modulated output beam, transmitter optics configured to propagate the multi-dimensional beam toward a target, receiver optics configured to receive the multi-dimensional beam as reflected by the target, an optical demodulator configured to demodulate the reflected multi-dimensional beam, electro-optical conversion circuitry configured to output an electrical signal representing the received reflected multi-dimensional beam, and digital signal processing circuitry configured to compare the electrical signal representing the received reflected multi-dimensional beam to the digitally-coded signal to determine at least one of (a) range, and (b) velocity, of the target.
A phase interpolation system including a clock source, a phase rotator, a non-linearity detector and a non-linearity corrector. The phase rotator receives outputs phase rotated clock signals derived from a clock signal and a different phase state. The non-linearity detector compares a phase of each of the rotated clock signals to a phase of a reference clock signal and outputs a signal indicating a phase difference between the clock signal and each of the rotated clock signals. The non-linearity corrector determines an extent to which the phase difference changes non-linearly as different phase states are selected by the phase rotator and provides a control signal based on which the phase rotator corrects the exhibited non-linearity.
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
25.
Method and Devices of Communication in a Computing Network using Switch Proxy
Methods for communicating in a computing network and corresponding devices are described. An example method of communicating in a computing network includes, by a scale-up switch, receiving a command packet generated by a compute component of a computing network, the command packet including a destination identifier and a memory address. The method further includes identifying a destination compute component based on the command packet received and determining if the destination compute component is in a scale-up network or a scale-out network. Responsive to the destination compute component being in the scale-out network, the method includes translating the command packet received into a network message, the translating including mapping the destination identifier to a network address and the memory address to a network resource index, and transmitting the network message to a scale-out fabric. Said communicating in the computing network can reduce demands upon the compute component and streamline network communication.
An electronic device (11) includes: (a) an integrated circuit (IC) die (22) mounted on a substrate (25); (b) a stiffener (55), on the substrate, having a bottom surface (53) facing the substrate and an opening (12) aligned with the IC die; (c) a liquid metal (LM) thermal interface material (TIM) (44) on the upper surface (23) of the IC die, and facing the opening; and (d) a lid (33) on the stiffener. The lid includes (i) a protrusion (26) extending from a lower surface (14) toward the IC die, aligned with the opening and configured to contact the LM TIM, and (ii) channels (35a, 35b) in the lower surface surrounding the protrusion. When the lid is placed on the stiffener, the protrusion displaces the LM TIM to fill the volume between the lid and the IC die, and the channels receive LM TIM overflow.
At a current clock cycle, a request is received for storing first-in-first-out (FIFO) buffer data portions in a FIFO buffer implemented with memory banks. In response to the request, memory bank selection methods are applied to select memory banks ordered in a first sequential order. It is determined whether the selected memory banks as ordered in the first sequential order starts with a first memory bank identical to a last memory bank written in a last clock cycle. IF SO, the first memory bank is swapped with a second memory bank immediately following the first memory bank in the first sequential order to generate a second sequential order. Writes is performed to store the FIFO buffer data portions into the selected memory banks in accordance with the second sequential order.
A method and corresponding computer device for a shared buffer able to consecutively store received data packets without wasted storage space and enabling first-in first-out processing order. The shared buffer is divided into segments, each segment having a complete count that tracks both number of data packet stored into the segment and the number of data packets read out of the segment. The complete counts of the segments provide a way to determine if segments contain unprocessed data packets and when the segments become free to store newly received data packets. Managing the shared buffer on a segment level, instead of a data packet level reduces the amount of memory needed to be dedicated to buffer management and streamlines the packet tracking and release procedures.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
H04L 47/43 - Assembling or disassembling of packets, e.g. segmentation and reassembly [SAR]
H04L 49/103 - Packet switching elements characterised by the switching fabric construction using a shared central bufferPacket switching elements characterised by the switching fabric construction using a shared memory
H04L 49/901 - Buffering arrangements using storage descriptor, e.g. read or write pointers
29.
METHOD AND SYSTEM FOR ENHANCING SECURITY OF A SYSTEM
A system includes a key provisioning and management unit configured to manage one or more cryptographical keys associated with one or more cryptographical operations. The system includes a hardware component for running an application supported by the hardware component. The key provisioning and management unit is configured to generate a cryptographic key within an internal environment of the key provisioning and management unit. The generated cryptographic key is transmitted from the key provisioning and management unit to the hardware component without exposing the generated cryptographic key in plaintext format to the application.
A detachable connector system for optical communication comprises a connector comprising first alignment features and a micro-lens array arranged on the connector. The micro-lens array comprises second alignment features that are complementary to the first alignment features. A detachable connector system for optical communication comprises a first connector comprising holes and first alignment features and a first micro-lens array arranged on the first connector. The first micro-lens array comprises second alignment features that are complementary to the first alignment features. The system comprises a second connector comprising shafts configured to insert into the holes and a second micro-lens array arranged on the second connector.
An electronic device includes: (a) an integrated circuit (IC) die mounted on a substrate; (b) a stiffener, on the substrate, having a bottom surface facing the substrate and an opening aligned with the IC die; (c) a liquid metal (LM) thermal interface material (TIM) on the upper surface of the IC die, and facing the opening; and (d) a lid on the stiffener. The lid includes (i) a protrusion extending from a lower surface toward the IC die, aligned with the opening and configured to contact the LM TIM, and (ii) channels in the lower surface surrounding the protrusion. When the lid is placed on the stiffener, the protrusion displaces the LM TIM to fill the volume between the lid and the IC die, and the channels receive LM TIM overflow.
Methods for communication in a computing network and accompanying scale-up switches and design structures are described herein. According to an example embodiment, a method of communication in a computing network includes, by a scale-up switch, receiving a command packet generated by a compute component of a computing network. The method further includes, by the scale-up switch, identifying a destination compute component based on the command packet received and determining if the destination compute component is in a scale-up network or a scale-out network of the computing network. Responsive to the destination compute component being in the scale-out network, the method further includes, by the scale-up switch, embedding the command packet received in a network message and transmitting the network message to a scale-out fabric of the scale-out network. Communication in the computing network as described can be helpful for reducing demands upon the compute component and streamlining network communication.
Some input termination networks in SerDes architectures, such as inductive-capacitive (LC) transmission‑line based structures or double T‑coil networks, offer only limited ability to extend bandwidth or control peaking. To address these challenges, an improved input termination network can be implemented. The improved input termination network includes a series impedance circuit between the T-coil network and the termination circuit. By isolating the T‑coil from the full capacitive loading of the termination circuit, the series impedance circuit significantly enhances the bandwidth and tunability of the input termination network, allowing more effective shaping of peaking and return‑loss characteristics. When combined with a parallel capacitor added to the termination circuit to stabilize high‑frequency impedance, the improved input termination network enables a more controlled and robust frequency response than other passive matching networks.
An equalizing circuit for a multi-stage analog front end may include an equalizing portion and a variable gain portion. The equalizing portion includes at least one controllable impedance element to apply a configurable, frequency-dependent peaking response to an input signal. The variable gain portion is coupled to the equalizing portion, and the variable gain portion applies an overall gain to the input signal. The overall gain is independent from the peaking response of the equalizing portion.
A method of reading data from a rotating magnetic storage medium, having at least one read head, includes storing respective digitized data samples from each respective read head of the at least one read head in a respective timing buffer, determining a zero-phase start phase angle from a preamble of the digitized data samples, feeding forward the zero-phase start phase angle to an interpolator, selecting an interpolation filter based on the fed-forward zero-phase start phase angle, releasing the respective digitized data from the respective timing buffer after a duration sufficient for completion of the determining, the feeding forward and the selecting, and interpolating samples of the digitized data released from the respective timing buffer.
A first network interface device receives a first synchronization signal transmitted by a second network interface device via a communication link. The first synchronization signal is for synchronizing the first network interface device and the second network interface device via the communication link. In response to detecting the first synchronization signal from the second network interface device, the first network interface device starts a timer that is configured to expire after transmission of the first synchronization signal by the second network interface device has ended. In response to the timer expiring, the first network interface device transmits a synchronization response signal to the second network interface device.
A phase interpolator (PI) is controlled by digital PI-codes generated by a clock and data recovery (CDR) loop in a high-speed receiver. PI-code monitoring and correction is included in the loop to detect and correct non-linearity in the PI and/or phase errors in a delay-locked loop (DLL) that feeds into the PI. A PI-code monitor accumulates PI-codes into bins and analyzes the resulting distribution to detect non-linearity in the PI. A correction table is generated based on the observed PI-code distribution. A PI-code corrector uses this table to adjust subsequent PI-codes, compensating for non-ideal analog behavior. The architecture enables real-time monitoring and digital correction of PI and DLL errors, improving timing alignment in high-speed links with shared phase-locked loops (PLLs) and per-lane DLLs and PIs.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
38.
DETECTION OF PHASE INTERPOLATOR AND DELAY-LOCKED LOOP ERRORS IN CLOCK AND DATA RECOVERY LOOP
A phase interpolator (PI) is controlled by digital PI-codes generated by a clock and data recovery (CDR) loop in a high-speed receiver. PI-code monitoring and correction is included in the loop to detect and correct non-linearity in the PI and/or phase errors in a delay-locked loop (DLL) that feeds into the PI. A PI-code monitor accumulates PI-codes into bins and analyzes the resulting distribution to detect non-linearity in the PI. A correction table is generated based on the observed PI-code distribution. A PI-code corrector uses this table to adjust subsequent PI-codes, compensating for non-ideal analog behavior. The architecture enables real-time monitoring and digital correction of PI and DLL errors, improving timing alignment in high-speed links with shared phase-locked loops (PLLs) and per-lane DLLs and PIs.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
In response to receiving a read request while non-volatile memory is performing an erase operation, a solid state drive (SSD) device controller suspends the erase operation to permit the non-volatile memory to execute a read operation corresponding to the read request. The SSD device controller determines a time delay for suspending the erase operation based on a metric that indicates a degree of completeness of the erase operation, and delays suspending the erase operation for the determined time delay when the determined time delay is non-zero.
A command is received at a first processor from a system component. The first processor instructs an available second processor to perform part of the command. The second processor constructs, based on the instruction, a hardware accelerator command and executes the hardware accelerator command using a hardware accelerator. The second processor then provides a result from the hardware accelerator to the first processor.
A flanged stiffener ring for device packages/electronic devices includes flanges protruding from the sides of the stiffener ring body. The flanged stiffener ring is of minimal material to keep weight low, but maintain rigidity and, thus provide stiffening forces to a substrate of the device package to inhibit substrate warpage.
A fractional-N phase locked loop (PLL) is described and includes a voltage-controlled oscillator (VCO) configured to output a VCO clock signal and a fractional feedback divider (FFD) connected to an output of the VCO, the FFD receiving the VCO clock signal and a feedback divider ratio, the feedback divider ratio comprising an integer portion and a fractional portion. The FFD further includes a multi-modulus divider (MMD) configured to divide the VCO clock signal by N or N+1; and a phase interpolator (PI) connected to an output of the MMD, the PI configured to interpolate between a first phase signal and a second phase signal to adjust an output phase of a feedback clock signal.
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
43.
SYNCHRONIZED FEED FORWARD FREQUENCY DECODER AND SCALABLE VOLTAGE CONTROLLED OSCILLATOR FOR FRACTIONAL-N PHASE LOCKED LOOP
A fractional-N phase locked loop (PLL) is described and includes a synchronized feed forward frequency decoder configured to generate a VCO frequency code from a feedback divider ratio and an update rate input thereto; and a scalable voltage-controlled oscillator (VCO) comprising an array of ring cells, wherein each of the ring cells comprises a multi-stage ring VCO comprising a plurality of inverters, wherein a transconductance of each of the ring cells is controlled by bias voltage signals applied to a selected one of the ring cells.
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
44.
NON-LINEARITIES MITIGATION INTERLEAVER FOR FORWARD ERROR CORRECTION ENCODER WITH PROBABILISTIC CONSTELLATION SHAPING
A system and method are provided for mitigating non-linear effects in high-speed optical communication systems using quadrature amplitude modulation (QAM) with probabilistic constellation shaping (PCS) and forward error correction (FEC). The transmitter includes a non-linear mitigation (NLM) interleaver, which permutes amplitude bits after FEC encoding to reduce energy variance in the transmitted signal. This targeted interleaving minimizes the impact of optical channel non-linearities, supporting various interleaving modes and advanced FEC schemes. At the receiver, a corresponding NLM de-interleaver restores the original bit order, enabling robust error correction and improved transmission performance.
A phase interpolator (PI) is controlled by digital PI-codes generated by a clock and data recovery (CDR) loop in a high-speed receiver. PI-code monitoring and correction is included in the loop to detect and correct non-linearity in the PI and/or phase errors in a delay-locked loop (DLL) that feeds into the PI. A PI-code monitor accumulates PI-codes into bins and analyzes the resulting distribution to detect non-linearity in the PI. A correction table is generated based on the observed PI-code distribution. A PI-code corrector uses this table to adjust subsequent PI-codes, compensating for non-ideal analog behavior. The architecture enables real-time monitoring and digital correction of PI and DLL errors, improving timing alignment in high-speed links with shared phase-locked loops (PLLs) and per-lane DLLs and PIs.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
46.
CORRECTION OF PHASE INTERPOLATOR AND DELAY-LOCKED LOOP ERRORS IN CLOCK AND DATA RECOVERY LOOP
A phase interpolator (PI) is controlled by digital PI-codes generated by a clock and data recovery (CDR) loop in a high-speed receiver. PI-code monitoring and correction is included in the loop to detect and correct non-linearity in the PI and/or phase errors in a delay-locked loop (DLL) that feeds into the PI. A PI-code monitor accumulates PI-codes into bins and analyzes the resulting distribution to detect non-linearity in the PI. A correction table is generated based on the observed PI-code distribution. A PI-code corrector uses this table to adjust subsequent PI-codes, compensating for non-ideal analog behavior. The architecture enables real-time monitoring and digital correction of PI and DLL errors, improving timing alignment in high-speed links with shared phase-locked loops (PLLs) and per-lane DLLs and PIs.
A new approach is proposed that contemplates system and method to support acoustic package health monitoring. A controller is configured to send a set of stimulating electrical signal waveforms to one or more acoustic transducers attached to/embedded in a package that encapsulates an electronic device. Upon receiving the set of stimulating electrical waveforms, each of the one or more acoustic transducers is configured to convert and send a set of acoustic signals through the package, receive a set of acoustic responses from the package, convert and send a set of responsive electrical signal waveforms back to the controller. The controller is configured to monitor and analyze the set of responsive electrical signal waveforms received back from the one or more acoustic transducers and send an alert if a significant deviation in the set of acoustic responses reflecting a physical change in structure of the package is detected.
Embodiments aggregate output content in a multiple queuing system. For example, an embodiment includes a plurality of input queues configured to receive data packets. In the embodiment, each respective data packet received includes a plurality of data chunks, and the plurality of data chunks for a respective data packet, when received in their entirety, define a completed data packet. The embodiment also includes an output buffer configured to maintain a list comprising respective entries of completed data packets received at each of the plurality of input queues, and a control logic configured to read the completed data packets received at at least one of the plurality of input queues based on entries in the output buffer list.
A three-dimensional (3D) integrated circuit (IC) includes a plurality of dies, a carrier die, and a plurality of channels embedded in the carrier die. The plurality of dies is stacked in the 3D IC. Each of the dies includes circuitry. The carrier die is disposed above the stacked dies in the 3D IC. The carrier die is configured to provide mechanical support to the stacked dies in the 3D IC. The plurality of channels is configured to carry a coolant to cool the 3D IC.
A circuit and corresponding method stop packet transmission, gracefully. The circuit comprises a packet buffer (PB) with at least one queue, PB write logic, and PB read logic. In response to a stop command, the PB write logic marks a start of packet (SoP) word of a packet with a synchronization indicator to produce a marked SoP word written to a queue of the at least one queue of the PB and writes, to descriptor logic, packet-delimiters of words of the packet written to the queue. The stop command identifies the queue. The PB read logic reads from the descriptor logic based on reading the marked SoP word from the queue and stops reading from the queue based on reading an active end of packet (EoP) delimiter from the descriptor logic. Transmission of the packet from the queue is stopped in a graceful manner via the reading stopped.
The present disclosure describes apparatuses and methods for implementing adaptive stream management. In aspects, an adaptive stream manager receives a read request from a host with an indication for a stream transaction of multiple reads of data from media coupled to a media controller. The adaptive stream manager determines a priority level for the stream transaction based on an identifier of the host and a quality-of-service indicator of the read request and allocates a stream identifier to the host for the read request based on the priority level determined. The stream transaction is then initiated to prefetch, from the media, respective data of at least one of the multiple reads to a cache of the media controller. By so doing, aspects of adaptive stream management can prioritize stream transactions among hosts to efficiently manage resources of the controller and improve processing of stream transactions and other data access requests.
A method includes storing a first/second set of biased exponents associated with a first/second plurality of input floating point data respectively in a memory. The first set of biased exponents defines a positive piecewise linear range associated with a positive piecewise linear approximation region of a function. The second set of biased exponents defines a negative piecewise linear range associated with a negative piecewise linear approximation region of the function. The positive/negative piecewise linear approximation regions include a first/second plurality of subregions respectively. Each subregion of the first and the second plurality of subregions includes at least one or more linear approximations. The method includes storing indices data for mapping each linear approximation with each subregion of the first and the second plurality of subregions to a unique index value. An offset and a slope for each of the unique index value are stored.
An approach is proposed to support schedule-based I/O multiplexing for scan testing of an IC. A plurality of I/Os are assigned to a plurality of blocks in the IC for scan testing based on a set of slots under a set of schedules. Each of the set of slots includes a fixed number of scan input pins/pads and scan output pins/pads of the IC. Each slot is then assigned to a specific block on the IC for the scan test until all of the slots available are utilized. The group of assigned blocks is referred to as a schedule, and all of these blocks belonging to this schedule are scan tested in parallel at the same time. The remaining blocks on the IC are also assigned to the slots until all blocks on the IC are assigned to a schedule to be scan tested.
A system and corresponding method perform verification. The system comprises a verification checker that monitors protocol messages of a coherency protocol. The coherency protocol is implemented via register-transfer level (RTL) logic of a chip to maintain cache coherency on the chip. The protocol messages are generated via the RTL logic. The system further comprises at least one memory. The verification checker performs verification of the coherency protocol based on system state stored in the at least one memory. The verification performed includes updating the system state based on the protocol messages monitored and controlling timing for the updating based on message classes. The message classes are associated with the protocol messages monitored. The verification checker reduces the likelihood that a processor design will have data inconsistency issues and can reduce time-to-market as verification implemented via the verification checker can make the verification effort more efficient.
An image is received/divided into a first/second slices, at a first convolutional layer in a CNN. A first/second tensor data for a second/third convolutional layer are generated for the first slice respectively using a kernel. The first tensor data is divided into a first/second portions. The second portion is needed by the second convolutional layer of the second slice to complement partial tensor data generated by the second slice. The second tensor data is divided into a first/second portions where the second portion is needed by the third convolutional layer of the second slice to complement partial tensor data generated by the second slice. The first/second/third convolutional layers of the first slice are processed using a subset of processing tiles. The second portion of the first tensor data and the second portion of the second tensor data generated by the first slice are stored in a memory component.
A method includes in a first iteration receiving a machine learning (ML) network model comprising a plurality of ML operations in high-level code; generating an internal representation (IR) for the ML network model, the IR mapped to one or more components in a multi-processing tile device; generating primitive functions based on the IR; generating an allocation list based on the primitive functions; determining when a tensor data within the allocation list is no longer needed; and inserting a deallocation function associated with the tensor data to the primitive functions to form an updated primitive functions, the inserting frees up a memory space associated with the tensor data when the tensor is no longer needed; and in a second iteration generating a compilation of the updated primitive functions to map the IR to the one or more components in the multi-processing device, wherein the compilation is a low-level instructions.
In one aspect, in general, a system for securely providing data for training a model comprises: a source entity comprising at least one processor and configured to: receive data configuration instructions associated with training the model, transform unprepared data from one or more data sources into prepared data based at least in part on the data configuration instructions, the prepared data comprising one or more prepared data units, and produce, using a signing module, a data package comprising the one or more prepared data units and a respective signature object associated with each of the one or more prepared data units; wherein the signing module comprises specialized circuitry configured for accelerating at least one quantum resistant computational operation.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
A network device monitors a buffer memory to detect congestion corresponding to data units received from multiple sources within the network device. In response to detecting congestion in the buffer memory, first messages are sent to the multiple sources, the first messages indicating that the multiple sources are to pause sending data units that are destined for the buffer memory. In response to determining that the congestion corresponding has ended, second messages are sent to the multiple sources, the second messages indicating that the multiple sources are to resume sending data units that are destined for the buffer memory. Circuitry limits a quantity of the second messages that are sent to the multiple sources during a particular time period to a maximum quantity such that one or more second messages are not sent to a subset of sources among the multiple sources during the time period.
An apparatus for releasing a substrate stack includes: a carrier configured to support the substrate stack; a fixture disposed on the carrier and configured to surround the substrate stack; first pins attached to the fixture and extending perpendicular to a top surface of the fixture; and a torque rod positioned between the first pins and configured to engage the first pins to apply torque on the fixture relative to the carrier to release the substrate stack from the carrier.
A multi-chip package includes first and second groups of integrated circuit (IC) chips and a transfer IC chip disposed in the multi-chip package. The transfer IC chip is communicatively interposed between the first and second groups of IC chips and is configured to transfer signals from at least a first IC chip of the first group of IC chips to at least a second IC chip of the second group of IC chips or an output interface. The output interface is configured to output first data from the multi-chip package. A first set of ultra-short reach (USR) signaling links connects the first group of IC chips to the transfer IC chip. A second set of USR signaling links connects the second group of IC chips to the transfer IC chip. Each of the USR signaling links comprises a trace length of less than one inch.
A method for producing a semiconductor device, the method includes forming a first ferromagnetic (FM) layer using a first process type. A tunnel barrier (TB) layer having a monocrystalline structure is formed over the first FM layer and using a second process type different from the first process type. A second FM layer is formed over the TB layer using the first process type.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
A single clock mesh is configured to provide a first clock signal at a first frequency. A number of divided clock signals are generated, each divided clock signal being at a frequency that is a respective integer division of the first frequency. The divided clock signals are received from a divider and output by a clock controller along with corresponding enable signals. For each divided clock, a shaped clock signal is generated. The shaped clock signal has rising edges and falling edges that algin with rising edges and falling edges of the first clock signal provided by the single clock mesh.
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
A transceiver for a network device includes clock-data recovery (CDR) circuitry that operates based on an input clock associated with a transmitted signal received by the transceiver. The CDR circuitry includes a phase interpolator (PI) core configured to process a plurality of phases of an the input clock, an inductor-capacitor (LC) tank configured to convert an output current of the PI core to an output voltage based on a frequency-dependent impedance, and control circuitry configured to tune the frequency-dependent impedance based on a frequency of the input clock.
Packet metadata for incoming packets are buffered in queue selection buffers associated with a port of a network node. Packet data for outgoing packets are buffered in a port selection buffer associated with the port. At a selection clock cycle, while a port scheduler of the network node selects a subset of the packet data for a subset of the outgoing packets from the port selection buffer, a queue scheduler of the port concurrently selects a subset of the packet metadata for a subset of the incoming packets from the queue selection buffers and adds new packet data for new outgoing packets to the port selection buffer of the port. The new packet data are derived based at least in part on the subset of the packet metadata for the subset of the incoming packets.
H04L 47/625 - Queue scheduling characterised by scheduling criteria for service slots or service orders
H04L 47/628 - Queue scheduling characterised by scheduling criteria for service slots or service orders based on packet size, e.g. shortest packet first
65.
OPERATIONAL STATISTICS ENCODING AND MAPPING IN NETWORK NODES
A pre-scaled accumulated byte count of a port of a network node over a sampling period is scaled with a scaling factor to generate a scaled accumulated byte count. The pre-scaled accumulated byte count represents a total number of bytes in packets transferred by the port. The scaling factor represents a first port-specific attribute of the port and scales a port-specific maximum throughput of the port to a specific maximum port throughput of the network node. An iterative vector encoding method is applied to the scaled accumulated byte count to generate an encoded bit vector comprising bits respectively ordered bit positions. Each set bit of the encoded bit vector represents a respective weighted value of port utilization of the port. The encoded bit vector is stored, at a map location, in an operational statistics map.
A system includes a trace generator module, simulators, a selector module, and an agentic AI module (analytical/decision making/execution agents). The trace generator module receives a workload data and generates a trace data. The selector module receives configuration data associated with another system to be simulated and selects a simulator to a run simulation. The simulator generates a simulation data. The analytical agent analyzes the simulation data to generate actionable insights. The decision making agent receives the actionable insights and generates recommendation associated with one or more modification to be made.
An electronic device includes a substrate and a semiconductor die formed over the substrate, the semiconductor die includes: (i) a core region containing at least logic circuitry, and (ii) a beachfront region surrounding at least part of the core region, the beachfront region includes a plurality of interface circuits configured to exchange signals between the core region and at least an external device, and the semiconductor die has an irregular perimeter.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
Methods and apparatus for workflow processing are disclosed. In an embodiment, a method includes receiving a workflow queue entry (WQE) that includes a key value and searching a plurality of memory tables for an address that contains the key value. When the address that contains the key value is found, obtaining a first queue identifier from the address. When the address that contains the key value is not found, storing the key value and a second queue identifier at a selected address in a selected memory table. The method also includes storing the WQE in an aggregation queue identified by one of the first and second queue identifiers, updating a count associated with the aggregation queue, and when the count reached a selected level, aggregating all WQE entries in the aggregation queue to form a vector WQE.
A method for checking integrity of data propagated, in either direction, between a first data link having a first data width and a first data speed, and a plurality of second data links each of which has a second data width narrower than the first width and a second data speed slower than the first speed, includes propagating data with a known pattern (a) from the first link to the plurality of second links, or (b) from the plurality of second links to the first link, selecting bits when transitioning (a) from the first link to each link in the plurality of second links, or (b) from each link in the plurality of second links to the first link, in a manner that preserves the known pattern, and checking for the known pattern when receiving the propagated data at (a) the plurality of second links, or (b) the first link.
A first intermediate network device among one or more intermediate network devices performs link training on a first network link extending between the first intermediate network device and a first host network device. The first intermediate network device or a second intermediate network device among the one or more intermediate network devices performs link training on a second network link extending between the first intermediate network device or the second intermediate network device and a second host network device. The one or more intermediate network devices determine when link training of the first network link and the second network link has been completed, and transmit respective link training completion indications to the first host network device and the second host network device. Transmission of the respective link training completion indications includes delaying transmission until link training of both the first network link and the second network link has been completed.
A semiconductor device, includes: (a) a substrate, (b) a gate electrode, disposed on a surface of the substrate, and including a plate, orthogonal to the surface, and having openings, a longest axis of the openings is orthogonal to the surface, and (c) elements having a shape that fits in the openings, the elements (i) are orthogonal both to the surface and to the gate electrode, (ii) extend through the openings, and (iii) are surrounded by the gate electrode and spaced away from the surface, the elements including: a first section that is located on a first side of the gate electrode and serves as a source; and a second section that is located on a second side of the gate electrode and serves as a drain, the gate electrode configured to control movement of charge carriers between the source and the drain in response to an applied electrical signal.
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
A Dynamic PHY-Level Collision Avoidance (DPLCA) system, method and device for implementing and operating an Ethernet network using dynamic physical layer node ID assignments and operating according to a communication protocol that defines repeating time cycles and specifies that each of multiple communication devices is provided a respective transmit opportunity in each time cycle, which enables dynamic addition or deletion of network nodes via assignment of Node IDs.
A Dynamic PHY-Level Collision Avoidance (DPLCA) system, method and device for implementing and operating an Ethernet network using dynamic physical layer node ID assignments and operating according to a communication protocol that defines repeating time cycles and specifies that each of multiple communication devices is provided a respective transmit opportunity in each time cycle, which enables dynamic addition or deletion of network nodes via assignment of Node IDs.
A Dynamic PHY-Level Collision Avoidance (DPLCA) system, method and device for implementing and operating an Ethernet network using dynamic physical layer node ID assignments and operating according to a communication protocol that defines repeating time cycles and specifies that each of multiple communication devices is provided a respective transmit opportunity in each time cycle, which enables dynamic addition or deletion of network nodes via assignment of Node IDs.
A method of Link Synchronization (LS) signal generation is robust to the presence of the clock frequency offset and is used to enable LS function in crystal-less mode of operation. In the method of LS signal generation, the binary chirp (linearly frequency modulated) signal is used.
An electro-optical system includes an optical source, an optical modulator, a first photodetector (PD), a second PD, and a control circuit. The optical source generates an optical signal. The optical modulator modulates the optical signal. The first PD detects the optical signal at an input to the optical modulator. The second PD detects the modulated optical signal at an output of the optical modulator. The control circuit sends to the optical modulator a modulation bias signal that includes a tone, determines a DC power ratio between the modulated optical signal detected by the second PD, and the optical signal detected by the first PD, and sets a bias of the optical modulator according to both (i) the DC power ratio and (i) an amplitude of a second harmonic of the tone in the modulated optical signal at the output of the optical modulator.
A Dynamic PHY-Level Collision Avoidance (DPLCA) system, method and device for implementing and operating an Ethernet network using dynamic physical layer node ID assignments and operating according to a communication protocol that defines repeating time cycles and specifies that each of multiple communication devices is provided a respective transmit opportunity in each time cycle, which enables dynamic addition or deletion of network nodes via assignment of Node IDs.
A Dynamic PHY-Level Collision Avoidance (DPLCA) system, method and device for implementing and operating an Ethernet network using dynamic physical layer node ID assignments and operating according to a communication protocol that defines repeating time cycles and specifies that each of multiple communication devices is provided a respective transmit opportunity in each time cycle, which enables dynamic addition or deletion of network nodes via assignment of Node IDs.
An interface reduces the impact of power fluctuations on data transmissions includes F forward error correction (FEC) encoders. A transmit (Tx) FEC mapping module is configured to receive Q bits corresponding to an info-message on a parallel input bus and map the Q bits to D data portions each corresponding to one of the F FEC encoders, S slices, and B time slots for time division multiplexing (TDM). Each of the F FEC encoders is configured to generate P/F FEC parity bits for D/F data portions. The interface includes S Tx parallel registers corresponding to the S slices, respectively and S sets of L lanes. Each of the S Tx parallel registers is connected to one of the S sets of L lanes and is configured to transmit D/S data portions and P/S FEC parity bits over a communications channel using TDM and the B time slots.
In an optical multiplexer, a first Mach-Zehnder interferometer (MZI) generates a first intermediate optical signal based on i) a first input optical signal at a first wavelength, and ii) a second input optical signal at a second wavelength. A second MZI generates a second intermediate optical signal based on i) a third input optical signal at a third wavelength, and ii) a fourth input optical signal at a fourth wavelength. A polarization combiner rotator (PCR) is coupled to the first MZI and the second MZI. The PCR generates an output optical signal based on i) the first intermediate optical signal received at a first input of the PCR, and ii) the second intermediate optical signal received at a second input of the PCR. The output optical signal includes the first input optical signal, the second input optical signal, the third input optical signal, and the fourth input optical signal.
H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
G02B 6/27 - Optical coupling means with polarisation selective and adjusting means
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
G02B 6/30 - Optical coupling means for use between fibre and thin-film device
G02B 6/42 - Coupling light guides with opto-electronic elements
A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.
A germanium-on-silicon avalanche photodetector includes a silicon device layer of a silicon-on-insulator substrate having a central region characterized by modest-heavy n+ doping state between a first electrode region and a second electrode region in heavy n++ doping state; a first sub-layer of the central region modified to nearly neutral doping state and located from a first depth down to a second depth below a top surface of the silicon device layer; a second sub-layer of the central region modified to modest p doping state embedded from the top surface down to the first depth to interface with the first sub-layer; a layer of germanium with a bottom side attached to the top surface of the second sub-layer; and a third sub-layer embedded into a top side of the layer of germanium, characterized by heavy p++ doping state.
H10F 30/225 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes
A circuit and corresponding method enable bitcoin mining in a blockchain network. The circuit comprises a nonce generator that generates a nonce value, on a cycle-by-cycle basis, and changes only one binary digit of the nonce value per cycle. The circuit further comprises a hash engine that inserts, on the cycle-by-cycle basis, the nonce value into a block header of a block candidate and generates a digest by applying a hash function to the block header. The block header includes a representation of a target value. The circuit further comprises a validator that compares, on the cycle-by-cycle basis, the digest to the target value. In an event the digest satisfies the target value, the validator submits the block candidate to the blockchain network, causing newly minted bitcoin to be mined from the blockchain network. Changing only one binary digit of the nonce value, per cycle, reduces the circuit's power consumption.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06Q 20/06 - Private payment circuits, e.g. involving electronic currency used only among participants of a common payment scheme
H04L 9/00 - Arrangements for secret or secure communicationsNetwork security protocols
84.
Methods and apparatus for distributing baseband signal processing of fifth generation (5G) new radio uplink signals
Methods and apparatus for distributing baseband signal processing of fifth generation (5G) new radio uplink signals. In one embodiment, an apparatus includes a radio frequency (“RF”) interface, direct current (“DC”) remover, time domain (“TD”) measurement circuit, and a compression block. The RF interface is able to receive uplink transmissions containing data from a communication network. While the DC remover generates DC adjusted signals by removing DC bias from the received uplink transmissions, the TD measurement circuit is configured to measure a TD power level associated with the DC adjusted signals. The compression block, in one aspect, is operable to generate compressed uplink base band packets in response to the uplink transmissions and the TD power level. The compressed packets is subsequently transmitted over a transmission medium to the central office.
An optical device for enabling more flexible and precise control of spectral reflectance in a selected wavelength range having a maximal wavelength (λmax) and a minimal wavelength (λmin). The device includes a first Mach-Zehnder interferometer (MZI), including first and second legs having a tunable first optical pathlength difference (OPD) greater than 2×λmax, and a second MZI, coupled in series with the first MZI and including third and fourth legs having a tunable second OPD less than 2×λmin. An optical coupler is configured to direct an input optical signal in the selected wavelength range into the first and second MZIs and to output a reflected optical signal from the first and second MZIs. A controller is configured to adjust the first and second tunable OPDs to control the spectral reflectance of the reflected output optical signal.
H01S 3/105 - Controlling the intensity, frequency, phase, polarisation or direction of the emitted radiation, e.g. switching, gating, modulating or demodulating by controlling the mutual position or the reflecting properties of the reflectors of the cavity
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
The present disclosure describes apparatuses and techniques for implementing a Quality of Service-enabled (QoS-enabled) storage controller. In various aspects, a QoS manager of a storage controller or hardware accelerator can implement credit-based policies for servicing inbound input/output (I/O) commands of a host. In some cases, the QoS manager implements a queue-based credit policy or function-based credit policy to manage traffic across host submission queues or functions of the storage controller. In a data phase of command processing, the QoS manager may segment or chunk an I/O command based on a size threshold to provide I/O command segments of similar amounts of respective data for processing by a direct memory access (DMA) engine of the storage controller. By so doing, the QoS manager can manage entity-based data traffic such that no entity within or associated with the storage controller exceeds its allocated bandwidth.
A first switching device in a switching system that includes a plurality of switching devices arranged in a partial mesh receives a packet directed to a second switching device in the switching system. The first switching device accesses a forwarding table to select a link via which to transmit the packet. The link is selected from among i) at least one destination link coupled to the first switching device, the destination link configured to only carry traffic, egressing the first switching device, that terminates at a next switching device directly coupled to the first switching device, and ii) at least one source link coupled to the first switching device, the source link configured to only carry traffic, egressing the first switching device, that is sourced, in the switching system, by the first switching device. The first switching device transmits the packet, via the selected link, towards the second switching device.
Methods and apparatus for control bit detection. In an exemplary embodiment, a method includes receiving a descrambled LLR sequence, decoding the descrambled LLR sequence to generate decoded bits, processing the decoded bits to generate a second LLR sequence, correlating the descrambled LLR sequence and the second LLR sequence to generate a correlated output, and detecting a discontinuous transmission (DTX) when the correlated output is less than a threshold level.
An electronic device, includes: (i) a processing chiplet configured to process data and having a first side and a second side, (ii) one or more first static random-access memory (SRAM) chiplets disposed on the first side of the processing chiplet and configured to store a first portion of the data, (iii) one or more second SRAM chiplets disposed on the second side of the processing chiplet and configured to store a second portion of the data, (iv) one or more first electrical terminals disposed on the first side of the processing chiplet and configured to electrically connect between the first side of the processing chiplet and the first SRAM chiplets, and (v) one or more second electrical terminals disposed on the second side of the processing chiplet and configured to electrically connect between the second side of the processing chiplet and the second SRAM chiplets.
In a communication network operating according to a communication protocol that defines a link establishment procedure having a training procedure, a first communication device performs the link establishment procedure with a second communication device. The first communication device negotiates one or more new parameter values for the link establishment procedure that are different than one or more mandated parameter values specified by the communication protocol. During the link establishment procedure, the first communication device uses the one or more new parameter values instead of using the one or more mandated parameter values specified by the communication protocol. The one or more new parameter values include at least one new initial PHY parameter value for starting the training procedure that is different as compared to at least one default initial PHY parameter value for starting the training procedure specified by the communication protocol.
A system includes a plurality of antennas that receive wireless data. A first memory component stores a first plurality of resource blocks and associated resource elements for the received data associated with a first antenna of the plurality of antennas in a first row of the first memory component. The first memory component stores the first plurality of resource blocks for a second antenna of the plurality of antennas in a second row of the first memory component. A conversion unit receives the stored first plurality of resource blocks from the first memory component and formats the stored first plurality of resource blocks and associated resource elements to arrange a first resource block of the first plurality of resource blocks from the first and the second antennas in a same row to form a formatted data. A second memory component is configured to store the formatted data.
A method includes receiving one or more configuration parameters associated with a neural processing unit (NPU), wherein the one or more configuration parameters defines a number of processing tiles within the NPU, and wherein a processing tile includes a processing element of a first type configured to perform a dense operation, a processing element of a second type configured to perform a sparse operation, and an on-chip memory (OCM) associated therewith; and automatically generating the NPU based on the one or more configuration parameters and further based on a hardware descriptive language (HDL).
A method of generating a physical unclonable function (PUF) key uses a value read from an array of bitcells in rows defined by pairs of true and complement wordlines and columns defined by pairs of true and complement bitlines, each bitcell having a pull-up network coupled to a complement wordline and to the true and complement bitlines, and having a pull-down network coupled to a true wordline and to the true and complement bitlines. A pull-up network of a first bitcell is activated by the complement wordline. A pull-down network of a second bitcell is activated by the true wordline. A first value based on the pull-up network of the first bitcell and the pull-down network of the second bitcell is read using a sense amplifier coupled to a true bitline and a complement bitline. A PUF key is generated using the first value.
A method for fabricating electronic devices includes applying an array of non-uniformly sized spots of solder material on a substrate. An average size of the spots is larger in a center portion of the array than in a peripheral portion of the array. A die is soldered to the substrate using the array.
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
AFE stages using positively coupled inductors and associated systems, components, and devices are disclosed. An example AFE component that may be included in an AFE stage of a system includes a differential circuit comprising a positive signal branch and a negative signal branch. The negative signal branch includes a first input transistor (e.g., a first common-source amplifier) and a first inductor coupled to a source terminal of the first input transistor. The positive signal branch includes a second input transistor (e.g., a second common-source amplifier) and a second inductor coupled to a source terminal of the second input transistor. A coupling coefficient of the first inductor and the second inductor is positive and sufficiently large to ensure that the common-mode impedance of the coupled inductors is greater than their differential-mode impedance.
A first network device determines a set of one or more first paths through the network switching system for forwarding a packet to a second network device in the network switching system, including determining the set of one or more first paths from amongst minimal paths through the network switching system. The first network device determines a set of one or more second paths through the network switching system for forwarding the packet to the second network device, including determining the set of one or more second paths from amongst non-minimal paths through the network switching system. The first network device selects one of the set of one or more first paths, and the set of one or more second paths for forwarding the packet through the network switching system, including sometimes selecting the set of one or more second paths for forwarding the packet through the network switching system.
A pluggable transceiver module is disclosed and includes first and second ends, lower and upper housings, and a thermal energy generating component. The first end plugs into a network device. The second end is opposite the first end and is located external to the network device when the first end is plugged into the network device. The lower housing enhouses a printed circuit board. The upper housing includes a heat sink and floats above the lower housing such that the upper housing is not fastened to and/or resting on the lower housing. At least side portions of the upper housing do not contact sides of the lower housing. The upper housing is held in place relative to the lower housing. A thermal energy generating component is mounted on the printed circuit board and supports the first heat sink, which dissipates thermal energy received from the thermal energy generating component.
UNIVERSITY OF VERMONT AND STATE AGRICULTURAL COLLEGE (USA)
Inventor
Hunt-Schroeder, Eric
Xia, Tian
Abstract
A method of operating a chip as an entropy source for generating a physical unclonable function (PUF) key includes: arranging in the chip a pre-amplifier array of bitcells in respective rows defined by respective pairs of true and complement wordlines and in columns defined by respective pairs of true and complement bitlines; reading, by a sense amplifier, a preferred state from a bitcell along a selected pair of the pairs of true and complement wordlines, where the pre-amplifier array of bitcells comprises the bitcell; performing feedback-reinforced accelerated aging via control circuitry in the chip including, based on the read preferred state, applying a stress condition that causes an accelerated aging effect including biasing the bitcell to the preferred state to reinforce the preferred state in the bitcell; subsequent to performing the feedback-reinforced accelerated aging, reading a value from the bitcell; and generating a PUF key using the value.
A recursive divide operation is performed on a logical address for a predetermined number of iterations. On each iteration of the recursive divide operation, a respective component of a physical address represented by the logical address is derived. The physical address corresponding to the logical address is the constructed from the derived components.
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 7/72 - Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radixComputing devices using combinations of denominational and non-denominational quantity representations using residue arithmetic
A system includes a component configured to send data in a first data format. The system includes a direct memory access (DMA) engine configured to receive the data in the first data format and convert the first data format to a second data format, wherein the second data format is associated with a data format of a machine learning (ML) hardware, wherein the second data format is different from the first data format. The ML hardware is configured to receive the data in the second format and perform at least one ML operation on the received data in the second format. The received data in the second data format is stored on an on-chip memory (OCM) of the ML hardware.
G06N 20/10 - Machine learning using kernel methods, e.g. support vector machines [SVM]
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
