A system includes a component configured to send data in a first data format. The system includes a direct memory access (DMA) engine configured to receive the data in the first data format and convert the first data format to a second data format, wherein the second data format is associated with a data format of a machine learning (ML) hardware, wherein the second data format is different from the first data format. The ML hardware is configured to receive the data in the second format and perform at least one ML operation on the received data in the second format. The received data in the second data format is stored on an on-chip memory (OCM) of the ML hardware.
G06N 20/10 - Machine learning using kernel methods, e.g. support vector machines [SVM]
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
A recursive divide operation is performed on a logical address for a predetermined number of iterations. On each iteration of the recursive divide operation, a respective component of a physical address represented by the logical address is derived. The physical address corresponding to the logical address is the constructed from the derived components.
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 7/72 - Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radixComputing devices using combinations of denominational and non-denominational quantity representations using residue arithmetic
An integrated circuit (IC) package comprises: at least two substrate sub-units configured to adjoin each other to form a substrate, each substrate sub-unit comprising electrical traces configured to couple i) to corresponding terminals of an integrated circuit component and ii) to corresponding terminals of an interposer or a printed circuit board; at least one coupler configured to: 1) align the substrate sub-units and 2) join the substrate sub-units together to form the substrate from the at least two substrate sub-units; and, an integrated circuit having terminals and configured to electrically couple to terminals of the substrate formed of at least two substrate sub-units.
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
Interface circuitry for an active cable includes a first active cable interface configured for coupling to a first end of the active cable, and a second active cable interface configured for coupling to a second end of the active cable. The first active cable interface includes first transmitter circuitry including linear driving circuitry or non-linear driving circuitry, and first receiver circuitry including linear receiving circuitry or non-linear receiving circuitry. The second active cable interface includes second transmitter circuitry including linear driving circuitry when first transmitter circuitry includes non-linear receiving circuitry, and non-linear driving circuitry when first transmitter circuitry includes linear receiving circuitry. The second receiver circuitry includes linear receiving circuitry when first receiver circuitry includes non-linear driving circuitry, and non-linear receiving circuitry when first receiver circuitry includes linear driving circuitry.
A system includes a first and a second processing tiles including a first and a second processing elements and on-chip memory (OCMs) respectively. The first and the second OCM are partitioned. A first partition of the first OCM receives and locally stores a first and a second set of data associated with a first operation and a second operations respectively and accessed by the first processing element for processing the first and the second operations. The second OCM receives and locally stores a third set of data associated with a third operation for access by the second processing element for processing the third operation. The first processing tile processes the first operation based on the first set of data as the second processing element is processing the third operation based on the third set of data while a fourth set of data is being received by the first processing tile.
A first optical module includes an optical transceiver and a chip. The optical transceiver, subsequent to completion of link training of an in-band transmission link between the first optical module and a host device, waits for a second optical module to come up including transmitting a first awake signal from the first optical module to the second optical module, and receives a second awake signal from the second optical module when the second optical module is up. The chip i) based on a first out-of-band signal transmitted via an out-of-band link, performs the link training of the in-band transmission link independently of an in-band reception link between the first optical module and the host device, and ii) based on the second awake signal and a second out-of-band signal transmitted via the out-of-band link, performs link training of the in-band reception link independent of the in-band transmission link.
A pilot-assisted fiber length estimation (FLE) technique estimates chromatic dispersion for optical signals. The pilot-assisted FLE technique is agnostic to the modulation format of the optical payload and is resilient to polarization effects, bandwidth limitations, and signal shaping, thus enabling consistent performance across a wide range of operating conditions. A transmitter periodically inserts a known pilot sequence into an optical signal, and a receiver processes the pilot sequence to estimate the length of the optical fiber, or to estimate chromatic dispersion of the optical fiber, which is related to the fiber length.
H04B 10/079 - Arrangements for monitoring or testing transmission systemsArrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
A multi-chip module includes an interposer including first and second interposer layers each including a first plurality of contacts and a second plurality of contacts. An embedded die includes a first phase-locked loop (PLL) circuit and arranged in the interposer. A first die includes a first die layer with a third plurality of contacts connected to the first plurality of contacts of the second interposer layer and a second die layer including at least one of a first clock buffer and a first circuit. A second die includes a first die layer with a fourth plurality of contacts connected to the second plurality of contacts of the second interposer layer and a second die layer including at least one of a second clock buffer and a second circuit. A reference clock is connected to the first PLL circuit through the first interposer layer and the second interposer layer.
H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
A PHY device for transmitting data over a communication channel comprises a distribution circuit and a failure management circuit. The distribution circuit is configured to receive data from a host via a first plurality of lanes at a first data rate, and distribute the data into a second plurality of lanes for transmission over the communication channel. The failure management circuit is configured to monitor the communication channel, and detect failure of one of the second plurality of lanes. Subsequent to the detected failure, the distribution circuit is configured to receive the data from the host through the first plurality of lanes at a second data rate that is less than the first data rate, and to distribute the data received from the host through the first plurality of lanes at the second data rate into remaining lanes of the second plurality of lanes at the first data rate.
Methods for chiplet communication and accompanying chiplets, integrated circuits, design structures are disclosed herein. According to an embodiment, a method of chiplet communication includes receiving, at a chiplet, a command via a serial peripheral communication interface. The method further includes parsing, by the chiplet in an uninitialized state, the command into a packet associated with an operation performable by the chiplet and performing, by the chiplet in the uninitialized state, the operation based on the command parsed. Chiplets and chiplet communication as described may be useful for configuring or initializing out of reset chiplets using a secondary or peripheral serial interface, for example, for extra short range link bring-up or peripheral component interface express initialization.
A method for bundling data packets in a single transmission job including creating a job descriptor for the transmission job based on at least one of a packet mode for the transmission job and a bundling mode for the transmission job, the job descriptor comprising a pointer to a read DMA section, the read DMA section including at least one read DMA command for fetching all of the data packets; storing the job descriptor in a memory device; enqueuing a job command associated with the job descriptor job to a hardware scheduler; and processing the job command by a transmission module by retrieving the job descriptor from the memory device; executing the at least one DMA command to fetch all of the data packets; and transmitting the data packets via the data communications system in accordance with the at least one of the packet mode and the bundling mode.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
A multi-chip module includes an interposer including first and second interposer layers each including a first plurality of contacts and a second plurality of contacts. An embedded die includes a first phase-locked loop (PLL) circuit and arranged in the interposer. A first die includes a first die layer with a third plurality of contacts connected to the first plurality of contacts of the second interposer layer and a second die layer including at least one of a first clock buffer and a first circuit. A second die includes a first die layer with a fourth plurality of contacts connected to the second plurality of contacts of the second interposer layer and a second die layer including at least one of a second clock buffer and a second circuit. A reference clock is connected to the first PLL circuit through the first interposer layer and the second interposer layer.
Integrated optical drivers for optical interconnect technologies and associated optical communication systems, components, and devices are disclosed. An example integrated optical driver may include a first input terminal and a second input terminal, a first transconductance transistor coupled with the first input terminal, a second transconductance transistor coupled with the second input terminal, a first cascode circuit coupled with a drain terminal of the first transconductance transistor, and a second cascode circuit coupled with a drain terminal of the second transconductance transistor and further coupled with the first cascode circuit.
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A method for bundling data packets in a single transmission job including creating a job descriptor for the transmission job based on at least one of a packet mode for the transmission job and a bundling mode for the transmission job, the job descriptor comprising a pointer to a read DMA section, the read DMA section including at least one read DMA command for fetching all of the data packets; storing the job descriptor in a memory device; enqueuing a job command associated with the job descriptor job to a hardware scheduler; and processing the job command by a transmission module by retrieving the job descriptor from the memory device; executing the at least one DMA command to fetch all of the data packets; and transmitting the data packets via the data communications system in accordance with the at least one of the packet mode and the bundling mode.
A method for recovering a clock from input data, in a deserializer that couples a transmission medium to receive circuitry of a data transceiver, includes operating, in a first clock recovery loop, on equalized input data from a data recovery loop to provide a first timing error signal, operating, in a second clock recovery loop, on unequalized input data to provide a second timing error signal, combining the first and second timing error signals, and deriving a recovered clock signal from the combined first and second timing error signals using an oscillator circuit. Combining the first and second timing error signals may include operating on the first and second timing error signals in a manner that filters the first timing error signal to remove low-frequency components including adaptation errors introduced by the data recovery loop, and that filters the second timing error signal to remove high frequency components including jitter.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 7/00 - Arrangements for synchronising receiver with transmitter
16.
Substrate embedded optical chiplet for integrated photonic interconnects
An optoelectronic device includes: (a) a substrate having (i) a surface, and (ii) a recess formed in the substrate that extends from the surface into the substrate, (b) an integrated circuit (IC) chip facing the surface of the substrate, (c) an optical connector mounted on the substrate, and (d) an optical chiplet embedded within the recess of the substrate. The optical chiplet being configured to exchange (i) optical signals with the optical connector, and (ii) electrical signals with the integrated circuit (IC) chip, and to convert between the optical signals and the electrical signals.
A cryptographic system includes a block transfer engine and a crypto map unit. The block transfer engine is configured to receive a plurality of encrypted counter values and a plurality of packet attributes. The block transfer engine is further configured to determine a subset of encrypted counter values from the plurality of counter values that is to be used to encrypt a subset of incoming packets from a plurality of incoming packets. Encrypted counter values other than the subset of encrypted counter values are stored for later encryption use.
A cryptographic system includes a block transfer engine and a crypto map unit. The block transfer engine is configured to receive a plurality of encrypted counter values and a plurality of packet attributes. The block transfer engine is further configured to determine a subset of encrypted counter values from the plurality of counter values that is to be used to encrypt a subset of incoming packets from a plurality of incoming packets. Encrypted counter values other than the subset of encrypted counter values are stored for later encryption use.
The crypto map unit is configured to receive the plurality of incoming packets and the subset of encrypted counter values from the block transfer engine. The crypto map unit is further configured to encrypt the subset of incoming packets from the received plurality of incoming packets with the subset of encrypted counter values.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
H04L 9/14 - Arrangements for secret or secure communicationsNetwork security protocols using a plurality of keys or algorithms
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
09 - Scientific and electric apparatus and instruments
Goods & Services
Downloadable computer software for use in monitoring circuit compliance with CMIS; Downloadable telemetry and data analytics software; Downloadable computer software for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Downloadable computer software for use in monitoring circuit compliance with CMIS; Downloadable telemetry and data analytics software; Downloadable computer software for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems. Design and development of software; Non-downloadable computer software for use in monitoring circuit compliance with CMIS; Computer chip design services; Non-downloadable telemetry and data analytics software; Non-downloadable computer software for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
semiconductors; Microprocessors; Semiconductor chips; Semiconductor computer chips; Semiconductor integrated circuits; integrated circuits; Electronic chips for use in the manufacture of integrated circuits; downloadable computer software and firmware for controlling and using integrated circuits; processors, namely, data processors for downloadable computer programs using artificial intelligence, data processors for computer network servers and central gateways deployed on a network, general purpose computer data processors, data processors for high-performance computing, data processors for digital signal, data processors, programmable data processors, data processors for downloadable audio and video files; digital signal processors; ethernet transceivers; wireless integrated circuits, namely transceivers and digital signal processors; integrated circuits for controlling solid state drives; amplifiers, namely, transimpedance amplifiers; semiconductor devices, namely retimers; electronic circuits; microchips; photonic microchips; Electronic and optical communications instruments and components, namely, optical transmitters; Electronic and optical communications instruments and components, namely, digital transmitters; Electronic and optical communications instruments and components, namely, optical transceivers; power amplifiers. design and development of computer software and hardware for the design and manufacture of semiconductors; design of computer hardware and integrated circuits; designing semiconductors, semiconductor chips and chip sets, integrated circuits, integrated circuit chips, integrated circuit chip sets, and software for others; design and development of computer software and hardware for the design and manufacture of semiconductor devices, namely digital signal processors, transceivers, amplifiers, retimers and microprocessors.
Memory free list latency bounding techniques may optimize the performance of parallel storage devices. In one example, a memory controller includes one or more registers that include pointers to free lists that include addresses of free locations in the memory devices. In various example, each free list corresponds to a memory device, memory module, or pseudo channel. The memory controller receives data to store in memory. The memory controller splits the data into data chunks, where a data chunk has a size that is greater than a memory access size. The memory controller then determines which free lists include addresses to free locations and selects one or more memory devices to store the data chunks based on the free lists. In one example, at least one of the memory devices is selected to store data chunks based on how recently the memory device was selected.
Short block data accumulation techniques with a storage accelerator device may be used to optimize the handling of read requests for data having a size smaller than a block. In one example, a requester (e.g., host) may aggregate requests to read data having a size smaller than a block and send, to a storage accelerator device, a single command (e.g., an NVMe vendor specific command) with information identifying the multiple read requests. The accelerator may then generate the individual block read requests to the SSDs. The storage accelerator may then accumulate the data returned from the storage devices in response to the multiple read requests into a single regular block and send the accumulated data back to the host.
Methods and systems for executing a communication protocol are provided. One method includes receiving, by a security module of a first computing device, an API call to authenticate a certificate received from a second computing device to establish a communication session between the computing devices; selecting, by the security module, an authentication module to authenticate the certificate; generating, by an encryption module of the security module, a shared secret key for the communication session based on a private key of the first computing device and a public key of the second computing device; encrypting, by the encryption module, the shared secret key using an algorithm negotiated between the first computing device and the second computing device; generating, by the security module, an encrypted message for the second computing device; and transmitting, by the first computing device, the encrypted shared secret key and message to the second computing device.
An optical device includes a substrate, at least first and second metal traces disposed on the substrate to define an electrical transmission line, and an optical waveguide, which is disposed on the substrate along a serpentine path passing between the metal traces, and which includes at least first and second electrooptical modulation segments, which are arranged in series along the optical waveguide between the first and second metal traces and are separated by bends in the serpentine path. The device further includes a plurality of electrode pairs, each electrode pair including first and second electrodes connected respectively to the first and second metal traces and disposed in mutual proximity on opposing sides of one of the electrooptical modulation segments, including at least first electrode pairs disposed on opposing sides of the first electrooptical modulation segment and second electrode pairs disposed on opposing sides of the second electrooptical modulation segment.
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference
25.
METHOD AND SYSTEM TO SUPPORT INPUT TENSOR OPTIMIZATION FOR TRANSPOSED CONVOLUTION FOR MACHINE LEARNING
A new approach is proposed that contemplates system and method to support efficient implementation of transposed convolution for machine learning (ML). Under the proposed approach, input data/tensor to a transposed convolution operation is optimized before the transposed convolution operation and each of a plurality of original kernels used for the transposed convolution operation is divided into a plurality of smaller sub-kernels. A plurality of direct sub-convolutions are then performed by sequentially applying each of the plurality of sub-kernels of each of the original kernels over the optimized input tensor without flattening either the input tensor or the plurality of sub-kernels. The output from the sub-convolutions using the plurality of sub-kernels are then combined as the final output tensor for each of the original kernels for the transposed convolution operation.
A new approach is proposed that contemplates system and method to support efficient implementation of transposed convolution for machine learning (ML). Under the proposed approach, input data/tensor to a transposed convolution operation is optimized before the transposed convolution operation and each of a plurality of original kernels used for the transposed convolution operation is divided into a plurality of smaller sub-kernels. A plurality of direct sub-convolutions are then performed by sequentially applying each sub-kernel of the plurality of sub-kernels of each of the original kernels over the optimized input tensor without flattening either the input tensor or the plurality of sub-kernels. The output from the sub-convolutions using the plurality of sub-kernels are then combined as the final output tensor for each of the original kernels for the transposed convolution operation.
An electronic device, includes (a) a semiconductor substrate, (b) a plurality of transistors formed on a first side of the semiconductor substrate, and (c) a first set of metal interconnect layers formed on the first side of the semiconductor substrate, and a second set of metal interconnect layers formed on a second side of the semiconductor substrate opposite to the first side, each of the first set and the second set of metal interconnect layers includes (i) one or more layers whose electrical resistance is in a first range of resistances, and (ii) at least one layer whose electrical resistance is in a second range of resistances, lower than the first range.
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/552 - Protection against radiation, e.g. light
28.
Reconfigurable streaming processor for security computations
A computing system includes a streaming engine and a graph core. The streaming engine includes an array of compute units (CUs), an array of crossbar switches, and a configurable interconnect circuit. The CUs perform logical operations on operands. The crossbar switches forward outputs of one or more CUs to inputs of one or more neighboring CUs. The configurable interconnect circuit forwards an output of at least one of the CUs to an input of at least one of the crossbar switches. The graph core programs the streaming processor to perform a security computation by selectively configuring the CUs to perform a plurality of respective logical operations in a programmable order to define a flow of logical operations to be performed by the CUs that effects the security computation, and configuring the crossbar switches and the interconnect circuit to perform the logical operations by traversing the CUs according to the flow.
An optical modulator includes a slab of silicon, a first layer of silicon disposed on the slab, and a second layer. The second layer includes a mixture of germanium and silicon. The second layer is at least partially disposed on the first layer. The second layer includes an intrinsic portion of the mixture and further includes first and second doped portions disposed on opposite sides of the intrinsic portion. The intrinsic portion and the first and second doped portions form an active region of the optical modulator.
G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
30.
Null data packet announcement frame for NDP ranging
A first communication device generates a null data packet announcement (NDPA) frame for use in a ranging measurement exchange session with a second communication device. The NDPA frame includes a station information field corresponding to the second communication device, the station information field having i) an 11-bit association identifier (AID) subfield that includes an identifier of the second communication device, ii) a disambiguation subfield set to a value that prevents a third communication device operating according to a second communication protocol from improperly processing the NDPA frame, and iii) sixteen bits between the AID subfield and the disambiguation subfield. The first communication device transmits the NDPA frame to the second communication device as part of the ranging measurement exchange session. After transmitting the NDPA frame, the first communication device transmits a null data packet (NDP) to the second communication device as part of the ranging measurement exchange session.
An optical driver device for driving a light emitting device includes a high-frequency current driver including a first switching circuit configured to generate a first portion of modulation current for driving the light emitting device. The first portion of modulating current is provided to the light emitting device via a coupling capacitor. The high-frequency current driver is configured in current-mode driver topology that utilizes a first current source for generating the first portion of the modulation current. The optical driver device further includes a second switching circuit configured to generate a second portion of modulation current for driving the light emitting device. The second portion of modulation current is provided to the light emitting device via a path that bypasses the coupling capacitor. The low-frequency current driver configured in current-mode driver topology that utilizes a second current source for generating the second portion of modulation current.
H01S 3/10 - Controlling the intensity, frequency, phase, polarisation or direction of the emitted radiation, e.g. switching, gating, modulating or demodulating
H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
H01S 5/02251 - Out-coupling of light using optical fibres
H01S 5/40 - Arrangement of two or more semiconductor lasers, not provided for in groups
32.
Digital control of analog amplification gain in a receiver device
A receiver device includes an analog front end configured to receive a communication signal transmitted over a communication channel. The analog front end including an amplifier comprising one or more amplification stages configured to amplify the communication signal. The receiver device also includes a sampler coupled to an output of a first amplification stage among the one or more amplification stages, the sampler configured to generate digital samples of the communication signal at the output of the first amplification stage, and a digital gain control engine configured to control, based on the digital samples of the communication signal at the output of the first amplification stage, a gain of at least the first amplification stage of the amplifier in the analog front end to track an envelope of an amplitude the communication signal at the output of the first amplification stage within a first amplitude range.
A first client station receives a multi-user physical layer (PHY) data unit from an access point. The multi-user PHY data unit includes i) a PHY preamble, and ii) an MU-MIMO transmission. The PHY preamble includes respective subfields that indicate respective numbers of spatial streams allocated to respective client stations. The respective subfields have been encoded according to an encoding that supports allocating up to sixteen spatial streams to up to eight intended receivers. The respective subfields are arranged in the PHY preamble according to an order. The first client station determines a position of a particular subfield corresponding to the first client station within the order, and uses the position of the particular subfield to decodes the particular subfield to determine a number of spatial streams allocated to the first client station. The first client station processes the determined number of spatial streams in the MU-MIMO transmission.
An example gearbox for connecting between a root complex and an endpoint in a computing device, includes a first port configured to connect to the root complex, a second port configured to connect to the endpoint, a first physical layer connected to the first port and a second physical layer connected to the second port, and a first data link layer and a second data link layer, the first data link layer connected between the second data link layer and the first physical layer, and the second data link layer connected between the first data link layer and the second physical layer. The first physical layer, the first data link layer, the second physical layer, and the second data link layer are configured to form one or more lanes for communicating data between the root complex and the endpoint.
A method includes receiving a high-level function in a first high-level code; generating an external strategy associated with the high-level function, wherein the external strategy is in a second high-level code; outputting the external strategy, wherein the external strategy is modifiable; compiling the high-level function into a first set of low-level instructions to be executed on the hardware based on the external strategy if the external strategy remains unchanged; and compiling the high-level function into a second set of low-level instructions to be executed on the hardware based on a modification made to the external strategy if the external strategy has been modified.
A transceiver for a network device includes clock data recovery (CDR) circuitry having a digitally controlled oscillator (DCO) and a CDR lock detector, the CDR lock detector including a frequency differential calculator coupled to a first portion of an input to the DCO and configured to determine frequency differentials between a plurality of respective pairs of present first portions of the input to the DCO and corresponding previous first portions of the input to the DCO, and to determine an average of the frequency differentials for the plurality of respective pairs, and circuitry configured to generate, based on the average, an indication of whether the CDR circuitry is locked.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 7/00 - Arrangements for synchronising receiver with transmitter
37.
Circuit and method for translation lookaside buffer (TLB) implementation
A circuit and corresponding method provide a translation lookaside buffer (TLB) implementation. The circuit comprises a plurality of TLB banks and TLB logic. The TLB logic computes a plurality of hash values of a tag included in a memory request. The TLB logic locates, based on hash values of the plurality of hash values computed, a contiguous translation entry (TE) and a non-contiguous TE in different TLB banks of the plurality of TLB banks. The TLB logic determines a result by comparing the tag with the contiguous TE located and by comparing the tag with the non-contiguous TE located. The TLB logic outputs the result determined toward servicing the memory request. The TLB logic advantageously enables the TLB implementation to support contiguous pages using standard random-access memories for the plurality of TLB banks.
G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 12/0864 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
G06F 12/1009 - Address translation using page tables, e.g. page table structures
38.
Method and apparatus for multi-stage equalization for reading data from storage media
Data read from a storage medium is first processed through a first data path including a first decoder configured to decode data output from at least one first finite impulse response (FIR) filter and first FIR adaptation circuitry configured to adjust a first FIR coefficient for the at least one first FIR filter. The data is then processed through a second data path, which includes at least one second FIR filter and second FIR adaptation circuitry configured to adjust a second FIR coefficient to reach an FIR coefficient that achieves a target minimum number of errors. The second FIR adaptation circuitry is configured to reach the FIR coefficient that achieves the target minimum number of errors faster than the first FIR adaptation circuitry. A second decoder in the second data path is configured to decode data output by the at least one second FIR filter.
A circuit includes a plurality of differential pairs of transistors and circuitry connected to the plurality of differential pairs of transistors. The plurality of differential pairs of transistors is configured to receive a first clock and a second clock and to generate an output representing an exclusive OR sum of the first and second clocks. The circuitry is configured to compensate for mismatch between the plurality of differential pairs of transistors so that the output is zero when the first and second clocks are in quadrature with each other and the output is non-zero when the first and second clocks are not in quadrature with each other regardless of mismatch between the plurality of differential pairs of transistors.
H03K 17/68 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being bipolar transistors specially adapted for switching AC currents or voltages
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
A leaf network switch in a machine learning system receives one or more first messages from one or more network devices, the one or more first messages corresponding to a machine learning operation. The leaf network switch determines one or more processing operations to be performed by the leaf network switch in connection with the one or more first messages. The leaf network switch performs the one or more processing operations, including generating a second message based on the one or more first messages, and transmitting the second message to another network switch. The leaf network switch receives a third message from the other network switch. The leaf switch replicates the third message to generate multiple instances of the third message, and transmits the multiple instances of the third message to respective network devices.
An ADPLL circuit includes a phase comparator for comparing a phase of a reference clock (REFCLK) input signal with a phase of a digitally controlled oscillator clock (DCO_CLK) signal output from a DCO. The phase comparator includes a first ADC connected to receive a REF_P signal corresponding to the phase of the REFCLK signal via a first switch and output an ADC0 signal and a second ADC connected to receive the signal REF_P via a second switch and output an ADC1 signal. The ADPLL circuit further includes a digital filter for receiving the ADC0 and ADC1 signals and determining therefrom a difference between the phases of the DCO_CLK signal and the REFCLK signal. The digital filter provides a DCO control signal to the DCO to control a frequency of operation of the DCO based on the phase difference.
H03L 7/097 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a comparator for comparing the voltages obtained from two frequency to voltage converters
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/14 - Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
A leaf network switch in a machine learning system receives one or more first messages from one or more network devices, the one or more first messages corresponding to a machine learning operation. The leaf network switch determines one or more processing operations to be performed by the leaf network switch in connection with the one or more first messages. The leaf network switch performs the one or more processing operations, including generating a second message based on the one or more first messages, and transmitting the second message to another network switch. The leaf network switch receives a third message from the other network switch. The leaf switch replicates the third message to generate multiple instances of the third message, and transmits the multiple instances of the third message to respective network devices.
H04L 41/16 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using machine learning or artificial intelligence
Some embodiments of the present disclosure provide an associatively indexed circular buffer (ACB). The ACB may be viewed as a dynamically allocatable memory structure that offers in-order data access (say, first-in-first-out, or “FIFO”) or random order data access at a fixed, relatively low latency. The ACB includes a data store of non-contiguous storage. To manage the pushing of data to, and popping data from, the data store, the ACB includes a contiguous pointer generator, a content addressable memory (CAM) and a free pool.
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 5/08 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
G06F 5/10 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
An integrated circuit device, having a first number of terminals, and a first plurality of functional circuits including a second number of functional circuits requiring access to the terminals in the first number of terminals, where the second number is greater than the first number, includes a second plurality of functional circuits from among the first plurality of functional circuits, the second plurality of functional circuits sharing access to a shared terminal among the first number of terminals, and a respective isolation circuit between the shared terminal among the first number of terminals and each respective functional circuit in the second plurality of functional circuits, the respective isolation circuit being configured to prevent coupling of noise from one respective functional circuit in the second plurality of functional circuits to another respective functional circuit in the second plurality of functional circuits via the shared terminal.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 23/528 - Layout of the interconnection structure
H01L 23/552 - Protection against radiation, e.g. light
An electronic network device includes a package substrate, an Integrated Circuit (IC) mounted on the package substrate, and a plurality of interconnection terminals disposed on a surface of the package substrate. The interconnection terminals include multiple pairs of signal terminals and multiple ground terminals. The interconnection terminals are arranged in a hexagonal grid in which (i) a given interconnection terminal is surrounded by six other interconnection terminals, and (ii) propagation paths between signal terminals that do not belong to a same pair are at least partially blocked by the ground terminals.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
46.
Wakeup mechanism for energy efficient ethernet (EEE) with time-sensitive communications
A communication device determines that a communication link will be used for a time-sensitive communication at a future time. In response to determining that the communication link will be used for the time-sensitive communication at the future time, the communication device transitions the communication link from a low power mode to a normal mode prior to the future time so that the communication link is in the normal mode when the future time occurs. The normal mode is for communicating packets via the communication link, and the low power mode reduces power consumption of the communication device as compared to the normal mode.
Linear unretimed interfaces lack clock and data recovery and retiming circuits implemented on a sophisticated digital signal processor. When the interface is not a retimed interface, it can be especially useful to extract some information about the link to allow for debugging and optimization of system deployment. An efficient solution can be implemented in unretimed interfaces to compute metrics such as the impulse response and signal histogram. Having the metrics allows for the solution to check and monitor the quality and the status of the link. Based on the link quality and status information, it is possible to address non-idealities and optimize performance of the unretimed interfaces and the link.
A transmitter generates a set of transmission symbols corresponding to a set of information bits. Generating the set of transmission symbols includes: performing probabilistic constellation shaping to set, in the set of transmission symbols, a quantity n1 of transmission symbols having a maximum transmission symbol amplitude value. Performing of the probabilistic constellation shaping includes performing a recursive procedure to map the set of information bits to a set of amplitude indicators that corresponds to amplitudes of transmission symbols. The set of amplitude indicators includes n1 amplitude indicators set to indicate the maximum transmission symbol amplitude value.
A new approach is proposed to support secured key distribution between a host and a resource-constrained Ethernet bridge using MACSec, wherein the resource-constrained Ethernet bridge is a hardware having a plurality of hardware blocks but no processor or non-volatile storage. Under the proposed approach, a protocol for secured key distribution is fully implemented using existing hardware blocks of the resource-constrained Ethernet bridge. First, session encryption keys (SEKs) are generated independently by both the host and the Ethernet bridge. If the SEKs match, the host is configured to generate and distribute a Secure Association Key (SAK) to the Ethernet bridge to be installed on it. After the SAK is installed on the Ethernet bridge, a secured communication channel is established between the host and the Ethernet bridge. The secured communication channel can be utilized for secured communication of sensitive data collected by the Ethernet bridge from a plurality of electronic devices.
A new approach is proposed that supports timer synchronization among multiple chips. Under the multi-chip configuration, a secondary timer circuitry of a secondary chip is to be synchronized with a primary timer circuitry of a primary chip. A first secondary timer value is sampled at the secondary timer circuitry as triggered by a first sampling trigger signal when the primary timer circuitry reaches a first primary timer value. A second primary timer value is then sampled at the primary timer circuitry as triggered by a second sampling trigger signal when the secondary timer circuitry reaches a second secondary timer value. A timer correction value is calculated based on the differences between the first primary and secondary timer values and the second primary and secondary timer values. The timer correction value is applied to the secondary timer circuitry to synchronize the primary timer circuitry with the secondary timer circuitry.
A device includes a substrate having a first side and a second side, wherein the first side faces opposite the second side. The device also includes a die positioned on the second side of the substrate and electrically coupled to the substrate. The device includes a signal routing component positioned on the first side of the substrate. The signal routing component is configured to route signals between the die and an external component to the device through the substrate. The device includes an electrical board positioned on the second side of the substrate. The electrical board is electrically coupled to the substrate.
A clock recovery loop in a digital signal processor for a serializer-deserializer data interface can be modified to achieve fractional lock and operate in a sampling scope mode. The clock recovery loop can control a phase locked loop to produce a clock signal that is at a rational fraction of a baud rate. The clock signal can be used by time-interleaved analog-to-digital converters to achieve oversampling of a periodic signal received over a receive channel. The samples can be used to reconstruct a continuous time signal bit response to characterize or debug the receive channel.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
A method for decoding data in a memory device includes attempting to decode, using a first decoder, initial bits based on original data read from memory, determining that the first decoding was not successful, and, in response to determining that the first decoding was not successful, attempting to decode, using a second decoder, the initial bits based on the original data and information derived during the first decoding. The first decoder may be a hard decoder, and the second decoder may be a soft decoder. The information derived during the first decoding may include soft information corresponding to each of the initial bits. The soft information may include LLR values corresponding to each of the initial bits. Alternatively, the information derived during the first decoding may include a syndrome weight, and the soft information may be based on the syndrome weight.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
54.
Skew detection and correction of complementary clock signals
A first network device includes a pair of clock tree circuits, a feedback path, and a transceiver. The pair of clock tree circuits is configured to generate output clock signals, which are complementary to each other. The feedback path includes a skew detection circuit and a gain amplifier. The skew detection circuit detects a skew in the output clock signals and generates a pair of voltage signals based on a voltage-to-current and a current-to-voltage conversion of the output clock signals. The pair of voltage signals is indicative of the skew between the output clock signals. The gain amplifier amplifies the pair of voltage signals and, based on the amplified pair of voltage signals, adjusts respective delays in the output clock signals. The transceiver, based on the output clock signals, controls transfer of data to or from a second network device that is separate from the first network device.
A system for designing placement locations for Input/Output (I/O) blocks in an electronic device is disclosed. The system includes an interface and a processor. The interface is configured to receive a requirement that specifies at least multiple I/O blocks to be laid-out along a periphery of an electronic device that implements a network communication device. The processor is configured to generate a plurality of candidate layouts for the electronic device, the candidate layouts differing from one another at least in an arrangement of the specified I/O blocks along the periphery, to estimate respective costs associated with at least some of the candidate layouts, and to present at least some of the candidate layouts and the respective estimated costs to a user.
A delay-locked loop (DLL) and corresponding method improve frequency of a chip. The DLL comprises a first programmable delay element configured to output a first clock, a second programmable delay element configured to output a second clock a phase detector. The phase detector includes a first clock input and a second clock input. The first and second programmable delay elements are further configured, in combination, to introduce a controllable skew between the first and second clocks. The DLL is configured to input the first and second clocks to the first and second clock inputs of the phase detector, respectively. The controllable skew is configured to improve the frequency of the chip.
G06F 1/324 - Power saving characterised by the action undertaken by lowering clock frequency
H03L 7/07 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
57.
Traffic characteristics for target wake time (TWT) negotiation
A first communication device generates a beacon frame that includes i) parameters of a broadcast target wake time (TWT) schedule and ii) information regarding a quantity of client stations that have currently joined the broadcast TWT schedule. The first communication device transmits the beacon frame to inform one or more second communication devices of i) the parameters of the broadcast TWT schedule and ii) the quantity of client stations that have currently joined the broadcast TWT schedule.
H04W 28/18 - Negotiating wireless communication parameters
H04L 69/324 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
A device includes an electrical board including a plurality of ball grid arrays (BGA) groups. Each BGA group of the plurality of BGA groups includes its respective BGA balls connected to its respective vias configured to route electrical signals between an integrated circuit and the electrical board. Vias for two adjacent BGA group of the plurality of BGA groups connect to different layers of the plurality of layers of the electrical board.
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
Digital signal processing (DSP) circuitry of a transceiver generates intermediate results corresponding to transmit bits that are to be transmitted. Each of at least some of the intermediate results correspond to an encoding of a respective set of multiple bits from amongst the transmit bits. The respective set of multiple bits includes bits corresponding to multiple modulation symbols to be transmitted by the transceiver. The DSP circuitry encodes, according to an FEC code, the intermediate results corresponding to the respective sets of multiple bits to generate parity bits. The DSP circuitry maps, according to a modulation technique, the transmit bits and the parity bits to modulation symbols to generate a digital transmit signal. A digital-to-analog converter (DAC) converts the digital transmit signal to an analog transmit signal.
A receiver device receives a signal transmitted to the receiver device over an optical communication channel and equalizes the signal using a multi-decision feedback equalizer of the receiver device. Equalizing the signal includes generating, using at least one decision feedback equalizer configured with a plurality of slicing thresholds, decisions on symbols transmitted to the receiver device, detecting that a decision made by the decision feedback equalizer is unreliable. Equalizing the signal also includes, in response to detecting that the decision is unreliable, tracking, for a tracking period, multiple decision paths that generate respective possible sequences of symbols transmitted to the receiver device, determining error energies in decisions made, during the tracking period, in respective decision paths, and selecting, based on a comparison between the respective error energies, a sequence of symbols generated in one of the multiple decision paths as an output of the multi-decision feedback equalizer.
This disclosure describes an apparatus that enables rapid transitions during microwave-assisted magnetic recording (MAMR) of storage media. In various aspects, the apparatus incorporates a driver circuit configured to provide a controlled bias current through separate source and sink output terminals, which respond to feedback signals. An MAMR sensor connects between the source and sink output terminals and generates microwave fields when receiving the controlled bias current from the driver circuit. A common-mode feedback (CMFB) loop connects to the source and sink output terminals, detects common-mode voltage (CMV), and delivers feedback signals to the driver circuit to maintain CMV regulation of the MAMR sensor. A differential voltage regulation loop connects to the source and sink output terminals, providing feedback signals that maintain the MAMR sensor voltage differential at a reference value. The apparatus controls the magnetic recording process of the MAMR sensor with rapid transition times.
The present disclosure describes aspects of a differential current-mode (iMode) driver for microwave-assisted magnetic recording (MAMR) application in hard-disk drives. In some aspects, an iMode driver circuitry employs a driver circuit coupled to power supply connections. The driver circuit is configured to provide a controlled differential bias current and includes separate source and sink output terminals. A MAMR sensor couples between the source and sink output terminals, through which the MAMR sensor receives the controlled differential bias current provided by the driver circuit. The MAMR sensor, which has a field-entry terminal and a field-exit terminal, generates microwave fields for the recording process. A common-mode feedback (CMFB) loop couples to the field-entry and field-exit terminals of the MAMR sensor, forming a feedback pathway with the driver circuit. This CMFB loop detects common-mode voltage (CMV) and adjusts the controlled differential bias current to maintain CMV regulation of the MAMR sensor.
G11B 19/04 - Arrangements for preventing, inhibiting, or warning against, double recording on the same blank, or against other recording or reproducing malfunctions
G11B 5/00 - Recording by magnetisation or demagnetisation of a record carrierReproducing by magnetic meansRecord carriers therefor
G11B 5/02 - Recording, reproducing or erasing methodsRead, write or erase circuits therefor
63.
Double seal ring and electrical connection of multiple chiplets
A package connecting first and second circuitry components includes: a semiconductor substrate, dielectric layers formed over the semiconductor substrate, first and second substrates of the first and second circuitry components, respectively, positioned side-by-side on one of the dielectric layers, first seal ring of the first circuitry component implemented in first metal layers embedded between the first substrate and a first surface of the first circuitry component, second seal ring of the second circuitry component implemented in second metal layers embedded between the second substrate and a second surface of the second circuitry component, and a third seal ring surrounds the first and second circuitry components and embedded in the dielectric layers extrinsic to the first and second metal layers and overlaying the first and second surfaces, at least a third section of the third seal ring disposed over first and second sections of the first and second seal rings, respectively.
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
64.
INTEGRATION OF BGA PACKAGE ON PCB WITH REDUCED CROSSTALK
A device includes an electrical board including a plurality of ball grid arrays (BGA) groups. Each BGA group of the plurality of BGA groups includes its respective BGA balls connected to its respective vias configured to route electrical signals between an integrated circuit to the electrical board. Vias for two adjacent BGA group of the plurality of BGA groups connect to different layers of the plurality of layers of the electrical board.
Digital signal processing (DSP) circuitry of a transceiver generates intermediate results corresponding to transmit bits that are to be transmitted. Each of at least some of the intermediate results correspond to an encoding of a respective set of multiple bits from amongst the transmit bits. The respective set of multiple bits includes bits corresponding to multiple modulation symbols to be transmitted by the transceiver. The DSP circuitry encodes, according to an FEC code, the intermediate results corresponding to the respective sets of multiple bits to generate parity bits. The DSP circuitry maps, according to a modulation technique, the transmit bits and the parity bits to modulation symbols to generate a digital transmit signal. A digital-to-analog converter (DAC) converts the digital transmit signal to an analog transmit signal.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/25 - Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
66.
MULTI-DECISION FEEDBACK EQUALIZATION IN A RECEIVER DEVICE
A receiver device receives a signal transmitted to the receiver device over an optical communication channel and equalizes the signal using a multi-decision feedback equalizer of the receiver device. Equalizing the signal includes generating, using at least one decision feedback equalizer configured with a plurality of slicing thresholds, decisions on symbols transmitted to the receiver device, detecting that a decision made by the decision feedback equalizer is unreliable. Equalizing the signal also includes, in response to detecting that the decision is unreliable, tracking, for a tracking period, multiple decision paths that generate respective possible sequences of symbols transmitted to the receiver device, determining error energies in decisions made, during the tracking period, in respective decision paths, and selecting, based on a comparison between the respective error energies, a sequence of symbols generated in one of the multiple decision paths as an output of the multi-decision feedback equalizer.
The present disclosure describes apparatuses and methods for hybrid logical to physical (LTP) address mapping in memory systems. In various aspects, a memory controller (132) maps, with an interleave map mode, a first portion of logical address space (406) to a first portion of the physical address space (416) of a memory. The memory controller also maps, with a fixed map mode, a second portion of logical address space (408, 410) to a second portion of the physical address space (418) of the memory. Thus, the memory controller may configure some memory banks (414) with interleave address mapping and other banks with fixed address mapping. In some cases, the memory controller may reconfigure a bank of the memory from one mapping mode to the other mapping mode. By so doing, the memory controller can leverage benefits provided by either mapping mode to optimize access performance, reduce power consumption, or isolate defective areas with minimal capacity loss.
The present disclosure describes System on Chip (SoC) architecture that facilitates disaggregation of memory-to-memory operations. The SoC architecture includes a host interface that communicates with a host system, processor cores, and an Advanced eXtensible Interface (AXI) interconnect coupling the host interface with processor cores. The SoC architecture includes an on- chip memory (OCM) subsystem coupled to the AXI interconnect, where the OCM subsystem contains memory banks, a Direct Memory Access (DMA) interconnect coupled directly with respective memories of processor cores, and a shared memory controller coupled with the AXI interconnect, memory banks, and DMA interconnect. The shared memory controller includes an OCM-internal path connecting the shared memory controller directly to memory banks within the OCM subsystem and a DMA engine that executes memory-to-memory operations by transferring data directly between memory banks through the OCM-internal path or respective memories of processor cores via a DMA interconnect.
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
69.
Shared Memory Controller with Direct Memory Access Architecture for On-Chip Memory
The present disclosure describes System on Chip (SoC) architecture that facilitates disaggregation of memory-to-memory operations. The SoC architecture includes a host interface that communicates with a host system, processor cores, and an Advanced extensible Interface (AXI) interconnect coupling the host interface with processor cores. The SoC architecture includes an on-chip memory (OCM) subsystem coupled to the AXI interconnect, where the OCM subsystem contains memory banks, a Direct Memory Access (DMA) interconnect coupled directly with respective memories of processor cores, and a shared memory controller coupled with the AXI interconnect, memory banks, and DMA interconnect. The shared memory controller includes an OCM-internal path connecting the shared memory controller directly to memory banks within the OCM subsystem and a DMA engine that executes memory-to-memory operations by transferring data directly between memory banks through the OCM-internal path or respective memories of processor cores via a DMA interconnect.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
70.
METHOD AND SYSTEM TO SUPPORT DATA STREAMING FOR MATRIX OPERATIONS VIA A MACHINE LEARNING HARDWARE
A system comprises an on-chip memory (OCM) configured to maintain blocks of data used for a matrix operation and result of the matrix operation, wherein each of the blocks of data is of a certain size. The system further comprises a first OCM streamer configured to stream a first matrix data from the OCM to a first storage unit, and a second OCM streamer configured to stream a second matrix data from the OCM to a second storage unit, wherein the second matrix data is from an unaligned address of the OCM that is a not a multiple of the certain size. The system further comprises a matrix operation block configured to retrieve the first matrix data and the second matrix data from the first storage unit and the second storage unit, respectively, and perform the matrix operation based on the first matrix data and the second matrix data.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
A system includes a compiler including a plurality of compiler blocks. The compiler blocks of the plurality of compiler blocks are compossible. The compiler is configured to identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code. The compiler is further configured to determine one or more processing operations to be performed that is associated with the high-level function in the high-level code. The determining of the one or more processing operations occurs based on architecture of the hardware. The compiler is configured to compile the high-level function in the high-level code of the application into the set of low-level instructions to be executed on the hardware.
A new approach is proposed to support hardware-based update of a software (e.g., a firmware) of an electronic device in a non-functional state. Under the proposed approach, the software is stored securely on a resource (e.g., a non-volatile storge) protected by a hardware-based lock mechanism. A first agent acquires a lock and authenticate the software. When a boot failure (e.g. authentication of the software fails) of the electronic device happens, an alert indicating the failure is generated and sent to a second agent (e.g., a sideband master) through an alert mechanism. The second agent then acquires a lock from the hardware-based lock mechanism to obtain exclusive excess to the resource and update the software stored in the non-volatile storage through, e.g., block write and/or read operations. The second agent then verifies that the software has been updated successfully so that the electronic device becomes functionally again.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
73.
Setup and training of links between host devices and optical modules including menu-based and multi-stage link training
A host device includes a transmitter, an out-of-band electrical interface and a processor. The transmitter transmits in-band signals on an in-band electrical interface from the host device to an optical module. The in-band signals are data signals transmitted to test a link between the host device and the optical module. The out-of-band electrical interface transmits first out-of-band messages from the host device to the optical module, and receives second out-of-band messages from the optical module. The first and second out-of-band messages being control messages for testing the link. The processor performs tests to test the link and selects a set of transmitter settings based on the tests. The processor: i) subsequent to performing the tests, receives via the out-of-band electrical interface one of the second out-of-band messages including an indication of the selected set; and ii) in response to receiving the indication, sets the transmitter according to the selected set.
H04B 10/079 - Arrangements for monitoring or testing transmission systemsArrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
A packet to be forwarded over a computer network to a destination is received. A group of multiple network paths is available to forward to the packet to the destination. One or more path selection factors are determined to be used to identify a specific network load balancing algorithm to select a specific network path from the group of multiple network paths. The one or more path selection factors include at least one path selection factor determined based at least in part on a dynamic state of the computer network or a network node in the computer network. In response to selecting, by the specific network load balancing algorithm, the specific network path from among the group of multiple network paths, the packet is forwarded over the specific network path.
An example method of low-latency decompression includes receiving a data read request to read data stored, in a compressed storage format, in a memory, and responsive to receiving the data read request, accessing compressed data sequences, splitting the compressed data sequences into three separate streams for parallel processing, the three separate streams including (i) a literal stream, (ii) a history cache stream, and (iii) a history buffer stream, for each data sequence in the literal stream, determining a literal decompressed block offset for the data sequence, for each data sequence in the history cache stream, determining a decompressed block offset using one or more history cache pointers associated with the data sequence, for each data sequence in the history buffer stream, determining the decompressed block offset via a history buffer, and generating a data output responsive to the data read request.
The present disclosure describes apparatuses and methods for hybrid logical to physical (LTP) address mapping in memory systems. In various aspects, a memory controller maps, with an interleave map mode, a first portion of logical address space to a first portion of the physical address space of a memory. The memory controller also maps, with a fixed map mode, a second portion of logical address space to a second portion of the physical address space of the memory. Thus, the memory controller may configure some memory banks with interleave address mapping and other banks with fixed address mapping. In some cases, the memory controller may reconfigure a bank of the memory from one mapping mode to the other mapping mode. By so doing, the memory controller can leverage benefits provided by either mapping mode to optimize access performance, reduce power consumption, or isolate defective areas with minimal capacity loss.
Clock distribution circuitry, for distributing clocks for scan operations in an integrated circuit device in which a mission mode clock is distributed by a mesh clock structure and a scan fabric clock is distributed by a scan clock bus, includes a mesh clock source, and a local distribution structure for distributing the clocks for scan operations to a local clock domain that includes a subset of taps of the mesh clock structure. The local distribution structure includes a local controller for controlling derivation of a scan capture clock from the mesh clock source, local scan host circuitry for deriving a local scan shift clock from the scan fabric clock, and specialized integrated clock gates corresponding in number to the subset of taps of the mesh clock structure, for selecting between the scan capture clock in a scan capture mode, and the local scan shift clock in a scan shift mode.
A bridge receives a first memory access command from a host computer, the first memory access command including an indication of one or more blocks of memory locations in a host memory of the host computer. The bridge device stores the first memory access command in a queue of the bridge device and determines one or more virtual addresses to be used by the solid state memory for the first memory access command. The bridge generates a second memory access command that is a revised copy of the first memory access command so that the indication of the one or more blocks of memory locations in the host memory is replaced with an indication of the one or more virtual addresses. The bridge sends the second memory access command to the solid state memory while keeping the first memory access command in the queue.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
semiconductors; Microprocessors; Semiconductor chips; Semiconductor computer chips; Semiconductor integrated circuits; integrated circuits; Electronic chips for use in the manufacture of integrated circuits; downloadable computer software and firmware for controlling and using integrated circuits; processors, namely, data processors for downloadable computer programs using artificial intelligence, data processors for computer network servers and central gateways deployed on a network, general purpose computer data processors, data processors for high-performance computing, data processors for digital signal, data processors, programmable data processors, data processors for downloadable audio and video files; digital signal processors; ethernet transceivers; wireless integrated circuits, namely transceivers and digital signal processors; integrated circuits for controlling solid state drives; amplifiers, namely, transimpedance amplifiers; semiconductor devices, namely retimers; electronic circuits; microchips; photonic microchips; Electronic and optical communications instruments and components, namely, optical transmitters; Electronic and optical communications instruments and components, namely, digital transmitters; Electronic and optical communications instruments and components, namely, optical transceivers; power amplifiers design and development of computer software and hardware for the design and manufacture of semiconductors; design of computer hardware and integrated circuits; designing semiconductors, semiconductor chips and chip sets, integrated circuits, integrated circuit chips, integrated circuit chip sets, and software for others; design and development of computer software and hardware for the design and manufacture of semiconductor devices, namely digital signal processors, transceivers, amplifiers, retimers and microprocessors.
80.
METHOD OF USING UNIT VECTORS TO ALLOW EXPANSION AND COLLAPSE OF HEADER LAYERS WITHIN PACKETS FOR ENABLING FLEXIBLE MODIFICATIONS AND AN APPARATUS THEREOF
Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header. The rewrite engine maintains a bit vector for the generalized protocol header with each bit in the bit vector representing a byte of the generalized protocol header. A bit marked as 0 in the bit vector corresponds to an invalid byte, while a bit marked as 1 in the bit vector corresponds to a valid byte. The rewrite engine uses the bit vector to remove all the invalid bytes after all commands have been operated on the generalized protocol header to thereby form a new protocol header.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Downloadable computer software for use in monitoring circuit compliance with CMIS; Downloadable telemetry and data analytics software; Downloadable computer software for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems Design and development of software; Non-downloadable computer software for use in monitoring circuit compliance with CMIS; Computer chip design services; Non-downloadable telemetry and data analytics software; Non-downloadable computer software for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems
09 - Scientific and electric apparatus and instruments
Goods & Services
Downloadable computer software for use in monitoring circuit compliance with CMIS; Downloadable telemetry and data analytics software; Downloadable computer software for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Computer hardware; Computer chips; Computer memory hardware; Electronic circuits; semiconductors; Semiconductor chips; Semiconductor computer chips; Semiconductor integrated circuits; Electronic chips for use in the manufacture of integrated circuits; Computer firmware for operating mixed signal adaption, digital processing, decision feedback equalization, and advance detector parameters; Computer firmware for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems; Integrated circuits for controlling hard disk drives; Integrated circuits for controlling solid state drives; Downloadable computer software for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems Design and development of computer hardware and software; Design and development of computer firmware; Computer chip design services; Non-downloadable computer software for operating mixed signal adaption, digital processing, decision feedback equalization, and advance detector parameters
84.
Physical layer transceiver with collision avoidance in high noise and interference environment
Systems and methods for using a physical layer transceiver (PHY) of an automobile to avoid data signal collision on a high noise or interference automotive multi-drop communication link are provided. A signal is received at a first PHY via a multi-drop communication link in a high noise or interference automotive environment. The received signal is separated into a first spectral component corresponding to a first logic level and into a second spectral component corresponding to a second logic level. Based on analysis of the first and second spectral components, respectively, a determination is made as to whether a second PHY device is concurrently transmitting data on the link, by determining whether both the first and second logic levels are detected in the first and second spectral components within a threshold period of time of one another. The first PHY device is permitted to transmit, or prevented from transmitting, data via the link based on whether the second PHY device is transmitting data on the link.
Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programed based on how the tiles are allocated for each lookup.
H03K 19/17728 - Reconfigurable logic blocks, e.g. lookup tables
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/0864 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
H04L 45/7452 - Multiple parallel or consecutive lookup operations
H04L 45/7453 - Address table lookupAddress filtering using hashing
86.
Silicon nitride-to-silicon waveguide assembly for broadband communication including concurrent propagation by TE0 and TM0 modes
A waveguide assembly includes first and second waveguides. The first waveguide includes silicon, first and second ends, an end member, and a tapered member. The end member extends from the first end. The tapered member extends from the end member to the second end. The second waveguide is optically coupled to and spaced away from the first waveguide. The second waveguide includes silicon nitride, first and second members, and a non-tapered member. The non-tapered member extends from the first member to the second member and in parallel with and opposing the tapered member. An effective refractive index of the non-tapered member matches an effective refractive index of the tapered member at a first plane. The first plane extends through the non-tapered member and the tapered member and perpendicular to a second plane. The second plane extends parallel to a direction of overlap between the first and second waveguides.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
A solid state drive (SSD) device includes a memory having a plurality of memory cells and an encoder configured to encode information using a polar code to generate encoded information to be stored in the memory. The polar code is constructed based on a plurality of channel models corresponding to different read channel scenarios, including at least a first channel model corresponding a first read channel scenario and a second channel model corresponding to a second read channel scenario, the second read channel scenario different from the first read channel scenario. The SSD device also includes a controller configured to write the encoded information to memory cells in the memory, and read the encoded information from the memory cells in the memory using a selected one of the first read channel scenario and the second read channel scenario.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
A digital signal processor (DSP) of an optical receiver processes one or more digital domain signals, which correspond to a received optical signal, to recover receive data from the one or more digital domain signals. The DSP compensates for a two-dimensional (2-D) warping of transmission symbols at a transmitter of the optical signal at least by: calculating a first adjustment of an in phase (I) component of the transmission symbol; modifying the I component of the transmission symbol using the first adjustment; calculating a second adjustment of a quadrature (Q) component of the transmission symbol; and modifying the Q component of the transmission symbol using the second adjustment
A link establishment process for establishing a network link between the first network interface device and a second network interface device is initiated at the first network interface device. During the link establishment process, the first network interface device receives from the second network interface device via the network link, one or more update messages requesting one or more changes to be applied at the first network interface device, the one or more changes for altering operation of one or both of software and firmware stored in one or more memories included in or coupled to the first network interface device. The one or more changes are applied based on the one or more update messages at the first network interface device.
An electrical circuit board assembly includes: (I) a surface, having a plurality of terminals disposed thereon for transferring a power signal to an electronic device, (II) at least first and second layers separated by at least one dielectric layer, the first and second layers being configured to (a) be connected to the power signal, and (b) electrically conduct at least a portion of the power signal, and (III) multiple vias that (i) mechanically traverse the first and second layers at respective traversal points, and (ii) are electrically connected to the terminals on the surface, the multiple vias including: first vias that, at the respective traversal points, are electrically connected to the first layer and electrically isolated from the second layer, and second vias that, at the respective traversal points, are electrically connected to the second layer and electrically isolated from the first layer.
A method of reducing impact of variation in latency in data transport between clock domains of a physical layer transceiver having physical coding sublayer circuitry with a first clock in a first clock domain and physical medium attachment circuitry with a second clock in a second clock domain, includes determining, during an initial training of a link, a transmit latency value in a transmit direction from the first clock domain to the second clock domain, determining, during the initial training of the link, separately from determining the transmit latency value, a receive latency value in a receive direction from the second clock domain to the first clock domain, and using the transmit latency value and the receive latency value to account for latency in transfer of data between the first clock domain and the second clock domain following the initial training until a subsequent training.
Systems and methods are described for a slave PHY device retransmitting a waking up command to a master PHY device in a low-power mode. After transmitting a wake-up command to the master PHY device, the slave PHY device starts a timer. If the timer reaches a threshold time, the slave device retransmits the wake-up command.
An optical signal transceiver includes a circuit board substrate, a silicon photonics-based interposer mounted on the circuit board substrate, the silicon photonics-based interposer including at least one of a waveguide configured to transmit optical communication signals and a photo detector configured to detect optical communication signals, and a planar lightwave circuit disposed on the circuit board substrate. The planar lightwave circuit is configured to perform at least a portion of propagation of light signals in an optical communication network, and the planar lightwave circuit is aligned with a side surface of the silicon photonics-based interposer to transmit optical communication signals between the silicon photonics-based interposer and the planar lightwave circuit. The optical signal transceiver includes at least one spacer component disposed between the planar lightwave circuit and the circuit board substrate, and epoxy material in contact with the spacer component.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
An electronic device includes (i) a substrate, (ii) first and second stacks of integrated circuit (IC) dies, the first and second stacks being positioned adjacent to one another over the substrate and having first and second surfaces facing one another, (iii) a first plate disposed between the substrate and the first surface of the first and second stacks, and (iv) a second plate disposed over the second surface of the first and second stacks, each of the first and second plates mechanically connects the first stack to the second stack, overlaps at least a portion of a combined footprint of the first and second stacks and configured to mitigate a warpage in at least one of the first and second stacks.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
In a network having at least one slave node including a slave clock, a method of adjusting the slave clock relative to a master clock of a master node includes, at the slave node, correcting a time of day of the slave clock using (a) a slave pulse signal having a known slave pulse rate, (b) a time-of-day counter of the slave node, and (c) a master pulse signal, based on values of the slave clock at nearest corresponding edges of the slave pulse signal and the master pulse signal, and correcting a frequency of the slave clock using the slave pulse signal, a clock signal of the slave node, and the master pulse signal, based on values of the slave clock at nearest corresponding edges of the master pulse signal. No other clock signal from outside the slave node is used for the corrections.
An electronic device (11) includes (i) a substrate (12), (ii) first and second stacks (22a, 22b) of integrated circuit (IC) dies (24a, 24b), the first and second stacks (22a, 22b) being positioned adjacent to one another over the substrate and having first and second surfaces (28, 25) facing one another, (iii) a first plate (21) disposed between the substrate (12) and the first surface (28) of the first and second stacks (22a, 22b), and (iv) a second plate (23) disposed over the second surface (25) of the first and second stacks (22a, 22b), each of the first and second plates (21, 23) mechanically connects the first stack (22a) to the second stack (22b), overlaps at least a portion of a combined footprint of the first and second stacks (22a, 22b) and configured to mitigate a warpage in at least one of the first and second stacks (22a, 22b).
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
97.
Active cable interface with hybrid direct drive and re-timer integration
Interface circuitry for an active cable includes a first active cable interface configured for coupling to a first end of the active cable, and a second active cable interface configured for coupling to a second end of the active cable. The first active cable interface includes first transmitter circuitry including linear driving circuitry or non-linear driving circuitry, and first receiver circuitry including linear receiving circuitry or non-linear receiving circuitry. The second active cable interface includes second transmitter circuitry including linear driving circuitry when first transmitter circuitry includes non-linear receiving circuitry, and non-linear driving circuitry when first transmitter circuitry includes linear receiving circuitry. The second receiver circuitry includes linear receiving circuitry when first receiver circuitry includes non-linear driving circuitry, and non-linear receiving circuitry when first receiver circuitry includes linear driving circuitry.
A semiconductor device includes circuitry configured for faster bitcell operation. That circuitry includes a plurality of bitcells readable as one of a ‘0’ value and a ‘1’ value, and voltage generation circuitry configured to apply an activation voltage to activate selected bitcells in the plurality of bitcells for reading. The voltage generation circuitry is further configured to switch between an overdrive mode and a steady-state mode where the voltage generation circuitry applies a first voltage during the overdrive mode and the voltage generation circuitry applies a second voltage, less than the first voltage, during the steady-state mode, interconnect circuitry configured to couple the plurality of bitcells to reading circuitry. The reading circuitry is configured to receive a differential signal from a bitcell and amplify the differential signal to a full digital logic level. The full digital logic level corresponds to one of the ‘0’ value and the ‘1’ value.
An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.
