An optical device includes a substrate, at least first and second metal traces disposed on the substrate to define an electrical transmission line, and an optical waveguide, which is disposed on the substrate along a serpentine path passing between the metal traces, and which includes at least first and second electrooptical modulation segments, which are arranged in series along the optical waveguide between the first and second metal traces and are separated by bends in the serpentine path. The device further includes a plurality of electrode pairs, each electrode pair including first and second electrodes connected respectively to the first and second metal traces and disposed in mutual proximity on opposing sides of one of the electrooptical modulation segments, including at least first electrode pairs disposed on opposing sides of the first electrooptical modulation segment and second electrode pairs disposed on opposing sides of the second electrooptical modulation segment.
G02F 1/225 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur par interférence dans une structure de guide d'ondes optique
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/125 - Courbures, branchements ou intersections
G02F 1/21 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur par interférence
2.
METHOD AND SYSTEM TO SUPPORT INPUT TENSOR OPTIMIZATION FOR TRANSPOSED CONVOLUTION FOR MACHINE LEARNING
A new approach is proposed that contemplates system and method to support efficient implementation of transposed convolution for machine learning (ML). Under the proposed approach, input data/tensor to a transposed convolution operation is optimized before the transposed convolution operation and each of a plurality of original kernels used for the transposed convolution operation is divided into a plurality of smaller sub-kernels. A plurality of direct sub-convolutions are then performed by sequentially applying each of the plurality of sub-kernels of each of the original kernels over the optimized input tensor without flattening either the input tensor or the plurality of sub-kernels. The output from the sub-convolutions using the plurality of sub-kernels are then combined as the final output tensor for each of the original kernels for the transposed convolution operation.
A new approach is proposed that contemplates system and method to support efficient implementation of transposed convolution for machine learning (ML). Under the proposed approach, input data/tensor to a transposed convolution operation is optimized before the transposed convolution operation and each of a plurality of original kernels used for the transposed convolution operation is divided into a plurality of smaller sub-kernels. A plurality of direct sub-convolutions are then performed by sequentially applying each sub-kernel of the plurality of sub-kernels of each of the original kernels over the optimized input tensor without flattening either the input tensor or the plurality of sub-kernels. The output from the sub-convolutions using the plurality of sub-kernels are then combined as the final output tensor for each of the original kernels for the transposed convolution operation.
An electronic device, includes (a) a semiconductor substrate, (b) a plurality of transistors formed on a first side of the semiconductor substrate, and (c) a first set of metal interconnect layers formed on the first side of the semiconductor substrate, and a second set of metal interconnect layers formed on a second side of the semiconductor substrate opposite to the first side, each of the first set and the second set of metal interconnect layers includes (i) one or more layers whose electrical resistance is in a first range of resistances, and (ii) at least one layer whose electrical resistance is in a second range of resistances, lower than the first range.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/552 - Protection contre les radiations, p. ex. la lumière
5.
Reconfigurable streaming processor for security computations
A computing system includes a streaming engine and a graph core. The streaming engine includes an array of compute units (CUs), an array of crossbar switches, and a configurable interconnect circuit. The CUs perform logical operations on operands. The crossbar switches forward outputs of one or more CUs to inputs of one or more neighboring CUs. The configurable interconnect circuit forwards an output of at least one of the CUs to an input of at least one of the crossbar switches. The graph core programs the streaming processor to perform a security computation by selectively configuring the CUs to perform a plurality of respective logical operations in a programmable order to define a flow of logical operations to be performed by the CUs that effects the security computation, and configuring the crossbar switches and the interconnect circuit to perform the logical operations by traversing the CUs according to the flow.
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
An optical modulator includes a slab of silicon, a first layer of silicon disposed on the slab, and a second layer. The second layer includes a mixture of germanium and silicon. The second layer is at least partially disposed on the first layer. The second layer includes an intrinsic portion of the mixture and further includes first and second doped portions disposed on opposite sides of the intrinsic portion. The intrinsic portion and the first and second doped portions form an active region of the optical modulator.
G02F 1/015 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des éléments à semi-conducteurs ayant des barrières de potentiel, p. ex. une jonction PN ou PIN
G02F 1/025 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des éléments à semi-conducteurs ayant des barrières de potentiel, p. ex. une jonction PN ou PIN dans une structure de guide d'ondes optique
7.
Null data packet announcement frame for NDP ranging
A first communication device generates a null data packet announcement (NDPA) frame for use in a ranging measurement exchange session with a second communication device. The NDPA frame includes a station information field corresponding to the second communication device, the station information field having i) an 11-bit association identifier (AID) subfield that includes an identifier of the second communication device, ii) a disambiguation subfield set to a value that prevents a third communication device operating according to a second communication protocol from improperly processing the NDPA frame, and iii) sixteen bits between the AID subfield and the disambiguation subfield. The first communication device transmits the NDPA frame to the second communication device as part of the ranging measurement exchange session. After transmitting the NDPA frame, the first communication device transmits a null data packet (NDP) to the second communication device as part of the ranging measurement exchange session.
G01S 13/76 - Systèmes utilisant la reradiation d'ondes radio, p. ex. du type radar secondaireSystèmes analogues dans lesquels des signaux de type pulsé sont transmis
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
An optical driver device for driving a light emitting device includes a high-frequency current driver including a first switching circuit configured to generate a first portion of modulation current for driving the light emitting device. The first portion of modulating current is provided to the light emitting device via a coupling capacitor. The high-frequency current driver is configured in current-mode driver topology that utilizes a first current source for generating the first portion of the modulation current. The optical driver device further includes a second switching circuit configured to generate a second portion of modulation current for driving the light emitting device. The second portion of modulation current is provided to the light emitting device via a path that bypasses the coupling capacitor. The low-frequency current driver configured in current-mode driver topology that utilizes a second current source for generating the second portion of modulation current.
H01S 3/10 - Commande de l'intensité, de la fréquence, de la phase, de la polarisation ou de la direction du rayonnement, p. ex. commutation, ouverture de porte, modulation ou démodulation
H01S 5/026 - Composants intégrés monolithiques, p. ex. guides d'ondes, photodétecteurs de surveillance ou dispositifs d'attaque
H01S 5/065 - Accrochage de modesSuppression de modesSélection de modes
H01S 5/183 - Lasers à émission de surface [lasers SE], p. ex. comportant à la fois des cavités horizontales et verticales comportant uniquement des cavités verticales, p. ex. lasers à émission de surface à cavité verticale [VCSEL]
H01S 5/02251 - Découplage de lumière utilisant des fibres optiques
H01S 5/40 - Agencement de plusieurs lasers à semi-conducteurs, non prévu dans les groupes
9.
Digital control of analog amplification gain in a receiver device
A receiver device includes an analog front end configured to receive a communication signal transmitted over a communication channel. The analog front end including an amplifier comprising one or more amplification stages configured to amplify the communication signal. The receiver device also includes a sampler coupled to an output of a first amplification stage among the one or more amplification stages, the sampler configured to generate digital samples of the communication signal at the output of the first amplification stage, and a digital gain control engine configured to control, based on the digital samples of the communication signal at the output of the first amplification stage, a gain of at least the first amplification stage of the amplifier in the analog front end to track an envelope of an amplitude the communication signal at the output of the first amplification stage within a first amplitude range.
H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
A first client station receives a multi-user physical layer (PHY) data unit from an access point. The multi-user PHY data unit includes i) a PHY preamble, and ii) an MU-MIMO transmission. The PHY preamble includes respective subfields that indicate respective numbers of spatial streams allocated to respective client stations. The respective subfields have been encoded according to an encoding that supports allocating up to sixteen spatial streams to up to eight intended receivers. The respective subfields are arranged in the PHY preamble according to an order. The first client station determines a position of a particular subfield corresponding to the first client station within the order, and uses the position of the particular subfield to decodes the particular subfield to determine a number of spatial streams allocated to the first client station. The first client station processes the determined number of spatial streams in the MU-MIMO transmission.
An example gearbox for connecting between a root complex and an endpoint in a computing device, includes a first port configured to connect to the root complex, a second port configured to connect to the endpoint, a first physical layer connected to the first port and a second physical layer connected to the second port, and a first data link layer and a second data link layer, the first data link layer connected between the second data link layer and the first physical layer, and the second data link layer connected between the first data link layer and the second physical layer. The first physical layer, the first data link layer, the second physical layer, and the second data link layer are configured to form one or more lanes for communicating data between the root complex and the endpoint.
A method includes receiving a high-level function in a first high-level code; generating an external strategy associated with the high-level function, wherein the external strategy is in a second high-level code; outputting the external strategy, wherein the external strategy is modifiable; compiling the high-level function into a first set of low-level instructions to be executed on the hardware based on the external strategy if the external strategy remains unchanged; and compiling the high-level function into a second set of low-level instructions to be executed on the hardware based on a modification made to the external strategy if the external strategy has been modified.
A transceiver for a network device includes clock data recovery (CDR) circuitry having a digitally controlled oscillator (DCO) and a CDR lock detector, the CDR lock detector including a frequency differential calculator coupled to a first portion of an input to the DCO and configured to determine frequency differentials between a plurality of respective pairs of present first portions of the input to the DCO and corresponding previous first portions of the input to the DCO, and to determine an average of the frequency differentials for the plurality of respective pairs, and circuitry configured to generate, based on the average, an indication of whether the CDR circuitry is locked.
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
14.
Circuit and method for translation lookaside buffer (TLB) implementation
A circuit and corresponding method provide a translation lookaside buffer (TLB) implementation. The circuit comprises a plurality of TLB banks and TLB logic. The TLB logic computes a plurality of hash values of a tag included in a memory request. The TLB logic locates, based on hash values of the plurality of hash values computed, a contiguous translation entry (TE) and a non-contiguous TE in different TLB banks of the plurality of TLB banks. The TLB logic determines a result by comparing the tag with the contiguous TE located and by comparing the tag with the non-contiguous TE located. The TLB logic outputs the result determined toward servicing the memory request. The TLB logic advantageously enables the TLB implementation to support contiguous pages using standard random-access memories for the plurality of TLB banks.
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB]
G06F 12/0864 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant des moyens pseudo-associatifs, p. ex. associatifs d’ensemble ou de hachage
G06F 12/1009 - Traduction d'adresses avec tables de pages, p. ex. structures de table de page
15.
Method and apparatus for multi-stage equalization for reading data from storage media
Data read from a storage medium is first processed through a first data path including a first decoder configured to decode data output from at least one first finite impulse response (FIR) filter and first FIR adaptation circuitry configured to adjust a first FIR coefficient for the at least one first FIR filter. The data is then processed through a second data path, which includes at least one second FIR filter and second FIR adaptation circuitry configured to adjust a second FIR coefficient to reach an FIR coefficient that achieves a target minimum number of errors. The second FIR adaptation circuitry is configured to reach the FIR coefficient that achieves the target minimum number of errors faster than the first FIR adaptation circuitry. A second decoder in the second data path is configured to decode data output by the at least one second FIR filter.
A circuit includes a plurality of differential pairs of transistors and circuitry connected to the plurality of differential pairs of transistors. The plurality of differential pairs of transistors is configured to receive a first clock and a second clock and to generate an output representing an exclusive OR sum of the first and second clocks. The circuitry is configured to compensate for mismatch between the plurality of differential pairs of transistors so that the output is zero when the first and second clocks are in quadrature with each other and the output is non-zero when the first and second clocks are not in quadrature with each other regardless of mismatch between the plurality of differential pairs of transistors.
H03K 17/68 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors bipolaires spécialement adaptée pour commuter des courants ou des tensions alternatifs
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H03K 19/21 - Circuits OU EXCLUSIF, c.-à-d. donnant un signal de sortie si un signal n'existe qu'à une seule entréeCircuits à COÏNCIDENCES, c.-à-d. ne donnant un signal de sortie que si tous les signaux d'entrée sont identiques
A leaf network switch in a machine learning system receives one or more first messages from one or more network devices, the one or more first messages corresponding to a machine learning operation. The leaf network switch determines one or more processing operations to be performed by the leaf network switch in connection with the one or more first messages. The leaf network switch performs the one or more processing operations, including generating a second message based on the one or more first messages, and transmitting the second message to another network switch. The leaf network switch receives a third message from the other network switch. The leaf switch replicates the third message to generate multiple instances of the third message, and transmits the multiple instances of the third message to respective network devices.
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
An ADPLL circuit includes a phase comparator for comparing a phase of a reference clock (REFCLK) input signal with a phase of a digitally controlled oscillator clock (DCO_CLK) signal output from a DCO. The phase comparator includes a first ADC connected to receive a REF_P signal corresponding to the phase of the REFCLK signal via a first switch and output an ADC0 signal and a second ADC connected to receive the signal REF_P via a second switch and output an ADC1 signal. The ADPLL circuit further includes a digital filter for receiving the ADC0 and ADC1 signals and determining therefrom a difference between the phases of the DCO_CLK signal and the REFCLK signal. The digital filter provides a DCO control signal to the DCO to control a frequency of operation of the DCO based on the phase difference.
H03L 7/097 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant un comparateur pour comparer les tensions obtenues à partir de deux convertisseurs de fréquence en tension
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/14 - Détails de la boucle verrouillée en phase pour assurer une fréquence constante quand la tension d'alimentation ou la tension de correction fait défaut
H03M 1/18 - Commande automatique pour modifier la plage des signaux que le convertisseur peut traiter, p. ex. réglage de la plage de gain
A leaf network switch in a machine learning system receives one or more first messages from one or more network devices, the one or more first messages corresponding to a machine learning operation. The leaf network switch determines one or more processing operations to be performed by the leaf network switch in connection with the one or more first messages. The leaf network switch performs the one or more processing operations, including generating a second message based on the one or more first messages, and transmitting the second message to another network switch. The leaf network switch receives a third message from the other network switch. The leaf switch replicates the third message to generate multiple instances of the third message, and transmits the multiple instances of the third message to respective network devices.
H04L 41/16 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p. ex. des réseaux de commutation de paquets en utilisant l'apprentissage automatique ou l'intelligence artificielle
H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
Some embodiments of the present disclosure provide an associatively indexed circular buffer (ACB). The ACB may be viewed as a dynamically allocatable memory structure that offers in-order data access (say, first-in-first-out, or “FIFO”) or random order data access at a fixed, relatively low latency. The ACB includes a data store of non-contiguous storage. To manage the pushing of data to, and popping data from, the data store, the ACB includes a contiguous pointer generator, a content addressable memory (CAM) and a free pool.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 5/08 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour modifier la vitesse de débit des données, c.-à-d. régularisation de la vitesse ayant une séquence d'emplacements d'emmagasinage, les emplacements intermédiaires n'étant pas accessibles pour des opérations soit de mise en file d'attente, soit de retrait de file d'attente, p. ex. utilisant un registre à décalage
G06F 5/10 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour modifier la vitesse de débit des données, c.-à-d. régularisation de la vitesse ayant une séquence d'emplacements d'emmagasinage, chacun étant individuellement accessible à la fois pour des opérations de mise en file d'attente et pour des opérations de retrait de file d'attente, p. ex. utilisant une mémoire à accès aléatoire
G11C 15/04 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristiques, c.-à-d. mémoires associatives ou mémoires adressables par leur contenu utilisant des éléments semi-conducteurs
An integrated circuit device, having a first number of terminals, and a first plurality of functional circuits including a second number of functional circuits requiring access to the terminals in the first number of terminals, where the second number is greater than the first number, includes a second plurality of functional circuits from among the first plurality of functional circuits, the second plurality of functional circuits sharing access to a shared terminal among the first number of terminals, and a respective isolation circuit between the shared terminal among the first number of terminals and each respective functional circuit in the second plurality of functional circuits, the respective isolation circuit being configured to prevent coupling of noise from one respective functional circuit in the second plurality of functional circuits to another respective functional circuit in the second plurality of functional circuits via the shared terminal.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/552 - Protection contre les radiations, p. ex. la lumière
H03H 7/01 - Réseaux à deux accès sélecteurs de fréquence
22.
Shielded ball-out and via patterns for land grid array (LGA) devices
An electronic network device includes a package substrate, an Integrated Circuit (IC) mounted on the package substrate, and a plurality of interconnection terminals disposed on a surface of the package substrate. The interconnection terminals include multiple pairs of signal terminals and multiple ground terminals. The interconnection terminals are arranged in a hexagonal grid in which (i) a given interconnection terminal is surrounded by six other interconnection terminals, and (ii) propagation paths between signal terminals that do not belong to a same pair are at least partially blocked by the ground terminals.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H05K 1/11 - Éléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
A communication device determines that a communication link will be used for a time-sensitive communication at a future time. In response to determining that the communication link will be used for the time-sensitive communication at the future time, the communication device transitions the communication link from a low power mode to a normal mode prior to the future time so that the communication link is in the normal mode when the future time occurs. The normal mode is for communicating packets via the communication link, and the low power mode reduces power consumption of the communication device as compared to the normal mode.
A transmitter generates a set of transmission symbols corresponding to a set of information bits. Generating the set of transmission symbols includes: performing probabilistic constellation shaping to set, in the set of transmission symbols, a quantity n1 of transmission symbols having a maximum transmission symbol amplitude value. Performing of the probabilistic constellation shaping includes performing a recursive procedure to map the set of information bits to a set of amplitude indicators that corresponds to amplitudes of transmission symbols. The set of amplitude indicators includes n1 amplitude indicators set to indicate the maximum transmission symbol amplitude value.
Linear unretimed interfaces lack clock and data recovery and retiming circuits implemented on a sophisticated digital signal processor. When the interface is not a retimed interface, it can be especially useful to extract some information about the link to allow for debugging and optimization of system deployment. An efficient solution can be implemented in unretimed interfaces to compute metrics such as the impulse response and signal histogram. Having the metrics allows for the solution to check and monitor the quality and the status of the link. Based on the link quality and status information, it is possible to address non-idealities and optimize performance of the unretimed interfaces and the link.
A new approach is proposed to support secured key distribution between a host and a resource-constrained Ethernet bridge using MACSec, wherein the resource-constrained Ethernet bridge is a hardware having a plurality of hardware blocks but no processor or non-volatile storage. Under the proposed approach, a protocol for secured key distribution is fully implemented using existing hardware blocks of the resource-constrained Ethernet bridge. First, session encryption keys (SEKs) are generated independently by both the host and the Ethernet bridge. If the SEKs match, the host is configured to generate and distribute a Secure Association Key (SAK) to the Ethernet bridge to be installed on it. After the SAK is installed on the Ethernet bridge, a secured communication channel is established between the host and the Ethernet bridge. The secured communication channel can be utilized for secured communication of sensitive data collected by the Ethernet bridge from a plurality of electronic devices.
A new approach is proposed that supports timer synchronization among multiple chips. Under the multi-chip configuration, a secondary timer circuitry of a secondary chip is to be synchronized with a primary timer circuitry of a primary chip. A first secondary timer value is sampled at the secondary timer circuitry as triggered by a first sampling trigger signal when the primary timer circuitry reaches a first primary timer value. A second primary timer value is then sampled at the primary timer circuitry as triggered by a second sampling trigger signal when the secondary timer circuitry reaches a second secondary timer value. A timer correction value is calculated based on the differences between the first primary and secondary timer values and the second primary and secondary timer values. The timer correction value is applied to the secondary timer circuitry to synchronize the primary timer circuitry with the secondary timer circuitry.
A device includes a substrate having a first side and a second side, wherein the first side faces opposite the second side. The device also includes a die positioned on the second side of the substrate and electrically coupled to the substrate. The device includes a signal routing component positioned on the first side of the substrate. The signal routing component is configured to route signals between the die and an external component to the device through the substrate. The device includes an electrical board positioned on the second side of the substrate. The electrical board is electrically coupled to the substrate.
A clock recovery loop in a digital signal processor for a serializer-deserializer data interface can be modified to achieve fractional lock and operate in a sampling scope mode. The clock recovery loop can control a phase locked loop to produce a clock signal that is at a rational fraction of a baud rate. The clock signal can be used by time-interleaved analog-to-digital converters to achieve oversampling of a periodic signal received over a receive channel. The samples can be used to reconstruct a continuous time signal bit response to characterize or debug the receive channel.
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
A method for decoding data in a memory device includes attempting to decode, using a first decoder, initial bits based on original data read from memory, determining that the first decoding was not successful, and, in response to determining that the first decoding was not successful, attempting to decode, using a second decoder, the initial bits based on the original data and information derived during the first decoding. The first decoder may be a hard decoder, and the second decoder may be a soft decoder. The information derived during the first decoding may include soft information corresponding to each of the initial bits. The soft information may include LLR values corresponding to each of the initial bits. Alternatively, the information derived during the first decoding may include a syndrome weight, and the soft information may be based on the syndrome weight.
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
H03M 13/15 - Codes cycliques, c.-à-d. décalages cycliques de mots de code produisant d'autres mots de code, p. ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
31.
Skew detection and correction of complementary clock signals
A first network device includes a pair of clock tree circuits, a feedback path, and a transceiver. The pair of clock tree circuits is configured to generate output clock signals, which are complementary to each other. The feedback path includes a skew detection circuit and a gain amplifier. The skew detection circuit detects a skew in the output clock signals and generates a pair of voltage signals based on a voltage-to-current and a current-to-voltage conversion of the output clock signals. The pair of voltage signals is indicative of the skew between the output clock signals. The gain amplifier amplifies the pair of voltage signals and, based on the amplified pair of voltage signals, adjusts respective delays in the output clock signals. The transceiver, based on the output clock signals, controls transfer of data to or from a second network device that is separate from the first network device.
A system for designing placement locations for Input/Output (I/O) blocks in an electronic device is disclosed. The system includes an interface and a processor. The interface is configured to receive a requirement that specifies at least multiple I/O blocks to be laid-out along a periphery of an electronic device that implements a network communication device. The processor is configured to generate a plurality of candidate layouts for the electronic device, the candidate layouts differing from one another at least in an arrangement of the specified I/O blocks along the periphery, to estimate respective costs associated with at least some of the candidate layouts, and to present at least some of the candidate layouts and the respective estimated costs to a user.
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
33.
DLL-based clocking architecture with programmable delay at phase detector inputs
A delay-locked loop (DLL) and corresponding method improve frequency of a chip. The DLL comprises a first programmable delay element configured to output a first clock, a second programmable delay element configured to output a second clock a phase detector. The phase detector includes a first clock input and a second clock input. The first and second programmable delay elements are further configured, in combination, to introduce a controllable skew between the first and second clocks. The DLL is configured to input the first and second clocks to the first and second clock inputs of the phase detector, respectively. The controllable skew is configured to improve the frequency of the chip.
G06F 1/324 - Économie d’énergie caractérisée par l'action entreprise par réduction de la fréquence d’horloge
H03L 7/07 - Commande automatique de fréquence ou de phaseSynchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase utilisant plusieurs boucles, p. ex. pour la génération d'un signal d'horloge redondant
H03L 7/081 - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
34.
Traffic characteristics for target wake time (TWT) negotiation
A first communication device generates a beacon frame that includes i) parameters of a broadcast target wake time (TWT) schedule and ii) information regarding a quantity of client stations that have currently joined the broadcast TWT schedule. The first communication device transmits the beacon frame to inform one or more second communication devices of i) the parameters of the broadcast TWT schedule and ii) the quantity of client stations that have currently joined the broadcast TWT schedule.
H04W 28/18 - Négociation des paramètres de télécommunication sans fil
H04L 69/324 - Protocoles de communication intra-couche entre entités paires ou définitions d'unité de données de protocole [PDU] dans la couche liaison de données [couche OSI 2], p. ex. HDLC
A device includes an electrical board including a plurality of ball grid arrays (BGA) groups. Each BGA group of the plurality of BGA groups includes its respective BGA balls connected to its respective vias configured to route electrical signals between an integrated circuit and the electrical board. Vias for two adjacent BGA group of the plurality of BGA groups connect to different layers of the plurality of layers of the electrical board.
Digital signal processing (DSP) circuitry of a transceiver generates intermediate results corresponding to transmit bits that are to be transmitted. Each of at least some of the intermediate results correspond to an encoding of a respective set of multiple bits from amongst the transmit bits. The respective set of multiple bits includes bits corresponding to multiple modulation symbols to be transmitted by the transceiver. The DSP circuitry encodes, according to an FEC code, the intermediate results corresponding to the respective sets of multiple bits to generate parity bits. The DSP circuitry maps, according to a modulation technique, the transmit bits and the parity bits to modulation symbols to generate a digital transmit signal. A digital-to-analog converter (DAC) converts the digital transmit signal to an analog transmit signal.
A receiver device receives a signal transmitted to the receiver device over an optical communication channel and equalizes the signal using a multi-decision feedback equalizer of the receiver device. Equalizing the signal includes generating, using at least one decision feedback equalizer configured with a plurality of slicing thresholds, decisions on symbols transmitted to the receiver device, detecting that a decision made by the decision feedback equalizer is unreliable. Equalizing the signal also includes, in response to detecting that the decision is unreliable, tracking, for a tracking period, multiple decision paths that generate respective possible sequences of symbols transmitted to the receiver device, determining error energies in decisions made, during the tracking period, in respective decision paths, and selecting, based on a comparison between the respective error energies, a sequence of symbols generated in one of the multiple decision paths as an output of the multi-decision feedback equalizer.
This disclosure describes an apparatus that enables rapid transitions during microwave-assisted magnetic recording (MAMR) of storage media. In various aspects, the apparatus incorporates a driver circuit configured to provide a controlled bias current through separate source and sink output terminals, which respond to feedback signals. An MAMR sensor connects between the source and sink output terminals and generates microwave fields when receiving the controlled bias current from the driver circuit. A common-mode feedback (CMFB) loop connects to the source and sink output terminals, detects common-mode voltage (CMV), and delivers feedback signals to the driver circuit to maintain CMV regulation of the MAMR sensor. A differential voltage regulation loop connects to the source and sink output terminals, providing feedback signals that maintain the MAMR sensor voltage differential at a reference value. The apparatus controls the magnetic recording process of the MAMR sensor with rapid transition times.
G11B 5/465 - Dispositions pour démagnétiser les têtes
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
39.
Differential Current-Mode Driver for Microwave Assisted Magnetic Recording
The present disclosure describes aspects of a differential current-mode (iMode) driver for microwave-assisted magnetic recording (MAMR) application in hard-disk drives. In some aspects, an iMode driver circuitry employs a driver circuit coupled to power supply connections. The driver circuit is configured to provide a controlled differential bias current and includes separate source and sink output terminals. A MAMR sensor couples between the source and sink output terminals, through which the MAMR sensor receives the controlled differential bias current provided by the driver circuit. The MAMR sensor, which has a field-entry terminal and a field-exit terminal, generates microwave fields for the recording process. A common-mode feedback (CMFB) loop couples to the field-entry and field-exit terminals of the MAMR sensor, forming a feedback pathway with the driver circuit. This CMFB loop detects common-mode voltage (CMV) and adjusts the controlled differential bias current to maintain CMV regulation of the MAMR sensor.
G11B 19/04 - Dispositions prévenant, évitant ou signalant la surimpression sur le même support, ou d'autres fonctionnements défectueux de l'enregistrement ou de la reproduction
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
G11B 5/02 - Procédés d'enregistrement, de reproduction ou d'effacementCircuits correspondants pour la lecture, l'écriture ou l'effacement
40.
Double seal ring and electrical connection of multiple chiplets
A package connecting first and second circuitry components includes: a semiconductor substrate, dielectric layers formed over the semiconductor substrate, first and second substrates of the first and second circuitry components, respectively, positioned side-by-side on one of the dielectric layers, first seal ring of the first circuitry component implemented in first metal layers embedded between the first substrate and a first surface of the first circuitry component, second seal ring of the second circuitry component implemented in second metal layers embedded between the second substrate and a second surface of the second circuitry component, and a third seal ring surrounds the first and second circuitry components and embedded in the dielectric layers extrinsic to the first and second metal layers and overlaying the first and second surfaces, at least a third section of the third seal ring disposed over first and second sections of the first and second seal rings, respectively.
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
41.
INTEGRATION OF BGA PACKAGE ON PCB WITH REDUCED CROSSTALK
A device includes an electrical board including a plurality of ball grid arrays (BGA) groups. Each BGA group of the plurality of BGA groups includes its respective BGA balls connected to its respective vias configured to route electrical signals between an integrated circuit to the electrical board. Vias for two adjacent BGA group of the plurality of BGA groups connect to different layers of the plurality of layers of the electrical board.
Digital signal processing (DSP) circuitry of a transceiver generates intermediate results corresponding to transmit bits that are to be transmitted. Each of at least some of the intermediate results correspond to an encoding of a respective set of multiple bits from amongst the transmit bits. The respective set of multiple bits includes bits corresponding to multiple modulation symbols to be transmitted by the transceiver. The DSP circuitry encodes, according to an FEC code, the intermediate results corresponding to the respective sets of multiple bits to generate parity bits. The DSP circuitry maps, according to a modulation technique, the transmit bits and the parity bits to modulation symbols to generate a digital transmit signal. A digital-to-analog converter (DAC) converts the digital transmit signal to an analog transmit signal.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/25 - Détection d'erreurs ou correction d'erreurs transmises par codage spatial du signal, c.-à-d. en ajoutant une redondance dans la constellation du signal, p. ex. modulation codée en treillis [TMC]
43.
MULTI-DECISION FEEDBACK EQUALIZATION IN A RECEIVER DEVICE
A receiver device receives a signal transmitted to the receiver device over an optical communication channel and equalizes the signal using a multi-decision feedback equalizer of the receiver device. Equalizing the signal includes generating, using at least one decision feedback equalizer configured with a plurality of slicing thresholds, decisions on symbols transmitted to the receiver device, detecting that a decision made by the decision feedback equalizer is unreliable. Equalizing the signal also includes, in response to detecting that the decision is unreliable, tracking, for a tracking period, multiple decision paths that generate respective possible sequences of symbols transmitted to the receiver device, determining error energies in decisions made, during the tracking period, in respective decision paths, and selecting, based on a comparison between the respective error energies, a sequence of symbols generated in one of the multiple decision paths as an output of the multi-decision feedback equalizer.
The present disclosure describes apparatuses and methods for hybrid logical to physical (LTP) address mapping in memory systems. In various aspects, a memory controller (132) maps, with an interleave map mode, a first portion of logical address space (406) to a first portion of the physical address space (416) of a memory. The memory controller also maps, with a fixed map mode, a second portion of logical address space (408, 410) to a second portion of the physical address space (418) of the memory. Thus, the memory controller may configure some memory banks (414) with interleave address mapping and other banks with fixed address mapping. In some cases, the memory controller may reconfigure a bank of the memory from one mapping mode to the other mapping mode. By so doing, the memory controller can leverage benefits provided by either mapping mode to optimize access performance, reduce power consumption, or isolate defective areas with minimal capacity loss.
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
45.
SHARED MEMORY CONTROLLER WITH DIRECT MEMORY ACCESS ARCHITECTURE FOR ON-CHIP MEMORY
The present disclosure describes System on Chip (SoC) architecture that facilitates disaggregation of memory-to-memory operations. The SoC architecture includes a host interface that communicates with a host system, processor cores, and an Advanced eXtensible Interface (AXI) interconnect coupling the host interface with processor cores. The SoC architecture includes an on- chip memory (OCM) subsystem coupled to the AXI interconnect, where the OCM subsystem contains memory banks, a Direct Memory Access (DMA) interconnect coupled directly with respective memories of processor cores, and a shared memory controller coupled with the AXI interconnect, memory banks, and DMA interconnect. The shared memory controller includes an OCM-internal path connecting the shared memory controller directly to memory banks within the OCM subsystem and a DMA engine that executes memory-to-memory operations by transferring data directly between memory banks through the OCM-internal path or respective memories of processor cores via a DMA interconnect.
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
46.
Shared Memory Controller with Direct Memory Access Architecture for On-Chip Memory
The present disclosure describes System on Chip (SoC) architecture that facilitates disaggregation of memory-to-memory operations. The SoC architecture includes a host interface that communicates with a host system, processor cores, and an Advanced extensible Interface (AXI) interconnect coupling the host interface with processor cores. The SoC architecture includes an on-chip memory (OCM) subsystem coupled to the AXI interconnect, where the OCM subsystem contains memory banks, a Direct Memory Access (DMA) interconnect coupled directly with respective memories of processor cores, and a shared memory controller coupled with the AXI interconnect, memory banks, and DMA interconnect. The shared memory controller includes an OCM-internal path connecting the shared memory controller directly to memory banks within the OCM subsystem and a DMA engine that executes memory-to-memory operations by transferring data directly between memory banks through the OCM-internal path or respective memories of processor cores via a DMA interconnect.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
47.
METHOD AND SYSTEM TO SUPPORT DATA STREAMING FOR MATRIX OPERATIONS VIA A MACHINE LEARNING HARDWARE
A system comprises an on-chip memory (OCM) configured to maintain blocks of data used for a matrix operation and result of the matrix operation, wherein each of the blocks of data is of a certain size. The system further comprises a first OCM streamer configured to stream a first matrix data from the OCM to a first storage unit, and a second OCM streamer configured to stream a second matrix data from the OCM to a second storage unit, wherein the second matrix data is from an unaligned address of the OCM that is a not a multiple of the certain size. The system further comprises a matrix operation block configured to retrieve the first matrix data and the second matrix data from the first storage unit and the second storage unit, respectively, and perform the matrix operation based on the first matrix data and the second matrix data.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
A system includes a compiler including a plurality of compiler blocks. The compiler blocks of the plurality of compiler blocks are compossible. The compiler is configured to identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code. The compiler is further configured to determine one or more processing operations to be performed that is associated with the high-level function in the high-level code. The determining of the one or more processing operations occurs based on architecture of the hardware. The compiler is configured to compile the high-level function in the high-level code of the application into the set of low-level instructions to be executed on the hardware.
A new approach is proposed to support hardware-based update of a software (e.g., a firmware) of an electronic device in a non-functional state. Under the proposed approach, the software is stored securely on a resource (e.g., a non-volatile storge) protected by a hardware-based lock mechanism. A first agent acquires a lock and authenticate the software. When a boot failure (e.g. authentication of the software fails) of the electronic device happens, an alert indicating the failure is generated and sent to a second agent (e.g., a sideband master) through an alert mechanism. The second agent then acquires a lock from the hardware-based lock mechanism to obtain exclusive excess to the resource and update the software stored in the non-volatile storage through, e.g., block write and/or read operations. The second agent then verifies that the software has been updated successfully so that the electronic device becomes functionally again.
G06F 21/44 - Authentification de programme ou de dispositif
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
50.
Setup and training of links between host devices and optical modules including menu-based and multi-stage link training
A host device includes a transmitter, an out-of-band electrical interface and a processor. The transmitter transmits in-band signals on an in-band electrical interface from the host device to an optical module. The in-band signals are data signals transmitted to test a link between the host device and the optical module. The out-of-band electrical interface transmits first out-of-band messages from the host device to the optical module, and receives second out-of-band messages from the optical module. The first and second out-of-band messages being control messages for testing the link. The processor performs tests to test the link and selects a set of transmitter settings based on the tests. The processor: i) subsequent to performing the tests, receives via the out-of-band electrical interface one of the second out-of-band messages including an indication of the selected set; and ii) in response to receiving the indication, sets the transmitter according to the selected set.
H04B 10/079 - Dispositions pour la surveillance ou le test de systèmes de transmissionDispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service utilisant des mesures du signal de données
A packet to be forwarded over a computer network to a destination is received. A group of multiple network paths is available to forward to the packet to the destination. One or more path selection factors are determined to be used to identify a specific network load balancing algorithm to select a specific network path from the group of multiple network paths. The one or more path selection factors include at least one path selection factor determined based at least in part on a dynamic state of the computer network or a network node in the computer network. In response to selecting, by the specific network load balancing algorithm, the specific network path from among the group of multiple network paths, the packet is forwarded over the specific network path.
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
H04L 45/00 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données
The present disclosure describes apparatuses and methods for hybrid logical to physical (LTP) address mapping in memory systems. In various aspects, a memory controller maps, with an interleave map mode, a first portion of logical address space to a first portion of the physical address space of a memory. The memory controller also maps, with a fixed map mode, a second portion of logical address space to a second portion of the physical address space of the memory. Thus, the memory controller may configure some memory banks with interleave address mapping and other banks with fixed address mapping. In some cases, the memory controller may reconfigure a bank of the memory from one mapping mode to the other mapping mode. By so doing, the memory controller can leverage benefits provided by either mapping mode to optimize access performance, reduce power consumption, or isolate defective areas with minimal capacity loss.
An example method of low-latency decompression includes receiving a data read request to read data stored, in a compressed storage format, in a memory, and responsive to receiving the data read request, accessing compressed data sequences, splitting the compressed data sequences into three separate streams for parallel processing, the three separate streams including (i) a literal stream, (ii) a history cache stream, and (iii) a history buffer stream, for each data sequence in the literal stream, determining a literal decompressed block offset for the data sequence, for each data sequence in the history cache stream, determining a decompressed block offset using one or more history cache pointers associated with the data sequence, for each data sequence in the history buffer stream, determining the decompressed block offset via a history buffer, and generating a data output responsive to the data read request.
Clock distribution circuitry, for distributing clocks for scan operations in an integrated circuit device in which a mission mode clock is distributed by a mesh clock structure and a scan fabric clock is distributed by a scan clock bus, includes a mesh clock source, and a local distribution structure for distributing the clocks for scan operations to a local clock domain that includes a subset of taps of the mesh clock structure. The local distribution structure includes a local controller for controlling derivation of a scan capture clock from the mesh clock source, local scan host circuitry for deriving a local scan shift clock from the scan fabric clock, and specialized integrated clock gates corresponding in number to the subset of taps of the mesh clock structure, for selecting between the scan capture clock in a scan capture mode, and the local scan shift clock in a scan shift mode.
A bridge receives a first memory access command from a host computer, the first memory access command including an indication of one or more blocks of memory locations in a host memory of the host computer. The bridge device stores the first memory access command in a queue of the bridge device and determines one or more virtual addresses to be used by the solid state memory for the first memory access command. The bridge generates a second memory access command that is a revised copy of the first memory access command so that the indication of the one or more blocks of memory locations in the host memory is replaced with an indication of the one or more virtual addresses. The bridge sends the second memory access command to the solid state memory while keeping the first memory access command in the queue.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
semiconductors; Microprocessors; Semiconductor chips; Semiconductor computer chips; Semiconductor integrated circuits; integrated circuits; Electronic chips for use in the manufacture of integrated circuits; downloadable computer software and firmware for controlling and using integrated circuits; processors, namely, data processors for downloadable computer programs using artificial intelligence, data processors for computer network servers and central gateways deployed on a network, general purpose computer data processors, data processors for high-performance computing, data processors for digital signal, data processors, programmable data processors, data processors for downloadable audio and video files; digital signal processors; ethernet transceivers; wireless integrated circuits, namely transceivers and digital signal processors; integrated circuits for controlling solid state drives; amplifiers, namely, transimpedance amplifiers; semiconductor devices, namely retimers; electronic circuits; microchips; photonic microchips; Electronic and optical communications instruments and components, namely, optical transmitters; Electronic and optical communications instruments and components, namely, digital transmitters; Electronic and optical communications instruments and components, namely, optical transceivers; power amplifiers design and development of computer software and hardware for the design and manufacture of semiconductors; design of computer hardware and integrated circuits; designing semiconductors, semiconductor chips and chip sets, integrated circuits, integrated circuit chips, integrated circuit chip sets, and software for others; design and development of computer software and hardware for the design and manufacture of semiconductor devices, namely digital signal processors, transceivers, amplifiers, retimers and microprocessors.
57.
METHOD OF USING UNIT VECTORS TO ALLOW EXPANSION AND COLLAPSE OF HEADER LAYERS WITHIN PACKETS FOR ENABLING FLEXIBLE MODIFICATIONS AND AN APPARATUS THEREOF
Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header. The rewrite engine maintains a bit vector for the generalized protocol header with each bit in the bit vector representing a byte of the generalized protocol header. A bit marked as 0 in the bit vector corresponds to an invalid byte, while a bit marked as 1 in the bit vector corresponds to a valid byte. The rewrite engine uses the bit vector to remove all the invalid bytes after all commands have been operated on the generalized protocol header to thereby form a new protocol header.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Downloadable computer software for use in monitoring circuit compliance with CMIS; Downloadable telemetry and data analytics software; Downloadable computer software for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems Design and development of software; Non-downloadable computer software for use in monitoring circuit compliance with CMIS; Computer chip design services; Non-downloadable telemetry and data analytics software; Non-downloadable computer software for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems
09 - Appareils et instruments scientifiques et électriques
Produits et services
Downloadable computer software for use in monitoring circuit compliance with CMIS; Downloadable telemetry and data analytics software; Downloadable computer software for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Computer hardware; Computer chips; Computer memory hardware; Electronic circuits; semiconductors; Semiconductor chips; Semiconductor computer chips; Semiconductor integrated circuits; Electronic chips for use in the manufacture of integrated circuits; Computer firmware for operating mixed signal adaption, digital processing, decision feedback equalization, and advance detector parameters; Computer firmware for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems; Integrated circuits for controlling hard disk drives; Integrated circuits for controlling solid state drives; Downloadable computer software for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems Design and development of computer hardware and software; Design and development of computer firmware; Computer chip design services; Non-downloadable computer software for operating mixed signal adaption, digital processing, decision feedback equalization, and advance detector parameters
61.
Physical layer transceiver with collision avoidance in high noise and interference environment
Systems and methods for using a physical layer transceiver (PHY) of an automobile to avoid data signal collision on a high noise or interference automotive multi-drop communication link are provided. A signal is received at a first PHY via a multi-drop communication link in a high noise or interference automotive environment. The received signal is separated into a first spectral component corresponding to a first logic level and into a second spectral component corresponding to a second logic level. Based on analysis of the first and second spectral components, respectively, a determination is made as to whether a second PHY device is concurrently transmitting data on the link, by determining whether both the first and second logic levels are detected in the first and second spectral components within a threshold period of time of one another. The first PHY device is permitted to transmit, or prevented from transmitting, data via the link based on whether the second PHY device is transmitting data on the link.
Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programed based on how the tiles are allocated for each lookup.
H03K 19/17728 - Blocs logiques reconfigurables, p. ex. tables de consultation
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/0864 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant des moyens pseudo-associatifs, p. ex. associatifs d’ensemble ou de hachage
G11C 15/04 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristiques, c.-à-d. mémoires associatives ou mémoires adressables par leur contenu utilisant des éléments semi-conducteurs
H04L 45/7452 - Opérations multiples parallèles ou consécutives de recherche
H04L 45/7453 - Recherche de table d'adressesFiltrage d'adresses en utilisant le hachage
63.
Silicon nitride-to-silicon waveguide assembly for broadband communication including concurrent propagation by TE0 and TM0 modes
A waveguide assembly includes first and second waveguides. The first waveguide includes silicon, first and second ends, an end member, and a tapered member. The end member extends from the first end. The tapered member extends from the end member to the second end. The second waveguide is optically coupled to and spaced away from the first waveguide. The second waveguide includes silicon nitride, first and second members, and a non-tapered member. The non-tapered member extends from the first member to the second member and in parallel with and opposing the tapered member. An effective refractive index of the non-tapered member matches an effective refractive index of the tapered member at a first plane. The first plane extends through the non-tapered member and the tapered member and perpendicular to a second plane. The second plane extends parallel to a direction of overlap between the first and second waveguides.
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
A solid state drive (SSD) device includes a memory having a plurality of memory cells and an encoder configured to encode information using a polar code to generate encoded information to be stored in the memory. The polar code is constructed based on a plurality of channel models corresponding to different read channel scenarios, including at least a first channel model corresponding a first read channel scenario and a second channel model corresponding to a second read channel scenario, the second read channel scenario different from the first read channel scenario. The SSD device also includes a controller configured to write the encoded information to memory cells in the memory, and read the encoded information from the memory cells in the memory using a selected one of the first read channel scenario and the second read channel scenario.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
A digital signal processor (DSP) of an optical receiver processes one or more digital domain signals, which correspond to a received optical signal, to recover receive data from the one or more digital domain signals. The DSP compensates for a two-dimensional (2-D) warping of transmission symbols at a transmitter of the optical signal at least by: calculating a first adjustment of an in phase (I) component of the transmission symbol; modifying the I component of the transmission symbol using the first adjustment; calculating a second adjustment of a quadrature (Q) component of the transmission symbol; and modifying the Q component of the transmission symbol using the second adjustment
A link establishment process for establishing a network link between the first network interface device and a second network interface device is initiated at the first network interface device. During the link establishment process, the first network interface device receives from the second network interface device via the network link, one or more update messages requesting one or more changes to be applied at the first network interface device, the one or more changes for altering operation of one or both of software and firmware stored in one or more memories included in or coupled to the first network interface device. The one or more changes are applied based on the one or more update messages at the first network interface device.
An electrical circuit board assembly includes: (I) a surface, having a plurality of terminals disposed thereon for transferring a power signal to an electronic device, (II) at least first and second layers separated by at least one dielectric layer, the first and second layers being configured to (a) be connected to the power signal, and (b) electrically conduct at least a portion of the power signal, and (III) multiple vias that (i) mechanically traverse the first and second layers at respective traversal points, and (ii) are electrically connected to the terminals on the surface, the multiple vias including: first vias that, at the respective traversal points, are electrically connected to the first layer and electrically isolated from the second layer, and second vias that, at the respective traversal points, are electrically connected to the second layer and electrically isolated from the first layer.
An optical signal transceiver includes a circuit board substrate, a silicon photonics-based interposer mounted on the circuit board substrate, the silicon photonics-based interposer including at least one of a waveguide configured to transmit optical communication signals and a photo detector configured to detect optical communication signals, and a planar lightwave circuit disposed on the circuit board substrate. The planar lightwave circuit is configured to perform at least a portion of propagation of light signals in an optical communication network, and the planar lightwave circuit is aligned with a side surface of the silicon photonics-based interposer to transmit optical communication signals between the silicon photonics-based interposer and the planar lightwave circuit. The optical signal transceiver includes at least one spacer component disposed between the planar lightwave circuit and the circuit board substrate, and epoxy material in contact with the spacer component.
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/13 - Circuits optiques intégrés caractérisés par le procédé de fabrication
An electronic device includes (i) a substrate, (ii) first and second stacks of integrated circuit (IC) dies, the first and second stacks being positioned adjacent to one another over the substrate and having first and second surfaces facing one another, (iii) a first plate disposed between the substrate and the first surface of the first and second stacks, and (iv) a second plate disposed over the second surface of the first and second stacks, each of the first and second plates mechanically connects the first stack to the second stack, overlaps at least a portion of a combined footprint of the first and second stacks and configured to mitigate a warpage in at least one of the first and second stacks.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
70.
PHYSICAL LAYER TRANSCEIVER WITH REDUCED VARIATION IN PACKET LATENCY
A method of reducing impact of variation in latency in data transport between clock domains of a physical layer transceiver having physical coding sublayer circuitry with a first clock in a first clock domain and physical medium attachment circuitry with a second clock in a second clock domain, includes determining, during an initial training of a link, a transmit latency value in a transmit direction from the first clock domain to the second clock domain, determining, during the initial training of the link, separately from determining the transmit latency value, a receive latency value in a receive direction from the second clock domain to the first clock domain, and using the transmit latency value and the receive latency value to account for latency in transfer of data between the first clock domain and the second clock domain following the initial training until a subsequent training.
Systems and methods are described for a slave PHY device retransmitting a waking up command to a master PHY device in a low-power mode. After transmitting a wake-up command to the master PHY device, the slave PHY device starts a timer. If the timer reaches a threshold time, the slave device retransmits the wake-up command.
In a network having at least one slave node including a slave clock, a method of adjusting the slave clock relative to a master clock of a master node includes, at the slave node, correcting a time of day of the slave clock using (a) a slave pulse signal having a known slave pulse rate, (b) a time-of-day counter of the slave node, and (c) a master pulse signal, based on values of the slave clock at nearest corresponding edges of the slave pulse signal and the master pulse signal, and correcting a frequency of the slave clock using the slave pulse signal, a clock signal of the slave node, and the master pulse signal, based on values of the slave clock at nearest corresponding edges of the master pulse signal. No other clock signal from outside the slave node is used for the corrections.
An electronic device (11) includes (i) a substrate (12), (ii) first and second stacks (22a, 22b) of integrated circuit (IC) dies (24a, 24b), the first and second stacks (22a, 22b) being positioned adjacent to one another over the substrate and having first and second surfaces (28, 25) facing one another, (iii) a first plate (21) disposed between the substrate (12) and the first surface (28) of the first and second stacks (22a, 22b), and (iv) a second plate (23) disposed over the second surface (25) of the first and second stacks (22a, 22b), each of the first and second plates (21, 23) mechanically connects the first stack (22a) to the second stack (22b), overlaps at least a portion of a combined footprint of the first and second stacks (22a, 22b) and configured to mitigate a warpage in at least one of the first and second stacks (22a, 22b).
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
74.
Active cable interface with hybrid direct drive and re-timer integration
Interface circuitry for an active cable includes a first active cable interface configured for coupling to a first end of the active cable, and a second active cable interface configured for coupling to a second end of the active cable. The first active cable interface includes first transmitter circuitry including linear driving circuitry or non-linear driving circuitry, and first receiver circuitry including linear receiving circuitry or non-linear receiving circuitry. The second active cable interface includes second transmitter circuitry including linear driving circuitry when first transmitter circuitry includes non-linear receiving circuitry, and non-linear driving circuitry when first transmitter circuitry includes linear receiving circuitry. The second receiver circuitry includes linear receiving circuitry when first receiver circuitry includes non-linear driving circuitry, and non-linear receiving circuitry when first receiver circuitry includes linear driving circuitry.
An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.
A semiconductor device includes circuitry configured for faster bitcell operation. That circuitry includes a plurality of bitcells readable as one of a ‘0’ value and a ‘1’ value, and voltage generation circuitry configured to apply an activation voltage to activate selected bitcells in the plurality of bitcells for reading. The voltage generation circuitry is further configured to switch between an overdrive mode and a steady-state mode where the voltage generation circuitry applies a first voltage during the overdrive mode and the voltage generation circuitry applies a second voltage, less than the first voltage, during the steady-state mode, interconnect circuitry configured to couple the plurality of bitcells to reading circuitry. The reading circuitry is configured to receive a differential signal from a bitcell and amplify the differential signal to a full digital logic level. The full digital logic level corresponds to one of the ‘0’ value and the ‘1’ value.
G11C 7/24 - Circuits de protection ou de sécurité pour cellules de mémoire, p. ex. dispositions pour empêcher la lecture ou l'écriture par inadvertanceCellules d'étatCellules de test
A communication device performs a first backoff operation with a first backoff counter to determine when to transmit in a first frequency segment, and performs a second backoff operation with a second backoff counter to determine when to transmit in a second frequency segment. In response to i) determining that first starts of first transmissions in the first frequency segment are to be synchronized with second starts of second transmissions in the second frequency segment, and ii) the first backoff counter expiring before the second backoff counter expires, the communication device waits to transmit a first packet in the first frequency segment for the second backoff counter to expire, and transmits the first packet in the first frequency segment and a second packet in the second frequency segment beginning at a same start time in connection with the second backoff timer expiring.
An optical receiver includes an error generator, a multipath interference estimator, and a combiner. The error generator is configured to receive an input comprising a received optical signal, to estimate a modulation level of samples of the received optical signal, and to generate an error signal based on the estimated modulation level of the samples, the error signal representing a difference between an actual level of the received optical signal and the estimated modulation level. The multipath interference estimator is configured to generate estimates of multipath interference (MPI) associated with the samples of the received optical signal based on the error signal. The combiner is configured to generate an MPI-mitigated signal based on a combination of the samples and the estimates of MPI.
H04B 10/58 - Compensation pour sortie d’émetteur non linéaire
H04B 10/00 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p. ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p. ex. les communications quantiques
H04B 10/2507 - Dispositions spécifiques à la transmission par fibres pour réduire ou éliminer la distorsion ou la dispersion
H04B 10/516 - Détails du codage ou de la modulation
An Integrated Circuit (IC) includes electronic circuitry, multiple sensors, and an Adaptive Voltage Scaling (AVS) circuit. The electronic circuitry is configured to be powered by one or more supply voltages. The multiple sensors are configured to measure values affected by the one or more supply voltages, and to produce multiple sensor outputs. The AVS circuit is configured to adaptively set the one or more supply voltages by applying to the sensor outputs an AVS model having one or more user-defined parameters, to generate performance data based on the sensor outputs, to export the performance data from the IC, to receive the one or more user-defined parameters into the IC in response to the performance data, and to configure the AVS model to operate in accordance with the received user-defined parameters.
A time-interleaved digital-to-analog converter for an optical transmitter includes a DAC core having a plurality of slices and current sources for converting complementary data signals to analog signals at output nodes of the DAC core, a down switch circuitry configured to connect, for each slice of the DAC core, a current from one of the current sources to a first data input path or a second data input path respectively corresponding to first complementary data signals and second complementary data signals supplied to the slice of the DAC core, an up switch circuitry configured to connect the current to the output nodes, and a data switch circuitry configured to, for each slice of the DAC core, selectively connect the current received via the down switch circuitry and either the first data input path or the second data input path.
A first communication device determines that a trigger frame and another frame are to be transmitted to at least a second communication device. The first communication device determines whether the second communication device announced support of aggregation of buffer status report (BSRP) trigger frames with additional frames. In response to the first communication device determining that the second communication device announced support of aggregation of BSRP trigger frames with additional frames, the first communication device generates an aggregate media access control protocol data unit (A-MPDU) to include the BSRP trigger frame and the other frame, and transmits the A-MPDU within a packet. In response to the first communication device determining that the second communication device did not announce support of aggregation of BSRP trigger frames with additional frames, the first communication device transmits a packet having only the BSRP trigger frame.
An optical communication system includes a transceiver device and a passive multiplexer and demultiplexer (PMAD). The transceiver device transmits or receives optical signals. The PMAD has a Mach-Zehnder interferometer structure, is connected to the transceiver device, and operates as a passive multiplexer or a passive demultiplexer. The PMAD includes: a first arm including a first waveguide, the first arm having a first dimension; a second arm including i) a second waveguide, and ii) a third waveguide, the second waveguide having a second dimension, the third waveguide having a third dimension, the second dimension being based on the first dimension and finely adjusts at least one performance parameter of the passive multiplexer and demultiplexer, and the third dimension being based on the first dimension and coarsely adjusts the at least one performance parameter; and a splitter and a coupler that propagate the optical signals.
H04B 10/079 - Dispositions pour la surveillance ou le test de systèmes de transmissionDispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service utilisant des mesures du signal de données
H04J 14/02 - Systèmes multiplex à division de longueur d'onde
83.
BACKSIDE CAPACITOR FOR REDUCING POWER DELIVERY NETWORK IMPEDANCE
A die has an integrated circuit with backside decoupling capacitance that reduces impact of noise caused by a power delivery network supplying power to the integrated circuit. The integrated circuit includes a power delivery network spanning a front end of line region, a back end of line region, and a backside region. The integrated circuit includes a decoupling capacitor disposed in the backside region to provide a backside decoupling capacitance. The decoupling capacitor includes at least two respective portions of at least two of backside metal traces such that each of the at least two respective portions are electrically coupled to at least one of the front end of line region or the back end of line region by at least two respective through-silicon vias among the plurality of through-silicon vias, and a dielectric material is arranged between the at least two respective portions of the backside metal traces.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A Physical Layer (PHY) device includes an ingress transceiver, an egress transceiver and a controller. The ingress transceiver and the egress transceiver each includes respective analog signal processing (ASP) circuitry and respective digital signal processing (DSP) circuitry. The controller is configured to select an operational mode, for one or both of the ingress transceiver and the egress transceiver, between (i) a digital mode in which both the ASP circuitry and the DSP circuitry are active, and (ii) an analog mode in which the ASP circuitry is active and the DSP circuitry is bypassed.
A die has an integrated circuit with backside decoupling capacitance that reduces impact of noise caused by a power delivery network supplying power to the integrated circuit. The integrated circuit includes a power delivery network spanning a front end of line region, a back end of line region, and a backside region. The integrated circuit includes a decoupling capacitor disposed in the backside region to provide a backside decoupling capacitance. The decoupling capacitor includes at least two respective portions of at least two of backside metal traces such that each of the at least two respective portions are electrically coupled to at least one of the front end of line region or the back end of line region by at least two respective through-silicon vias among the plurality of through-silicon vias, and a dielectric material is arranged between the at least two respective portions of the backside metal traces.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
A Physical Layer (PHY) device (100) includes an ingress transceiver (102), an egress transceiver (104) and a controller (118). The ingress transceiver and the egress transceiver each includes respective analog signal processing (ASP) circuitry (106, 110)) and respective digital signal processing (DSP) circuitry (108, 112). The controller is configured to select an operational mode, for one or both of the ingress transceiver and the egress transceiver, between (i) a digital mode in which both the ASP circuitry and the DSP circuitry are active, and (ii) an analog mode in which the ASP circuitry is active and the DSP circuitry is bypassed.
A packet processor of a network device includes a first lookup engine that generates a first lookup key for a packet, performs a first lookup in a first database using the first lookup key, and in response to finding a match of the first lookup key in the first database, determines a plurality of processing actions to be performed for the packet. Each of multiple second lookup engines selectively performs a respective second lookup in a respective second database for the packet using a respective second lookup key, and ii) selectively determines, based on the second lookup, one or more processing actions to be performed for the packet. The second lookup engines skip performing the second lookups for the packet in response to the first lookup engine finding the match of the first lookup key in the first database.
An integrated circuit device includes functional circuitry including transistors, and testing circuitry configured to test effects of different layouts of the functional circuitry, relative to physical features of the integrated circuit device, on operation of the transistors. The testing circuitry includes at least one first test circuit having a first physical relationship relative to the physical features of the integrated circuit device, at least one second test circuit having a second physical relationship, different from the first physical relationship, relative to the physical features of the integrated circuit device, and sensing circuitry for reading outputs of the at least one first test circuit and the at least one second test circuit. Imbalance circuitry is configured to apply compensation to the functional circuitry to compensate for a sensed imbalance. There may be a plurality of instances of the first test circuit, and a plurality of instances of the second test circuit.
A method includes receiving a high-level function in a first high-level code; compiling the high-level function into a first set of low-level instructions to be executed on a hardware or a simulator; transmitting the first set of low-level instructions to the hardware or the simulator; receiving a plurality of statistical data generated by the hardware or the simulator in response to execution of the first set of low-level instructions, wherein the plurality of statistical data is performance related; determining whether to make changes to the compilation associated with the high-level function in the first high-level code based on the plurality of statistical data; recompiling the high-level function into a second set of low-level instructions to be executed on the hardware or the simulator based on the changes to the compilation; and transmitting the second set of low-level instructions to the hardware or the simulator.
A semiconductor package includes a first chip including a first die-to-die interface with a first plurality of flip-flops, and a second chip including a second die-to-die interface with a second plurality of flip-flops, and an interposer configured to provide paths for data to flow between the first die-to-die interface and the second die-to-die interface. The interposer is mechanically coupled to the first chip and to the second chip by a first hybrid bond and a second hybrid bond, respectively, the interposer including a first plurality of interposer vias coupled to the first plurality of flip-flops across the first hybrid bond, a second plurality of interposer vias coupled to the second plurality of flip-flops across the second hybrid bond, and a plurality of lateral metal traces coupling respective vias among the first plurality of interposer vias to respective vias among the second plurality of interposer vias to provide the paths.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/14 - Supports, p. ex. substrats isolants non amovibles caractérisés par le matériau ou par ses propriétés électriques
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
A network interface device operates in a normal transmit operating mode in which the network interface device continually receives transmission symbols from a link partner via the communication link. The network interface device determines that receive circuitry of the network interface device is to transition to a low power mode in response to receiving a sleep signal from the link partner. The network interface device then operates according to a quiet/refresh cycle of the low power mode to conserve power. The quiet/refresh cycle corresponds to a time schedule that includes a refresh time window in which receive circuitry of the network interface device is to be powered to receive a refresh signal from the link partner. Immediately after transmission of the sleep signal, the network interface device transitions to a quiet time window of the time schedule in which the network interface device ignores transmissions from the link partner.
A system includes first memory, a controller, and a processor. The controller is indirectly connected to the memory, configured to perform at least one function, and configured to handle data generated or received during performance of the at least one function. The processor is connected between the memory and the controller. The processor reconfigures a map before and during performance of the at least one function by the controller. The reconfiguring of the map includes changing i) a first allocated portion of the memory for program instructions, and ii) a second allocated portion of the memory for the data. The processor, based on the map, i) routes the program instructions and the data between the controller and the first memory, ii) stores the program instructions at addresses of the memory allocated for the program instructions, and iii) stores the data at addresses of the memory allocated for the data.
A semiconductor package includes a first chip including a first die-to-die interface with a first plurality of flip-flops, and a second chip including a second die-to-die interface with a second plurality of flip-flops, and an interposer configured to provide paths for data to flow between the first die-to-die interface and the second die- to-die interface. The interposer is mechanically coupled to the first chip and to the second chip by a first hybrid bond and a second hybrid bond, respectively, the interposer including a first plurality of interposer vias coupled to the first plurality of flip-flops across the first hybrid bond, a second plurality of interposer vias coupled to the second plurality of flip-flops across the second hybrid bond, and a plurality of lateral metal traces coupling respective vias among the first plurality of interposer vias to respective vias among the second plurality of interposer vias to provide the paths.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
94.
METHOD AND APPARATUS FOR AUTOMATIC DESIGN CONSTRAINT GENERATION FOR CHIP IP USING GENERATIVE ARTIFICIAL INTELLIGENCE
A new approach is disclosed to support automatic design constraint generation for chip IP using generative artificial intelligence (AI). A document ingress module accepts a plurality of inputs from multiple design documentation sources describing a chip IP. An LLM training module trains the one or more LLMs with targeted training materials on embodiments of the specific chip IP. A generative AI module automatically generates a set of design constraints for the chip IP using the one or more trained LLMs based on the plurality of inputs from multiple design documentation sources. Once the set of design constraints have been generated, a document egress module is configured to verify accuracy of the set of design constraints by converting the set of design constraints into a format of a human language document that includes attributes specific to design configuration of the chip IP.
G06F 30/3315 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle utilisant une analyse temporelle statique [STA]
G06F 119/02 - Analyse de fiabilité ou optimisation de fiabilitéAnalyse de défaillance, p. ex. performance dans le pire scénario, analyse du mode de défaillance et de ses effets [FMEA]
G06F 119/12 - Analyse temporelle ou optimisation temporelle
95.
METHOD AND APPARATUS FOR GENERATING ORDER OF MAGNITUDE DATA ASSOCIATED WITH TENSOR DATA
A system includes a machine learning (ML) accelerator running a first code generated by a first compiler that generates a first plurality of tensors associated with one or more ML operations of a ML model. The system includes a processor that receives the first and the second plurality of tensors associated with the ML model. The second plurality of tensors is generated by a second code generated by a second compiler running on a hardware executing the one or more ML operations of the ML model. The processor generates a plurality of relative errors associated with the first and second plurality of tensors. The processor calculates an order of magnitude associated with the first plurality of tensors and generates a graph associated with the plurality of relative errors and the calculated order of magnitude associated with the first plurality of tensors. The graph is rendered.
To improve time synchronization in a communication network, a first communication device generates a measurement of a first latency of a transmit path of a communication link between the first communication device and a second communication device. The communication link also includes a receive path. The first communication device compensates for an asymmetry between the first latency of the transmit path and a second latency of the receive path using the measurement of the first latency.
To improve time synchronization in a communication network, a first communication device generates a measurement of a first latency of a transmit path of a communication link between the first communication device and a second communication device. The communication link also includes a receive path. The first communication device compensates for an asymmetry between the first latency of the transmit path and a second latency of the receive path using the measurement of the first latency.
A silicon photonics modulator includes a substrate, a PN junction disposed on the substrate, the PN junction formed by a first L-shaped region doped with a p-type doping abutting a second L-shaped region doped with an n-type doping, a first plurality of regions each having different p-type doping concentrations greater than the first L-shaped region, and a second plurality of regions each having different n-type doping concentrations greater than the second L-shaped region. The silicon photonics modulator includes a first electrical contact on one of the first plurality of regions, a second electrical contact on one of the second plurality of regions, and multiple grating pillars doped with the n-type doping or the p-type doping, each of the multiple grating pillars spaced apart from the PN junction and spaced apart from one another.
G02F 1/025 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des éléments à semi-conducteurs ayant des barrières de potentiel, p. ex. une jonction PN ou PIN dans une structure de guide d'ondes optique
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
99.
PACKET BUFFER LATENCY MITIGATION IN A NETWORK DEVICE
A network device includes a plurality of network interfaces and an ingress processor configured to process packets received by the network device to determine network interfaces, among the plurality of network interfaces, via which the packets are to be transmitted by the network device. The network device also includes a memory device configured to buffer packet data corresponding to the packets while the packets are being processed by the network device and a memory controller configured to select a buffering scheme for buffering a packet in the memory device based on a congestion state of a network interface via which the packet is to be transmitted. The buffering scheme is selected among a first buffering scheme having a first latency associated with buffering packet data and a second buffering scheme having a second latency, smaller than the first latency, associated with buffering packet data.
A network device includes a plurality of network interfaces and an ingress processor configured to process packets received by the network device to determine network interfaces, among the plurality of network interfaces, via which the packets are to be transmitted by the network device. The network device also includes a memory device configured to buffer packet data corresponding to the packets while the packets are being processed by the network device and a memory controller configured to select a buffering scheme for buffering a packet in the memory device based on a congestion state of a network interface via which the packet is to be transmitted. The buffering scheme is selected among a first buffering scheme having a first latency associated with buffering packet data and a second buffering scheme having a second latency, smaller than the first latency, associated with buffering packet data.
H04L 49/25 - Routage ou recherche de route dans une matrice de commutation
H04L 49/50 - Détection ou protection de surcharge dans un seul élément de commutation
H04L 49/901 - Dispositions de mémoires tampon en utilisant un descripteur de stockage, p. ex. des pointeurs de lecture ou d'écriture
H04L 49/103 - Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation en utilisant une mémoire tampon centrale partagéeÉléments de commutation de paquets caractérisés par la construction de la matrice de commutation en utilisant une mémoire partagée
