The present invention realizes a data processing device for convolution processing capable of reducing the number of executions of processing for reading feature quantity data, shortening the time required for the entire convolution processing including the processing for reading the feature quantity data, and performing data processing for realizing a high-performance and high-speed CNN model. [Solution] In the data processing device for convolution processing, (1) a plurality of access buses are provided in each of a plurality of bank memories (Tmem_k) of a memory unit (22), and data for a plurality of channels can be accessed simultaneously (in parallel); and (2) since different (independent) bank memories Tmem_k are allocated for each height direction of a convolution processing target region (region to be convolved with a kernel), a plurality of data items having different height directions can be accessed simultaneously (in parallel).
According to the present invention, a decoding unit has a decoding circuit configured as hardware, and the decoding circuit includes: a first entropy decoding circuit that decodes encoded data by use of a first decoding mode that is an entropy decoding mode specified by a first specification; and a universal decoding circuit that decodes the data, which has been decoded by use of the first decoding mode, by use of a second decoding mode that is a universal decoding mode specified by a second specification different from the first specification.
Provide is data processing apparatus that performs highly accurate data processing accompanying vector decomposition processing, quantization processing, convolution processing and the like for any distribution of data. The data processing apparatus obtains a plurality of local solutions in the vector decomposition processing, selects a plurality of data adjustment processes performed before the quantization processing for each of the obtained local solutions of the vector decomposition processing, obtains the accuracy of the convolution processing, and then determines a local solution of the vector decomposition processing with highest accuracy and the data adjustment processing, with highest accuracy, performed before the quantization.
A communication terminal device has circuitry configured to: judge, based on received information, whether or not source of the received information is intra-group communication destination; monitor whether or not the intra-group communication destination is the master unit based on the judgement; acquire the judging criterion information of the intra-group communication destination detected as the master unit; and switch, while the self device is operating by a master unit operation mode and when the other master unit is detected by monitoring, a master unit operation mode of the self device to a slave unit operation mode based on the judging criterion information of the self device and the judging criterion information of the other master unit.
A communication system includes a first communication apparatus communicating with a processing apparatus and a second communication apparatus performing an obtainment/transmission procedure of obtaining sensor information from a sensor unit and transmitting the sensor information to the first communication apparatus. The sensor unit includes at least one sensor. The first communication apparatus transmits the sensor information from the second communication apparatus to the processing apparatus, in response to an obtainment wish timing with which the processing apparatus wishes to obtain the sensor information. The second communication apparatus determines a start timing to start the obtainment/transmission procedure, based on a first time required to communicate between the first and second communication apparatuses when the second communication apparatus transmits the sensor information to the first communication apparatus.
H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
H04B 3/54 - Systems for transmission via power distribution lines
H04L 47/28 - Flow controlCongestion control in relation to timing considerations
6.
Communication system, master device, slave device and communication method
A master device transmits a first control signal including TS0(S) to a slave device and transmits a first data signal including TS0(M) to the master, the slave sets a point in time in the slave to T0(S) in time when the first control signal is received and transmits a second data signal including TS1(S) to the master, the master receives the second data signal and subtract TS1(S) from TS2(S) to calculate a round-trip delay time RTTs, and receives the first data signal and subtract TS0(M) from TS1(M) to calculate a round-trip delay time RTTm, the master transmits a data signal to the slave at a point in time that is obtained by TA−RTTm, and the slave puts the slave in a data receivable state at a point in time that is obtained by TA−RTTs.
H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
H04B 10/079 - Arrangements for monitoring or testing transmission systemsArrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
There is provided a to-be-protection circuit that is high in operation accuracy and that prevents overvoltage on a protected circuit. A protection circuit is configured to protect a to-be-protected circuit from overvoltage. The to-be-protected circuit is connected to an external output terminal. The protection circuit includes: a current path unit connected to the external output terminal and including at least one first element; a reference voltage generation unit which generates and outputs a reference voltage; and an amplifier circuit outputs a target voltage based on a difference between a first input voltage and a second input voltage. The amplifier circuit operates using the reference voltage as the first input voltage and using a feedback voltage based on the target voltage as the second input voltage, and outputs the target voltage to the current path unit. The reference voltage generation unit includes at least one second element having an operating characteristic corresponding to an operating characteristic of the at least one first element of the current path unit, and generates the reference voltage based on a voltage drop caused by the at least one second element.
H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage
H02H 1/00 - Details of emergency protective circuit arrangements
8.
POSE DATA GENERATION DEVICE, POSE DATA GENERATION METHOD, AND PROGRAM
The present invention achieves a low-cost pose data generation device for acquiring accurate pose data. The pose data generation device (100) integrates, for each part of a subject, a first reliability level based on a heatmap acquired by a heatmap acquisition unit and a second reliability level acquired by a reliability level acquisition unit, to thereby enable acquisition of an integrated reliability level, which is a more accurate reliability level, for each part. Accordingly, a precise two-dimensional pose data acquisition unit of the pose data generation device (100) acquires precise pose data on the basis of the integrated reliability level, enabling acquisition of accurate two-dimensional pose data. The pose data generation device (100) subjects the precise two-dimensional pose data acquired as described above to 2D-3D transformation, to thereby enable acquisition of accurate three-dimensional pose data.
09 - Scientific and electric apparatus and instruments
Goods & Services
Video cameras; mobile phones; integrated circuit chips for use with processing video; downloadable computer game software; recorded computer game software; computer hardware; computer storage devices, namely blank flash drives and solid state memory drives; computer peripherals; computers; calculators; cordless telephone devices; data processors; DVD players; electronic personal organizers; integrated circuits; interfaces for computers; memory cards for video game machines; microprocessors; laptop computers; electronic reading devices, namely, data processors; electric control machines and apparatus, namely, electronic control systems for machines; semi-conductors; smartphones; sound reproducing apparatus; sound transmitting apparatus; tablet computers; transmitting apparatus for wired and wireless telecommunications for industrial equipment, namely production machinery and equipment used in productions facilities of factories; central processing units; transmitters for electronic signals; transmitters for telecommunications; programming software for computer games recorded on ROM cartridge; video recorders; video screens; virtual reality headsets; clock generators for computers; oscillators; electronic data encryption devices for protecting data stored on computers; electronic integrated circuit providing authentication function; electronic encryption devices; real-time clocks (RTC) being electronic integrated circuits; electrical controlling devices; electric image analysis equipment, namely, scanner for capturing images for analysis for use in life science research; electronic control systems for machines; electric current control devices; testing apparatus, namely, continuity testing apparatus for electrical circuits; inspection devices, namely, ultrasound inspection devices for non-medical and non-destructive testing; apparatus for regulating the distribution or use of electric current; diagnostic apparatus, namely, electronic computer hardware for diagnostics of production machinery and equipment used in production facilities of factories; network servers; computer servers; machine learning devices, namely, data processors; inference apparatus, namely, data processors; inference engine being recorded computer search engine software; computers with a downloadable function of artificial intelligence; computers with a recorded function of artificial intelligence; downloadable computer programs and downloadable computer software for performing inference processing for production machinery and equipment used in productions facilities of factories for database management with a function of artificial intelligence; computer hardware with a function of artificial intelligence; data processors with a function of artificial intelligence; integrated circuits for use with artificial intelligence; integrated circuit chip for use in encoding and decoding digital video with artificial intelligence; downloadable computer programs and downloadable computer software for performing inference processing for artificial intelligence; information processing devices, namely, central processing units for processing information; memory cards
10.
Nonvolatile semiconductor storage device and read voltage correction method
A memory stores dummy data including a first data area having more “0” than “1” of a binary logic and a second data area having more “1” than “0” of the binary logic. An ECC processor detects a first error bit number related to the first data area and a second error bit number related to the second data area. A calculator calculates a relative difference of the first error bit number from the second error bit number. A comparator compares the relative difference with a predetermined value. A corrector corrects a read voltage on the basis of a result of comparison by the comparator.
A clock and data recovery circuit includes a phase detector that outputs phase characteristic data based on a digital data signal and an adjustment circuit that adjusts phase characteristic data. The clock and data recovery circuit sets an adjustment value in an adjustment circuit by calculating an adjustment value of phase characteristic data using a monitor circuit while changing a phase of a reference clock signal to be adjusted in a phase interpolation circuit based on offset data output from an offset output circuit in a training period before communication starts.
H03K 5/13 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
12.
Pose data generation device, CG data generation system, pose data generation method, and non-transitory computer readable storage medium
Provided is a system that estimates pose data of a person with high accuracy at low cost. At a time step at which image data is to be captured and obtained, a pose data generation system obtains pose data based on the image data. At a time step at which image data is not to be obtained, the pose data generation system predicts pose data at a current time step from a previous time step using IMU data and performs interpolation processing to obtain pose data. Thus, even when a rate of obtaining the image data is low, the pose data generation system performs the above interpolation processing using IMU data to obtain pose data with a high frame rate.
A clock and data recovery circuit includes a phase interpolation circuit that adjusts a phase of a reference clock signal generated by a reference clock generation circuit to generate a reception clock signal, a filter that performs filter processing on a data signal output from an ADC that converts an analog data signal to a digital data signal in synchronization with the clock signal, a phase comparison circuit that outputs phase difference data between a transmission-side clock signal and the reference clock signal based on an output of the filter, and a loop filter that generates phase data to be set in the phase interpolation circuit. The filter includes an FIR filter with a tap number N, and an FIR filter with a tap number N+1 that outputs a signal delayed by half a clock than the former FIR filter.
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
14.
PROCESSOR FOR NEURAL NETWORK, PROCESSING METHOD FOR NEURAL NETWORK, AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM
Provided is a processor for a neural network whose high-performance compact model can be incorporated into low-spec devices such as embedded devices or mobile devices without requiring re-training. The processor for a neural network, which uses a multi-valued basis matrix, widens the range of integer values that can be taken by each element of the multi-valued basis matrix; thus, the number of dimensions (the number of elements) of a scaling coefficient vector is reduced accordingly. The elements of the scaling coefficient vector are real numbers, and thus reducing the amount of processing of real number calculation processing allows for reducing the number of dimensions (the number of elements) of the scaling coefficient vector. As a result, this neural network processor significantly reduces the amount of calculation processing while ensuring the calculation accuracy when performing matrix calculation processing using the binary basis matrix.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
15.
Non-volatile storage device, data readout method, and non-transitory computer readable storage medium
Provided is a non-volatile storage system that performs error correction processing at high speed while ensuring error correction capability. When error correction decoding processing using data read first with hard-decision decoding processing has failed, a non-volatile storage device 2 reads data on the same page again, performs diversity synthesis processing on the readout data for the first time and the readout data for the second time on the same page as one for the first time, and then performs error correction processing using data after diversity synthesis processing.
An information processing apparatus includes: control circuitry; encryption processing circuitry; and communication circuitry. The control circuitry controls execution of predetermined processing in the information processing apparatus. The encryption processing circuitry encrypts or decrypts data flowing between the control circuitry and the communication circuitry. The communication circuitry transmits and receives the encrypted or decrypted data to and from an external device other than the information processing apparatus.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
H04L 29/06 - Communication control; Communication processing characterised by a protocol
17.
LED DRIVER MODULE AND METHOD FOR CORRECTING PWM SIGNAL BY LED DRIVER MODULE
The present invention is an LED driver module for controlling at least one LED panel provided with a group of pixels arranged into an array. This module is provided with: a PWM signal retention unit that retains PWM signals of respective subpixels constituting the pixels in at least one line of the LED panel, based on an image signal; and a correction processing unit that corrects, on the basis of a correction amount, the PWM signal retained in the PWM signal retention unit, and then outputs same. The correction processing unit determines the correction amount using a PWM value of a reference subpixel in one line of the LED panel, and corrects PWM values of subpixels to be corrected in the one line. The invention curbs the occurrence of a fringe phenomenon/reddishness phenomenon in image display of the LED display. Due to this configuration, the occurrence of the fringe phenomenon/reddishness phenomenon in image display of the LED display is curbed.
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
18.
INFORMATION PROCESSING SYSTEM, SERVER DEVICE, INFORMATION PROCESSING DEVICE, AND OPERATION CONTROL DEVICE
When this operation control device determines that a first signature in a first storage unit is correct, this information processing device transmits first version information. This server device transmits prescribed data upon determination that a version indicated by the first version information is older than a version indicated by second version information. When the operation control device determines that a second signature included in the prescribed data is correct, the information processing device updates first software, the first version information, and the first signature in the storage unit respectively by second software, the second version information, and the second signature included in the prescribed data.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
In a pose data generation system (1000): it is possible, in time steps in which image data is captured and acquired, to acquire pose data on the basis of the image data; and, in a period between the time steps in which image data is acquired, it is possible to acquire pose data through a process for predicting and interpolating the pose data of the current time step from the previous time step using IMU data, wherefore, even when the acquisition rate of image data is low, it is possible to acquire pose data having a high frame rate through the interpolation process in which IMU data is used.
A communication device includes a zero-forcing equalizer that receives a receipt signal and execute zero-forcing equalization on the receipt signal, a partial response equalizer that receives the receipt signal and execute partial response equalization on the receipt signal, a first weighted value calculator that calculates a first weighted value based on signal quality of the receipt signal output from the zero-forcing equalizer, a second weighted value calculator that calculates a second weighted value based on signal quality of the receipt signal output from the partial response equalizer, and an estimator that estimates a maximum likelihood sequence by supplying the first weighted value to state transition based on output by the zero-forcing equalizer and supplying the second weighted value to state transition based on output by the partial response equalizer.
SELF-ORGANIZING MAP LEARNING DEVICE AND METHOD, NON-TRANSITORY COMPUTER READABLE MEDIUM STORING SELF-ORGANIZING MAP LEARNING PROGRAM AND STATE DETERMINATION DEVICE
A Self-Organizing Map learning device includes a distance calculator that obtains a distance D between an input vector in an observation space and a reference vector of each neuron in a latent space, a smallest value neuron specifier that specifies a smallest value neuron having the smallest distance D, a neuron selector that selects M (M is an integer smaller than L) selection neurons from the L (L is equal to or larger than 2) smallest value neurons in a case where the L smallest value neurons are present, and an updater that updates the reference vector of each neuron in the latent space with the M selection neurons as winner neurons.
The purpose of the present invention is to provide an information processing device for cost reduction. In the present invention, command information (CM), which is output from a control unit (2) and intended to control a communication unit (3), flows, as communication data-on-bus (D1), on a bus (B1) that is a communication unit bus between the control unit (2) and the communication unit (3). A feature extraction device (4) receives the communication data-on-bus (D1) on the bus (B1) and executes a feature extraction process for extracting the feature expressed by the communication data-on-bus (D1) as a feature extraction log (L1). The feature extraction log (L1) extracted by the feature extraction device (4) is transmitted to an external server (8) through the control unit (2), the bus (B1), and the communication unit (3).
The present invention achieves a neural network processor which performs a high-performance neural network process while suppressing an increase of a hardware scale. In a neural network processor (100), process data of a feature extraction layer which is determined when a model of a neural network is decided is written in a ROM which is small in a hardware scale in the case of implementing hardware, and process data for a determination layer, data of which can be changed is held in a random access memory in which data is rewritable. Then, in the neural network processor (100), in the state described above, a process by the neural network is performed. As a result, it is possible to perform a high-performance neural network process while suppressing an increase of the hardware scale.
The objective of the present invention is to achieve a processor for a neural network with which a compact, high-performance model can be installed in a low-spec device such as a built-in device or a mobile device without requiring learning. A neural network processor (100) uses a multi-valued basic matrix, and there is accordingly a wide range of possible integer values that can be taken by each element in the multi-valued basic matrix; accordingly, the number of dimensions (number of elements) of a scaling coefficient vector can be reduced. The elements of the scaling coefficient vector are real numbers, so the processing load of real-number arithmetic processing can be reduced by reducing the number of dimensions (number of elements) of the scaling coefficient vector. Thus, this neural network processor (100) makes it possible to significantly reduce the arithmetic processing load while ensuring calculation precision when executing a matrix arithmetic processing using a binary basic matrix.
A communication system that uses a wired transmission line and multi-carrier modulation includes a transmitting device and a receiving device that are connected through the wired transmission line, wherein the receiving device includes an estimator configured to estimate a first SINR (Signal-to-Interference-Plus-Noise Ratio) of a first sub-carrier and a second SINR of a second sub-carrier, the transmitting device includes a power adjustor configured to boost a transmission power for the first sub-carrier such that an SINR of the first sub-carrier reaches a first SINR threshold corresponding to a first MCS (Modulation and Coding Scheme) that is larger than the first SINR, and back off a transmission power for the second sub-carrier such that an SINR of the second sub-carrier is lowered to a second SINR threshold corresponding to a second MCS that is smaller than the second SINR, and the transmitting device allocates the first MCS to the first sub-carrier.
An information processing system includes an information processing apparatus having a first function, and a server apparatus being configured to communicate with the information processing apparatus via a communication network. The information processing apparatus includes an operation control apparatus being configured to control the first function. The server apparatus transmits operation permission information indicating operation permission for the first function to the information processing apparatus, in response to satisfaction of a predetermined condition related to the information processing apparatus. The operation control apparatus activates the first function, in response to the operation permission information received by the information processing apparatus.
A memory device includes a memory core that stores data, an access controlling unit that controls an access to the memory core, and a random number generating unit that generates a random number based on an unstable factor related to an access operation to the memory core performed by the access controlling unit.
The present invention achieves a non-volatile storage system that executes error correction processing which enables high-speed processing while ensuring error correction capability. At a non-volatile storage device (2), if error correction decoding processing, which uses data read out a first time, fails according to hard-decision decoding processing: the same page of data is read out again; diversity synthesis processing is executed on the data read out the first time and the data read out the second time; and error correction processing is executed using the data after diversity synthesis processing.
A memory system connected to a host computer generating input information, includes a storage configured to store application program executed by the host computer, a contents database relating various contents candidate information used by the host computer with either of plural adjustment candidate identification information, and input information inputted from the host computer, circuitry configured to infer, by executing inference by an artificial intelligence algorithm, specific adjustment candidate identification information as adjustment identification information from the plurality of adjustment candidate identification information according to the input information and select specific contents candidate information as adjustment contents information from the contents database using the adjustment identification information and an interface configured to output the adjustment contents information to the host computer.
G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
A63F 13/60 - Generating or modifying game content before or while executing the game program, e.g. authoring tools specially adapted for game development or game-integrated level editor
G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
G06F 16/16 - File or folder operations, e.g. details of user interfaces specifically adapted to file systems
G06F 16/14 - Details of searching files based on file metadata
A63F 13/69 - Generating or modifying game content before or while executing the game program, e.g. authoring tools specially adapted for game development or game-integrated level editor by enabling or updating specific game elements, e.g. unlocking hidden features, items, levels or versions
A control circuit causes a first cryptographic module to perform a dummy operation in a command processing period and a data processing period in which a second cryptographic module performs a normal operation while the first cryptographic module does not perform a normal operation.
G06F 21/85 - Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
G09C 1/00 - Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
(n-1) base circuits and an (n−2)-bit decoder circuit in cases of n≥3, and includes the 1-bit decoder circuit in cases of n=2. The 1-bit decoder circuit outputs ‘00’ in cases of the binary input BIN<0>=‘0’ and outputs ‘01’ in cases of the binary input BIN<0>=‘1’ as thermometer outputs THM(1)<1:0>.
The present invention realizes a neural network processor which has a high-performance compact model mountable onto a low-specification device such as a built-in device or a mobile device without needing to learn. A neural network processor (100) can carry out a convolution layer process and a fully-connected layer process by commonizing portions of similar processes in the convolution layer process and the fully-connected layer process, and executing a process obtained by combining processes of a norm mode and an inner product calculation mode. Thus, the neural network processor (100) can carry out a multivalued neural network process at a high speed while curbing increases in hardware size.
A clock determination apparatus includes a signal wire and a clock determiner. A clock signal is input to the signal wire. A period made up of cycles corresponding to a predetermined number of cycles of the clock signal is referred to as a unit period. The clock determiner includes circuitry configured to perform determination processing whether the clock signal is a random clock signal including a cycle changing substantially irregularly as time proceeds or a regular clock signal including substantially a constant cycle based on a comparison between waveforms of the clock signals in a plurality of unit periods.
Macronix International Co., Ltd. (Taiwan, Province of China)
MegaChips Corporation (Japan)
Inventor
Yeh, Yuchih
Kuo, Naping
Tamagawa, Yuko
Abstract
Methods, systems and apparatus including computer-readable mediums for rearranging data for refresh operations in memory systems such as NAND flash memory devices are provided. In one aspect, a method includes: determining that a particular logical page in a logical block fails based on error bits in a particular physical page that is in a first physical block mapped with the logical block and corresponds to the particular logical page, logical pages in the logical block being mapped to physical pages in the first physical block with an initial mapping order, and executing a refresh operation on the first physical block with a rearranged mapping order for the logical block, the rearranged mapping order being different from the initial mapping order. For the refresh operation, the logical pages in the logical block are mapped to physical pages in a second physical block with the rearranged mapping order.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
This communication system using a wired transmission line and multi-carrier modulation comprises a transmitter and a receiver. The receiver includes an estimation unit that estimates a first SINR of a first sub-carrier and a second SINR of a second sub-carrier. The transmitter includes a power modulation unit which causes the transmission power of the first sub-carrier to increase such that the SINR of the first sub-carrier reaches a first SINR threshold value corresponding to a first MCS that is larger than the first SINR, and which causes the transmission power of the second sub-carrier to decrease such that the SINR of the second sub-carrier drops to a second SINR threshold value corresponding to a second MCS that is smaller than the second SINR. The transmitter allocates the first MCS to the first sub-carrier.
A host device includes a power supply unit configured to supply power to a SoC, a current measurement circuit configured to measure a current from the power supply unit to the SoC, a detection unit configured to detect a power supply glitch in the host device, on the basis of a result of current measurement by the current measurement circuit, and a controller configured to suspend transmission of encrypted command from the host device to the memory device if the detection unit detects a power supply glitch in the host device.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
H04L 9/00 - Arrangements for secret or secure communicationsNetwork security protocols
37.
INFORMATION PROCESSING SYSTEM, SERVER APPARATUS, INFORMATION PROCESSING APPARATUS, OPERATION CONTROL DEVICE, AND METHOD FOR OPERATING INFORMATION PROCESSING SYSTEM
This information processing system is provided with: an information processing apparatus having a first function; and a server apparatus capable of communicating with the information processing apparatus via a communication network. The information processing apparatus has an operation control device for controlling the first function. The server apparatus transmits, to the information processing apparatus, operation permission information indicative of permission for enabling the first function in response to fulfillment of a prescribed condition pertaining to the information processing apparatus. The operation control device enables the first function in accordance with the operation permission information received by the information processing apparatus.
G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
38.
Image processing device and image processing method
In the image processing device, to display, by the panel self-refresh, a still image corresponding to the image data having undergone the image processing, the switch signal generating circuit generates the switch signal controlling switching of the image data selected by the first to fourth switch circuits such that the input image data is subjected to the image processing by the first image processing circuit, that the image data having undergone the image processing is written in the frame buffer through control by the panel self-refresh control circuit, and that the image data having undergone the image processing as read out from the frame buffer is output from the fourth switch circuit or the image data having undergone the image processing is output from the fourth switch circuit via the third switch circuit.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
39.
High performance equalizer achieving low deterministic jitter across PVT for various channel lengths and data rates
A high performance equalization method is disclosed for achieving low deterministic jitter across Process, Voltage and Temperature (PVT) for various channel lengths and data rates. The method includes receiving input signal at front end of a receiver upon passing through a channel, generating with an eye-opening monitor circuit a control code based on channel conditions, and equalizing with a continuous-time linear equalization equalizer (CTLE) circuit the input signal based on the control code such that the eye-opening monitor circuit and the CTLE circuit are biased based on their corresponding replica circuits, and the control code is generated in a feedforward configuration.
A circuitry is configured to calculate a measured average value based on measured current values obtained in a target period for determination, and determine whether a memory device is an authorized or an unauthorized product, based on a comparison result between a measured average value and a reference average value.
G01R 21/133 - Arrangements for measuring electric power or power factor by using digital technique
G01R 21/06 - Arrangements for measuring electric power or power factor by measuring current and voltage
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G01R 19/257 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques using analogue/digital converters of the type with comparison of different reference values with the value of voltage or current, e.g. using step-by-step method
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
G06F 1/26 - Power supply means, e.g. regulation thereof
The circuitry is configured to determine whether an appurtenance device is an authorized or an unauthorized product, based on a comparison result between a measured current value pattern produced for a predetermined period and a reference current value pattern obtained in advance for the predetermined period.
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
G06F 1/26 - Power supply means, e.g. regulation thereof
G06F 21/73 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
42.
Information processing system, and method for determining authenticity of appurtenance device
Circuitry is configured to cause a memory device to perform a predetermined power consumption operation for authentication of the memory device in addition to a normal operation, and determine whether the memory device is an authorized or an unauthorized product, based on a measured current value measured in a period when the memory device performs the power consumption operation and a reference current value that is a current value in the power consumption operation by an authorized product.
A high performance phase-locked loop, the device includes a phase frequency detector, a charge pump, a loop filter, a first oscillator having inverters, configured to generate a first current, a second oscillator having a scaled version of the inverters of the first oscillator, a digital to analog converter, configured to generate a second current by multiplying the first current and a frequency code, a voltage to current converter, configured to generate a third current by converting voltage output of the loop filter to current, wherein input current to the second oscillator is sum of the second current and the third current.
H03K 5/1252 - Suppression or limitation of noise or interference
H03L 7/10 - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
H03K 3/011 - Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
The position of a moving object is estimated with high accuracy using landmark information, and highly accurate state estimation is performed appropriately at high speed. A landmark detection unit obtains a distance between the moving object and each of two or more landmarks as landmark distance information based on observation data obtained by an observation obtaining unit. A candidate area obtaining unit determines a candidate area for a position of the moving object based on the landmark distance information obtained by the landmark detection unit, and obtains candidate area information indicating the determined candidate area. A state estimation unit estimates an internal state of the moving object based on the observation data, the landmark distance information, and the candidate area information to obtain moving object internal state estimation data, and estimates the environmental map based on the candidate area information and the landmark distance information to obtain environmental map data.
09 - Scientific and electric apparatus and instruments
Goods & Services
Video cameras; mobile phones; integrated circuit chips for digital video compression and decompression; recorded computer game software; computer hardware; computer storage devices, namely, blank flash drives and external computer hard drives; computer peripherals; computers; calculators; cordless telephones; data processors; DVD players; electronic personal organizers; integrated circuits; interfaces for computers; memory cards for game machines; microprocessors; laptop computers; electronic reading devices, namely, data processors; electric control machines and apparatus, namely, electrical controlling devices; semi-conductors; smartphones; sound reproducing apparatus; sound transmitting apparatus; tablet computers; central processing units; telecommunications transmitters; transmitters of electronic signals; computer software for programming games recorded on ROM cartridge; video recorders; video screens; virtual reality headsets; clock generators for computers; oscillators; data encryption devices for protecting data stored on computers, namely, electronic encryption units; integrated circuit providing authentication function; electronic encryption units; real-time clocks; electrical controlling devices; electric image analysis equipment, namely, scanner for capturing images for analysis for use in life science research; electronic control system for engines and machines; control devices, namely, electronic controlling devices; testing apparatus, namely, electronic computer hardware for testing materials, parts and assemblies used or fabricated in production facilities of factories; inspection devices, namely, electronic computer hardware for inspecting materials, parts and assemblies used or fabricated in production facilities of factories; regulating apparatus, namely, electronic computer hardware for regulating production machinery and equipment used in production facilities of factories; diagnostic apparatus, namely, electronic computer hardware for diagnostics of production machinery and equipment used in production facilities of factories; network servers; computer servers; machine learning devices, namely, electronic computer hardware with recorded computer programs to perform machine learning in factory robots, testing apparatus, inspection devices, regulating apparatus, diagnostic apparatus, robots, game machines, smartphones, laptop computers, data processing circuits for factory machines, data processing circuits for handheld or portable devices, and electrical machine controllers using artificial intelligence; inference apparatus, namely, electronic computer hardware with recorded computer programs to perform an inference engine in factory robots, testing apparatus, inspection devices, regulating apparatus, diagnostic apparatus, robots, game machines, smartphones, laptop computers, data processing circuits for factory machines, data processing circuits for handheld or portable devices, and electrical machine controllers using artificial intelligence; recorded computer programs for performing an inference engine using artificial intelligence; computers with a function of artificial intelligence; recorded computer programs for performing artificial intelligence tasks; computer hardware with a function of artificial intelligence; processors with a function of artificial intelligence, namely, microprocessors, signal processors, and data processors with a function of artificial intelligence; integrated circuits with a function of artificial intelligence; integrated circuit chip for artificial intelligence; engines for artificial intelligence, namely, integrated circuit, computer hardware devices, field programmable gate arrays in the nature of an integrated circuit, digital signal processors, microprocessors, signal processors, and data processors; information processing devices, namely, microprocessors, signal processors, and data processors; and memory cards
09 - Scientific and electric apparatus and instruments
Goods & Services
Video cameras; mobile phones; integrated circuit chip recorded computer game software; computer hardware; computer storage devices, namely, recorded flash drives featuring games; computer peripherals; computers; calculators; cordless phone devices, namely, devices for hands-free use of mobile phones; data processors; DVD players; electronic personal organizers; integrated circuits; interfaces for computers; memory cards for game machines; microprocessors; laptop computers; electronic reading devices, namely, data processors; electric control machines and apparatus, namely, electrical controlling devices; semi-conductors; smart phones; sound reproducing apparatus; sound transmitting apparatus; tablet computers; central processing units; transmitting apparatus for telecommunications, namely, apparatus for transmitting and reproducing sound or images; transmitters for electronic signals; transmitters for telecommunications; recorded computer game software for programming games recorded on ROM cartridge; video recorders; video screens; virtual reality headsets; clock generators for computers; oscillators; data encryption devices for protecting data stored on computers, namely, electronic encryption units; integrated circuit providing authentication function; electronic encryption devices, namely, electronic encryption units; real-time clocks, namely, a computer clock in the form of an integrated circuit that keeps track of the current time; electrical controlling devices; electric image analysis equipment, namely, scanners and cameras for capturing images for analysis for use in the life science research field; electronic control system for engines and machines; control devices, namely, electronic controlling devices; testing apparatus, namely, electronic computer hardware apparatus for testing of material and parts and assemblies used or manufactured in production facilities of factories; inspection devices, namely, electronic computer hardware apparatus for inspecting materials, parts and assemblies used or manufactured in production facilities of factories for electronic goods; regulating apparatus, namely, electronic computer hardware apparatus for controlling operation of production machinery and equipment used in production facilities of factories; diagnostic apparatus, namely, electronic computer hardware apparatus that provides diagnostics of production machinery and equipment used in production facilities of factories; network servers; computer servers; machine learning devices, namely, electronic computer hardware apparatus with recorded computer programs to provide artificial intelligence functionality in factory robots, testing apparatus, inspection devices, regulating apparatus, diagnostic apparatus, robots, game machines, smart phones, laptop computers, data processing circuits for factory machines, data processing circuits for handheld or portable devices, and electrical machine controllers using artificial intelligence; inference apparatus, namely, electronic computer hardware apparatus with recorded computer programs to control operating conditions to improve and optimize performance in factory robots, testing apparatus, inspection devices, regulating apparatus, diagnostic apparatus, robots, game machines, smart phones, laptop computers, data processing circuits for factory machines, data processing circuits for handheld or portable devices, and electrical machine controllers using artificial intelligence; recorded computer programs for operating an inference engine using artificial intelligence; computers with a function of artificial intelligence; recorded computer programs for performing artificial intelligence tasks; computer hardware with a function of artificial intelligence; processors, namely, microprocessors, signal processors, data processors with a function of artificial intelligence; integrated circuits with a function of artificial intelligence; integrated circuit chip for artificial intelligence; engines for artificial intelligence, namely, integrated circuit hardware devices in the nature of integrated circuits, filed-programmable gate array, digital signal processors, microprocessors, signal processors, and data processors; information processing devices, namely, microprocessors, signal processors, data processors, and digital signal processors; memory cards
47.
BINARIZED NEURAL NETWORK PROCESSOR, DATA PROCESSING METHOD, AND PROGRAM
The purpose of the present invention is to achieve a binarized neural network processor capable of installing a high-performance, compact model in a low-specification device such as an embedded device or a mobile device, without learning being required. Provided is a binarized neural network processor (1000) wherein a weight computation process is executed by treating the majority of weight computation processes as bit computation processes using a binary base matrix and carrying out a very small quantity of real number computations (multiplication processes using a scaling coefficient vector). Thus, the binarized neural network processor (1000) enables execution of a high-precision weight computation process while restraining increase in hardware scale. Due to the above, the binarized neural network processor (1000) makes it possible to execute a weight computation process commensurate with that of a compact model (an approximation model of a learned model learned and acquired with a large-scale system) without re-learning being required.
A communication terminal device connected to a network and performing data communications between another communication terminal device through the network, includes a storage configured to store proper information used as a criterion for switching an operation mode between a master unit operation mode and a slave unit operation mode, and circuitry configured to switch the master unit operation mode of a self device to the slave unit operation mode based on the proper information, while the self device is operating by the master unit operation mode. The master unit operation mode is the operation mode of the communication terminal device operating as a master unit, and the slave unit operation mode is the operation mode of the communication terminal device operating as a slave unit.
This image processing device is provided with a generation unit, a determination unit, a first encoding unit, and a first transmission unit. The determination unit generates hierarchized data indicating a first image. The determination unit determines, from the hierarchized data on the basis of a prescribed reference, data to be transmitted. The first encoding unit generates first encoded data by compressing and encoding the data to be transmitted determined by the determination unit. The first transmission unit transmits the first encoded data.
This image processing device is provided with: a first generation unit; a second generation unit; a first determination unit; an encoding unit; and a first transmission unit. The first generation unit generates hierarchized data indicating a frame image. The second generation unit generates differential hierarchized data indicating differences in the hierarchized data of two frame images. The first determination unit determines data to be transmitted from the differential hierarchized data, on the basis of first data, among the differential hierarchized data, which has an absolute value equal to or greater than a threshold value. The encoding unit generates encoded data by compressing and encoding the data to be transmitted. The first transmission unit transmits the encoded data.
H04N 19/30 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability
H04N 19/63 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using sub-band based transform, e.g. wavelets
51.
MOTION ANALYSIS DEVICE, INFORMATION ACCEPTING SYSTEM, AND INPUT ACCEPTING METHOD
This information accepting system is configured to be provided with: a motion analysis device which analyzes the motion of an object; and an input analysis device. Further, the motion analysis device is configured to be provided with: a storage device which stores component definition information that defines a plurality of basic motion components constituting the motion of the object; an MPU which generates presence information by determining, on the basis of the component definition information and detection information indicating physical quantities involved in actual motion of the object, whether the basic motion components are present in the actual motion of the object; and an interface unit which outputs, to the input analysis device, the presence information as a result of analysis of the motion of the object.
Upon receiving an erase command and a first logical address, a controller in a first mode sets, as an erasure waiting area, an erasure unit area assigned with a first physical address associated with the first logical address in a first table. The controller in the first mode replaces, in the first table, the first physical address with a physical address assigned to an erasure completion area. The controller in a second mode sets the erasure waiting area as the erasure completion area. Upon receiving a release command to release the second mode at some point in time of data erasure from the erasure waiting area, the controller changes the operation mode to a third mode. The controller operating in the third mode erases un-erased data from the erasure waiting area and changes the operation mode from the third mode to the first mode.
A pattern antenna, with excellent broadband antenna characteristics, that is formed in a small area is provided. The pattern antenna includes a substrate, a first ground portion formed on a first surface of the substrate, an antenna element portion, a protruding and short-circuiting portion, and a second ground portion. The antenna element portion includes a conductor pattern in which a plurality of bent portions are formed. The conductor pattern is formed on the first surface of the substrate and is electrically connected to the first ground portion. The protruding and short-circuiting portion includes a taper portion with a tapered shape, a protruding portion, and an extended portion extended toward a side opposite to a feed point as viewed in planar view. The second ground portion, with no contact with the taper portion, with such a shape that sandwiches at least a part of a tapered section of the taper portion as viewed in planar view.
A noise generation module generates power consumption noise to conceal the power consumption characteristics of a cryptographic module. The cryptographic module performs first non-linear transformation on received data, and the noise generation module performs second non-linear transformation on received data during the operational period of the first non-linear transformation.
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04L 9/00 - Arrangements for secret or secure communicationsNetwork security protocols
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
G06F 7/58 - Random or pseudo-random number generators
55.
Projection system, projector apparatus, imaging apparatus, and projection method
Even when a high-performance imaging apparatus is not used, luminance unevenness and color unevenness of an image (video) projected on a projection plane by the projection type projector apparatus are appropriately reduced. Using a coefficient Br (0≤Br≤1) set by a coefficient setting unit, the projection system obtains, based on the gamma characteristic of the entire system of the projection system, a target image for reducing the number of pixels saturated when the image is projected. Then, the projection system performs correction processing using the obtained target image based on the gamma characteristic of the entire system of the projection system and a white value. This reduces the number of saturated pixels of the projected image in the projection system. Furthermore, even in a case or similar cases when a captured image obtained by capturing a projected image has a bad S/N ratio, image projection processing that does not cause a user discomfort in viewing the projected image (or captured image) is achieved.
G03B 21/14 - Projectors or projection-type viewersAccessories therefor Details
H04N 9/31 - Projection devices for colour picture display
G03B 21/13 - Projectors for producing special effects at the edges of picture, e.g. blurring
G06T 3/00 - Geometric image transformations in the plane of the image
G03B 37/04 - Panoramic or wide-screen photographyPhotographing extended surfaces, e.g. for surveyingPhotographing internal surfaces, e.g. of pipe with cameras or projectors providing touching or overlapping fields of view
56.
Projection system, projector apparatus, and projection method
Provided is a projection system that easily and appropriately reduces the geometric distortion of the image projected on the projection plane. The projection circuitry 3 of the projection system 1000 projects a test image onto the projection plane. The three-dimensional shape measurement circuitry 4 measures the three-dimensional shape of the projection plane. The controller 200 generates a control signal. Based on the measured three-dimensional shape data, the projection image adjustment circuitry 1 performs correction processing and rotation processing on a test, in accordance with the control signal, such that the geometrical image distortion is reduced as viewed from the user's viewpoint.
Provided is a projection system that sets an arbitrary three-dimensional shape as a projection target and properly corrects geometric distortion of a projected image even when a user's viewpoint is not fixed. A projection unit of the projector apparatus projects a test image for first adjustment. A three-dimensional shape measurement unit measures the three-dimensional shape of the projection target. An image capturing apparatus captures the test image for first adjustment projected by the projection unit to obtain a captured image for first adjustment. A projected image adjustment unit (1) performs first adjustment processing for correcting an image such that geometric image distortion viewed from an imaging point, at which the captured image for first adjustment has been captured, is reduced, based on a captured image for first adjustment obtained by the image capturing apparatus, and (2) performs second adjustment processing for correcting the image such that the geometric image distortion is reduced based on a state in which the image adjusted by the first adjustment processing is projected by the projection unit.
H04N 9/31 - Projection devices for colour picture display
G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
G09G 5/36 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory
G09G 3/00 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
G01B 11/24 - Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures
G01B 11/25 - Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures by projecting a pattern, e.g. moiré fringes, on the object
58.
Semiconductor device and method for designing a semiconductor device
A semiconductor design apparatus computes a consumption current in a macro cell region in the semiconductor device. A first region is defined to be a first shape and size on an upper surface on at least one end of a one-side end portion of the macro cell region based on the consumption current in the macro cell region and an allowable current per via that connects a power supply layer and the macro cell region to each other. A second region is defined as a second shape and size on the upper surface of the macro cell region based on the first region. The apparatus determines an arrangement of the macro cell region and the power supply layer based on the second region and determines the arrangement of vias in the second region based on the arrangement of the macro cell region and the power supply layer.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/528 - Layout of the interconnection structure
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
09 - Scientific and electric apparatus and instruments
38 - Telecommunications services
Goods & Services
Video cameras; mobile phones; integrated circuit chip; computer game software; computer hardware; computer storage devices; computer peripherals; computers; calculators; cordless phone devices; data processors; DVD players; electronic personal organizers; integrated circuits; interfaces for computers; memory cards for video game machines; micro processors; laptop computers; electronic reading devices namely data processors; electric control machines and apparatus; semi-conductors; smartphones; sound reproducing apparatus; sound transmitting apparatus; tablet computers; central processing units; transmitting apparatus for telecommunications; transmitters for electronic signals; transmitters for telecommunications; programming software for TV-game recorded on ROM cartridge; video recorders; video screens; virtual reality headsets; clock generators for computers; oscillators; data encryption devices for protecting data stored on computers; integrated circuit providing authentication function; electronic encryption devices; real-time clocks; electrical controlling devices; electric image analysis equipment Communication by mobile phones; communication by computer terminals; communication by fiber optic networks; transmission exchange of messages and images using computers; communication by electronic bulletin boards; providing information about telecommunications; providing communication network connection by computer terminals; provision of video conferencing services; streaming of data; providing on-line forums for transmission of messages among computer users; providing telecommunications channels for teleshopping services; wireless broadband communications services; telecommunications services namely transmission of voice, data, graphics, sound and video by means of broadband power lines of wireless networks; broadcast communication services, namely transmissions of e-mails, faxes, text messages and telephone messages to dedicated recipients, for others
09 - Scientific and electric apparatus and instruments
38 - Telecommunications services
Goods & Services
Video cameras; mobile phones; integrated circuit chip; computer game software; computer hardware; computer storage devices; computer peripherals; computers; calculators; cordless phone devices; data processors; DVD players; electronic personal organizers; integrated circuits; interfaces for computers; memory cards for video game machines; micro processors; laptop computers; electronic reading devices namely data processors; electric control machines and apparatus; semi-conductors; smartphones; sound reproducing apparatus; sound transmitting apparatus; tablet computers; central processing units; transmitting apparatus for telecommunications; transmitters for electronic signals; transmitters for telecommunications; programming software for TV-game recorded on ROM cartridge; video recorders; video screens; virtual reality headsets; clock generators for computers; oscillators; data encryption devices for protecting data stored on computers; integrated circuit providing authentication function; electronic encryption devices; real-time clocks; electrical controlling devices; electric image analysis equipment Communication by mobile phones; communication by computer terminals; communication by fiber optic networks; transmission exchange of messages and images using computers; communication by electronic bulletin boards; providing information about telecommunications; providing communication network connection by computer terminals; provision of video conferencing services; streaming of data; providing on-line forums for transmission of messages among computer users; providing telecommunications channels for teleshopping services; wireless broadband communications services; telecommunications services namely transmission of voice, data, graphics, sound and video by means of broadband power lines of wireless networks; broadcast communication services, namely transmissions of e-mails, faxes, text messages and telephone messages to dedicated recipients, for others
61.
Blood pressure measurement apparatus and blood pressure measurement method
A blood pressure measurement apparatus includes circuitry configured to: detect a pulse of a subject, and obtain a photoplethysmography signal; and obtain estimated blood pressure of the subject based on the photoplethysmography signal. The circuitry receives parameter information, generates time information based on the photoplethysmography signal, applies a blood pressure estimation equation to the time information and the parameter information to calculate the estimated blood pressure, receives basic blood pressure information for the subject and the time information, and performs learning processing of applying a learning operational equation to statistical time information, which is obtained by performing statistical processing on the time information, and the basic blood pressure information to update the parameter information.
Provided is a state determination apparatus that appropriately performs pattern classification processing and/or pattern determination processing even when a map generated by the SOM technique includes discontinuous image regions. In the state determination apparatus, the matching processing unit obtains adaptability data indicating a correlation degree between template data indicating a state and the SOM output data. The state determination unit obtains a state evaluation value based on an activity value obtained by the activity value obtaining unit and the adaptability value. The time series estimation unit determines a state of an input data based on the state evaluation value and state transition probability between states. This allows for appropriately performing pattern classification processing and/or pattern determination processing even when a map generated by the SOM technique includes discontinuous image regions.
An encryption circuit includes a fundamental vector generation circuit configured to generate a random number sequence for serving as a fundamental vector based on an initial vector, an image mask generation circuit configured to generate an image mask with a mask value set for each pixel in a region to be encrypted smaller than a frame size of the image, based on the fundamental vector and coordinate information for specifying the region to be encrypted, and an XOR operation circuit configured to compute an exclusive OR between each mask value of the image mask and each pixel value of the image data to generate encrypted image data.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
A frequency stable oscillator with compensation circuit, the device includes a ring oscillator circuit having S number of stages, a current generator circuit configured to generate a first current, a replica circuit having an inverter with output connected to input, configured to generate a first voltage upon dumping a second current onto the replica circuit, a first operational transconductance amplifier (OTA) with an input as the first voltage, configured to generate a third current and a current mirror circuit configured to generate a fourth current by adding the first current and the third current in a particular ratio M:N, wherein the inverter of the replica circuit is equivalent to a single stage of the ring oscillator circuit and wherein the fourth current is the total current for the ring oscillator circuit and is as close as possible to S times the second current.
A signal generation device outputs a signal based on a predetermined pattern with a logic transition to a predetermined external device. The signal generation device comprises an output driver which outputs respective signals based on at least two test patterns different in the frequency of the logic transition respectively to the predetermined external device, a regulator which supplies power to the output driver, a current compensation circuit which generates a compensation current, and a control circuit which adjusts a value of the compensation current. The control circuit adjusts, for each test pattern, the value of the compensation current such that a difference value calculated based on output voltages of the regulator becomes a determination criteria value or less.
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
A clock correction device performs skew adjustment and duty correction of an input clock concurrently or in parallel. The clock correction device includes a correction circuit that performs skew adjustment of an input clock by analog control using a skew adjustment signal based on a phase difference between an output clock and a reference clock, receives a duty control signal, and performs duty correction of the input clock by digital control, a skew detection circuit that receives inputs of the output clock and the reference clock and, when only the reference clock is in a predetermined state, outputs a detection signal that changes to the predetermined state, an integration circuit that integrates the detection signal and generates a first voltage signal, and a comparator that compares the first voltage signal and a first reference signal to thereby generate the skew adjustment signal.
Provided is a state determination apparatus that appropriately performs pattern classification processing and/or pattern determination processing even when a map generated by the SOM technique includes discontinuous image regions (e.g., split image regions). In the state determination apparatus, the matching processing unit obtains adaptability data indicating a correlation degree between template data indicating a predetermined state and the SOM output data. The state determination unit determines a state of an input data. This allows for appropriately performing pattern classification processing and/or pattern determination processing even when a map generated by the SOM technique includes discontinuous image regions (e.g., split image regions).
An efficient test for a flash memory combined with a logic chip and incorporated in a semiconductor integrated device can be executed.
A logic chip combined with a rewritable nonvolatile memory and incorporated in a semiconductor integrated device is provided with a test circuit. The test circuit reads a programmable test sequence transmitted from an external tester and stored, generates a memory control signal specific to the nonvolatile memory in accordance with a product ID read on the basis of the test sequence, executes a test in which the generated memory control signal is outputted to the nonvolatile memory, and outputs, to the tester, a test result based on a value outputted from the nonvolatile memory in response to the memory control signal.
G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
G11C 29/48 - Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
A feature image generation apparatus includes circuitry. The circuitry generates, on the basis of a processing target image in which an object appears, a first image showing the object, and generates, as a feature image showing a feature of the object, at least a part of a rotational composite image obtained by composition of a plurality of rotated images obtained by rotating the first image.
G06K 9/48 - Extraction of features or characteristics of the image by coding the contour of the pattern
G06K 9/46 - Extraction of features or characteristics of the image
G07D 5/00 - Testing specially adapted to determine the identity or genuineness of coins, e.g. for segregating coins which are unacceptable or alien to a currency
G06K 9/62 - Methods or arrangements for recognition using electronic means
G06K 9/32 - Aligning or centering of the image pick-up or image-field
A positioning device is provided with a storage device for storing reference position information and parameter information, an observation device for acquiring observation information, a first positioning unit for acquiring relative position information on the basis of the observation information and the parameter information, a second positioning unit for acquiring absolute position information, a position computation unit for computing position information that indicates the position where the positioning apparatus is present on the basis of the reference position information and the relative position information, a situation determination unit for estimating the situation on the basis of the observation information, and a data updating unit for updating the parameter information on the basis of the position information and the absolute position information in accordance with the result of estimation by the situation determination unit. The observation device includes a motion detection sensor for acquiring motion information that pertains to movement of the positioning apparatus and including the motion information in the observation information.
G01C 21/26 - NavigationNavigational instruments not provided for in groups specially adapted for navigation in a road network
G01C 21/28 - NavigationNavigational instruments not provided for in groups specially adapted for navigation in a road network with correlation of data from several navigational instruments
71.
Scan test circuit, scan test method, and method of designing scan test circuit
A scan test circuit includes a scan chain formed of a plurality of sub-scan chains, an input distribution circuit, and an output compression circuit. With the use of a bypass circuit, a plurality of sub-scan chains are formed in a compression scan mode by connecting scan cell circuits of a high confidentiality-requiring circuit among a plurality of scan cell circuits included in an internal circuit, and a plurality of sub-scan chains are formed in a non-compression scan mode by bypassing the scan cell circuits of the high confidentiality-requiring circuit.
In the frequency calibration circuit, the digital phase-locked-loop circuit repeats a calibration operation involving outputting the digital control signal corresponding to a time difference between the first clock signal which is input from the first oscillator and has a first frequency accuracy, and the second clock signal which is input from the second oscillator and has a second frequency accuracy lower than the first frequency accuracy, changing the capacitance of the discrete type capacitor bank in accordance with the digital control signal using the second oscillator as a digital control oscillator, and changing an oscillation frequency of the second clock signal in accordance with the capacitance of the discrete type capacitor bank, thereby calibrating a phase of the second clock signal to a phase of the first clock signal.
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
H03L 1/02 - Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
A light receiving element includes a first semiconductor layer of a first conductivity type to which a first potential is to be applied, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, first and second regions of the first conductivity type formed in an upper portion of the second semiconductor layer, a first electrode that is located on the first region and is to be subjected to application of a second potential, a second electrode located on the second region, an insulation layer formed on the second semiconductor layer between the first and the second regions, and a gate electrode that is formed on the insulation layer and is to be subjected to application of a gate voltage. A current readout unit detects, as a pixel signal reflecting an amount of light received, a current flowing from the first region to the second region.
H01L 31/113 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect photo- transistor being of the conductor-insulator- semiconductor type, e.g. metal- insulator-semiconductor field-effect transistor
H04N 5/232 - Devices for controlling television cameras, e.g. remote control
In an earliest vertical synchronization period after sending an encoded image data is restarted, a first reference image determination circuit determines to employ a local decoded image generated in a vertical synchronization period immediately preceding a vertical synchronization period in which an error occurs among multiple local decoded images stored in a first DRAM as a reference image. In an earliest vertical synchronization period after a decoding circuit is reset, a second reference image determination circuit determines to employ a decoded image generated in the vertical synchronization period immediately preceding the vertical synchronization period in which the error occurs among multiple decoded images stored in a second DRAM as a reference image.
G06K 9/36 - Image preprocessing, i.e. processing the image information without deciding about the identity of the image
G06K 9/46 - Extraction of features or characteristics of the image
H04N 19/65 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using error resilience
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 19/164 - Feedback from the receiver or from the transmission channel
75.
Method and device for calculating average received power
A device for calculating an indication of power of a received radio signal is disclosed. In one aspect, the device includes a receiver for receiving a plurality of logarithmic values representing a sequence of measurements of power of the received radio signal, and circuitry for determining a sum of the plurality of logarithmic values. The circuitry includes an adder for pairwise summing of two logarithmic values and a plurality of memory registers. The plurality of memory registers are arranged to store intermediate sums of logarithmic values. The circuitry is arranged to control the adder to sum the plurality of logarithmic values by a recursive procedure such that the first and the second logarithmic value in individual summations of the recursive procedure represent substantially same number of power measurements.
Provided is a state estimation apparatus that enables more accurate and robust detection and tracking of an object by obtaining a plurality of sets of observation data for a tracking target object and estimating the internal state of the object using a plurality of likelihoods calculated from the obtained sets of observation data. The state estimation apparatus obtains first observation data and second observation data, each of which is composed of a plurality of pieces of observation data, and obtains possibility measurement data and necessity measurement data from the obtained plurality of pieces of observation data. In the state estimation apparatus, a likelihood obtaining unit obtains a first likelihood wp and a second likelihood wn from the possibility measurement data and the necessity measurement data. Using the obtained first likelihood wp and second likelihood wn enables the internal state of the object to be estimated.
A random number generating device includes an uncertain circuit which outputs uncertain data, and a cipher processing device. The cipher processing device encrypts input data using a cipher function of the cipher processing device, and generates a random number including higher uniformity than data outputted from said uncertain circuit using the cipher function of the cipher processing device and the data outputted from the uncertain circuit.
H04L 9/26 - Pseudorandom key sequence combined element-for-element with data sequence with particular pseudorandom sequence generator producing a nonlinear pseudorandom sequence
G09C 1/00 - Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
G06F 7/58 - Random or pseudo-random number generators
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
A pattern antenna, with excellent broadband antenna characteristics, that is formed in a small area is provided. The pattern antenna includes a substrate, a first ground portion formed on a first surface of the substrate, an antenna element portion, a protruding and short-circuiting portion, and a second ground portion. The antenna element portion includes a conductor pattern in which a plurality of bent portions are formed. The conductor pattern is formed on the first surface of the substrate and is electrically connected to the first ground portion. The protruding and short-circuiting portion includes a taper portion with a tapered shape, a protruding portion, and an extended portion extended toward a side opposite to a feed point as viewed in planar view. The second ground portion, with no contact with the taper portion, with such a shape that sandwiches at least a part of a tapered section of the taper portion as viewed in planar view.
A control circuit causes a first cryptographic module to perform a dummy operation in a command processing period and a data processing period in which a second cryptographic module performs a normal operation while the first cryptographic module does not perform a normal operation.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
G06F 21/85 - Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
G09C 1/00 - Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
A control circuit of a memory device feeds a first clock received from a transmission control circuit of a host device back to a reception control circuit of the host device as a second clock. The reception control circuit controls data reception from the memory device in synchronization with the fed-back second clock.
The present invention addresses the problem of generating a composite image having a restored ROI even when using an insufficient ROI, and the problem of adjusting the compositing state. A compositing execution unit (1270) distinguishes an ROI coefficient and a non-ROI coefficient, in relation to first wavelet coefficient data (A61) corresponding to a first target image, on the basis of mask data (B61) expanded for use with the first wavelet coefficient data (A61). The compositing execution unit (1270) composites (carries out coefficient compositing processing on) the ROI coefficient, which is within the first wavelet coefficient data (A61), and a coefficient that is within second wavelet coefficient data (D61) corresponding to a second target image. As a result, composited coefficient data (E61) is generated. An inverse wavelet conversion unit (1280) carries out inverse wavelet conversion on the composited coefficient data (E61) until the decomposition level reaches a predetermined termination level. As a result, composite image data (E80) is generated.
H04N 19/167 - Position within a video image, e.g. region of interest [ROI]
H04N 19/122 - Selection of transform size, e.g. 8x8 or 2x4x8 DCTSelection of sub-band transforms of varying structure or type
H04N 19/18 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a set of transform coefficients
H04N 19/63 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using sub-band based transform, e.g. wavelets
82.
IMAGE PROCESSING SYSTEM AND IMAGE PROCESSING METHOD
The present invention addresses the problem of generating a composite image having a restored ROI even when using an insufficient ROI, and the problem of adjusting the compositing state. A wavelet conversion unit (510) carries out wavelet conversion on image data (A60, D60) up to a designated decomposition level that is designated by compositing control data (C50), and generates wavelet coefficient data (A61, D61). On the basis of mask data (B60), a compositing execution unit (520) distinguishes an ROI coefficient and a non-ROI coefficient, which pertain to an ROI, in relation to the coefficient data (A61), and generates composited coefficient data (E61) by compositing an ROI coefficient, which is within the coefficient data (A61), and a wavelet coefficient, which is within the coefficient data (D61). An inverse wavelet conversion unit (530) carries out inverse wavelet conversion on the coefficient data (E61) until the decomposition level reaches 0, and thereby generates composite image data (E80).
H04N 19/167 - Position within a video image, e.g. region of interest [ROI]
H04N 19/122 - Selection of transform size, e.g. 8x8 or 2x4x8 DCTSelection of sub-band transforms of varying structure or type
H04N 19/18 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a set of transform coefficients
H04N 19/63 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using sub-band based transform, e.g. wavelets
83.
PROJECTION SYSTEM, PROJECTOR DEVICE, IMAGING DEVICE, AND PROGRAM
The present invention appropriately reduces brightness unevenness and color unevenness in an image (video) projected on a projection surface by a projection-type projector device even when a high-performance imaging device is not used. In this projection system (1000), a target image, in which the number of pixels saturated when being projected is reduced, is obtained using a coefficient Br (0≤Br≤1) set by a coefficient setting unit (1), on the basis of the gamma characteristics of the entire projection system. Then, in the projection system (1000), correction processing is performed on the obtained target image on the basis of the gamma characteristics of the entire projection system and the white value. Thus, in the projection system (1000), the number of saturated pixels in the projected image is reduced, and, for example, even when a captured image obtained through capture of the projected image has a poor S/N ratio, image projection processing can be achieved without bringing discomfort to a user who watches the projected image.
A makeup assistance system configured with a portable terminal device carried by a user when the user applies makeup to her or himself and a measurement device configured as a stationary device differing from the portable terminal device and connected in a state in which data communication to the portable terminal device is possible. The measurement device is provided with a measurement control unit for acquiring information pertaining to the three-dimensional shape of the user and creating three-dimensional shape information, and a communication unit for transmitting the three-dimensional shape information created by the measurement control unit to the portable terminal device. The portable terminal device is provided with an image-capturing unit for image-capturing the user when applying makeup and acquiring image-capture information, and an information creation unit for creating makeup assistance information for assisting with the makeup applied to the user on the basis of the received three-dimensional shape information and the image-capture information acquired by the image-capturing unit.
G06T 19/00 - Manipulating 3D models or images for computer graphics
G01B 11/25 - Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures by projecting a pattern, e.g. moiré fringes, on the object
The present invention realizes a projection system for easily and appropriately reducing the geometric distortion of an image projected to a projection plane. The projection unit (3) of a projection system (1000) projects a test image to the projection plane. A three-dimensional shape measurement unit (4) measures the three-dimensional shape of the projection plane. A controller (200) generates a control signal. A projection image adjustment unit (1) executes, in accordance with the control signal, a correction process and a rotation process on the test image on the basis of data of the measured three-dimensional shape, so that the geometric distortion of an image is reduced when seen from a user’s viewpoint.
H04N 5/74 - Projection arrangements for image reproduction, e.g. using eidophor
G03B 21/14 - Projectors or projection-type viewersAccessories therefor Details
G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
G09G 5/36 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory
H04N 9/31 - Projection devices for colour picture display
In a clustering device 10, a feature extraction unit 11 extracts features from each of a plurality of transition candidate data items 141 used in machine learning that has transition learning introduced, and generates a plurality of transition candidate feature data items 142. A classification unit 12 classifies the transition candidate feature data items 142 into a plurality of groups including a first group, on the basis of a feature amount of each of the plurality of transition candidate feature data 142 items. A pre-domain determination unit 14 determines the first group to be a pre-domain if the number of transition candidate feature data items 142 that have been classified into the first group is equal to or less than a prescribed classification continuation reference value, and makes the determination to further classify the transition candidate feature data items 142 that have been classified into the first group if the number of transition candidate feature data items 142 is larger than the classification continuation reference value.
A pixel interpolation processing apparatus and an image capturing apparatus are provided that are capable of performing a pixel interpolation process properly even when the pattern of color filter array is unknown. An imaging apparatus includes an imaging unit having a single-chip image sensor having four-color filter array for obtaining an image signal, and the imaging apparatus uses pixel data for a surrounding area around a target pixel to calculate a plurality of sets of correlation values in two directions orthogonal to each other, and determines the correlation direction based on these correlation values. The imaging apparatus obtains first to fourth color component pixel values for the target pixel relying on the fact that the high-frequency components of pixel signals in a direction orthogonal to a direction with high correlation have high correlation regardless of the color of color filters, thus allowing for performing pixel interpolation processing properly even if the four colors of color filters are unknown.
A testing circuit is arranged in a semiconductor integrated circuit so as to detect a delay fault in the semiconductor integrated circuit. The semiconductor integrated circuit includes a first output control circuit having a plurality of sequential circuits, a first combination circuit connected to the first output control circuit, and a memory circuit connected to the first combination circuit. The testing circuit includes the first output control circuit; a second output control circuit; and a third output control circuit. The testing circuit, under control of a testing apparatus connected to the semiconductor integrated circuit, is configured to perform steps to detect the delay fault in the semiconductor integrated circuit.
The position of a moving object is estimated with high accuracy based on landmark information, and highly accurate state estimation is performed appropriately at high speed. A landmark detection unit obtains a distance between the moving object and each of two or more landmarks as landmark distance information based on observation data obtained by an observation obtaining unit. A candidate area obtaining unit determines a candidate area for a position of the moving object based on the landmark distance information obtained by the landmark detection unit, and obtains candidate area information indicating the determined candidate area. A state estimation unit estimates an internal state of the moving object based on the observation data, the landmark distance information, and the candidate area information to obtain moving object internal state estimation data, and estimates the environmental map based on the candidate area information and the landmark distance information to obtain environmental map data.
A moving object controller efficiently generates an environmental map and performs highly accurate state estimation in a short time to appropriately control a moving object. An observation obtaining unit obtains observation data from an observable event. A landmark prediction unit generates a landmark prediction signal including predictive information about a landmark at a current time. A landmark detection unit detects information about the landmark at the current time, and generates a landmark detection signal indicating the detection result. A state estimation unit estimates an internal state of the moving object to obtain data indicating an estimated internal state of the moving object at the current time, and estimates the environmental map based on the landmark detection signal to obtain data indicating an estimated environmental map at the current time.
The present invention implements a projection system which appropriately corrects geometric distortion of a projected image even when an object to be projected has an arbitrary three-dimensional shape and a user's point of view is not fixed. A projection unit (3) of a projector device 100 projects a first adjustment test image. A three-dimensional shape measurement unit (4) measures a three-dimensional shape of the object to be projected. An image capturing device (200) captures the first adjustment test image projected by the projection unit (3), and acquires a first adjustment captured image. A projected image adjustment unit (1) executes: (1) first adjustment processing for, on the basis of the first adjustment captured image acquired by the image capturing device (200), correcting the image such that geometric image distortion is reduced at an image capturing point at which the first adjustment captured image was captured; and (2) second adjustment processing for, on the basis of a state when the image adjusted by the first adjustment processing was projected by the projection unit (3), correcting the image such that geometric image distortion is reduced.
H04N 5/74 - Projection arrangements for image reproduction, e.g. using eidophor
G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
G09G 5/36 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory
92.
VOICE RECOGNITION SYSTEM AND VOICE RECOGNITION METHOD
[Solution] A portable terminal apparatus of this voice recognition system is provided with: a CPU capable of switching the operation mode between normal operation mode and power-saving mode; and an MPU including an event detection unit that detects a currently occurring event from among a plurality of events estimated in advance on the basis of observation information indicating a physical quantity for detecting an event, and a voice recognition unit that executes voice recognition on the basis of voice information and selected dictionary information. One voice dictionary candidate is selected from among a plurality of voice dictionary candidates according to the detected event, and the selected voice dictionary candidate is stored, as selected dictionary information, in a storage device. Further, the MPU is designed such that power consumption when operating the MPU while the CPU is in the power-saving mode is less than power consumption when operating the CPU in the normal operation mode.
An information reception system for receiving input information in accordance with an operation performed by a user is provided with: an operation unit having thereon an operation surface that is adjusted so as to generate specific indicative vibrations when touched by an object; a storage device for storing, in the form of a database, candidate information for input information candidates in association with the specific indicative vibrations; microphones for monitoring actual vibrations occurring in the surrounding environment and acquiring the monitored result as monitoring information; and a selection unit that determines the presence of indicative vibrations in the acquired monitored information and, when the presence of an indicative vibration is determined, selects candidate information associated with the indicative vibration as input information.
The objective of the present invention is to provide a pulse measuring device employing an optical pulse sensor, with which a pulse can be measured accurately using a relatively simple configuration. An FFT (64), which is a Fourier transform processing unit in the pulse measuring device according to the present invention, obtains a Fourier calculation mean value (M50), which is the mean value of Fourier calculation results (D51 to D55) obtained by subjecting each of a plurality of segment signals (S51 to S55) to Fourier transform processing. A pulse detecting unit (65) executes a pulse detecting process in which a peak frequency, which is a frequency component at a peak position, is obtained from the Fourier calculation mean value (M50), and a BPM value corresponding to the peak frequency is output as a pulse detection result (D65). The pulse detecting unit (65) executes the pulse detecting process taking as a detection target only a frequency domain having a standard pulse width indicated by standard pulse width information (D67), in a body movement recognition period in which a body movement recognition signal (S26) indicates that the body is moving.
The purpose of the present invention is to provide a blood pressure measuring device that is easy to use and capable of accurately measuring blood pressure. According to the present invention, a blood pressure calculation unit (6) calculates time information (CT) on the basis of a pulse signal (S5) and applies received parameter information (PR) and the time information (CT) to a blood pressure deriving equation to calculate a measured blood pressure. A parameter learning unit (7) obtains statistical time information (TJ) by statistically processing the time information (CT). The statistical time information (TJ) and basic blood pressure information (JB) are then applied to a learning computing equation to update the parameter information (PR), and the updated parameter information (PR) is output to the blood pressure calculation unit (6).
The first synchronous FF is disposed at the starting point of the clock tree of the frequency-divided clock of each lower hierarchical block, and the first maximum delay time of the reference clock from the branch point of the reference clock and the frequency-divided clock to the first synchronous FF is acquired. The second maximum delay time of the reference clock between adjacent two of second synchronous FFs is determined so as to be less than half the period of the reference clock. The number of stages of the second synchronous FFs is determined according to the first and second maximum delay times. The target delay time from the branch point is determined so as to be not more than the second maximum delay time, and the second synchronous FF and a latch are disposed so as to achieve the target delay time.
The differential output buffer comprises the differential output circuit, and the bias voltage generation circuit that is the replica circuit of the differential output circuit. The bias voltage generation circuit generates, by the operational amplifier, the bias voltage for controlling currents respectively flowing in the first current source of the differential output buffer and the second current source of the bias voltage generation circuit such that the voltage of the third internal node between the third internal and external resistors and the third switch of the bias voltage generation circuit becomes equal to the reference voltage equal to the voltage of the first internal node when the first switch of the differential output buffer is in an ON state or equal to the voltage of the second internal node when the second switch of the differential output buffer is in an ON state.
H03B 1/00 - GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNERGENERATION OF NOISE BY SUCH CIRCUITS Details
H03K 3/00 - Circuits for generating electric pulsesMonostable, bistable or multistable circuits
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
98.
Feature image generation apparatus, classification apparatus and non-transitory computer-readable memory, and feature image generation method and classification method
A feature image generation apparatus includes circuitry. The circuitry generates, on the basis of a processing target image in which an object appears, a first image showing the object, and generates, as a feature image showing a feature of the object, at least a part of a rotational composite image obtained by composition of a plurality of rotated images obtained by rotating the first image.
G06K 9/48 - Extraction of features or characteristics of the image by coding the contour of the pattern
G06K 9/62 - Methods or arrangements for recognition using electronic means
G07D 5/00 - Testing specially adapted to determine the identity or genuineness of coins, e.g. for segregating coins which are unacceptable or alien to a currency
G06K 9/32 - Aligning or centering of the image pick-up or image-field
G06K 9/46 - Extraction of features or characteristics of the image
99.
State estimation apparatus, state estimation method, integrated circuit, and non-transitory computer-readable storage medium
A state estimation apparatus obtains observation data sets for a tracking target object, and estimates an internal state of the object using likelihoods obtained from the observation data sets and the reliability of each observation data set. A first observation obtaining unit obtains first observation data. A second observation obtaining unit obtains second observation data. A first likelihood obtaining unit obtains a first likelihood based on the first observation data. A second likelihood obtaining unit obtains a second likelihood based on the second observation data. A likelihood combining unit obtains a combined likelihood based on the first and second likelihoods, first reliability data indicating the reliability of the first observation data, and second reliability data indicating the reliability of the second observation data. A posterior probability distribution obtaining unit obtains posterior probability distribution data indicating a probability distribution of the internal state of the observation target at current time t from the combined likelihood and predictive probability distribution data.
A clock generator that outputs multiphase clocks comprises a ring oscillator that includes a plurality of inverter circuits connected in a circular pattern and outputs, from the inverter circuits, clocks provided with a delay time based on a delay control signal, a first frequency divider that divides an injection clock by a first value and outputs the clock as a reference clock, a second frequency divider that divides one of the multiphase clocks by a second value and outputs the clock as a comparison clock, and a frequency comparator that compares frequencies of the reference clock and the comparison clock and output the delay control signal based on a result of the comparison. The ring oscillator is configured to adjust the delay time based on the delay control signal.
