In some implementations, a controller may initiate a read operation associated with a storage medium. The controller may identify a first estimation of a first expected error rate for a first data set stored on the storage medium and a second estimation of a second expected error rate for a second data set stored on the storage medium. The controller may perform a first decoding operation on the first data set based at least in part on the first expected error rate. The controller may perform a second decoding operation on the second data set based at least in part on the second expected error rate.
A device including a transceiver and a first logic circuit electrically coupled to the transceiver. The device including a first electrical conductor electrically coupled to the transceiver and to a first mechanical connection of a first vehicle safety system of a vehicle. The first mechanical connection to provide a first electrical path to a ground of the vehicle. The device including a second electrical conductor electrically coupled to the transceiver and to a second mechanical connection of a second vehicle safety system of the vehicle. The second vehicle safety system separate from the first vehicle safety system. The second mechanical connection to provide a data link to communicate data with a communication network of the vehicle.
B60Q 9/00 - Arrangement or adaptation of signal devices not provided for in one of main groups
B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
In some implementations, a storage device may perform a read operation to obtain data stored on the storage device performing a decoding operation on the data. The storage device may identify a refined hard bit read voltage based on constructed data. The storage device may apply the refined hard bit read voltage. In some aspects, the storage device may use the refined hard bit read voltage to determine bit values of the storage device in a subsequent decoding operation associated with a subsequent read operation.
Communication circuits and systems may include circuitry to detect the loss of the input signal. These circuits may be termed Loss of Signal (LOS) circuits. Changes to channel length and frequency of transmission may introduce uncertainty in detection circuits. A system may include a offset calibration mode and a hysteresis calibration mode to modify circuit performance in the presence of variations in process, voltage and temperature (PVT) and may improve performance of LOS circuits.
H04B 17/21 - MonitoringTesting of receivers for calibrationMonitoringTesting of receivers for correcting measurements
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
A device including a transceiver and a first logic circuit electrically coupled to the transceiver. The device including a first electrical conductor electrically coupled to the transceiver and to a first mechanical connection of a first vehicle safety system of a vehicle. The first mechanical connection to provide a first electrical path to a ground of the vehicle. The device including a second electrical conductor electrically coupled to the transceiver and to a second mechanical connection of a second vehicle safety system of the vehicle. The second vehicle safety system separate from the first vehicle safety system. The second mechanical connection to provide a data link to communicate data with a communication network of the vehicle.
B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
6.
SYSTEM AND METHODS FOR SOFTWARE PROGRAMMABLE CACHE MEMORY
A software programmable cache memory may enable fast execution of frequently used blocks of code. The software programmable cache memory may match incoming instruction addresses with addresses stored in a content-addressable memory (CAM) and may read matching addresses from a volatile cache memory. Instruction addresses which do not match with addresses stored in the CAM may be fetched from a non-volatile memory coupled to the software programmable cache memory.
In some implementations, a controller may detect a power loss event on a non-volatile memory device. The controller may perform, based on detecting the power loss event, a first write operation to write data to a first portion of a block of the non-volatile memory device. Prior to the first write operation, the data may be stored in a memory of a controller of the non-volatile memory device. After the first write operation, the first portion of the block may include programmed wordlines. After the first write operation, a second portion of the block may include unprogrammed wordlines. The controller may perform a second write operation to write padding data to an unprogrammed wordline of the unprogrammed wordlines that is adjacent to a last programmed wordline of the programmed wordlines.
A cloud-based computer system for electronic design automation (EDA) is provided. The cloud-based computer system may include one or more processors, and a memory storing instructions executable by the one or more processors. The instructions, when executed, may cause the system to provide a cloud EDA artificial intelligence (AI) expert module to learn and evolve in an electronic designing field using a new set of electronic design methodologies data, store a new set of refined electronic design methodologies data, and update an AI agent associated with an EDA tool executed on a user device. The AI agent may receive a set of EDA-related knowledge data associated with a user activity on the EDA tool, transmit the received data to a cloud EDA AI expert module for processing, and receive the new set of refined electronic design methodologies data to enhance user assistance in the electronic design process.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
9.
SYSTEM AND METHODS FOR SOFTWARE PROGRAMMABLE CACHE MEMORY
A software programmable cache memory may enable fast execution of frequently used blocks of code. The software programmable cache memory may match incoming instruction addresses with addresses stored in a content-addressable memory (CAM) and may read matching addresses from a volatile cache memory. Instruction addresses which do not match with addresses stored in the CAM may be fetched from a non-volatile memory coupled to the software programmable cache memory.
G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
In some implementations, a controller of a storage device may configure the storage device with a multi-plane word line that includes a first word line of a first plane having a first index, and a second word line of a second plane having a second index that is offset from the first index. The controller may perform a write operation or read operation on the multi-plane word line. In this way, the multi-plane word line may include word lines that are at different indices at different planes and thereby reduce high error rates for particular multi-plane word lines that may otherwise be caused by physical imperfections shared by word lines at the same indices at different planes.
An apparatus comprises a position sensor circuit including an offset compensation circuitry (804A) to compensate for an offset voltage of a position signal. The offset compensation circuitry includes at least a first current digital-to-analog converter, DAC (1002), and a second current DAC (1004). The first current DAC includes a first reference input (1010) to receive a first input current that varies in response to changes in amplitude of an excitation signal. The first current DAC further includes first logic inputs (1012) to adjustably set to respective logic levels to produce a first output current (1013) to substantially match a predetermined constant current. The second current DAC includes a second reference input (1015) to receive the first output current from the first current DAC. The second current DAC further includes second logic inputs (1014) to adjustably set to respective logic levels to produce a second output current (1020) to compensate for the offset voltage.
G01D 18/00 - Testing or calibrating apparatus or arrangements provided for in groups
G01D 3/036 - Measuring arrangements with provision for the special purposes referred to in the subgroups of this group mitigating undesired influences, e.g. temperature, pressure on measuring arrangements themselves
G01D 5/20 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
12.
SECRET-SHARING ENCODING AND DECODING USING EXCLUSIVE OR OPERATIONS
A system and method for a secret-sharing encoding and decoding using exclusive OR (XOR) operations. A first apparatus includes a data splitting circuit to receive a secret and generate first, second, third, and fourth secret segments based on the secret and a secret share encoding circuit to generate first, second, third, and fourth secret shares by application of XOR operations to the first, second, third, and fourth secret segments. A second apparatus includes a secret share decoding circuit to receive first, second, third, and fourth secret shares and generate first, second, third, and fourth secret segments by application of an XOR operation to share encoded data of the first, second, third, and fourth secret shares, and a data aggregating circuit to: receive the first, second, third, and fourth secret segments; and recreate a secret by combining the first, second, third, and fourth secret segments.
In some implementations, a controller may initiate a read operation associated with a storage medium. The controller may identify a first estimation of a first expected error rate for a first data set stored on the storage medium and a second estimation of a second expected error rate for a second data set stored on the storage medium. The controller may perform a first decoding operation on the first data set based at least in part on the first expected error rate. The controller may perform a second decoding operation on the second data set based at least in part on the second expected error rate.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
14.
Use of an LBA scatter list to calculate an address corresponding to an entry in the LBA scatter list
Systems and methods for using a logical block addressing (LBA) scatter list to calculate an address corresponding to an entry in the LBA scatter list are disclosed. A system may include a non-transitory memory including machine-readable instructions that, when executed by a processor, cause the processor to allocate an LBA scatter list array and send an initializing command to a target storage device to provide to the target storage device an address to the LBA scatter list array. The instructions cause the processor to gather a plurality of read requests and select an available LBA scatter list index. The instructions cause the processor to populate a LBA list indicated by the selected LBA scatter list index and send a subsequent command to the target storage device to cause the target storage device to calculate an address corresponding to a given entry in the selected LBA scatter list index.
A metal-insulator-metal (MIM) capacitor module includes an outer electrode, an insulator, an inner electrode, an outer electrode extension structure, an inner electrode contact element, and an outer electrode contact element. The outer electrode includes a plurality of vertically-extending outer electrode sidewalls. The insulator is formed in an opening defined by the vertically-extending outer electrode sidewalls, and includes a plurality of vertically-extending insulator sidewalls. The inner electrode formed in an interior opening defined by the insulator. The outer electrode extension structure extends laterally from a particular vertically-extending outer electrode sidewall. The inner electrode contact element and outer electrode contact element are formed in a metal layer. The inner electrode contact element is electrically connected to the inner electrode, and the outer electrode contact element is electrically connected to the outer electrode extension structure.
H10D 1/68 - Capacitors having no potential barriers
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
16.
PRODUCT IDENTIFICATION AND LOCATION NOTIFICATION BASED ON USER PRODUCT SPECIFICATION
Methods and systems are provided for associating respective ones of a plurality of beacons with respective ones of a plurality of products; receiving a product specification from a user; identifying a product of the plurality of products corresponding to the product specification; and notifying the user of the location of a respective beacon of the plurality of beacons associated with the identified product.
G06K 7/10 - Methods or arrangements for sensing record carriers by electromagnetic radiation, e.g. optical sensingMethods or arrangements for sensing record carriers by corpuscular radiation
17.
DATA RETENTION OF PARTIALLY PROGRAMMED BLOCKS OF NON-VOLATILE MEMORY DEVICES
In some implementations, a controller may detect a power loss event on a non-volatile memory device. The controller may perform, based on detecting the power loss event, a first write operation to write data to a first portion of a block of the non-volatile memory device. Prior to the first write operation, the data may be stored in a memory of a controller of the non-volatile memory device. After the first write operation, the first portion of the block may include programmed wordlines. After the first write operation, a second portion of the block may include unprogrammed wordlines. The controller may perform a second write operation to write padding data to an unprogrammed wordline of the unprogrammed wordlines that is adjacent to a last programmed wordline of the programmed wordlines.
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
18.
POWER CONSUMPTION MANAGEMENT OF A SOLID STATE DEVICE BASED ON OPERATION PRIORITY
In some implementations, a controller may initiate a first operation on a first die of a storage device. The controller may detect a request to perform a second operation on a second die of the storage device. The first die may be different than the second die. The controller may suspend the first operation based on detecting the request.
A system and method for a secret-sharing encoding and decoding using exclusive OR (XOR) operations. A first apparatus includes a data splitting circuit to receive a secret and generate first, second, third, and fourth secret segments based on the secret and a secret share encoding circuit to generate first, second, third, and fourth secret shares by application of XOR operations to the first, second, third, and fourth secret segments. A second apparatus includes a secret share decoding circuit to receive first, second, third, and fourth secret shares and generate first, second, third, and fourth secret segments by application of an XOR operation to share encoded data of the first, second, third, and fourth secret shares, and a data aggregating circuit to: receive the first, second, third, and fourth secret segments; and recreate a secret by combining the first, second, third, and fourth secret segments.
A phase interpolator may include a decoding logic circuit. The decoding logic circuit may take as input an input control code and an update clock. The decoding logic circuit may generate one or more outputs which may be input to a retiming circuit. The retiming circuit may generate retimed outputs which may be input to a delay modulation circuit. The delay modulation circuit may generate a delayed clock select control signal and a delayed phase select control signal. The delayed clock select control signal and delayed phase select control signal may be input to a phase interpolator circuit and may generate an output clock based on two or more multi-phase input clocks. The delayed clock select control signal and delayed phase select control signal may eliminate overshoot and undershoot events in the output clock.
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
21.
ANALOG DYNAMIC CALIBRATION OF SENSOR SIGNAL OFFSET FOR INDUCTIVE POSITION SENSOR, AND RELATED APPARATUSES AND METHODS
An apparatus comprises a position sensor circuit including an offset compensation circuitry to compensate for an offset voltage of a position signal. The offset compensation circuitry includes at least a first current digital-to-analog converter (DAC) and a second current DAC. The first current DAC includes a first reference input to receive a first input current that varies in response to changes in amplitude of an excitation signal. The first current DAC further includes first logic inputs to adjustably set to respective logic levels to produce a first output current to substantially match a predetermined constant current. The second current DAC includes a second reference input to receive the first output current from the first current DAC. The second current DAC further includes second logic inputs to adjustably set to respective logic levels to produce a second output current to compensate for the offset voltage.
G01D 5/20 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
G01D 18/00 - Testing or calibrating apparatus or arrangements provided for in groups
22.
PRODUCT IDENTIFICATION AND LOCATION NOTIFICATION BASED ON USER PRODUCT SPECIFICATION
Methods and systems are provided for associating respective ones of a plurality of beacons with respective ones of a plurality of products; receiving a product specification from a user; identifying a product of the plurality of products corresponding to the product specification; and notifying the user of the location of a respective beacon of the plurality of beacons associated with the identified product.
A device may have a processor to execute a first process comprising a plurality of instructions; a plurality of processor registers to store data associated with one or more of the plurality of instructions; and a context switch instruction, executable by the processor, to move a contiguous set of the plurality of processor registers to or from a memory corresponding to a given memory address, wherein the contiguous set of the plurality of processor registers comprises at least two processor registers and is a proper subset of a total number of processor registers available in the device.
In some implementations, a controller may initiate a first operation on a first die of a storage device. The controller may detect a request to perform a second operation on a second die of the storage device. The first die may be different than the second die. The controller may suspend the first operation based on detecting the request.
A device including a substrate having a first aperture, a second aperture and a third aperture. Where a bottom surface of the first and second covers may be bonded to the top surface of substrate to cover the first and second apertures, respectively, and with first and second leads bonded to the bottom surface of the first and second covers, respectively, so the first and second leads extend through the first and second apertures, respectively. The top surface of a third cover may be bonded to the bottom surface of the substrate to cover the third aperture. The bottom portion of a seal ring may be bonded to the top portion of the substrate to surround the first, second, and third apertures, and a cap may be bonded to the top portion of the seal ring. The components may be bonded to create hermetic seals for an SMD package.
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/057 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body the leads being parallel to the base
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
26.
ELECTROSTATIC DISCHARGE CLAMP CIRCUIT CONTAINING A DISABLE CIRCUIT TO SELECTIVELY DISABLE A DISCHARGE CIRCUIT
A system and method for an electrostatic discharge (ESD) clamp circuit containing a disable circuit to selectively disable a discharge circuit is disclosed. An electrostatic discharge (ESD) clamp circuit including a discharge circuit to discharge a current flow during a transient ESD voltage event; a disable input to receive a disable input signal; and a disable circuit to, based upon the disable input signal, selectively disable the discharge circuit. When the disable input signal is a first logic state, the disable circuit is to allow the discharge circuit to be enabled; and when the disable input signal is in a second logic state, the disable circuit is to disable the discharge circuit.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A device may have a processor to execute a first process comprising a plurality of instructions; a plurality of processor registers to store data associated with one or more of the plurality of instructions; and a context switch instruction, executable by the processor, to move a contiguous set of the plurality of processor registers to or from a memory corresponding to a given memory address, wherein the contiguous set of the plurality of processor registers comprises at least two processor registers and is a proper subset of a total number of processor registers available in the device.
A method may include: generating round-trip pulses at one or more nodes of a multidrop network, respective ones of the round-trip pulses selectively traversing one or more of: internal circuitry of the one or more nodes, or a physical medium between a first node and a second node of the one or more nodes; determining a total delay and an internal delay of the one or more nodes at least partially based on a measurement window error and measured round trips of the round-trip pulses within a predetermined measurement window; and determining a distance between the first node and second node at least partially based on the measured round trips of the round-trip pulses and the internal delay of at least one of the first node or the second node.
A device including a substrate having a first aperture, a second aperture and a third aperture. Where a bottom surface of the first and second covers may be bonded to the top surface of substrate to cover the first and second apertures, respectively, and with first and second leads bonded to the bottom surface of the first and second covers, respectively, so the first and second leads extend through the first and second apertures, respectively. The top surface of a third cover may be bonded to the bottom surface of the substrate to cover the third aperture. The bottom portion of a seal ring may be bonded to the top portion of the substrate to surround the first, second, and third apertures, and a cap may be bonded to the top portion of the seal ring. The components may be bonded to create hermetic seals for an SMD package.
H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups or
H01L 23/055 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body the leads having a passage through the base
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
30.
DETERMINING DISTANCE BETWEEN A REFERENCE NODE AND A MEASURED NODE OF A MULTIDROP NETWORK
A method may include: generating round-trip pulses at one or more nodes of a multidrop network, respective ones of the round-trip pulses selectively traversing one or more of: internal circuitry of the one or more nodes, or a physical medium between a first node and a second node of the one or more nodes; determining a total delay and an internal delay of the one or more nodes at least partially based on a measurement window error and measured round trips of the round-trip pulses within a predetermined measurement window; and determining a distance between the first node and second node at least partially based on the measured round trips of the round-trip pulses and the internal delay of at least one of the first node or the second node.
An apparatus for power management of a static random access memory (SRAM) bank is provided. The apparatus may include a memory core to store data, a memory peripheral connected to the memory core for supporting memory operations, a core power pin connected to a power source to supply power to the memory core, a peripheral power pin connected to the power source via a power switch, the power switch to selectively gate power to the memory peripheral, an isolation cell connected to one or more data pins of the SRAM bank, the isolation cell to isolate the data pins when the memory peripheral is powered down, and power management circuitry to monitor access patterns of the SRAM bank, determine how frequently the SRAM bank is accessed, and place the SRAM bank in deep retention mode by controlling the power switch and the isolation cell.
A controller may determine data type information regarding a data type to be written to a memory device. The data type information may identify a first data type associated with single-level cell data storage or a second data type associated with triple-level cell data storage or quad-level cell data storage. The controller may select, based on the data type information, a sector size for the memory device. The sector size may be a first value when the data type information identifies the first data type or may be a second value when the data type information identifies the second data type, and wherein the first value exceeds the second value. The controller may generate a logical to physical (L2P) data structure based on the sector size. The controller may store the L2P data structure in a memory of a controller of the memory device.
An apparatus for power management of a static random access memory (SRAM) bank is provided. The apparatus may include a memory core to store data, a memory peripheral connected to the memory core for supporting memory operations, a core power pin connected to a power source to supply power to the memory core, a peripheral power pin connected to the power source via a power switch, the power switch to selectively gate power to the memory peripheral, an isolation cell connected to one or more data pins of the SRAM bank, the isolation cell to isolate the data pins when the memory peripheral is powered down, and power management circuitry to monitor access patterns of the SRAM bank, determine how frequently the SRAM bank is accessed, and place the SRAM bank in deep retention mode by controlling the power switch and the isolation cell.
G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
34.
INTERFACE CIRCUIT FOR STACK COMPRISING A PLURALITY OF VECTOR-BY-MATRIX MULTIPLICATION ARRAYS
In one example, a system comprises a first device; a first interface coupled to the first device and comprising one or more device control lines to identify a second device within a plurality of devices for which a communication is intended, the plurality of devices respectively containing vector-by-matrix multiplication arrays; and a stack comprising an interface circuit coupled to the first interface, the plurality of devices, and a second interface comprising lines compliant with a legacy standard, the second interface coupled between the interface circuit and the plurality of devices.
A system and method for an electrostatic discharge (ESD) clamp circuit containing a disable circuit to selectively disable a discharge circuit is disclosed. An electrostatic discharge (ESD) clamp circuit including a discharge circuit to discharge a current flow during a transient ESD voltage event; a disable input to receive a disable input signal; and a disable circuit to, based upon the disable input signal, selectively disable the discharge circuit. When the disable input signal is a first logic state, the disable circuit is to allow the discharge circuit to be enabled; and when the disable input signal is in a second logic state, the disable circuit is to disable the discharge circuit.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
36.
INTERFACE CIRCUIT FOR STACK COMPRISING A PLURALITY OF VECTOR-BY-MATRIX MULTIPLICATION ARRAYS
In one example, a system comprises a first device; a first interface coupled to the first device and comprising one or more device control lines to identify a second device within a plurality of devices for which a communication is intended, the plurality of devices respectively containing vector-by-matrix multiplication arrays; and a stack comprising an interface circuit coupled to the first interface, the plurality of devices, and a second interface comprising lines compliant with a legacy standard, the second interface coupled between the interface circuit and the plurality of devices.
An apparatus may include a transceiver(102), a cable(112) in communication with the transceiver(102) via a medium dependent interface (MDI)(114) of the transceiver(102), and a controller(104) in communication with the transceiver(102) via the hardware interface. The controller(104) may be to instruct, via the hardware interface, the transceiver(102) to provide a transmit signal to the cable(112), sample, via the three pin interface, a first comparison signal at a pin of the transceiver(102) to generate first samples responsive to the first diagnostics threshold, instruct, via the hardware interface, the transceiver(102) to provide the transmit signal to the cable(112), sample, via the three pin interface, a second received signal at a pin of the transceiver(102) to generate second samples responsive to the second diagnostics threshold, detect a discontinuity in a cable(112) responsive to a the first samples and the second samples.
A system and method for a mobile microscope is disclosed. The system includes a platform to move about an environment; a sampler tool coupled to the platform; a microscope coupled to the platform; a camera coupled to the microscope; and a control circuit to: instruct the platform to move about an environment; instruct the sampler tool to obtain a sample and place the sample in a view field of the microscope; instruct the camera to capture an image of the sample, the image enlarged by the microscope; receive the image from the camera; analyze, using a neural network, the image to classify the sample; and output a classification of the sample.
G01N 15/1433 - Signal processing using image recognition
G02B 21/36 - Microscopes arranged for photographic purposes or projection purposes
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
G06V 20/69 - Microscopic objects, e.g. biological cells or cellular parts
39.
GENERATING A LOGICAL TO PHYSICAL DATA STRUCTURE FOR A SOLID STATE DRIVE USING SECTORS OF DIFFERENT SIZES
A controller may determine data type information regarding a data type to be written to a memory device. The data type information may identify a first data type associated with single-level cell data storage or a second data type associated with triple-level cell data storage or quad-level cell data storage. The controller may select, based on the data type information, a sector size for the memory device. The sector size may be a first value when the data type information identifies the first data type or may be a second value when the data type information identifies the second data type, and wherein the first value exceeds the second value. The controller may generate a logical to physical (L2P) data structure based on the sector size. The controller may store the L2P data structure in a memory of a controller of the memory device.
In one example, a system comprises: a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an output block coupled to the vector-by-matrix multiplication array comprising: a current-to-voltage converter to convert current received from a column of the vector-by-matrix multiplication array into a voltage, an analog-to-digital converter to convert the voltage into digital bits, and a configuration circuit to convert the digital bits into unsigned digital bits.
A circuit to suppress ringing in a Controller Area Network (CAN) bus having a CAN high (CANH) wire and a CAN low (CANL) wire is provided. The circuit may include processing circuitry to generate a CAN control signal, and a transconductance amplifier to receive a first input signal corresponding to the CAN control signal and a voltage signal from the CANL wire, and to generate an output current signal based on a difference between the first input signal and the voltage signal from the CANL wire. An output terminal of the transconductance amplifier may be coupled to the CANH wire to source current to or sink current from the CANH wire.
A system and method for a mobile microscope is disclosed. The system includes a platform to move about an environment; a sampler tool coupled to the platform; a microscope coupled to the platform; a camera coupled to the microscope; and a control circuit to: instruct the platform to move about an environment; instruct the sampler tool to obtain a sample and place the sample in a view field of the microscope; instruct the camera to capture an image of the sample, the image enlarged by the microscope; receive the image from the camera; analyze, using a neural network, the image to classify the sample; and output a classification of the sample.
In one example, a system comprises: a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an output block coupled to the vector-by-matrix multiplication array comprising: a current-to-voltage converter to convert current received from a column of the vector-by-matrix multiplication array into a voltage, an analog-to-digital converter to convert the voltage into digital bits, and a configuration circuit to convert the digital bits into unsigned digital bits.
G06F 7/40 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using contact-making devices, e.g. electromagnetic relay
44.
DEVICE AND METHODS FOR SINGLE-CHIP PCIE VIRTUALIZATION
A switch may include one or more input ports, a forwarder, a virtualizer and one or more control units. The switch may receive a data packet at an input port and the forwarder may send the data packet to the virtualizer. The virtualizer may convert the data packet into a PCIe signal and may transmit the PCIe signal to the one or more control units.
A semiconductor device includes a semiconductor substrate having an upper surface with a semiconductor member extending vertically from the upper surface, wherein the semiconductor member has a first conductivity type. A first region of a second conductivity type different than the first conductivity type is formed at a proximal end of the semiconductor member adjacent the upper surface. A second region of the second conductivity type is formed at a distal end of the semiconductor member. A channel region of the semiconductor member extends between the first and second regions. A floating gate laterally wraps around a first portion of the channel region. A control gate laterally wraps around the floating gate. A select gate laterally wraps around a second portion of the channel region. An erase gate laterally wraps around the semiconductor member.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
46.
DEVICE AND METHODS FOR SINGLE-CHIP PCIe VIRTUALIZATION
A switch may include one or more input ports, a forwarder, a virtualizer and one or more control units. The switch may receive a data packet at an input port and the forwarder may send the data packet to the virtualizer. The virtualizer may convert the data packet into a PCIe signal and may transmit the PCIe signal to the one or more control units.
A power semiconductor device is provided that includes paralleled transistor cells, and a common source, a common drain and a common gate operatively coupled to the paralleled transistor cells. The power semiconductor device also includes a plurality of common gate contact pads operatively coupled to the common gate, and one or more resistors coupled to respective one or more common gate contact pads of the plurality of common gate contact pads. The one or more resistors are also coupled between the respective one or more common gate contact pads and the common gate. The plurality of common gate contact pads provide a selectable resistive decoupling of the common gate by connection of one of the plurality of common gate contact pads.
A method comprises forming a first insulation layer on an upper surface of a semiconductor substrate, forming a first conductive layer on the first insulation layer, and forming a compound insulation layer on the first conductive layer, wherein the compound insulation layer comprises a nitride sublayer between a lower oxide sublayer and an upper oxide sublayer. A second insulation layer is formed on the compound insulation layer. A trench is formed that extends through the second insulation layer, the compound insulation layer, the first conductive layer, the first insulation layer, and into the semiconductor substrate. The trench is filled with fill insulation material. The second insulation layer and an upper portion of the fill insulation material are removed. A second conductive layer is formed on the compound insulation layer, and on the fill insulation material in the trench.
A method of programming non-volatile memory cells comprising determining a target read current for respective ones of the memory cells based upon incoming data, associating respective ones of the memory cells with a respective one of a plurality of cell groups based upon the determined target read current for the respective memory cell being within a target read current range associated with the respective cell group, fast programming respective ones of the memory cells to a coarse target read current associated with the cell group to which the respective memory cell is associated, wherein the coarse target read current for respective ones of the cell groups is greater than the target read current range for the respective cell group, and then slow programming respective ones of the memory cells until the target read current determined for the respective memory cell is achieved.
A method comprises forming a first insulation layer on an upper surface of a semiconductor substrate, forming a first conductive layer on the first insulation layer, and forming a compound insulation layer on the first conductive layer, wherein the compound insulation layer comprises a nitride sublayer between a lower oxide sublayer and an upper oxide sublayer. A second insulation layer is formed on the compound insulation layer. A trench is formed that extends through the second insulation layer, the compound insulation layer, the first conductive layer, the first insulation layer, and into the semiconductor substrate. The trench is filled with fill insulation material. The second insulation layer and an upper portion of the fill insulation material are removed. A second conductive layer is formed on the compound insulation layer, and on the fill insulation material in the trench.
A job manager may receive a request for a design of a semiconductor device to be verified by a set of computing devices, wherein the request comprises design parameters regarding the design of the semiconductor device. The job manager may provide the design parameters as inputs to a machine learning model trained to predict amounts of computational resources and amounts of compute time for verifying designs of semiconductor devices. The job manager may obtain, as an output from the machine learning model, a predicted amount of computational resources and a predicted amount of compute time for verifying the design of the semiconductor device. The job manager may determine an availability of resources, of the set of computing devices, for verifying the design of the semiconductor device. The job manager may cause the design of the semiconductor device to be verified by one or more computing devices.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
G06F 21/10 - Protecting distributed programs or content, e.g. vending or licensing of copyrighted material
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06Q 10/04 - Forecasting or optimisation specially adapted for administrative or management purposes, e.g. linear programming or "cutting stock problem"
G06Q 10/06 - Resources, workflows, human or project managementEnterprise or organisation planningEnterprise or organisation modelling
G06F 111/02 - CAD in a network environment, e.g. collaborative CAD or distributed simulation
G06F 115/08 - Intellectual property [IP] blocks or IP cores
A method of programming non-volatile memory cells comprising determining a target read current for respective ones of the memory cells based upon incoming data, associating respective ones of the memory cells with a respective one of a plurality of cell groups based upon the determined target read current for the respective memory cell being within a target read current range associated with the respective cell group, fast programming respective ones of the memory cells to a coarse target read current associated with the cell group to which the respective memory cell is associated, wherein the coarse target read current for respective ones of the cell groups is greater than the target read current range for the respective cell group, and then slow programming respective ones of the memory cells until the target read current determined for the respective memory cell is achieved.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
54.
POWER SEMICONDUCTOR DEVICE INTEGRATED SELECTABLE GATE RESISTANCE
A power semiconductor device is provided that includes paralleled transistor cells, and a common source, a common drain and a common gate operatively coupled to the paralleled transistor cells. The power semiconductor device also includes a plurality of common gate contact pads operatively coupled to the common gate, and one or more resistors coupled to respective one or more common gate contact pads of the plurality of common gate contact pads. The one or more resistors are also coupled between the respective one or more common gate contact pads and the common gate. The plurality of common gate contact pads provide a selectable resistive decoupling of the common gate by connection of one of the plurality of common gate contact pads.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
55.
VERTICALLY ORIENTED SPLIT GATE NON-VOLATILE MEMORY CELLS, AND METHOD OF MAKING SAME
A semiconductor device includes a semiconductor substrate having an upper surface with a semiconductor member extending vertically from the upper surface, wherein the semiconductor member has a first conductivity type. A first region of a second conductivity type different than the first conductivity type is formed at a proximal end of the semiconductor member adjacent the upper surface. A second region of the second conductivity type is formed at a distal end of the semiconductor member. A channel region of the semiconductor member extends between the first and second regions. A floating gate laterally wraps around a first portion of the channel region. A control gate laterally wraps around the floating gate. A select gate laterally wraps around a second portion of the channel region. An erase gate laterally wraps around the semiconductor member.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
downloadable and recorded computer software for monitoring, correcting, verifying, updating, and synchronizing device time references in the field of position, navigation, and time (PNT) signal traceability; downloadable and recorded computer software for comparing and synchronizing time references between networked devices; downloadable and recorded computer software for comparing and synchronizing time references with an authoritative time source; downloadable and recorded computer software for configuring, managing, and monitoring position, navigation, and time (PNT) devices; user manuals sold together with the foregoing Software as a services (SaaS) services featuring computer software for monitoring, correcting, verifying, updating, and synchronizing device time references in the field of position, navigation, and time (PNT) signal traceability; software as a services (SaaS) services featuring computer software for comparing and synchronizing time references between networked devices; software as a services (SaaS) services featuring computer software for comparing and synchronizing time references with an authoritative time source; software as a services (SaaS) services featuring computer software for configuring, managing, and monitoring position, navigation, and time (PNT) devices
An apparatus (100) may include a first node (104) coupled to a first terminal, the first terminal to receive a first control signal (S_IN); a second node (102) coupled to a second terminal, the second terminal to receive a second control signal (H_IN); a first capacitor (CO) having a first plate coupled to the first node and a second plate coupled to a first output terminal (H); a second capacitor (Cl) having a first plate coupled to the second node and a second plate coupled to a second output terminal (S); a first stack of transistors (M223, M24, M25) coupled between a positive supply terminal (POS through M2, X0) and a common mode terminal (CM), the first stack operable to divide voltage: and a second stack of transistors (M5, M4, M3) coupled between a negative supply terminal (NEG through M1, X10) and the common mode terminal (CM), the second stack operable to divide voltage.
A job manager may receive a request for a design of a semiconductor device to be verified by a set of computing devices, wherein the request comprises design parameters regarding the design of the semiconductor device. The job manager may provide the design parameters as inputs to a machine learning model trained to predict amounts of computational resources and amounts of compute time for verifying designs of semiconductor devices. The job manager may obtain, as an output from the machine learning model, a predicted amount of computational resources and a predicted amount of compute time for verifying the design of the semiconductor device. The job manager may determine an availability of resources, of the set of computing devices, for verifying the design of the semiconductor device. The job manager may cause the design of the semiconductor device to be verified by one or more computing devices.
An apparatus may include a first node coupled to a first terminal, the first terminal to receive a first control signal; a second node coupled to a second terminal, the second terminal to receive a second control signal; a first capacitor having a first plate coupled to the first node and a second plate coupled to a first output terminal; a second capacitor having a first plate coupled to the second node and a second plate coupled to a second output terminal; a first stack of transistors coupled between a positive supply terminal and a common mode terminal, the first stack operable to divide voltage; and a second stack of transistors coupled between a negative supply terminal and the common mode terminal, the second stack operable to divide voltage.
Knob on display (KoD) devices and related systems, methods, and devices are disclosed. A KoD device includes at least one electrode including an electrically conductive material. The KoD device also includes a base assembly configured to be positioned between a touch screen of a touch screen device and the at least one electrode. The at least one electrode is configured to be positioned in engagement proximity to a touch sensor of the touch screen device through the base assembly.
G06F 1/16 - Constructional details or arrangements
G05G 9/047 - Manually-actuated control mechanisms provided with one single controlling member co-operating with two or more controlled members, e.g. selectively, simultaneously the controlling member being movable in different independent ways, movement in each individual way actuating one controlled member only in which movement in two or more ways can occur simultaneously the controlling member being movable by hand about orthogonal axes, e.g. joysticks
G06F 3/0354 - Pointing devices displaced or positioned by the userAccessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
G06F 3/0362 - Pointing devices displaced or positioned by the userAccessories therefor with detection of 1D translations or rotations of an operating part of the device, e.g. scroll wheels, sliders, knobs, rollers or belts
G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
61.
APPARATUS FORMED FROM ELECTRONIC COMPONENTS HAVING DIFFERENT RESPECTIVE THICKNESSES AND METHODS OF FORMING AN APPARATUS FROM ELECTRONIC COMPONENTS HAVING DIFFERENT RESPECTIVE THICKNESSES
An apparatus includes a pair of substrates with conductive material formed on portions of inwardly facing surfaces thereof, and a step formed in or on the conductive material on one of the pair of substrates. A lead frame having leads and electronic components having different respective thicknesses are mounted between the conductive materials on the pair of substrates. The step has a step thickness dimensioned to facilitate electrical contact between a thickest one of the electronic components or the leads with the step in the conductive material on one of the pair of substrates and the conductive material on the one other of the pair of substrates. An electrical signal path is formed between the electronic components or the leads disposed in electrical contact with the step and the conductive material on the one other of the pair of substrates.
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
62.
APPARATUS FORMED FROM ELECTRONIC COMPONENTS HAVING DIFFERENT RESPECTIVE THICKNESSES AND METHODS OF FORMING AN APPARATUS FROM ELECTRONIC COMPONENTS HAVING DIFFERENT RESPECTIVE THICKNESSES
An apparatus includes a pair of substrates with conductive material formed on portions of inwardly facing surfaces thereof, and a step formed in or on the conductive material on one of the pair of substrates. A lead frame having leads and electronic components having different respective thicknesses are mounted between the conductive materials on the pair of substrates. The step has a step thickness dimensioned to facilitate electrical contact between a thickest one of the electronic components or the leads with the step in the conductive material on one of the pair of substrates and the conductive material on the one other of the pair of substrates. An electrical signal path is formed between the electronic components or the leads disposed in electrical contact with the step and the conductive material on the one other of the pair of substrates.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A FinFET device that may include a substrate (20). A drain layer (30) on a first side of the substrate. A drift layer (40) on a second side of the substrate. The drift layer having a fin-shaped portion (50) and a recessed portion. A doped-well layer (70) over the recessed portion of the drift layer and along sides of the fin-shaped portion of the drift layer. A body layer (80) and a source layer (90) formed over a portion of the doped-well layer over the recessed portion of the drift layer. An insulating layer (75) over the doped-well layer. A gate electrode (110) over the insulating layer.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
A FinFET device that may include a substrate. A drain layer on a first side of the substrate. A drift layer on a second side of the substrate. The drift layer having a fin-shaped portion and a recessed portion. A doped-well layer over the recessed portion of the drift layer and along sides of the fin-shaped portion of the drift layer. A body layer and a source layer formed over a portion of the doped-well layer over the recessed portion of the drift layer. An insulating layer over the doped-well layer. A gate electrode over the insulating layer.
In one example, a system comprises a programmable logic block comprising programmable logic and a configuration block to store and provide configuration data to the programmable logic, the configuration block comprising a flash memory array to store the configuration data, and the flash memory array comprising an array of split-gate flash memory cells.
A FinFET device that may include a substrate. A drain layer on a first side of the substrate. A drift layer on a second side of the substrate. The drift layer having a fin-shaped portion and a recessed portion. A doped-well layer over the fin-shaped portion of the drift layer. An insulating layer over the doped-well layer and over the recessed portion of the drift layer. A gate electrode over the insulating layer.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/336 - Field-effect transistors with an insulated gate
67.
SYSTEM AND METHODS FOR PHYSICAL IDENTIFICATION OF MANUFACTURED PRODUCTS
A manufactured product may include a machine-readable physical identifier and the machine-readable physical identifier may be stored in a tracking file. The machine-readable physical identifier may be encoded with manufacturing information related to the manufactured product, including but not limited to manufacturing location, lot number and manufacturing date. The tracking file may be updated based on one or more supply chain operations, including but not limited to a testing operation, a shipping operation or a delivery operation. The tracking file may include information on testing results, shipping origin and destinations and delivery locations. The tracking file may be delivered to a customer along with the manufactured products listed in the tracking file.
A FinFET device that may include a substrate. A drain layer on a first side of the substrate. A drift layer on a second side of the substrate. The drift layer having a fin-shaped portion and a recessed portion. A doped-well layer over the fin-shaped portion of the drift layer. An insulating layer over the doped-well layer and over the recessed portion of the drift layer. A gate electrode over the insulating layer.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A manufactured product may include a machine-readable physical identifier and the machine-readable physical identifier may be stored in a tracking file. The machine-readable physical identifier may be encoded with manufacturing information related to the manufactured product, including but not limited to manufacturing location, lot number and manufacturing date. The tracking file may be updated based on one or more supply chain operations, including but not limited to a testing operation, a shipping operation or a delivery operation. The tracking file may include information on testing results, shipping origin and destinations and delivery locations. The tracking file may be delivered to a customer along with the manufactured products listed in the tracking file.
G06Q 10/06 - Resources, workflows, human or project managementEnterprise or organisation planningEnterprise or organisation modelling
G06K 19/06 - Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
G06Q 10/08 - Logistics, e.g. warehousing, loading or distributionInventory or stock management
A circuit to suppress ringing in a Controller Area Network (CAN) bus having a CAN high (CANH) wire and a CAN low (CANL) wire is provided. The circuit may include processing circuitry to generate a CAN control signal, and a transconductance amplifier to receive a first input signal corresponding to the CAN control signal and a voltage signal from the CANL wire, and to generate an output current signal based on a difference between the first input signal and the voltage signal from the CANL wire. An output terminal of the transconductance amplifier may be coupled to the CANH wire to source current to or sink current from the CANH wire.
In one example, a system comprises a programmable logic block comprising programmable logic and a configuration block to store and provide configuration data to the programmable logic, the configuration block comprising a flash memory array to store the configuration data, and the flash memory array comprising an array of split-gate flash memory cells.
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
72.
STORING AND PROVIDING ACCESS TO ROUND KEYS OF ADVANCED ENCRYPTION STANDARD USING DUAL PORT MEMORY DEVICES
A system includes one or more processing units adapted to generate, using a first encryption key, a first set of round keys for rounds of an advanced encryption standard (AES) algorithm; generate, using a second encryption key, a second set of round keys; and determine different addresses, of a plurality of memory devices, for the first and second sets of round keys; and store the first and second sets of round keys in the different addresses, wherein the first round key is stored in a memory device, of the plurality of memory devices, using a first port of the memory device, and wherein the memory device is a dual port memory device that includes the first port and a second port.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
73.
High Electron Mobility Transistor and Method for Manufacturing Same
A High-Electron-Mobility-Transistor that may include a substrate with a buffer layer formed on the substrate. A recess formed in the buffer layer. A barrier layer formed on the buffer layer. A gate recess formed in the barrier layer, the gate recess overlaps the recess in the buffer layer. A drain terminal formed at a first side of the barrier layer. A source terminal formed at a second side of the barrier layer. An isolation structure formed within the gate recess proximate the drain terminal. A doped structure formed adjacent to the isolation structure within the gate recess proximate the source terminal. A gate terminal formed on the doped structure.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
74.
TERMINATION STRUCTURE FOR A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A termination structure for a semiconductor device that may include a substrate having a first type dopant. A plurality of doped-wells having a second type dopant formed in the substrate. A plurality of trenches formed into the plurality of doped-wells, respective ones of the formed trenches exposing a bottom surface of the doped-well, and exposing side surfaces of the doped-well, and a material within respective ones of the formed trenches, wherein the material in respective ones of the formed trenches is surrounded by the exposed bottom surface of the doped-well of the respective formed trench and the exposed side surfaces of the doped-well of the respective formed trench.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
75.
HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR MANUFACTURING SAME
A High-Electron-Mobility-Transistor includes a substrate (20) with a buffer layer (30) formed on the substrate. A recess (50) is formed in the buffer layer. A barrier layer (40) is formed on the buffer layer. A gate recess (55) is formed in the barrier layer, wherein the gate recess overlaps the recess in the buffer layer. A drain terminal (60) is formed at a first side of the barrier layer. A source terminal (70) is formed at a second side of the barrier layer. An isolation structure (80) is formed within the gate recess proximate the drain terminal. A doped structure (90) is formed adjacent to the isolation structure within the gate recess proximate the source terminal. A gate terminal (100) is formed on the doped structure.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
76.
DETERMINING PHYSICAL ADDRESSES OF MEMORY DEVICES USING DIVISION BY PRIME NUMBERS
A processing unit, associated with a host device, adapted to receive a request to calculate a first physical address of an external device based on a second physical address of the host device; determine a tree of parallel adders corresponding to the division operation; obtain an output value from the tree of parallel adders based on the input values; and calculate the first physical address using the output value. The first physical address of the external device is to be calculated based on a division operation that divides the second physical address by a divisor. The tree of parallel adders is determined based on input values that include a number of bits of the second physical address and a divisor.
A Controller Area Network (CAN) bus driver for driving a CAN bus is provided. The bus driver may include a first translinear loop circuit to receive an input voltage and output a first output current signal corresponding to an exponential function, a second translinear loop circuit to receive the input voltage and output a second output current signal corresponding to a hyperbolic function, a divider circuit to output a divided output current signal corresponding to the first output current signal divided by the second output current signal, a CAN Lo driver circuit to output the divided output current signal to a CAN Lo wire of the CAN bus, and a CAN Hi driver circuit to output the divided output current signal to a CAN Hi wire of the CAN bus.
A transistor comprising a drain layer, a drift layer over the drain layer, a channel layer over the drift layer, and a source layer over the channel layer. A trench formed through the source layer, through the channel layer and into at least partially the drift layer. A gate formed within the trench.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A termination structure for a semiconductor device that may include a substrate having a first type dopant. A plurality of doped-wells having a second type dopant formed in the substrate. A plurality of trenches formed into the plurality of doped-wells, respective ones of the formed trenches exposing a bottom surface of the doped-well, and exposing side surfaces of the doped-well, and a material within respective ones of the formed trenches, wherein the material in respective ones of the formed trenches is surrounded by the exposed bottom surface of the doped-well of the respective formed trench and the exposed side surfaces of the doped-well of the respective formed trench.
A processing unit, associated with a host device, adapted to receive a request to calculate a first physical address of an external device based on a second physical address of the host device; determine a tree of parallel adders corresponding to the division operation; obtain an output value from the tree of parallel adders based on the input values; and calculate the first physical address using the output value. The first physical address of the external device is to be calculated based on a division operation that divides the second physical address by a divisor. The tree of parallel adders is determined based on input values that include a number of bits of the second physical address and a divisor.
A transistor comprising a drain layer, a drift layer over the drain layer, a channel layer over the drift layer, and a source layer over the channel layer. A trench formed through the source layer, through the channel layer and into at least partially the drift layer. A gate formed within the trench.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/336 - Field-effect transistors with an insulated gate
82.
PROGRAMMING OF A SELECTED NON-VOLATILE MEMORY CELL BY CHANGING PROGRAMMING PULSE CHARACTERISTICS
In one example, a method comprises applying a first programming pulse to a terminal of a selected non-volatile memory cell; and applying a second programming pulse to the terminal of the selected non-volatile memory cell, wherein a magnitude of a voltage the second programming pulse is equal to or lower than a magnitude of a voltage of the first programming pulse; wherein the selected non-volatile memory cell is programmed to a target value by the first programming pulse and the second programming pulse.
G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using elements simulating biological cells, e.g. neuron
The disclosed memory device (60) includes a first conductive contact (36) extending through a first insulation material (32), a second conductive material (38a) on the first conductive contact, a resistive switching dielectric material (42a) on the second conductive material, a first conductive material (44a) on the resistive switching dielectric material, and an insulation layer (46) disposed over the first conductive material, the resistive switching dielectric material, and the second conductive material, wherein the resistive switching dielectric material and the upper conductive material are laterally displaced from the first conductive contact. Fabrication involves at least two annealing processes, one after forming the resistive switching dielectric material and another after forming the upper conductive material and/or insulation layer.
A method of forming a semiconductor device by providing a substrate having bulk silicon (10a), an insulation layer (10b) over the bulk silicon, and a silicon layer (10c) over the insulation layer. The silicon and insulation layers are removed from first (16) and second areas (18), while maintained in a third area (20). A memory cell (24) is formed in the first area having a floating gate (32) over a first portion of a memory cell channel region (30) and a control gate (34) over a second portion of the memory cell channel region. A transistor device (40) is formed in the second area having a transistor gate (48) over a transistor channel region (46). A logic device (60) is formed in the third area having a logic device gate (68) over a logic device channel region (66). The memory cell channel region and the transistor channel region are disposed in the bulk silicon. The logic device channel region is disposed in the silicon layer.
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H10B 41/49 - Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
85.
STORING AND PROVIDING ACCESS TO ROUND KEYS OF ADVANCED ENCRYPTION STANDARD USING DUAL PORT MEMORY DEVICES
A system includes one or more processing units adapted to generate, using a first encryption key, a first set of round keys for rounds of an advanced encryption standard (AES) algorithm; generate, using a second encryption key, a second set of round keys; and determine different addresses, of a plurality of memory devices, for the first and second sets of round keys; and store the first and second sets of round keys in the different addresses, wherein the first round key is stored in a memory device, of the plurality of memory devices, using a first port of the memory device, and wherein the memory device is a dual port memory device that includes the first port and a second port.
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
86.
CONTROLLER AREA NETWORK (CAN) BUS DRIVER USING TRANSLINEAR LOOPS
A Controller Area Network (CAN) bus driver for driving a CAN bus is provided. The bus driver may include a first translinear loop circuit to receive an input voltage and output a first output current signal corresponding to an exponential function, a second translinear loop circuit to receive the input voltage and output a second output current signal corresponding to a hyperbolic function, a divider circuit to output a divided output current signal corresponding to the first output current signal divided by the second output current signal, a CAN Lo driver circuit to output the divided output current signal to a CAN Lo wire of the CAN bus, and a CAN Hi driver circuit to output the divided output current signal to a CAN Hi wire of the CAN bus.
H03K 17/60 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being bipolar transistors
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
87.
TRANSMISSION OF SIGNALS FOR RANGING, TIMING, AND DATA TRANSFER
A method is disclosed. In various examples, the method may include receiving an instruction for generating a ranging signal, and transmitting the ranging signal at least partially responsive to the instruction. In various examples the ranging signal may be transmitted via a terrestrial transmitter for transmitting radio waves having encoded messaging information and timing information for one or more of positioning, navigation and timing. In various examples, the ranging signal may exhibit a first ranging pulse and a second ranging pulse of a pulse group and an encoded transmitter identifier, the transmitter identifier encoded by modulating an inter-pulse interval defined between a start of the first ranging pulse and a start of the second ranging pulse.
G01S 1/04 - Beacons or beacon systems transmitting signals having a characteristic or characteristics capable of being detected by non-directional receivers and defining directions, positions, or position lines fixed relatively to the beacon transmittersReceivers co-operating therewith using radio waves Details
88.
METHOD OF MAKING MEMORY CELLS, TRANSISTOR DEVICES AND LOGIC DEVICES ON SILICON-ON-INSULATOR SUBSTRATE
A method of forming a semiconductor device by providing a substrate having bulk silicon, an insulation layer over the bulk silicon, and a silicon layer over the insulation layer. The silicon and insulation layers are removed from first and second areas, while maintained in a third area. A memory cell is formed in the first area having a floating gate over a first portion of a memory cell channel region and a control gate over a second portion of the memory cell channel region. A transistor device is formed in the second area having a transistor gate over a transistor channel region. A logic device is formed in the third area having a logic device gate over a logic device channel region. The memory cell channel region and the transistor channel region are disposed in the bulk silicon. The logic device channel region is disposed in the silicon layer.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A method of programming a memory device comprising control gate lines, erase gate lines, select gate lines, source lines and bit lines connected to rows and columns of memory cells, the method comprising performing an erase operation that includes applying a first voltage to one of the erase gate lines, performing a pre-program operation that includes electrically connecting the one of the erase gate lines to a pair of the control gate lines to use positive charge on the one of the erase gate lines from the erase operation to pre-charge the pair of the control gate lines, and performing a program operation that includes applying a second voltage to the one of the erase gate lines and the pair of the control gate lines.
A trench power semiconductor device comprising a silicon carbide drain layer, a silicon carbide drift layer over the silicon carbide drain layer and a first silicon layer over the silicon carbide drift layer. A second silicon layer over the first silicon layer with a source silicon carbide layer over the second silicon layer. A trench formed through the source silicon carbide layer, through the second silicon layer and into at least partially the first silicon layer. A gate terminal contact formed on the trench with a drain terminal contact formed on the silicon carbide drain layer.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
91.
IDENTIFYING WORDLINES SUSCEPTIBLE TO DEEPER ERASE CONDITIONS
In some implementations, a controller may identify a block of a memory device that is scheduled for an erase operation. The controller may determine, using a machine learning model or a data structure, whether a wordline of the block is susceptible to a deeper erase condition before the erase operation. The data structure identifies wordlines that are susceptible to deeper erase conditions. The controller may perform a programming operation, on the wordline, to program a predetermined bit pattern on the wordline based on the wordline being susceptible to the deeper erase condition. The controller may perform the erase operation on the block after performing the programming operation.
A method of programming memory cells that includes reading the memory cells to determine respective read currents for the memory cells. Respective ones of the memory cells are assigned to one of a plurality of groups of the memory cells, wherein respective ones of the plurality of groups of the memory cells are associated with a different range of read currents, such that the determined read current for a respective one of the memory cells is within the range of read currents for the group of the memory cells to which the memory cell is assigned. The memory cells are programmed using program currents that vary for respective ones of the memory cells depending upon the group of the memory cells to which the memory cell is assigned.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/26 - Sensing or reading circuitsData output circuits
93.
ACCELERATED PROGRAMMING OF FOUR-GATE, SPLIT-GATE FLASH MEMORY CELLS
A method of programming a memory device comprising control gate lines, erase gate lines, select gate lines, source lines and bit lines connected to rows and columns of memory cells, the method comprising performing an erase operation that includes applying a first voltage to one of the erase gate lines, performing a pre-program operation that includes electrically connecting the one of the erase gate lines to a pair of the control gate lines to use positive charge on the one of the erase gate lines from the erase operation to pre-charge the pair of the control gate lines, and performing a program operation that includes applying a second voltage to the one of the erase gate lines and the pair of the control gate lines.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
94.
Silicon Carbide Driver Using High Voltage Capacitors for Isolation and Signal Transmission
A gate driver circuit to receive an input drive signal and output an output drive signal is provided. The gate driver circuit may include a first capacitor having first and second terminals, a second capacitor having first and second terminals, a first set of switches to selectively couple the first terminals of the first and second capacitors to the input drive signal and a power supply voltage, a second set of switches to selectively couple the second terminals of the first and second capacitors to a reference voltage and a high impedance node, and a comparator having a first terminal coupled to the reference voltage and a second terminal coupled to the high impedance node. The comparator may output the output drive signal based on a comparison of the reference voltage and a voltage at the high impedance node.
H03K 17/567 - Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
95.
Apparatus and Method for Clock Frequency Estimation With Subsets of Time Measurements
An apparatus includes a clock signal input, a sampling circuit, and an estimation circuit. The clock signal input receives N time measurements. A time measurement denotes a respective portion of a given cycle of a clock signal. The sampling circuit is to generate a first and second sampled window from the clock signal input. The first sampled window includes a sum of a plurality of a first m of the N time measurements. The second sampled window includes a sum of a plurality of a last m of the N time measurements. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.
A trench power semiconductor device comprising a silicon carbide drain layer, a silicon carbide drift layer over the silicon carbide drain layer and a first silicon layer over the silicon carbide drift layer. A second silicon layer over the first silicon layer with a source silicon carbide layer over the second silicon layer. A trench formed through the source silicon carbide layer, through the second silicon layer and into at least partially the first silicon layer. A gate terminal contact formed on the trench with a drain terminal contact formed on the silicon carbide drain layer.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
A method of programming memory cells that includes reading the memory cells to determine respective read currents for the memory cells. Respective ones of the memory cells are assigned to one of a plurality of groups of the memory cells, wherein respective ones of the plurality of groups of the memory cells are associated with a different range of read currents, such that the determined read current for a respective one of the memory cells is within the range of read currents for the group of the memory cells to which the memory cell is assigned. The memory cells are programmed using program currents that vary for respective ones of the memory cells depending upon the group of the memory cells to which the memory cell is assigned.
A memory device, and method of formation, that includes a first insulation material disposed over a semiconductor substrate. A first conductive contact extends through the first insulation material. A second block of conductive material is disposed on the first insulation material and on, and in electrical contact with, the first conductive contact. A block of resistive switching dielectric material is disposed directly on the second block of conductive material. A first block of conductive material is disposed directly on the block of resistive switching dielectric material. The block of resistive switching dielectric material and the first block of conductive material are displaced laterally from the first conductive contact. An insulation layer is disposed over the first block of conductive material, the block of resistive switching dielectric material and the second block of conductive material.
Systems and methods for controlling an air flow rate provided to a burner based on the concentration of one or more gases provided to the burner are disclosed. A method for controlling a burner including receiving a gas concentration value indicating a concentration of one or more gases in a gas mixture provided to a burner; determining, using the gas concentration value, an air flow rate to input to the burner; and controlling the air flow rate provided to the burner based on the determined air flow rate.
NN time measurements. The sampling circuit is to generate a second sampled window from the clock signal input including an accumulation of a plurality of products. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.
