Systems for authenticating a file are disclosed. A system may include one or more physical devices. The one or more physical devices may select, based on an identifier, a subset of data segments of a computer file for generating a first digest with a cryptographic function. The one or more physical devices may also execute the cryptographic function on the selected subset of data segments of the computer file to generate the first digest. Further, the one or more physical devices may generate an authenticator based on the first digest and a private key. The one or more physical devices may further send the computer file, the identifier, and the authenticator to a secure node. Associated methods and non-transitory machine-readable medium are also disclosed.
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
2.
SYSTEM AND METHODS FOR COMPUTING PARITY INFORMATION IN A RAID ARRAY
A redundant disk array may include redundant information to facilitate rebuilding the array in the event of a disk failure. A host processor may allocate buffers in an accelerator memory. Data may be moved from one or more storage devices to the buffers. An accelerator engine may perform parity calculations required to rebuild the array based on data in the buffers without requiring a host CPU to perform the parity calculation.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
3.
SYSTEM AND METHODS FOR COMPUTING PARITY INFORMATION IN A RAID ARRAY
A redundant disk array may include redundant information to facilitate rebuilding the array in the event of a disk failure. A host processor may allocate buffers in an accelerator memory. Data may be moved from one or more storage devices to the buffers. An accelerator engine may perform parity calculations required to rebuild the array based on data in the buffers without requiring a host CPU to perform the parity calculation.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
4.
HIGH VOLTAGE WAKE SIGNALING INPUT/OUTPUT FOR 10BASE-T1S SYSTEM-BASIS-CHIP
A method may include receiving signaling at a system basis chip implementing a transceiver of a 10SPE PHY; changing, at the system basis chip, the signaling from first voltage levels incompatible with a voltage domain of a microcontroller (MCU) implementing a controller of the 10SPE PHY to second voltage levels compatible with the voltage domain of the MCU;and communicating the changed signaling to the MCU.
A circuit may enable communication between a primary device and one or more secondary devices. The communication may utilize a Universal Asynchronous Receiver Transmitter (UART) protocol. In operation, the primary device may require information on the baud rate of the secondary device. The UART may operate in an inverted polarity mode, and this inverted polarity may be interpreted by the secondary device as a request to enter an auto-baud detection mode. Using the inverted polarity mode to enter the auto-baud detection mode may prevent excessive delays in the UART communication and may prevent the need for additional pins to implement the auto-baud detection mode.
G06F 13/10 - Commande par programme pour dispositifs périphériques
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
A circuit may enable communication between a primary device and one or more secondary devices. The communication may utilize a Universal Asynchronous Receiver Transmitter (UART) protocol. In operation, the primary device may require information on the baud rate of the secondary device. The UART may operate in an inverted polarity mode, and this inverted polarity may be interpreted by the secondary device as a request to enter an auto-baud detection mode. Using the inverted polarity mode to enter the auto-baud detection mode may prevent excessive delays in the UART communication and may prevent the need for additional pins to implement the auto-baud detection mode.
A high voltage wake signaling input/output for 10BASE-T1S system basis chip. An apparatus includes a pad associated with wake signaling at a 10BASET 1S PHY, the wake signaling represented by voltage changes between first voltage levels; a system basis chip, comprising: a circuit to change a voltage received from the pad from first voltage levels to second, corresponding voltage levels, the second voltage levels lower than the first voltage levels; and a logic circuit to detect a valid voltage change at the pad responsive to the changed voltage.
Examples include managing address space in a register bank of a system basis chip. An apparatus includes a bus slave and a system basis chip including. The system basis chip includes a register bank, an access controller to confine reach of the bus slave to a select set of addresses of the register bank, and an address space manager to set the select set of addresses of the register bank.
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
9.
MANAGING ADDRESS SPACE IN REGISTER BANK OF SYSTEM BASIS CHIP
Examples include managing address space in a register bank of a system basis chip. An apparatus includes a bus slave and a system basis chip including. The system basis chip includes a register bank, an access controller to confine reach of the bus slave to a select set of addresses of the register bank, and an address space manager to set the select set of addresses of the register bank.
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
A powered device (PD) interface controller is provided that includes a switch and control circuitry. The switch controls current to a PD from a power sourcing equipment (PSE). The PD accepts power from a network cable over which data is carried, and the PSE provides the power to the network cable. The PD also accepts power from an auxiliary power source. The control circuitry detects a change-over from the auxiliary power source to the PSE as a source of power. The control circuitry turns on the switch to control the current to a short circuit current limit level, greater than a startup inrush current limit of the PD, for a period of time less than a short circuit time limit, to charge a bulk capacitor of the PD. The control circuitry turns on the switch fully to allow the current to flow towards the PD.
H02J 9/06 - Circuits pour alimentation de puissance de secours ou de réserve, p. ex. pour éclairage de secours dans lesquels le système de distribution est déconnecté de la source normale et connecté à une source de réserve avec commutation automatique
H02M 3/04 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques
A powered device (PD) interface controller is provided that includes a switch and control circuitry. The switch controls current to a PD from a power sourcing equipment (PSE). The PD accepts power from a network cable over which data is carried, and the PSE provides the power to the network cable. The PD also accepts power from an auxiliary power source. The control circuitry detects a change-over from the auxiliary power source to the PSE as a source of power. The control circuitry turns on the switch to control the current to a short circuit current limit level, greater than a startup inrush current limit of the PD, for a period of time less than a short circuit time limit, to charge a bulk capacitor of the PD. The control circuitry turns on the switch fully to allow the current to flow towards the PD.
A method includes providing a system basis chip that supports at least two power states: a sleep state and an awake state; monitoring for power state information via a hardware interface and via a communication interface, wherein the hardware interface allows communication between a physical layer (PHY) transceiver implemented at the system basis chip and a PHY controller implemented at a microcontroller, and wherein the communication interface allows communication between the system basis chip and the microcontroller; and coordinating a change in power state of the system basis chip at least partially based on reception of power state information via the hardware interface and the communication interface.
A method may include executing, by a processor of a microcontroller system, instructions fetched from a first memory of the microcontroller system; setting the processor of the microcontroller to execute instructions from a second memory of the microcontroller at least partially responsive to a state of an internal signal of the microcontroller; and executing, by the processor of the microcontroller system, instructions fetched from the second memory of the microcontroller system.
A method includes providing a system basis chip that supports at least two power states: a sleep state and an awake state; monitoring for power state information via a hardware interface and via a communication interface, wherein the hardware interface allows communication between a physical layer (PHY) transceiver implemented at the system basis chip and a PHY controller implemented at a microcontroller, and wherein the communication interface allows communication between the system basis chip and the microcontroller; and coordinating a change in power state of the system basis chip at least partially based on reception of power state information via the hardware interface and the communication interface.
G06F 1/3209 - Surveillance d’une activité à distance, p. ex. au travers de lignes téléphoniques ou de connexions réseau
G06F 1/3234 - Économie d’énergie caractérisée par l'action entreprise
G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
15.
CONTROLLING WHICH MEMORY SOURCE IS UTILIZED FOR FETCHING INSTRUCTIONS BY A PROCESSOR OF A MICROCONTROLLER
A method may include executing, by a processor of a microcontroller system, instructions fetched from a first memory of the microcontroller system; setting the processor of the microcontroller to execute instructions from a second memory of the microcontroller at least partially responsive to a state of an internal signal of the microcontroller, and executing, by the processor of the microcontroller system, instructions fetched from the second memory of the microcontroller system.
G01F 23/263 - Indication ou mesure du niveau des liquides ou des matériaux solides fluents, p. ex. indication en fonction du volume ou indication au moyen d'un signal d'alarme en mesurant des variables physiques autres que les dimensions linéaires, la pression ou le poids, selon le niveau à mesurer, p. ex. par la différence de transfert de chaleur de vapeur ou d'eau en mesurant les variations de capacité ou l'inductance de condensateurs ou de bobines produites par la présence d'un liquide ou d'un matériau solide fluent dans des champs électriques ou électromagnétiques en mesurant les variations de capacité de condensateurs
G01F 23/80 - Dispositions pour le traitement des signaux
G01F 25/20 - Test ou étalonnage des appareils pour la mesure du volume, du débit volumétrique ou du niveau des liquides, ou des appareils pour compter par volume des appareils pour mesurer le niveau des liquides
17.
ADAPTING TO SUPPLY VOLTAGE STRESS AT A SYSTEM BASIS CHIP
An apparatus may include a voltage source, a voltage protection circuit, and a chip powered at least in part via the voltage protection circuit. The chip may include at least one regulated voltage source; and a logic circuit. The logic circuit may determine a state of a supply voltage produced by the voltage protection circuit; determine a state of an input voltage produced by the voltage source; and determine and indicate a predicted state of the supply voltage produced by the voltage protection circuit or a predicted state of the at least one regulated voltage source, in either case at least partially based on the determined state of the supply voltage produced by the voltage protection circuit and the determined state of the input voltage produced by the voltage source.
An apparatus comprises an electrostatic discharge (ESD) protection circuitry including a first diode having a cathode coupled to a first signal input and an anode coupled to a signal ground input, a second diode having a cathode coupled to a second signal input and an anode coupled to the signal ground input, and a third diode having a cathode coupled to the signal ground input and an anode coupled to a substrate ground. In one or more examples, the apparatus comprises an analog front-end including a first analog front-end circuitry coupled to the first signal input and the signal ground input, and a second analog front-end circuitry coupled to the second signal input and the signal ground input.
An apparatus comprises an electrostatic discharge (ESD) protection circuitry including a first diode having a cathode coupled to a first signal input and an anode coupled to a signal ground input, a second diode having a cathode coupled to a second signal input and an anode coupled to the signal ground input, and a third diode having a cathode coupled to the signal ground input and an anode coupled to a substrate ground. In one or more examples, the apparatus comprises an analog front-end including a first analog front-end circuitry coupled to the first signal input and the signal ground input, and a second analog front-end circuitry coupled to the second signal input and the signal ground input.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
G01D 5/20 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p. ex. une armature mobile
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
20.
ELECTRONIC PACKAGE WITH REDISTRIBUTION LAYER PLATE FORMED VIA TEMPORARY PLUG
Electronic packages comprising: a die with a bond pad, a mold compound encapsulating at least exposed surfaces of the die surrounding the bond pad, and a unitary redistribution layer plate on at least a portion of the mold compound and extending through the mold compound in electrical communication with the bond pad. A method comprising: depositing a plug on a die bond pad, encapsulating a proximal end of the plug and at least a portion of the die proximate the proximal end of the plug with a mold compound, removing the plug from the bond pad to form an opening in the mold compound, and depositing a redistribution layer plate on the mold compound and in the opening in the mold compound on the bond pad.
A controller is provided that includes a serial data (SDA) line interface to connect the controller to an SDA line of a two-wire, shared, serial data bus. The controller includes processing circuitry to sample the SDA line to obtain samples of a voltage level on the SDA line, and monitor the samples. The processing circuitry detects a predetermined number of consecutive ones of the monitored samples at a low voltage level, without a low-to-high transition in the voltage level. The processing circuitry indicates a stuck SDA condition based on the detected, predetermined number of consecutive ones of the monitored samples.
A method comprising: molding a structural support coating over the gate pad and source pad at the front side of a wafer; back-side processing the wafer to remove a portion of a silicon layer so that the silicon layer has a post-process thickness, wherein the post-process thickness is less than the pre-process thickness; and removing the structural support coating at the front side of the wafer sufficiently to expose the gate pad and source pad. An electronic device comprising: a silicon layer less than 50 µm thick and defining a back side of the electronic device, a metal layer on the silicon layer, wherein the metal layer defines a front side of the electronic device, wherein the metal layer has a source pad and a gate pad; and a structural support coating between the source pad and the gate pad.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
23.
ELECTRONIC PACKAGE WITH REDISTRIBUTION LAYER PLATE FORMED VIA TEMPORARY PLUG
Electronic packages comprising: a die with a bond pad, a mold compound encapsulating at least exposed surfaces of the die surrounding the bond pad, and a unitary redistribution layer plate on at least a portion of the mold compound and extending through the mold compound in electrical communication with the bond pad. A method comprising: depositing a plug on a die bond pad, encapsulating a proximal end of the plug and at least a portion of the die proximate the proximal end of the plug with a mold compound, removing the plug from the bond pad to form an opening in the mold compound, and depositing a redistribution layer plate on the mold compound and in the opening in the mold compound on the bond pad.
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
24.
DETECTION OF A STUCK DATA LINE OF A SERIAL DATA BUS
A controller is provided that includes a serial data (SDA) line interface to connect the controller to an SDA line of a two-wire, shared, serial data bus. The controller includes processing circuitry to sample the SDA line to obtain samples of a voltage level on the SDA line, and monitor the samples. The processing circuitry detects a predetermined number of consecutive ones of the monitored samples at a low voltage level, without a low-to-high transition in the voltage level. The processing circuitry indicates a stuck SDA condition based on the detected, predetermined number of consecutive ones of the monitored samples.
A target is provided that includes a serial data (SDA) line interface to connect the target to a SDA line of a two-wire, shared, serial data bus. The target includes processing circuitry to transfer output data on to the SDA line, and monitor data on the SDA line. The processing circuitry compares the data on the SDA line and the output data to detect an error condition when the data on the SDA line and the output data differ. And the processing circuitry performs at least one operation to recover from the detected error condition, including at least one of disabling an output SDA pad buffer of the target that transfers the output data on to the SDA line, or asserting a stop condition on the data bus.
A target is provided that includes a serial data (SDA) line interface to connect the target to a SDA line of a two-wire, shared, serial data bus. The target includes processing circuitry to transfer output data on to the SDA line, and monitor data on the SDA line. The processing circuitry compares the data on the SDA line and the output data to detect an error condition when the data on the SDA line and the output data differ. And the processing circuitry performs at least one operation to recover from the detected error condition, including at least one of disabling an output SDA pad buffer of the target that transfers the output data on to the SDA line, or asserting a stop condition on the data bus.
A method comprising: molding a structural support coating over the gate pad and source pad at the front side of a wafer; back-side processing the wafer to remove a portion of a silicon layer so that the silicon layer has a post-process thickness, wherein the post-process thickness is less than the pre-process thickness; and removing the structural support coating at the front side of the wafer sufficiently to expose the gate pad and source pad. An electronic device comprising: a silicon layer less than 50 μm thick and defining a back side of the electronic device, a metal layer on the silicon layer, wherein the metal layer defines a front side of the electronic device, wherein the metal layer has a source pad and a gate pad; and a structural support coating between the source pad and the gate pad.
A device includes a switched power converter with an inductor, the power converter to produce a voltage output based on a pulse-width modulated (PWM) signal, and produce a peak current feedback signal, the peak current feedback signal representative of a peak current through the inductor. The device includes a comparator to generate a PWM control input (PCI) signal based on whether the peak current feedback signal has reached a reference current. The device includes a PWM generation circuit to generate the PWM signal to control switching of the switched power converter based on the PCI signal. The device includes a synchronization circuit to delay a change in the PCI signal.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
29.
TECHNIQUES FOR CONTROLLING VAPOR PRESSURE OF SUBJECT MATERIALS IN VAPOR CELLS AND RELATED METHODS
A method of manufacturing a vapor cell includes forming a body of the vapor cell having walls defining a cavity thereinbetween, the cavity having an amount of a subject material contained therein. The method also includes forming a pore structure having a substrate material with pores of a substantially uniform dimension formed therein, the pore structure disposed along a portion of one or more of the walls of the vapor cell. The method further includes forming a liner material of a uniform thickness over one or more internal surfaces of the pores, wherein the subject material exhibits a reduced wetting angle on the liner material which is less than a wetting angle of the subject material on the substrate material.
H03L 7/26 - Commande automatique de fréquence ou de phaseSynchronisation utilisant comme référence de fréquence les niveaux d'énergie de molécules, d'atomes ou de particules subatomiques
A device includes a switched power converter with an inductor, the power converter to produce a voltage output based on a pulse-width modulated (PWM) signal, and produce a peak current feedback signal, the peak current feedback signal representative of a peak current through the inductor. The device includes a comparator to generate a PWM control input (PCI) signal based on whether the peak current feedback signal has reached a reference current. The device includes a PWM generation circuit to generate the PWM signal to control switching of the switched power converter based on the PCI signal. The device includes a synchronization circuit to delay a change in the PCI signal.
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
31.
TECHNIQUES FOR CONTROLLING VAPOR PRESSURE OF SUBJECT MATERIALS IN VAPOR CELLS AND RELATED METHODS
A method of manufacturing a vapor cell includes forming a body of the vapor cell having walls defining a cavity thereinbetween, the cavity having an amount of a subject material contained therein. The method also includes forming a pore structure having a substrate material with pores of a substantially uniform dimension formed therein, the pore structure disposed along a portion of one or more of the walls of the vapor cell. The method further includes forming a liner material of a uniform thickness over one or more internal surfaces of the pores, wherein the subject material exhibits a reduced wetting angle on the liner material which is less than a wetting angle of the subject material on the substrate material.
G01R 33/26 - Dispositions ou appareils pour la mesure des grandeurs magnétiques faisant intervenir la résonance magnétique pour la mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques utilisant le pompage optique
H03L 7/26 - Commande automatique de fréquence ou de phaseSynchronisation utilisant comme référence de fréquence les niveaux d'énergie de molécules, d'atomes ou de particules subatomiques
32.
WIRELESS POWER TRANSMITTER HAVING MULTI-FREQUENCY OPERATION FOR REDUCED ELECTROMAGNETIC INTERFERENCE, AND RELATED METHODS AND APPARATUSES
A method comprises generating a wireless power transmission signal in one or more transmit coils of a wireless power transmitter and, in a multi-frequency operation of the wireless power transmitter, controlling an operating frequency of the wireless power transmission signal to repeatedly switch between a fundamental frequency and one of a lower frequency and an upper frequency in an alternating manner. The lower frequency is offset from the fundamental frequency by a first offset. The upper frequency is offset from the fundamental frequency by a second offset. The second offset is different from the first offset. The first offset associated with the lower frequency and the second offset associated with the upper frequency are to ensure a transmit power in the multi-frequency operation is substantially the same as a transmit power at the fundamental frequency.
H02J 50/70 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique mettant en œuvre la réduction des champs de fuite électriques, magnétiques ou électromagnétiques
H02J 50/00 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique
H02J 50/12 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif du type couplage à résonance
33.
SWITCHED CAPACITORS TO GALVANICALLY ISOLATE AND AMPLIFY ANALOG SIGNALS VIA TRANSFERRED DIFFERENTIAL VOLTAGE SIGNAL
Integrated circuits and methods to provide an operative coupling comprising an input stage and an output stage between an analog input and an analog output; synchronously operate a plurality of high voltage domain switches of the input stage and a plurality of low voltage domain switches of the output stage at a frequency to galvanically isolate the input stage from the output stage across a plurality of capacitors having a plurality of input plates respectively connected to the switches of the input and output stages; supply an analog input signal to the input stage; transfer a differential voltage signal component within a range of a common mode voltage supply from the high voltage domain of the input stage to the low voltage domain of the output stage; differentially amplify the low voltage domain differential voltage signal component; and output an analog output signal.
Integrated circuits and methods to provide an operative coupling comprising an input stage and an output stage between an analog input and an analog output; synchronously operate a plurality of high voltage domain switches of the input stage and a plurality of low voltage domain switches of the output stage at a frequency to galvanically isolate the input stage from the output stage across a plurality of capacitors having a plurality of input plates respectively connected to the switches of the input and output stages; supply an analog input signal to the input stage; transfer a differential voltage signal component within a range of a common mode voltage supply from the high voltage domain of the input stage to the low voltage domain of the output stage; differentially amplify the low voltage domain differential voltage signal component; and output an analog output signal.
A method comprises generating a wireless power transmission signal in one or more transmit coils of a wireless power transmitter and, in a multi-frequency operation of the wireless power transmitter, controlling an operating frequency of the wireless power transmission signal to repeatedly switch between a fundamental frequency and one of a lower frequency and an upper frequency in an alternating manner. The lower frequency is offset from the fundamental frequency by a first offset. The upper frequency is offset from the fundamental frequency by a second offset. The second offset is different from the first offset. The first offset associated with the lower frequency and the second offset associated with the upper frequency are to ensure a transmit power in the multi-frequency operation is substantially the same as a transmit power at the fundamental frequency.
H02J 50/00 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique
H02J 50/12 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif du type couplage à résonance
H02J 50/40 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant plusieurs dispositifs de transmission ou de réception
H02J 50/90 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique mettant en œuvre la détection ou l'optimisation de la position, p. ex. de l'alignement
09 - Appareils et instruments scientifiques et électriques
Produits et services
Computer hardware; semiconductors; microcontrollers;
microcontroller units comprised of semiconductor chips,
integrated circuits, computer memories, electronic memories,
data processing apparatus, and electronic and electrical
control apparatus.
In one implementation a processor has an instruction fetch circuit fetching instructions, the instruction fetch circuit having an input and an output and a decode circuit to decode the fetched instructions, the decode circuit having a first and second input, and an output, wherein the decode circuit first input is coupled to the instruction fetch circuit output receiving the fetched instructions, and an execution circuit executing the decoded fetched instructions, the execution circuit having an input coupled to the decode circuit output to receive the decoded fetched instructions, and a switch instruction circuit (SIC) to detect and execute switch instructions of the fetched instructions, the SIC having an input and an output, wherein the SIC input is coupled to the instruction fetch circuit output to receive the fetched instructions, wherein the SIC output is coupled to the decode circuit second input and the instruction fetch circuit input.
In one implementation a processor has an instruction fetch circuit fetching instructions, the instruction fetch circuit having an input and an output and a decode circuit to decode the fetched instructions, the decode circuit having a first and second input, and an output, wherein the decode circuit first input is coupled to the instruction fetch circuit output receiving the fetched instructions, and an execution circuit executing the decoded fetched instructions, the execution circuit having an input coupled to the decode circuit output to receive the decoded fetched instructions, and a switch instruction circuit (SIC) to detect and execute switch instructions of the fetched instructions, the SIC having an input and an output, wherein the SIC input is coupled to the instruction fetch circuit output to receive the fetched instructions, wherein the SIC output is coupled to the decode circuit second input and the instruction fetch circuit input.
An ideal diode bridge controller is provided that includes gate drivers to connect to transistors of a bridge rectifier in which the transistors are arranged as high-side transistors and low-side transistors. The gate drivers alternately switch the transistors to cause the bridge rectifier to convert an input voltage of either of two polarities to an output voltage of one of the two polarities. The gate drivers include low-side gate drivers for the low-side transistors, and respective ones of the low-side gate drivers include linear drive circuitry and digital drive circuitry. The linear drive circuitry drives a respective low-side transistor to switch on and off based on forward current through the respective low-side transistor. The digital drive circuitry detects a reverse current through the respective low-side transistor, and causes the respective low-side transistor to switch off in response to the reverse current.
H02M 7/219 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continu sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs dans une configuration en pont
H02M 1/00 - Détails d'appareils pour transformation
H03K 17/06 - Modifications pour assurer un état complètement conducteur
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
40.
Memory Device Formed On Silicon-On-Insulator Substrate, And Method Of Making Same
A memory device includes a SOI substrate comprising bulk silicon, an insulation layer vertically over the bulk silicon, and a silicon layer vertically over the insulation layer. A memory cell includes source and drain regions formed in the bulk silicon with a channel region of the bulk silicon extending therebetween, and a floating gate which includes a first portion of the silicon layer disposed vertically over and insulated from a first portion of the channel region by the insulation layer. The first portion of the silicon layer is epitaxially thickened or a layer of polysilicon is formed on the first portion of the silicon layer. A select gate is disposed vertically over and insulated from a second portion of the channel region. A control gate is disposed vertically over and insulated from the floating gate. An erase gate is disposed vertically over and insulated from the source region.
H10B 41/30 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
An ideal diode bridge controller is provided that includes gate drivers to connect to transistors of a bridge rectifier in which the transistors are arranged as high-side transistors and low-side transistors. The gate drivers alternately switch the transistors to cause the bridge rectifier to convert an input voltage of either of two polarities to an output voltage of one of the two polarities. The gate drivers include low-side gate drivers for the low-side transistors, and respective ones of the low-side gate drivers include linear drive circuitry and digital drive circuitry. The linear drive circuitry drives a respective low-side transistor to switch on and off based on forward current through the respective low-side transistor. The digital drive circuitry detects a reverse current through the respective low-side transistor, and causes the respective low-side transistor to switch off in response to the reverse current.
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02M 7/219 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continu sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs dans une configuration en pont
H03K 17/00 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts
42.
MEMORY DEVICE FORMED ON SILICON-ON-INSULATOR SUBSTRATE, AND METHOD OF MAKING SAME
A memory device includes a SOI substrate comprising bulk silicon (12), an insulation layer (14) vertically over the bulk silicon, and a silicon layer (16) vertically over the insulation layer. A memory cell (20) includes source (30) and drain (32) regions formed in the bulk silicon with a channel region (34) of the bulk silicon extending therebetween, and a floating gate (36) which includes a first portion of the silicon layer disposed vertically over and insulated from a first portion of the channel region by the insulation layer. The first portion of the silicon layer is epitaxially thickened or a layer of polysilicon (62) is formed on the first portion of the silicon layer. A select gate (38) is disposed vertically over and insulated from a second portion of the channel region. A control gate (40) is disposed vertically over and insulated from the floating gate. An erase gate (42) is disposed vertically over and insulated from the source region.
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H10B 41/30 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire
H10B 41/43 - Fabrication simultanée de périphérie et de cellules de mémoire ne comprenant qu’un type de transistor de périphérie
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 29/66 - Types de dispositifs semi-conducteurs
43.
INDICATING PRESENCE OF A PORTION OF DATA CORRESPONDING TO A PREDETERMINED PATTERN AT A RECEPTION DATAPATH OF A PHYSICAL LAYER
One or more examples relate to a method that includes: applying oversampling to data on a reception datapath of a physical layer; generating a first signal indicating relationships between patterns exhibited by portions of oversampled data and a predetermined pattern; generating a second signal indicating an observed feature of the first signal, the observed feature indicative of a highest relationship between the patterns exhibited by respective portions of oversampled data and the predetermined pattern; and providing the second signal to indicate presence of a portion of data corresponding to the predetermined pattern at a coupled portion of the reception datapath of the physical layer.
One or more examples relate to a method that includes: applying oversampling to data on a reception datapath of a physical layer; generating a first signal indicating relationships between patterns exhibited by portions of oversampled data and a predetermined pattern; generating a second signal indicating an observed feature of the first signal, the observed feature indicative of a highest relationship between the patterns exhibited by respective portions of oversampled data and the predetermined pattern; and providing the second signal to indicate presence of a portion of data corresponding to the predetermined pattern at a coupled portion of the reception datapath of the physical layer.
An apparatus is provided that includes one or more leads and processing circuitry. The one or more leads are to connect the apparatus to one or more light-emitting diode (LED) leads of an LED controller. The processing circuitry is to receive a pulse-width modulation (PWM) signal from the LED controller. The processing circuitry decodes the PWM signal to recover downstream information from the PWM signal, and performs an operation based on the downstream information.
An apparatus is provided that includes a controlled voltage source and processing circuitry. The controlled voltage source connects to one or more light-emitting diode (LED) leads of a light-emitting diode (LED) controller that is in communication with a host. The processing circuitry selects a particular one of a plurality of predetermined voltages based on upstream information to be communicated to the host. The processing circuitry causes the controlled voltage source to impose the particular one of the plurality of predetermined voltages on the one or more LED leads, and thereby communicate the upstream information to the host via the LED controller.
An apparatus is provided that includes a controlled voltage source and processing circuitry. The controlled voltage source connects to one or more light-emitting diode (LED) leads of a light-emitting diode (LED) controller that is in communication with a host. The processing circuitry selects a particular one of a plurality of predetermined voltages based on upstream information to be communicated to the host. The processing circuitry causes the controlled voltage source to impose the particular one of the plurality of predetermined voltages on the one or more LED leads, and thereby communicate the upstream information to the host via the LED controller.
An apparatus and method coupling a first and a second data bus comprising selectors for routing first bus egress lanes to egress memories, each egress memory coupled to one second bus egress lane, where the second bus has more egress lanes than the first. Each egress memory corresponds to one second bus egress lane. A first FSM selecting which first bus egress lane to load into each egress memory synchronous with the first bus clock. A second FSM outputting egress memory values to the second bus synchronous with the second bus clock. A set of ingress memories, each memory coupled to one second bus ingress lane and to an input of each ingress selector. A third FSM loading the ingress memories synchronous with the second bus clock. A fourth FSM selecting which ingress memory to route to each first bus ingress lane synchronous with the first bus clock.
A system may include a communication circuit as part of a microcontroller. One or more registers may be configured to enable communication between the communication circuit and one or more external peripherals without a CPU or other processor controlling the communication. The one or more registers may be configured to allow a specific trigger event to initiate communication between the communication circuit and the external peripheral. A DMA controller may transmit data from the communication circuit to a memory and may transmit data from the memory to the external peripheral.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
50.
APPARATUS TO RECEIVE DOWNSTREAM INFORMATION VIA A LIGHT-EMITTING DIODE (LED) CONTROLLER
An apparatus is provided that includes one or more leads and processing circuitry. The one or more leads are to connect the apparatus to one or more light-emitting diode (LED) leads of an LED controller. The processing circuitry is to receive a pulse-width modulation (PWM) signal from the LED controller. The processing circuitry decodes the PWM signal to recover downstream information from the PWM signal, and performs an operation based on the downstream information.
A system may include a communication circuit as part of a microcontroller. One or more registers may be configured to enable communication between the communication circuit and one or more external peripherals without a CPU or other processor controlling the communication. The one or more registers may be configured to allow a specific trigger event to initiate communication between the communication circuit and the external peripheral. A DMA controller may transmit data from the communication circuit to a memory and may transmit data from the memory to the external peripheral.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 13/24 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant l'interruption
An apparatus comprises a discrete-time linear equalizer circuit. The discrete-time linear equalizer circuit comprises a sample and hold circuitry including multiple switched-capacitor circuits. The multiple switched-capacitor circuits include at least a switched-capacitor circuit of a pre-cursor tap, a switched-capacitor circuit of a cursor tap, and a switched-capacitor circuit of a post-cursor tap. A clock-driven switch circuitry is to switchably couple a capacitor of the switched-capacitor circuit of the pre-cursor tap to a signal input over a first time period, a capacitor of the switched-capacitor circuit of the cursor tap to the signal input over a second time period, and a capacitor of the switched-capacitor circuit of the post-cursor tap to the signal input over a third time period. The clock-driven switch circuitry is to switchably couple the capacitor of the switched-capacitor circuit of the cursor tap to an output, and the capacitors of the SHCs of the pre-cursor and post-cursor taps in a closed feedback loop with the capacitor of the switched-capacitor circuit of the cursor tap, over a fourth time period.
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
53.
COIL STRUCTURES FOR INDUCTIVE ANGULAR-POSITION SENSING
An apparatus comprises a target to rotate about an axis; an excitation coil to carry an excitation signal; and a first sense coil to carry a sense signal induced by the excitation signal. The first sense coil comprises two or more lobes in one or more planes that are perpendicular to the axis. The two or more lobes comprise a first lobe at a first position relative to the axis and a second lobe at a second position relative to the axis. The second position is substantially the same radial distance from the axis as the first position is from the axis. The second position is at an angular distance of Θ from the first position, where Θ=180°±α/2, and α is a measurement range for angular-position sensing (e.g., α=60°) within a range of 50% to 150% of α.
G01B 7/30 - Dispositions pour la mesure caractérisées par l'utilisation de techniques électriques ou magnétiques pour mesurer des angles ou des cônesDispositions pour la mesure caractérisées par l'utilisation de techniques électriques ou magnétiques pour tester l'alignement des axes
G01D 5/20 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p. ex. une armature mobile
54.
SEAMLESS HANDOVER OF WIRELESS CONNECTIONS USING LOW-THROUGHPUT COMMUNICATION DEVICES, INCLUDING RELATED METHODS AND APPARATUSES
A method of a controller comprises receiving a first message from a peripheral device that operates in a receiving and transmitting mode for communication of data over a wireless connection with a central device; sending a second message to respective ones of one or more other peripheral devices, the second message indicating a command to synchronize with the wireless connection in a receiving-only mode; and at least partially responsive to identifying a handover condition, sending a third message to a respective one of the one or more other peripheral devices, the third message indicating a command to switch to the receiving and transmitting mode for communication of data over the wireless connection with the central device.
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
H04W 36/00 - Dispositions pour le transfert ou la resélection
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Ethernet transceivers; ethernet switches; semiconductors;
integrated circuits; microprocessors; system on a chip
(SoC); recorded and downloadable computer software and
firmware for ethernet configuration; recorded and
downloadable computer software and firmware for automotive
networking and data communication. Consulting and advising in the fields of computer network
configuration and ethernet configuration.
56.
SEAMLESS HANDOVER OF WIRELESS CONNECTIONS USING LOW-THROUGHPUT COMMUNICATION DEVICES, INCLUDING RELATED METHODS AND APPARATUSES
A method of a controller comprises receiving a first message from a peripheral device that operates in a receiving and transmitting mode for communication of data over a wireless connection with a central device; sending a second message to respective ones of one or more other peripheral devices, the second message indicating a command to synchronize with the wireless connection in a receiving-only mode; and at least partially responsive to identifying a handover condition, sending a third message to a respective one of the one or more other peripheral devices, the third message indicating a command to switch to the receiving and transmitting mode for communication of data over the wireless connection with the central device.
H04W 36/18 - Exécution d'une resélection à des fins spécifiques pour permettre une resélection sans coupure, p. ex. une resélection en douceur
H04W 36/00 - Dispositions pour le transfert ou la resélection
H04W 52/40 - Commande de puissance d'émission [TPC Transmission power control] le TPC étant effectué dans des situations particulières en macrodiversité ou en transfert progressif
57.
TRANSMIT COIL SELECTION RESPONSIVE TO AVERAGE PEAK TO PEAK MEASUREMENT VOLTAGE POTENTIALS AND RELATED APPARATUSES AND METHOD
Object detection in wireless power systems and related system, methods, and devices are disclosed. A controller for a wireless power transmitter includes a measurement voltage potential input terminal and a processing core. The processing core is to determine an average of peak to peak amplitude differences present in sampled measurement voltage potentials for each of the plurality of transmit coils, determine a lowest average of the peak to peak amplitude differences, and select a transmit coil corresponding to the lowest average of the peak to peak amplitude differences to transmit wireless power to a receive coil of a wireless power receiver. A wireless power system includes a tank circuit selectively including any one of a plurality of transmit coils.
H02J 50/60 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique sensibles à la présence d’objets étrangers, p. ex. détection d'êtres vivants
H02J 50/05 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage capacitif
H02J 50/12 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif du type couplage à résonance
H02J 50/40 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant plusieurs dispositifs de transmission ou de réception
58.
DISCRETE-TIME ANALOG FRONT-END FOR HIGH-SPEED SERIAL DATA RECEIVERS
An apparatus comprises a discrete-time analog front-end circuit. The discrete-time analog front-end circuit includes a sample and hold circuit, a discrete-time linear equalizer circuit having an input coupled to an output of the sample and hold circuit, and a discrete-time programmable gain amplifier circuit having an input coupled to an output of the discrete-time linear equalizer circuit. The sample and hold circuit is to generate a discrete-time modulated signal at least partially based on a continuous-time modulated signal. The discrete-time linear equalizer circuit is to generate an equalized discrete-time modulated signal at least partially based on the discrete-time modulated signal. The discrete-time programmable gain amplifier circuit is to generate an amplified equalized discrete-time modulated signal at least partially based on the equalized discrete-time modulated signal. The discrete-time analog front-end circuit may include a quantizer circuit having an input coupled to an output of the discrete-time programmable gain amplifier circuit.
An apparatus comprises a discrete-time linear equalizer circuit. The discrete-time linear equalizer circuit includes a sample and hold circuitry including multiple switched-capacitor circuits. The multiple switched-capacitor circuits include at least a switched-capacitor circuit of a pre-cursor tap, a switched-capacitor circuit of a cursor tap, and a switched-capacitor circuit of a post-cursor tap. A clock-driven switch circuitry is to switchably couple a capacitor of the switched-capacitor circuit of the pre-cursor tap to a negative signal input over a first time period, a capacitor of the switched-capacitor circuit of the cursor tap to a positive signal input over a second time period, and a capacitor of the switched-capacitor circuit of the post-cursor tap to the negative signal input over a third time period. The clock-driven switch circuitry is to switchably couple the capacitors of the switched-capacitor circuits in parallel over a fourth time period.
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
Systems having a capacitive touch sensing system with transmit and receive electrodes positioned to have mutual capacitances at node intersections that deviate when a node is touched; a processor; and a machine readable storage medium with instructions to: assign complete code words to transmit electrodes; identify a subset of transmit electrodes based on a prior touch position estimate; generate a transmit signal for the transmit electrodes; receive a first portion of a receive signal for receive electrodes indicative of capacitances; decode the first portion of the receive signal of receive electrodes using the first portions of the code words; and compute touch position estimates for the subset of transmit electrodes based on the decoded first portions of the receive signals.
Methods may involve supporting a plurality of microelectronic dice on a printed circuit panel. Respective microelectronic dice of the plurality of microelectronic dice may be electrically connected to at least one via of the printed circuit panel. Microelectronic device packages may be singulated from the printed circuit panel, respective microelectronic device packages including at least one microelectronic die of the plurality of microelectronic dice and a portion of the printed circuit panel. Structures may include a plurality of microelectronic dice supported on a printed circuit panel. The printed circuit panel may include vias, subsets of the vias positioned for electrical connection to a respective microelectronic die of the plurality of microelectronic dice
An apparatus comprises a discrete-time linear equalizer circuit. The discrete-time linear equalizer circuit comprises a sample and hold circuitry including multiple switched-capacitor circuits. The multiple switched-capacitor circuits include at least a switched-capacitor circuit of a pre-cursor tap, a switched-capacitor circuit of a cursor tap, and a switched-capacitor circuit of a post-cursor tap. A clock-driven switch circuitry is to switchably couple a capacitor of the switched-capacitor circuit of the pre-cursor tap to a signal input over a first time period, a capacitor of the switched-capacitor circuit of the cursor tap to the signal input over a second time period, and a capacitor of the switched-capacitor circuit of the post-cursor tap to the signal input over a third time period. The clock-driven switch circuitry is to switchably couple the capacitor of the switched-capacitor circuit of the cursor tap to an output, and the capacitors of the SHCs of the pre-cursor and post-cursor taps in a closed feedback loop with the capacitor of the switched-capacitor circuit of the cursor tap, over a fourth time period.
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
A circuit for electrostatic discharge (ESD) protection may protect sensitive circuits in the presence of both positive and negative ESD events. A protection transistor may be coupled to a pad, and a protection clamp may be coupled to the protection transistor. The protection transistor may be in an isolation n-well, and a current limiting resistor may be coupled from the pad to the isolation n-well. In operation, the current limiting resistor may limit the current during negative ESD events.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
Methods may involve supporting a plurality of microelectronic dice on a printed circuit panel. Respective microelectronic dice of the plurality of microelectronic dice may be electrically connected to at least one via of the printed circuit panel. Microelectronic device packages may be singulated from the printed circuit panel, respective microelectronic device packages including at least one microelectronic die of the plurality of microelectronic dice and a portion of the printed circuit panel. Structures may include a plurality of microelectronic dice supported on a printed circuit panel. The printed circuit panel may include vias, subsets of the vias positioned for electrical connection to a respective microelectronic die of the plurality of microelectronic dice.
A circuit for electrostatic discharge (ESD) protection may protect sensitive circuits in the presence of both positive and negative ESD events. A protection transistor may be coupled to a pad, and a protection clamp may be coupled to the protection transistor. The protection transistor may be in an isolation n-well, and a current limiting resistor may be coupled from the pad to the isolation n-well. In operation, the current limiting resistor may limit the current during negative ESD events.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
Systems having a capacitive touch sensing system with transmit and receive electrodes positioned to have mutual capacitances at node intersections that deviate when a node is touched; a processor; and a machine readable storage medium with instructions to: assign complete code words to transmit electrodes; identify a subset of transmit electrodes based on a prior touch position estimate; generate a transmit signal for the transmit electrodes; receive a first portion of a receive signal for receive electrodes indicative of capacitances; decode the first portion of the receive signal of receive electrodes using the first portions of the code words; and compute touch position estimates for the subset of transmit electrodes based on the decoded first portions of the receive signals.
An apparatus comprises a discrete-time analog front-end circuit. The discrete-time analog front-end circuit includes a sample and hold circuit, a discrete-time linear equalizer circuit having an input coupled to an output of the sample and hold circuit, and a discrete-time programmable gain amplifier circuit having an input coupled to an output of the discrete-time linear equalizer circuit. The sample and hold circuit is to generate a discrete-time modulated signal at least partially based on a continuous-time modulated signal. The discrete-time linear equalizer circuit is to generate an equalized discrete-time modulated signal at least partially based on the discrete-time modulated signal. The discrete-time programmable gain amplifier circuit is to generate an amplified equalized discrete-time modulated signal at least partially based on the equalized discrete-time modulated signal. The discrete-time analog front-end circuit may include a quantizer circuit having an input coupled to an output of the discrete-time programmable gain amplifier circuit.
An apparatus comprises a discrete-time linear equalizer circuit. The discrete-time linear equalizer circuit includes a sample and hold circuitry including multiple switched-capacitor circuits. The multiple switched-capacitor circuits include at least a switched-capacitor circuit of a pre-cursor tap, a switched-capacitor circuit of a cursor tap, and a switched-capacitor circuit of a post-cursor tap. A clock-driven switch circuitry is to switchably couple a capacitor of the switched-capacitor circuit of the pre-cursor tap to a negative signal input over a first time period, a capacitor of the switched-capacitor circuit of the cursor tap to a positive signal input over a second time period, and a capacitor of the switched-capacitor circuit of the post-cursor tap to the negative signal input over a third time period. The clock-driven switch circuitry is to switchably couple the capacitors of the switched-capacitor circuits in parallel over a fourth time period.
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
09 - Appareils et instruments scientifiques et électriques
Produits et services
Computer hardware; semiconductors; microcontrollers; microcontroller units comprised of semiconductor chips, integrated circuits, computer memories, electronic memories, data processing apparatus, and electronic and electrical control apparatus
70.
Verifying Or Reading A Cell In An Analog Neural Memory In A Deep Learning Artificial Neural Network
In one example, a circuit for comparing current drawn by a selected memory cell for a vector-matrix-multiplier with current drawn by a reference matrix comprises a first circuit comprising a first PMOS transistor coupled to a first NMOS transistor coupled to the selected memory cell; and a second circuit comprising a second PMOS transistor coupled to a second NMOS transistor coupled to the reference matrix; wherein a node between the second PMOS transistor and the second NMOS transistor outputs a current indicative of a value stored in the selected memory cell.
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
71.
MASKING SPARSE INPUTS AND OUTPUTS IN NEURAL NETWORK ARRAY
Numerous examples are disclosed of a masking circuit for inputs and outputs in a neural network array. In one example, a system comprises a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent an application of a sparse input to one or more rows in the array when a condition is satisfied.
G11C 11/54 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments simulateurs de cellules biologiques, p. ex. neurone
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G11C 8/08 - Circuits de commande de lignes de mots, p. ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots
72.
ANALOG COMPUTATION-IN-MEMORY ENGINE AND DIGITAL COMPUTATION-IN-MEMORY ENGINE TO PERFORM OPERATIONS IN A NEURAL NETWORK
In one example disclosed herein, a system comprises an analog computation-in-memory engine to perform operations in a first layer in a neural network and a digital computation-in-memory engine to perform operations in a second layer different than the first layer in the neural network. The system optionally comprises a dynamic weight engine to perform operations in a third layer different than the first layer and the second layer in the neural network.
G11C 11/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G11C 11/54 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments simulateurs de cellules biologiques, p. ex. neurone
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 27/00 - Mémoires analogiques électriques, p. ex. pour emmagasiner des valeurs instantanées
G11C 11/413 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c.-à-d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p. ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
73.
ANALOG COMPUTATION-IN-MEMORY ENGINE AND DIGITAL COMPUTATION-IN-MEMORY ENGINE TO PERFORM OPERATIONS IN A NEURAL NETWORK
In one example disclosed herein, a system comprises an analog computation-in-memory engine to perform operations in a first layer in a neural network and a digital computation-in-memory engine to perform operations in a second layer different than the first layer in the neural network. The system optionally comprises a dynamic weight engine to perform operations in a third layer different than the first layer and the second layer in the neural network.
Numerous examples are disclosed of a row address decoding scheme. In one example, a memory system comprises m banks of non-volatile memory cells, the m banks respectively comprising n or fewer sectors and the sectors respectively comprising p rows, and a row decoder to receive a row address comprising r bits and to identify (i) a row using the least significant t bits in the r bits, (ii) a bank using the next u least significant bits, and (iii) a sector using the next v least significant bits, where m≤2u, n≤2v, and p≤2t.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/12 - Circuits de commande de lignes de bits, p. ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, circuits d'égalisation, pour lignes de bits
A device and method for sigma-delta modulation may include an input signal and a plurality of integrators. The output of the integrators and a data input may be input to an adder, the sum output to be input to a quantizer to generate a quantized output signal. A reset input to the first integrator may be asserted during a first sample of the quantized output signal to reduce the signal discontinuity at the input of the first integrator, which improves the stability of the sigma-delta modulator.
A device (100) includes a high-voltage amplifier (120) to amplify a bursted signal (115) and couples to a driver circuit (128) to drive a piezoelectric actuator (150). During the on-time of the bursted signal, a feedback circuit (190) may compensate for non-idealities in the system and may equalize the signal at the actuator and the output of the high-voltage amplifier. During the off-time of the bursted signal, a signal conditioning circuit (160) may sense a difference signal between the signal at the actuator and the signal at the high-voltage amplifier output and interprets this difference signal as pressure applied to the piezoelectric actuator.
An excitation circuit is provided for a transformer-based measuring device that includes an excitation coil. The excitation circuit includes an H-bridge circuit and a compensation circuit. The H-bridge circuit is to convert a unipolar square wave signal to a bipolar square wave signal to drive the excitation coil. The H-bridge circuit includes push-pull amplifiers arranged in two legs. The compensation circuit is coupled between the two legs of the H-bridge circuits, and compensates for any distortion in the bipolar square wave signal caused by the excitation coil as an inductive load on the H-bridge circuit.
G01D 5/20 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p. ex. une armature mobile
G01D 3/028 - Dispositions pour la mesure prévues pour les objets particuliers indiqués dans les sous-groupes du présent groupe pour atténuer les influences indésirables, p. ex. température, pression
78.
ROW DECODER AND ROW ADDRESS SCHEME IN A MEMORY SYSTEM
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 8/12 - Circuits de sélection de groupe, p. ex. pour la sélection d'un bloc de mémoire, la sélection d'une puce, la sélection d'un réseau de cellules
79.
H-BRIDGE PUSH-PULL EXCITATION CIRCUIT FOR A TRANSFORMER-BASED MEASURING DEVICE
An excitation circuit is provided for a transformer-based measuring device that includes an excitation coil. The excitation circuit includes an H-bridge circuit and a compensation circuit. The H-bridge circuit is to convert a unipolar square wave signal to a bipolar square wave signal to drive the excitation coil. The H-bridge circuit includes push-pull amplifiers arranged in two legs. The compensation circuit is coupled between the two legs of the H-bridge circuits, and compensates for any distortion in the bipolar square wave signal caused by the excitation coil as an inductive load on the H-bridge circuit.
G01D 5/22 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p. ex. une armature mobile influençant deux bobines par une action différentielle
80.
SYSTEM AND METHODS FOR LOW VOLTAGE SENSING IN PIEZOELECTRIC HAPTICS
A device includes a high-voltage amplifier to amplify a bursted signal and may couple to a driver circuit to drive a piezoelectric actuator. During the on-time of the bursted signal, a feedback circuit may compensate for non-idealities in the system and may equalize the signal at the actuator and the output of the high-voltage amplifier. During the off-time of the bursted signal, a signal conditioning circuit may sense a difference signal between the signal at the actuator and the signal at the high-voltage amplifier output and may interpret this difference signal as pressure applied to the piezoelectric actuator.
Numerous examples are disclosed of a masking circuit for inputs and outputs in a neural network array. In one example, a system comprises a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent an application of a sparse input to one or more rows in the array when a condition is satisfied.
Systems and methods for communicating brain waves or control signals via body communication from the brain to body extremities to control or activate body parts or even external devices. An EEG coupler/transceiver couples to a person's scalp, wherein the EEG coupler/transceiver comprises an EEG electrode to receive a brain wave from the person, an EEG body communication coupler and an EEG antenna to transmit a signal via the EEG body communication coupler. An activator coupler/transceiver couples to the person's body to stimulate a muscle of the person's body, wherein the activator coupler/transceiver comprises a muscle activator, an activator body communication coupler, and an activator antenna to receive the signal via the activator body communication coupler.
A61B 5/00 - Mesure servant à établir un diagnostic Identification des individus
A61B 5/291 - Électrodes bioélectriques à cet effet spécialement adaptées à des utilisations particulières pour l’électroencéphalographie [EEG]
A61B 5/395 - Détails de la stimulation, p. ex. stimulation d’un nerf pour provoquer une réponse EMG
A61N 1/36 - Application de courants électriques par électrodes de contact courants alternatifs ou intermittents pour stimuler, p. ex. stimulateurs cardiaques
A device and method for sigma-delta modulation may include an input signal and a plurality of integrators. The output of the integrators and a data input may be input to an adder, the sum output to be input to a quantizer to generate a quantized output signal. A reset input to the first integrator may be asserted during a first sample of the quantized output signal to reduce the signal discontinuity at the input of the first integrator, which improves the stability of the sigma-delta modulator.
A device having a co-operative scheduler of a task of an application, a timer circuit to detect a task of the application executing longer than an expected execution time for the task without interrupting execution of the task; and a record circuit to record that a task has been detected by the timer circuit executing longer than the expected execution time. A method for co-operative scheduling of tasks of an application, detecting a task of an application executing longer than an expected execution time for the task without interrupting execution of the task, and recording that an overrun has been detected.
A system having a camera to capture a scene image of a scene having an object as viewed from a perspective of an operator through a windscreen; a computer vision circuit to identify an object image corresponding to the object in the scene image captured by the camera; a marker generator circuit to generate a marker indicative of the identified object image and to determine a marker position in the operator's line of sight between the object and the operator; and a screen to display the generated marker in the marker position to appear associated with the identified object as viewed from the perspective of the operator through the windscreen. Also, methods for marking objects.
G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p. ex. des objets vidéo
G06V 10/22 - Prétraitement de l’image par la sélection d’une région spécifique contenant ou référençant une formeLocalisation ou traitement de régions spécifiques visant à guider la détection ou la reconnaissance
G06V 10/24 - Alignement, centrage, détection de l’orientation ou correction de l’image
G06V 20/20 - ScènesÉléments spécifiques à la scène dans les scènes de réalité augmentée
G06V 20/58 - Reconnaissance d’objets en mouvement ou d’obstacles, p. ex. véhicules ou piétonsReconnaissance des objets de la circulation, p. ex. signalisation routière, feux de signalisation ou routes
G06V 40/18 - Caractéristiques de l’œil, p. ex. de l’iris
86.
INTERPOSER WITH LINES HAVING PORTIONS SEPARATED BY BARRIER LAYERS
Interposers and methods for making interposers having a substrate having a surface defining a plane; a first portion of a metal line directly or indirectly supported by the substrate; a barrier layer on the first portion of the metal line; a second portion of the metal line on the first barrier layer, wherein the second portion is opposite the first portion across the barrier layer. The method includes etching a line pattern in a first portion of a metal layer through a first photoresist layer to form a first portion of a metal line, depositing a barrier layer on the first portion of the metal line, and etching a line pattern in a second portion of the metal layer through a second photoresist layer to form a second portion of a metal line wherein the second portion is opposite the first portion across the barrier layer.
A device having a co-operative scheduler of a task of an application, a timer circuit to detect a task of the application executing longer than an expected execution time for the task without interrupting execution of the task; and a record circuit to record that a task has been detected by the timer circuit executing longer than the expected execution time. A method for co-operative scheduling of tasks of an application, detecting a task of an application executing longer than an expected execution time for the task without interrupting execution of the task, and recording that an overrun has been detected.
A fully-differential amplifier is provided that includes one or more stages and a class-AB output stage. The one or more stages amplify a differential pair of input signals to produce an amplified differential pair of signals, and the class-AB output stage further amplifies the amplified differential pair of signals to produce a differential pair of output signals. The class-AB output stage includes a pair of differential outputs. For respective ones of the pair of differential outputs, the class-AB output stage includes a folded mesh of transistors and a feedback circuit. Transistors of the folded mesh of transistors form a control amplifier to regulate control inputs of the pair of output transistors, and the feedback circuit drives this control amplifier. The folded mesh of transistors biases a pair of output transistors in class-AB.
A method may include generating a first computational circuit of a current iteration of a Berlekamp algorithm, the first computational circuit to determine a Berlekamp discrepancy value at least partially based on a current Error-Locator Polynomial (ELP) and observed syndromes; and generating a second computational circuit of the current iteration of the Berlekamp algorithm, the second computational circuit to determine an intermediate value, the intermediate value useable by one or more first computational circuits of one or more subsequent iterations of the Berlekamp algorithm to determine Berlekamp discrepancy values.
H03M 13/15 - Codes cycliques, c.-à-d. décalages cycliques de mots de code produisant d'autres mots de code, p. ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
90.
SPLIT ARRAY ARCHITECTURE FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
Numerous embodiments are disclosed for splitting a physical array into multiple arrays for separate vector-by-matrix multiplication (VMM) operations. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns; and a plurality of sets of output lines, where each column contains a set of output lines; wherein each row is coupled to only one output line in the set of output lines for each column.
A fully-differential amplifier is provided that includes one or more stages and a class-AB output stage. The one or more stages amplify a differential pair of input signals to produce an amplified differential pair of signals, and the class-AB output stage further amplifies the amplified differential pair of signals to produce a differential pair of output signals. The class-AB output stage includes a pair of differential outputs. For respective ones of the pair of differential outputs, the class-AB output stage includes a folded mesh of transistors and a feedback circuit. Transistors of the folded mesh of transistors form a control amplifier to regulate control inputs of the pair of output transistors, and the feedback circuit drives this control amplifier. The folded mesh of transistors biases a pair of output transistors in class-AB.
Interposers and methods for making interposers having a substrate having a surface defining a plane; a first portion of a metal line directly or indirectly supported by the substrate; a barrier layer on the first portion of the metal line; a second portion of the metal line on the first barrier layer, wherein the second portion is opposite the first portion across the barrier layer. The method includes etching a line pattern in a first portion of a metal layer through a first photoresist layer to form a first portion of a metal line, depositing a barrier layer on the first portion of the metal line, and etching a line pattern in a second portion of the metal layer through a second photoresist layer to form a second portion of a metal line wherein the second portion is opposite the first portion across the barrier layer.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A method may include generating a first computational circuit of a current iteration of a Berlekamp algorithm, the first computational circuit to determine a Berlekamp discrepancy value at least partially based on a current Error-Locator Polynomial (ELP) and observed syndromes; and generating a second computational circuit of the current iteration of the Berlekamp algorithm, the second computational circuit to determine an intermediate value, the intermediate value useable by one or more first computational circuits of one or more subsequent iterations of the Berlekamp algorithm to determine Berlekamp discrepancy values.
H03M 13/15 - Codes cycliques, c.-à-d. décalages cycliques de mots de code produisant d'autres mots de code, p. ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
An apparatus comprises a computing device including one or more processors, multiple peripheral communication devices of different communication protocol types operably connected to the one or more processors, and a memory to store processor-executable instructions comprising an application layer protocol stack. The processor-executable instructions are such that, when executed by the one or more processors, cause the one or more processors to perform operations for respective ones of messages to be communicated to and from the computing device via respective ones of the multiple peripheral communication devices. The operations comprise communicating the respective ones of messages via the respective ones of the multiple peripheral communication devices according to a unified messaging protocol that is common to the multiple peripheral communication devices.
An apparatus comprising a computing device including one or more processors, multiple peripheral communication devices, and a memory to store processor-executable instructions. The one or more processors are to perform operations of a gateway node comprising receiving a message from a first end node via a first one of the peripheral devices, the message including a source identifier comprising a first end node identifier assigned to the first end node and a destination identifier comprising a second end node identifier assigned to a second end node; consulting a routing table at least partially responsive to receiving the message; and forwarding the message to the second end node via a second one of the peripheral devices based on an entry in the routing table, the entry including an interface identifier stored in association with the second end node identifier, the interface identifier corresponding to the second one of the peripheral devices.
In one example, a method comprises erasing at the same time a word of non-volatile memory cells in an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal, by turning on an erase gate enable transistor coupled to erase gate terminals of the word of non-volatile memory cells.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
97.
CONNECTIVITY FRAMEWORK HAVING UNIFIED STACK AND MESSAGING PROTOCOL FOR EMBEDDED SECURE CONNECTIVITY
An apparatus comprises a computing device including one or more processors, multiple peripheral communication devices of different communication protocol types operably connected to the one or more processors, and a memory to store processor-executable instructions comprising an application layer protocol stack. The processor-executable instructions are such that, when executed by the one or more processors, cause the one or more processors to perform operations for respective ones of messages to be communicated to and from the computing device via respective ones of the multiple peripheral communication devices. The operations comprise communicating the respective ones of messages via the respective ones of the multiple peripheral communication devices according to a unified messaging protocol that is common to the multiple peripheral communication devices.
H04L 67/02 - Protocoles basés sur la technologie du Web, p. ex. protocole de transfert hypertexte [HTTP]
H04L 67/10 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau
H04W 4/70 - Services pour la communication de machine à machine ou la communication de type machine
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
H04L 69/18 - Gestionnaires multi-protocoles, p. ex. dispositifs uniques capables de gérer plusieurs protocoles
H04L 51/214 - Surveillance ou traitement des messages en utilisant le transfert sélectif
H04L 67/63 - Ordonnancement ou organisation du service des demandes d'application, p. ex. demandes de transmission de données d'application en utilisant l'analyse et l'optimisation des ressources réseau requises en acheminant une demande de service en fonction du contenu ou du contexte de la demande
H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p. ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance
A method comprises receiving a message, the received message including a header and a payload; preparing a publish message at least partially based on the received message, the publish message including one or more headers and a payload, the one or more headers of the publish message including a topic, the topic comprising at least a portion of a destination identifier from the header of the received message, the payload of the publish message including the received message; and sending the publish message including the received message to a server, for communicating the received message to a computing device identified by the at least portion of the destination identifier. In one or more examples, the method is performed at a front-end server of a cloud computing service, the cloud computing service including the server adapted with a publish-subscribe messaging protocol.
H04L 67/02 - Protocoles basés sur la technologie du Web, p. ex. protocole de transfert hypertexte [HTTP]
H04L 67/10 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau
H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p. ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance
An apparatus comprising a computing device including one or more processors, multiple peripheral communication devices, and a memory to store processor-executable instructions. The one or more processors are to perform operations of a gateway node comprising receiving a message from a first end node via a first one of the peripheral devices, the message including a source identifier comprising a first end node identifier assigned to the first end node and a destination identifier comprising a second end node identifier assigned to a second end node; consulting a routing table at least partially responsive to receiving the message; and forwarding the message to the second end node via a second one of the peripheral devices based on an entry in the routing table, the entry including an interface identifier stored in association with the second end node identifier, the interface identifier corresponding to the second one of the peripheral devices.
H04L 67/10 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau
H04L 69/08 - Protocoles d’interopérabilitéConversion de protocole
H04W 4/70 - Services pour la communication de machine à machine ou la communication de type machine
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
H04L 69/18 - Gestionnaires multi-protocoles, p. ex. dispositifs uniques capables de gérer plusieurs protocoles
H04L 51/214 - Surveillance ou traitement des messages en utilisant le transfert sélectif
H04L 67/63 - Ordonnancement ou organisation du service des demandes d'application, p. ex. demandes de transmission de données d'application en utilisant l'analyse et l'optimisation des ressources réseau requises en acheminant une demande de service en fonction du contenu ou du contexte de la demande
H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p. ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance
Systems and methods for generating login passwords for a personal computer applications, comprising: providing a personal computer utility; providing a universal serial bus dongle to generate pseudo-random strings of characters via a pseudo-random character generator to be used as passwords, retrieving a first index value by identifying a uniform resource locator of an internet resource requesting a password from a non-volatile index table of the personal computer utility; sending the first index value and a first request for a password from the personal computer utility to the universal serial bus dongle; retrieving a first seed value from a non-volatile seed table using the first index value received from the personal computer utility; and generating a first pseudo-random number password via a pseudo-random character generator using the first seed value.
G06F 21/34 - Authentification de l’utilisateur impliquant l’utilisation de dispositifs externes supplémentaires, p. ex. clés électroniques ou cartes à puce intelligentes
