One or more examples relate, generally to phase and frequency error processing. An apparatus includes a phase path and a frequency path. The phase path processes phase error of communications between network nodes. The phase path includes a closed-loop feedback loop controller. The frequency path processes frequency error of the communications between the network nodes. The frequency path is separate from the phase path. A method of processing phase error and frequency error includes selecting first packets for phase processing, processing the first packets for phase error, selecting second packets for frequency processing, and processing the second packets for frequency error independently of the processing of the first packets.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 7/00 - Arrangements for synchronising receiver with transmitter
2.
SYSTEMS AND METHODS FOR TRANSPORTING CONSTANT BIT RATE CLIENT SIGNALS OVER A PACKET TRANSPORT NETWORK
A method for transporting Ethernet frame packets assembled from a constant bit rate (CBR) client stream from an ingress network node to an egress network node, each Ethernet frame packet including a payload region having a number of bytes of CBR client data from the CBR client stream determined by a client rate value of the CBR client stream. The method including synchronizing a reference clock signal and a ToD in the ingress network node to a packet-based time distribution mechanism, independently synchronizing a reference clock signal and a ToD in the egress network node to the packet-based time distribution mechanism, for an Ethernet frame packet assembling a presentation time packet including a sequence number and a presentation ToD for the Ethernet frame packet, and transmitting the Ethernet frame packets and the presentation time packet to the egress network node over the packet transport network.
A method for transporting Ethernet frame packets assembled from a constant bit rate (CBR) client stream from an ingress network node to an egress network node, each Ethernet frame packet including a payload region having a number of bytes of CBR client data from the CBR client stream determined by a client rate value of the CBR client stream. The method including synchronizing a reference clock signal and a ToD in the ingress network node to a packet-based time distribution mechanism, independently synchronizing a reference clock signal and a ToD in the egress network node to the packet-based time distribution mechanism, for an Ethernet frame packet assembling a presentation time packet including a sequence number and a presentation ToD for the Ethernet frame packet, and transmitting the Ethernet frame packets and the presentation time packet to the egress network node over the packet transport network.
H04J 3/16 - Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
4.
CIRCUIT AND METHOD FOR GENERATING TEMPERATURE-STABLE CLOCKS USING ORDINARY OSCILLATORS
A circuit for generating temperature-stable clocks including first and second crystal oscillators, an input for a reference clock source, a clock output, a first phase acquisition circuit coupled to the first and second crystal oscillators, a second phase acquisition circuit coupled to the input for the reference clock source and to the second crystal oscillator, a first DPLL coupled to the first phase acquisition circuit, a crystal oscillator variation estimator coupled to the first DPLL, a second DPLL coupled to the second phase acquisition circuit and including a phase-frequency detector having a input coupled to the second phase acquisition circuit, a loop filter, a frequency subtractor having an input coupled to the loop filter and an input coupled to the crystal oscillator variation estimator, and a DCO coupled to the frequency subtractor and driving an input of the phase-frequency detector.
A method for transferring first and second encoded client clock signals over a carrier clock domain between integrated circuits, including in a first integrated circuit encoding a phase change of the first client clock signal from a last recorded phase onto the carrier clock signal in first bit positions, encoding a phase change of the second client clock signal from a last recorded phase onto the carrier clock signal in second bit positions different from the first bit positions, and transmitting the carrier clock signal with the encoded phases of the first client clock signal and the second client clock signal over a single wire from the first integrated circuit to a second integrated circuit.
A circuit for generating temperature-stable clocks including first and second crystal oscillators, an input for a reference clock source, a clock output, a first phase acquisition circuit coupled to the first and second crystal oscillators, a second phase acquisition circuit coupled to the input for the reference clock source and to the second crystal oscillator, a first DPLL coupled to the first phase acquisition circuit, a crystal oscillator variation estimator coupled to the first DPLL, a second DPLL coupled to the second phase acquisition circuit and including a phase-frequency detector having a input coupled to the second phase acquisition circuit, a loop filter, a frequency subtractor having an input coupled to the loop filter and an input coupled to the crystal oscillator variation estimator, and a DCO coupled to the frequency subtractor and driving an input of the phase-frequency detector.
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/07 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
7.
Circuits and methods for transferring two differentially encoded client clock domains over a third carrier clock domain between integrated circuits
A method for transferring first and second encoded client clock signals over a carrier clock domain between integrated circuits, including in a first integrated circuit encoding a phase change of the first client clock signal from a last recorded phase onto the carrier clock signal in first bit positions, encoding a phase change of the second client clock signal from a last recorded phase onto the carrier clock signal in second bit positions different from the first bit positions, and transmitting the carrier clock signal with the encoded phases of the first client clock signal and the second client clock signal over a single wire from the first integrated circuit to a second integrated circuit.
H03D 3/24 - Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits
H03L 7/07 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
8.
EMBEDDED TIME OF DAY RECEIVER FOR CLOCK TRANSMISSION
In a receiver a method for extracting first and second signals from a single signal includes receiving the single signal, generating a recovered first signal by extracting and phase locking the first signal with respect to the phase of a local clock, decoding over a decode frame time the data representing an encoded phase difference at the start of the decode frame time, generating a phase difference between the first signal and the second signal as a function of data representing phase difference from a current decode frame time and data representing an encoded phase difference from an immediately prior decode frame time, subtracting the generated phase difference from the phase of the recovered first signal, and generating a recovered second signal by phase locking a signal at the second frequency at the recovered second phase.
Substrates configured to route electrical signals may include a first dielectric material and an electrically conductive material located on a first side of the first dielectric material. A second dielectric material may be located on a second, opposite side of the first dielectric material. A series of voids may be defined by the second dielectric material extending from the first dielectric material at least partially through the second dielectric material. Footprints of at least some of the voids of the series of voids may at least partially laterally overlap with the electrically conductive material.
Substrates configured to route electrical signals may include a first dielectric material and an electrically conductive material located on a first side of the first dielectric material. A second dielectric material may be located on a second, opposite side of the first dielectric material. A series of voids may be defined by the second dielectric material extending from the first dielectric material at least partially through the second dielectric material. Footprints of at least some of the voids of the series of voids may at least partially laterally overlap with the electrically conductive material.
In a receiver a method for extracting first and second signals from a single signal includes receiving the single signal, generating a recovered first signal by extracting and phase locking the first signal with respect to the phase of a local clock, decoding over a decode frame time the data representing an encoded phase difference at the start of the decode frame time, generating a phase difference between the first signal and the second signal as a function of data representing phase difference from a current decode frame time and data representing an encoded phase difference from an immediately prior decode frame time, subtracting the generated phase difference from the phase of the recovered first signal, and generating a recovered second signal by phase locking a signal at the second frequency at the recovered second phase.
H04W 4/00 - Services specially adapted for wireless communication networksFacilities therefor
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04J 3/02 - Time-division multiplex systems Details
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
An acoustic signal delay measurement apparatus constituted of: an acoustic signal input terminal; an acoustic signal output terminal; at least one echo input terminal; an adjustable tapped delay line exhibiting a plurality of taps, a first end of the tapped delay line coupled to the acoustic signal input terminal, each of the taps exhibiting a respective predetermined delay; a processor, an output of the processor coupled to a control input of the adjustable tapped delay line; and a plurality of adaptive filters, a first input of each of the plurality of adaptive filters coupled to a respective one of the at least one echo input terminal, a second input of each of the plurality of adaptive filters coupled to a respective one of the plurality of taps and an output of each of the plurality of adaptive filters coupled to a respective input of the processor, wherein the processor is arranged to determine a system delay responsive to: the amount of time it takes for one of the plurality of adaptive filters to converge; and the delay of the tap associated with the converged adaptive filter.
A clock recovery device recovers frequency and timing information from an incoming packet stream over asynchronous packet networks. A phase locked loop (PLL) block has predefined states and includes a type II PLL. One of the states involves type II PLL operation. A state machine controller for controls the transition between the predefined states in response to changes in the incoming packet stream. A controlled oscillator is responsive to the PLL block to generate an output signal.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
A compensation circuit for an oven-controlled crystal oscillator serving as a reference for a phase-locked loop in holdover mode is disclosed. A non-linear function module generates a modified aging signal that is a non-linear function of an aging signal. A first Kalman filter generates an estimate of the frequency drift of the crystal oscillator based on the temperature signal. A second Kalman filter generates an estimate of the frequency drift based on the modified aging signal. A combining and comparing module combines the estimates generated by the first and second Kalman filters and compares the estimates with detected frequency drift to produce an error signal to update the Kalman filters. In holdover mode the Kalman filters generate an error signal to correct the oscillator frequency based on updates obtained during operation of the phase-locked loop in normal mode.
A clock recovery device recovers frequency and timing information from an incoming packet stream over asynchronous packet networks. A phase locked loop (PLL) block has predefined states and includes a type II PLL. One of the states involves type II PLL operation. A state machine controller for controls the transition between the predefined states in response to changes in the incoming packet stream. A controlled oscillator is responsive to the PLL block to generate an output signal.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
An acoustic signal delay measurement apparatus constituted of: an acoustic signal input terminal; an acoustic signal output terminal; at least one echo input terminal; an adjustable tapped delay line exhibiting a plurality of taps, a first end of the tapped delay line coupled to the acoustic signal input terminal, each of the taps exhibiting a respective predetermined delay; a processor, an output of the processor coupled to a control input of the adjustable tapped delay line; and a plurality of adaptive filters, a first input of each of the plurality of adaptive filters coupled to a respective one of the at least one echo input terminal, a second input of each of the plurality of adaptive filters coupled to a respective one of the plurality of taps and an output of each of the plurality of adaptive filters coupled to a respective input of the processor, wherein the processor is arranged to determine a system delay responsive to: the amount of time it takes for one of the plurality of adaptive filters to converge; and the delay of the tap associated with the converged adaptive filter.
samp is coupled to an output of the loop filter for providing the control input to the HDCO. A second, first order linear interpolation anti-imaging filter running at said second clock rate coupled to the output of said loop filter to provide an input to said SDCO.
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
A compensation circuit for an oven-controlled crystal oscillator serving as a reference for a phase-locked loop in holdover mode is disclosed. A non-linear function module generates a modified aging signal that is a non-linear function of an aging signal. A first Kalman filter generates an estimate of the frequency drift of the crystal oscillator based on the temperature signal. A second Kalman filter generates an estimate of the frequency drift based on the modified aging signal. A combining and comparing module combines the estimates generated by the first and second Kalman filters and compares the estimates with detected frequency drift to produce an error signal to update the Kalman filters. In holdover mode the Kalman filters generate an error signal to correct the oscillator frequency based on updates obtained during operation of the phase-locked loop in normal mode.
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03L 7/14 - Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
19.
Clock synthesizer with hitless reference switching and frequency stabilization
A clock synthesizer for synthesizing an output clock locked to a selected reference clock input has a pair of phase locked loops locked to respective reference clock inputs first generating first and second frequencies. One of the frequencies is selected to control a controlled oscillator for generating an output clock. The frequency offset between the first and second frequencies at the time of switching is stored and added to the frequency controlling the controlled oscillator.
H03B 21/00 - Generation of oscillations by combining unmodulated signals of different frequencies
G06F 1/12 - Synchronisation of different clock signals
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/07 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
20.
Clock synthesizer with integral non-linear interpolation (INL) distortion compensation
sys, involves introducing a selected nominal analog delay I*dt with an actual delay of I*dt+δ at the output of the a first path with a digital controlled oscillator (DCO) and a digital-to-time converter (DTC) and a nominal digital delay I*D with an actual delay of I*D+Δ at the input of a second path with a DCO and a DTC that offsets the actual analog delay in the first path, adjusting the contents x(k) of a compensation module in the second path to align the output pulses of the first and second paths for different values of k, where k represents an interpolation point, iteratively repeating the two preceding steps for all N values of I, and averaging the contents x(k) of the compensation module to derive the compensation values to be applied to a one of the DTCs to correct for INL distortion.
H03B 21/00 - Generation of oscillations by combining unmodulated signals of different frequencies
H03K 5/1252 - Suppression or limitation of noise or interference
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
21.
Clock recovery device with switchable transient non-linear phase adjuster
A clock recovery device recovers a master clock over a packet network from incoming synchronization packets. A frequency locked loop generates a control input to a controlled oscillator, which generates an output clock. The frequency locked loop is responsive to pure offset information obtained from the incoming synchronization packets. A transient phase adjuster extracts information from the incoming synchronization packets taking into account transit delays to effect fast frequency adjustment of the control input and to provide a phase adjustment input to the frequency locked loop. A secondary phase path is selectable in response to de-activation of the transient phase adjuster to provide a phase correction to the control input derived from said pure offset information when the transient phase adjuster is inactive.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
22.
Time-to-digital converter with phase-scaled course-fine resolution
A multi-format signal driver interface has first, second and third pairs of transistors arranged in a back-to-back relationship. First transistors and second transistors of the first and second pairs of transistors form respective first and second parallel arrangement. The first transistors of the third pair of transistors are in series with the first parallel arrangement, and the second transistors of the third pair of transistors are in series with the second parallel arrangement. The sizing of the second pair of transistors is greater than the first and third pairs of transistors. A pre-driver module configures the multi-format signal driver interface to output a selected signal format. A differential amplifier is selectively couple-able to said pre-driver module to provide a common mode voltage. In each format the interface employs a current loop in the output. The transistor pairs are one-to-one loaded in each mode.
H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
H03K 19/094 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors
G06F 13/368 - Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 5/134 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices with field-effect transistors
24.
Method of speeding up output alignment in a digital phase locked loop
To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.
H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/10 - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
A method for reducing the jitter introduced into a digital signal by a non-linear processing element involves applying an input word representing the digital signal to a first signal path comprising a first non-linear processing element, and a complementary version of the input word to a second signal path comprising a second non-linear processing element. A common mode dither signal is injected into each signal path upstream of the non-linear processing elements. The outputs of the non-linear processing elements are combined to produce a common output with the common mode dither signal removed.
A method for reducing the jitter introduced into a digital signal by a non-linear processing element involves applying an input word representing the digital signal to a first signal path comprising a first non-linear processing element, and a complementary version of the input word to a second signal path comprising a second non-linear processing element. A common mode dither signal is injected into each signal path upstream of the non-linear processing elements. The outputs of the non-linear processing elements are combined to produce a common output with the common mode dither signal removed.
A master phase locked loop device is operable in association with one or more slave devices including slave digitally controlled oscillators (sDCOs), one or more digital PLL (DPLL) channels include a master digitally controlled oscillator (mDCO). A master synchronization timer generating master timing pulses to read phase and frequency information from the mDCO(s). A peripheral interface sends the read frequency and phase information to the one or more slave devices. A synchronization interface sends the master timing pulses to synchronize a replica synchronization timer in the sDCO(s) that generates slave timing pulses for use in updating the phase and frequency information received at the slave device(s).
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 13/364 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
G06F 1/08 - Clock generators with changeable or programmable clock frequency
28.
Apparatus for generating clock signals having a PLL part and synthesizer part with programmable output dividers
A clock signal generator responsive to synchronization pulses to perform actions has a phase locked loop (PLL) part including a digitally controlled oscillator (DCO) and an output driver coupled to the DCO, and a synthesizer part including a frequency synthesizer responsive to frequency and phase information from the DCO to generate a synthesized clock and programmable output dividers for generating output clocks from the synthesized clock. An interface establishes communication between the PLL part and the synthesizer part. The output driver is programmed to compute a phase offset required to align a selected output divider with the phase of the DCO and transmit the computed offset to the selected output divider over said interface for application to said selected output divider upon the occurrence of a synchronization pulse.
G06F 1/12 - Synchronisation of different clock signals
H03B 19/00 - Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
H03L 7/16 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
A low latency digital clock fault detector has an edge detector including a delay line generating pulses on edges o an incoming clock signal of a width determined by the length of said delay line. A watchdog timer with flip-flops in a pipeline configuration has a first input held at a static logic level, a second input receiving a reference clock, and a third reset input. The watchdog is being responsive to the pulses to maintain a stable output in the presence of said pulses and generate a fault indication in the absence of the pulses.
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
30.
Digital phase locked loop arrangement with master clock redundancy
Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating clock signals is selected to drive the DCO. The performance of the crystal oscillators is monitored, and the DCO is switched from being driven by a previously selected crystal oscillator to a newly selected crystal oscillator upon loss of a clock signal from the previously selected crystal oscillator or when the performance of the previously selected crystal oscillator falls below a predetermined acceptable level.
H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/07 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
H03L 7/14 - Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
31.
Method for improving the performance of synchronous serial interfaces
A slave device for exchanging data with a master device over a serial interface sends data to the master device upon receipt of a command from the master device. A controller responsive to a command byte in a receive register commences transmission of data in the transmit register under the control of a clock signal prior to reception of a complete command.
A multi-channel phase locked loop (PLL) device has a plurality of PLL channels. Each channel includes a digitally controlled oscillator (DCO) supplying an output clock, via an output divider, to a respective output pin. A first multiplexer selects any of the PLL channels for alignment. A feedback calibration PLL is responsive to a feedback signal derived from an output clock of a selected channel at the respective output pin. A delay control module is responsive to an output of the feedback calibration PLL to adjust the phase of the output clock.
H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/07 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
H03L 7/23 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H04L 5/06 - Channels characterised by the type of signal the signals being represented by different frequencies
33.
DIGITAL PHASE LOCKED LOOP ARRANGEMENT WITH MASTER CLOCK REDUNDANCY
Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating clock signals is selected to drive the DCO. The performance of the crystal oscillators is monitored, and the DCO is switched from being driven by a previously selected crystal oscillator to a newly selected crystal oscillator upon loss of a clock signal from the previously selected crystal oscillator or when the performance of the previously selected crystal oscillator falls below a predetermined acceptable level.
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H03K 5/22 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
A phase locked loop with holdover mode has a loop filter for creating an offset frequency value for a controlled oscillator. The loop filter includes a register for storing the current offset frequency value the said controlled oscillator. A first multiplexer responsive to a holdover signal selects, depending on the quality of a reference signal, the output of the loop filter or a holdover queue to control the controlled oscillator. A second multiplexer responsive to the holdover signal selects for input to the register, depending on the quality of the reference signal, the sum of an output of the register and a value derived from the current phase difference between the output of the controlled oscillator and the reference signal or a current output value of the holdover queue.
H03L 7/00 - Automatic control of frequency or phaseSynchronisation
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
35.
Hardware delay compensation in digital phase locked loop
In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.
H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/07 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
A universal input buffer has a pair of input pins. A first input of a multiplexer is coupled to the second input pin and a second input of the multiplexer receives a common mode voltage of a differential signal applied to the first pin. The multiplexer is responsive to a selection signal to select either of the first and second inputs of said multiplexer. A pair of single-input buffers have inputs coupled respectively to the first and second input pins. A first input of a first differential buffer is coupled to the first input pin, a first input of a second differential buffer is coupled to the second input pin, the second input of the first differential buffer is coupled to the output of the multiplexer, and the second input of the second differential buffer receives a common mode voltage of a differential signal applied to the second pin.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
H03K 5/13 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
A universal input buffer has a pair of input pins. A first input of a multiplexer is coupled to the second input pin and a second input of the multiplexer receives a common mode voltage of a differential signal applied to the first pin. The multiplexer is responsive to a selection signal to select either of the first and second inputs of said multiplexer. A pair of single-input buffers have inputs coupled respectively to the first and second input pins. A first input of a first differential buffer is coupled to the first input pin, a first input of a second differential buffer is coupled to the second input pin, the second input of the first differential buffer is coupled to the output of the multiplexer, and the second input of the second differential buffer receives a common mode voltage of a differential signal applied to the second pin.
A loop filter in a modified phase locked loop has a proportional path generating first output signal that is proportional to an input signal and an integral path for generating a second output signal that is an integral of the input signal. An additional functional path generates a third output signal that is a predetermined function of the input signal. The predetermined function is of the form f(s)/g(s), where f and g are polynomial functions. An adder combines the first, second, and third output signals into a common output signal.
H03D 3/24 - Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03L 7/00 - Automatic control of frequency or phaseSynchronisation
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
A precision frequency monitor provides a precision frequency monitor value (PFM) indicative of the precision of the frequency or period of an input reference signal. A first averaging module is responsive to the input reference signal to find an average frequency or period during successive predetermined time periods defining operational cycles. A second averaging module is responsive to an output of the first averaging module to average the output of the first averaging module over N operational cycles, where N is an integer, and output an updated PFM value every N operational cycles. An infinite impulse response (IIR) filter is responsive to the output of the first averaging module to filter the output of the first averaging module to output interim updated PFM values within each sequence of N operational cycles.
A multi-loop phase locked loop (PLL) system with noise attenuation has a first PLL including a local oscillator, a second PLL coupled to an output of the first PLL, and a third PLL in a feedback path between the second PLL and first PLL. A first phase comparator compares an input signal with the first feedback signal to generate a first phase error signal for the first PLL. The first phase error signal is multiplied by a scaling factor k determining the amount of noise attenuation. The third PLL has a bandwidth preferably at least ten times higher than the second PLL so that the overall transfer function of the second and third PLLs is approximately the transfer function of the second PLL. The transfer function of the third PLL is multiplied by a scaling factor 1/k. This arrangement allows the use of an uncompensated local oscillator in the first PLL. The noise generated in the uncompensated local oscillator is reduced by the attenuation factor k.
H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
H03L 7/07 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
41.
Double phase-locked loop with frequency stabilization
A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source. The second clock has a frequency close to said first clock. The first loop has a bandwidth at least an order of magnitude less than the second loop. A coupler couples the first and second phase-locked loops to provide a common output. The double phase-locked loop can be used, for example, to provide time-of-day information in wireless networks or as a fine filter for cleaning phase noise from clock signals recovered over telecom/datacom networks.
H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/07 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
H03L 7/22 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
42.
DOUBLE PHASE-LOCKED LOOP WITH FREQUENCY STABILIZATION
A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source. The second clock has a frequency close to said first clock. The first loop has a bandwidth at least an order of magnitude less than the second loop. A coupler couples the first second phase-locked loops to provide a common output. The double phase locked loop can be used, for example, to provide time-of-day information in wireless networks or as a fine filter for cleaning phase noise from clock signals recovered over telecom/datacom networks
H03L 7/07 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H04L 7/00 - Arrangements for synchronising receiver with transmitter
43.
Phase locked loop with the ability to accurately apply phase offset corrections while maintaining the loop filter characteristics
A digital phase locked loop has a phase acquisition module that outputs a first phase value representative of the phase of a reference signal expressed with respect to an internal phase reference. A phase offset write module convert a phases offset commanded from an external source into a phase offset correction value expressed with respect to the internal phase reference. A phase offset controller sums the phase offset correction values to produce a second phase value, which is added to the first phase value to produce a third phase value expressed with respect to the internal phase reference. A digital controlled oscillator (DCO) outputs a fourth phase value expressed with respect to the internal phase reference. A phase detector outputs a fifth phase value representing the difference between the third and fourth phase values. A loop filter derives a frequency offset for the DCO based on the fifth phase value. An output module generates one or more output clocks from the fourth phase value.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
A clock generator with glitchless phase adjustment having a phase locked loop with a controlled oscillator providing an output representing a phase value. One or more output modules generate one or more output clocks from the output. One or more adjustment modules add a requested phase adjustment to an output clock. The phase adjustment modules are configured to break the requested phase adjustment into smaller increments and apply the increments to an output clock generated in said at the output modules one cycle at a time.
H03D 3/24 - Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
45.
Network interface with clock recovery module on line card
A network interface for recovering timing information over packet networks has line card at the edge of a local network and a timing card separate from the line card. A physical interface time-stamps incoming timing packets based on smoothed recovered clock signals. A clock recovery module on the line card generates timing signals from the time-stamped incoming timing packets. A first phase locked generates raw clock signals from the timing signals. A second phase locked loop on the timing card generates the smoothed clock signals from said raw clock signals and applies them to the clock recovery module on the line card.
H03D 3/34 - Demodulation of angle-modulated oscillations by means of electromechanical devices
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
46.
Digital phase locked loop with reduced convergence time
A digital phase locked loop has a digital controlled oscillator, a phase comparator comparing the output signal of the digital controlled oscillator, or a signal derived therefrom, with a reference signal to produce a phase error signal. A loop filter produces a control signal for the digital controlled oscillator from an output of the phase comparator the loop filter. The loop filter has a proportional part producing a proportional component of the control signal, an integral part producing an integral component of the control signal, and an adder receiving the respective proportional and integral components at first and second inputs thereof to produce the control signal. The integral part includes a delayed feedback loop normally configured to accept the integral component at an input thereof. A first switch replaces the integral component at the input of the delayed feedback loop by the control signal in response to an activation signal. A control module produces the activation signal to activate the switch for brief periods when the phase error is non-zero and the rate of change of phase is less than a threshold value.
H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/14 - Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
47.
PHASE LOCKED LOOP WITH PRECISE PHASE AND FREQUENCY SLOPE LIMITER
Phase slope is controlled in a phase locked loop wherein a phase error signal controlling a controlled oscillator has a proportional component and an integral component, by determining whether the proportional component falls within a range bounded by upper and lower limit values. The proportional component is combined with the integral component if the proportional component falls within the range to provide the phase error signal. Otherwise, the proportional component is modified to meet a phase slope requirement while leaving the integral component unmodified. The modifed proportional component is combined with the unmodified integral component to provide the phase error signal.
H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
48.
PHASE LOCKED LOOP WITH SIMULTANEOUS LOCKING TO LOW AND HIGH FREQUENCY CLOCKS
A phase-locked loop is simultaneoulsy synchronized to high and low frequency clocks by (i) locking an output of the phase-locked loop to high-frequency reference clock, (ii) measuring at a high rate a first phase difference between the high-frequency refrerence clock and the output of the phase-locked loop, (iii) measuring at a high rate a second phase difference between a low-frequency reference clock and the output of the phase-locked loop; (iv) computing at a low rate from said first and second phase differences a third phase difference between the high-frequency and low frequency clocks; (v) combining at a low rate said third phase difference with said second phase-difference to obtain a total phase difference; and (vi) adjusting the output of the phase-locked loop at a low rate to reduce the obtained total phase difference.
H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
49.
Phase locked loop with precise phase and frequency slope limiter
Phase slope is controlled in a phase locked loop wherein a phase error signal controlling a controlled oscillator has a proportional component and an integral component, by determining whether the proportional component falls within a range bounded by upper and lower limit values. The proportional component is combined with the integral component if the proportional component falls within the range to provide the phase error signal. Otherwise, the proportional component is modified to meet a phase slope requirement while leaving the integral component unmodified. The modified proportional component is combined with the unmodified integral component to provide the phase error signal.
H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/107 - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
50.
Phase locked loop with simultaneous locking to low and high frequency clocks
A phase-locked loop to is simultaneously synchronized to high and low frequency clocks by (i) locking an output of the phase-locked loop to a high-frequency reference clock, (ii) measuring at a high rate a first phase difference between the high-frequency reference clock and the output of the phase-locked loop, (iii) measuring at a high rate a second phase difference between a low-frequency reference clock and the output of the phase-locked loop; (iv) computing at a low rate from said first and second phase differences a third phase difference between the high-frequency and low frequency clocks; (v) combining at a low rate said third phase difference with said second phase-difference to obtain a total phase difference; and (vi) adjusting the output of the phase-locked loop at a low rate to reduce the obtained total phase difference.
A phase locked loop frequency synthesizer has a controlled oscillator for generating an output signal at a desired frequency, a phase/frequency detector module for comparing a feedback signal derived from the controlled oscillator with a reference signal to generate an error signal, a loop filter for processing said at least one error signal from said phase/frequency detector module to generate a combined control signal for the controlled oscillator. The gain of the phase/frequency detector module can be adjusted, preferably by varying the pulse width and pulse cycle, to maintain the overall gain of the phase locked loop within a given range and thereby maximize signal to noise ratio.
H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/00 - Automatic control of frequency or phaseSynchronisation
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
52.
METHOD OF ADJUSTING A LOCAL CLOCK IN ASYNCHRONOUS PACKET NETWORKS
In a computer-implemented method of adjusting a local clock at a receiver in a packet network, the local clock is generated by a phase locked loop locked to a master clock with the aid of time-stamped timing packets arriving over the network from the master clock with a packet delay distribution about a nominal delay. The timing packets are filtered to adjust for the packet delay distribution. A control input for the phase locked loop is derived from the timing packets. The amount of skew in the packet delay distribution about the nominal delay is determined, and the arrival times of timing packets are then selectively modified to correct for the amount of skew in the packet delay variation distribution prior to filtering the timing packets.
A digital infinite impulse response filter has a plurality of cascaded filter elements, with each filter element defining a pole of the filter and wherein the poles lie inside a unit circle. The filter elements are configured such that the output of the last filter element is a real number. In one embodiment the poles are arranged as complex conjugate pairs. In another embodiment the real part of the output of each filter element is extracted before being passed to the next filter element. This architecture offers improved idle tone with reduced complexity.
2(t) with respective first and second linear filters having filter coefficients obtained by computing eigenfilters corresponding to data samples from the respective microphones for noise only and signal only conditions.
G10L 21/0264 - Noise filtering characterised by the type of parameter measurement, e.g. correlation techniques, zero crossing techniques or predictive techniques
A multi-mode differential termination circuit has a pair of differential input terminals for receiving external differential signals, a pair of series-connected load elements coupled between said differential input terminals, and an analog interface terminal coupled a common junction point of said load elements. A bias circuit is coupled to the common junction point of the load elements for selectively applying a bias voltage thereto in response to a digital control signal. A control input receives the digital control signal to activate the bias circuit.
H03K 3/00 - Circuits for generating electric pulsesMonostable, bistable or multistable circuits
H03B 1/00 - GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNERGENERATION OF NOISE BY SUCH CIRCUITS Details
56.
Feedforward synchronization in asynchronous packet networks
To perform timing synchronization in an asynchronous packet network, remote timestamps representative of a transmitter clock at a transmitter are received over a packet network. These are compared with local timestamps representative of the timing of a local oscillator at the receiver to produce an estimate of the offset between the transmitter clock and the local oscillator at the receiver. This estimate is then used to generate update values for a digital controlled oscillator producing the output clock at the receiver. The system operates in a feedforward configuration wherein the local oscillator at the receiver serves as one input to the offset estimator.
In a method of recovering timing information over packet networks, a receiver receives a plurality of packet streams over different paths from the same source. The raw delays experienced by the timing packets for each stream are filtered to provide a filtered delay for each stream. The filtered delays are weighted based on the quality of each stream, and the weighted filtered delays are then combined to form an aggregate delay estimate. Frequency adjustments for a local clock at the receiver are derived from the aggregate delay estimate.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
In a method of recovering timing information over packet networks, raw network delays are measured using timing packets sent between a transmitter and receiver. The expected delay is predicted using a minimum statistics adaptive filter to track local minima of measured time delays over a smoothing window. Only those incoming timing packets which meet a particular criterion relative to the expected delay within a smoothing window are selected, and a local clock is adjusted based on the measured timing delays from the selected timing packets.
In a method of recovering timing information over a packet network at a local receiver, timing information is received at intervals timing from a remote source and compared with a locally generated clock signal to generate an input signal y(k) subject to noise representative of the phase difference between the source clock signal and the local receiver clock signal. The input signal is applied to a state feedback controller, preferably including a Kalman filter, to generate a control signal with reduced noise. The control signal is used to control an oscillator in a way so as to reduce the phase difference and generate a slave clock.
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