Microsemi Semiconductor ULC

Canada

 
Total IP 60
Total IP Rank # 22,663
IP Activity Score 1.8/5.0    11
IP Activity Rank # 80,998
Dominant Nice Class Scientific and electric apparatu...

Patents

Trademarks

43 1
0 0
16 0
0
 
Last Patent 2022 - Phase and frequency error proces...
First Patent 2009 - Phase locked loop with optimal s...
Last Trademark 2001 - ZARLINK
First Trademark 2001 - ZARLINK

Industry (Nice Classification)

Latest Inventions, Goods, Services

2022 Invention Phase and frequency error processing. One or more examples relate, generally to phase and freque...
2020 Invention Systems and methods for transporting constant bit rate client signals over a packet transport net...
Invention Circuit and method for generating temperature-stable clocks using ordinary oscillators. A circuit...
Invention Circuits and methods for transferring two differentially encoded client clock domains over a thir...
2019 Invention Embedded time of day receiver for clock transmission. In a receiver a method for extracting first...
Invention Techniques for routing electrical signals through electrical components and related methods. Subs...
Invention Acoustic delay estimation. An acoustic signal delay measurement apparatus constituted of: an acou...
Invention Clock recovery device with state machine controller. A clock recovery device recovers frequency a...
Invention Non-linear oven-controlled crystal oscillator compensation circuit. A compensation circuit for an...
2018 Invention Digital phase locked loop clock synthesizer with image cancellation. samp is coupled to an output...
Invention Clock synthesizer with hitless reference switching and frequency stabilization. A clock synthesiz...
2017 Invention Clock synthesizer with integral non-linear interpolation (inl) distortion compensation. sys, invo...
Invention Time-to-digital converter with phase-scaled course-fine resolution. Tot. The TDC uses simpler enc...
Invention Clock recovery device with switchable transient non-linear phase adjuster. A clock recovery devic...
Invention Multi-format driver interface. A multi-format signal driver interface has first, second and third...
Invention Method of speeding up output alignment in a digital phase locked loop. To speed up output clock a...
2016 Invention Noise reduction in non-linear signal processing. A method for reducing the jitter introduced into...
Invention Apparatus for generating clock signals having a pll part and synthesizer part with programmable o...
Invention Pll system with master and slave devices. A master phase locked loop device is operable in associ...
Invention Phase locked loop with accurate alignment among output clocks. A multi-channel phase locked loop ...
Invention Universal input buffer. A universal input buffer has a pair of input pins. A first input of a mul...
Invention Method for improving the performance of synchronous serial interfaces. A slave device for exchang...
Invention Low latency digital clock fault detector. A low latency digital clock fault detector has an edge ...
Invention Digital phase locked loop arrangement with master clock redundancy. Master clock redundancy is pr...
Invention Phase locked loop with jump-free holdover mode. A phase locked loop with holdover mode has a loop...
Invention Hardware delay compensation in digital phase locked loop. In a digital phase locked loop comprisi...
2015 Invention Phase locked loop with modified loop filter. A loop filter in a modified phase locked loop has a ...
Invention Precision frequency monitor. A precision frequency monitor provides a precision frequency monitor...
Invention Crystal oscillator noise compensation method for a multi-loop pll. A multi-loop phase locked loop...
Invention Phase locked loop with the ability to accurately apply phase offset corrections while maintaining...
Invention Pll glitchless phase adjustment system. A clock generator with glitchless phase adjustment having...
Invention Double phase-locked loop with frequency stabilization. A double phase-locked has a first phase-lo...
Invention Network interface with clock recovery module on line card. A network interface for recovering tim...
2014 Invention Digital phase locked loop with reduced convergence time. A digital phase locked loop has a digita...
Invention Phase locked loop with precise phase and frequency slope limiter. Phase slope is controlled in a ...
Invention Phase locked loop with simultaneous locking to low and high frequency clocks. A phase-locked loop...
2001 G/S Semiconductors and computer programs for testing, analyzing, and operating semiconductors Printed...