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1.

METHOD AND APPARATUS FOR SUPPORTING DISTRIBUTED GRAPHICS AND COMPUTE ENGINES AND SYNCHRONIZATION IN MULTI-DIELET PARALLEL PROCESSOR ARCHITECTURES -- MEMORY BARRIERS

      
Application Number 18606960
Status Pending
Filing Date 2024-03-15
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Milne, Timothy Ian
  • Kulkarni, Vaishali
  • Bhattacharya, Debajit
  • Maurya, Ashish Kumar
  • Tong, Tong
  • Ayachit, Vadiraj Alias Abhay
  • Wheeler, Chase Caldwell

Abstract

This disclosure describes supporting distributed graphics and compute engines in a multi-dielet processor, such as, for example, a multi-dielet graphics processing unit (GPU), architectures and synchronization in such architectures. Each multi-dielet processor includes a hardware-implemented remapping capability and/or a hardware-implemented memory barrier capability.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 13/18 - Handling requests for interconnection or transfer for access to memory bus with priority control

2.

TECHNIQUES FOR ROBOT CONTROL USING NEURAL IMPLICIT VALUE FUNCTIONS

      
Application Number 19219934
Status Pending
Filing Date 2025-05-27
First Publication Date 2025-09-18
Owner NVIDIA CORPORATION (USA)
Inventor
  • Murali, Adithyavairavan
  • Sundaralingam, Balakumar
  • Chen, Yun-Chun
  • Fox, Dieter
  • Garg, Animesh

Abstract

One embodiment of a method for controlling a robot includes receiving sensor data associated with an environment that includes an object; applying a machine learning model to a portion of the sensor data associated with the object and one or more trajectories of motion of the robot to determine one or more path lengths of the one or more trajectories; generating a new trajectory of motion of the robot based on the one or more trajectories and the one or more path lengths; and causing the robot to perform one or more movements based on the new trajectory.

IPC Classes  ?

3.

LANGUAGE MODEL-BASED VIRTUAL ASSISTANTS FOR CONTENT STREAMING SYSTEMS AND APPLICATIONS

      
Application Number 18606278
Status Pending
Filing Date 2024-03-15
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Paul, Jason
  • Siman, Guillermo
  • Mawdsley, Jason
  • Prasad, Nikhil
  • Shekhar, Deep
  • Lin, Henry Cheng-Han
  • Rangan, Ram
  • Patney, Anjul
  • Kumar, Ritesh
  • Schneider, Seth

Abstract

In various examples, providing virtual assistants for content streaming systems and applications is described herein. For instance, systems and methods are disclosed that use a virtual assistant associated with an application, such as a gaming application, to at least process queries received from a user in order to provide the user with information on how to perform various tasks associated with the application. In some examples, to determine the output information, data associated with the application is processed in order to determine state information describing a current state of the application. Additionally, the query, the state information, and/or additional information may be used to determine contextual information related to the query. One or more language models may then process the query and/or the information to determine the output information associated with the query. The output information may then be provided using various techniques, such as text, graphics, and/or audio.

IPC Classes  ?

4.

POLICY PREDICTION-BASED MOTION PLANNER FOR AUTONOMOUS SYSTEMS AND APPLICATIONS

      
Application Number 18604078
Status Pending
Filing Date 2024-03-13
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Chen, Yuxiao
  • Tonkens, Sander
  • Schmerling, Edward
  • Pavone, Marco

Abstract

In various examples, policy prediction-based motion planner systems and methods for autonomous and semi-autonomous systems and applications are provided. A scenario tree structure may be generated that represents potential behaviors of one or more peripheral agents based on perception data of a scene within which an ego vehicle operates. A joint MPC algorithm may optimize the motion of an ego vehicle within the context of the scenario tree structure to produce a policy tree structure. An MPC policy prediction model may be trained to predict the policy tree structures that a joint MPC algorithm would produce, given a set of environmental perception data. An ego vehicle may comprise a trained MPC policy prediction model that receives perception data, and based on that input predicts a policy tree structure that may be used to define a motion policy for navigating the ego vehicle through the scene.

IPC Classes  ?

  • B60W 60/00 - Drive control systems specially adapted for autonomous road vehicles

5.

FUSED VECTOR STORE FOR EFFICIENT RETRIEVAL-AUGMENTED AI PROCESSING

      
Application Number 18674734
Status Pending
Filing Date 2024-05-24
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor Angilly, Ryan

Abstract

In various examples, systems and techniques are provided that encapsulate indexing and query operations into an application programming interface (API) that automates and coordinates calls to various local and cloud-based services. When a user has a document(s) to add to a retrieval augmented generation (RAG) database, the API may offer to the user multiple document processing pipelines (DPPs) having pre-set indexing configurations. Similarly, when a user query is received, the API may generate calls to implement query processing that does not require the user to manually configure retrieval and processing of the embeddings. The API may further implement calls that locate a relevant embedding store and provide the stored embeddings, together with the query embeddings, to a search engine that identifies the most relevant matches. The API may then access the embedding-to-text indexing and identify relevant text segments and documents to a prompt generator.

IPC Classes  ?

6.

DEEP-LEARNING BASED-ENVIRONMENTAL MODELING FOR VEHICLE ENVIRONMENT VISUALIZATION

      
Application Number 18680174
Status Pending
Filing Date 2024-05-31
First Publication Date 2025-09-18
Owner NVIDIA CORPORATION (USA)
Inventor
  • Arar, Nuri Murat
  • Avadhanam, Niranjan
  • Badki, Abhishek Haridas
  • Su, Hang
  • Kautz, Jan
  • Gallo, Orazio

Abstract

In various examples, an environment visualization pipeline may determine whether to generate or otherwise enable a visualization using an environmental modeling pipeline that models an environment as a 3D bowl or using an environmental modeling pipeline that models the environment using some other 3D representation, such as a detected 3D surface topology. The determination may made based on various factors, such as ego-machine state, (e.g., one or more detected features indicative of a designated operational scenario, proximity to a detected object, speed of ego-machine, etc.), estimated image quality of a corresponding environment visualization, and/or other factors. Accordingly, an environment around an ego-machine, such as a vehicle, robot, and/or other type of object, may be visualized in systems such as parking visualization systems, Surround View Systems, and/or others.

IPC Classes  ?

  • B60W 50/14 - Means for informing the driver, warning the driver or prompting a driver intervention
  • G06T 7/50 - Depth or shape recovery
  • G06T 17/20 - Wire-frame description, e.g. polygonalisation or tessellation
  • G06V 10/26 - Segmentation of patterns in the image fieldCutting or merging of image elements to establish the pattern region, e.g. clustering-based techniquesDetection of occlusion
  • G06V 10/98 - Detection or correction of errors, e.g. by rescanning the pattern or by human interventionEvaluation of the quality of the acquired patterns
  • G06V 20/56 - Context or environment of the image exterior to a vehicle by using sensors mounted on the vehicle

7.

FEATURE GENERATION OF DASHED LINE COMPONENTS FOR AUTONOMOUS SYSTEMS AND APPLICATIONS

      
Application Number 18606899
Status Pending
Filing Date 2024-03-15
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Zhang, Yu
  • Gupta, Alok Kumar

Abstract

In various examples, systems and methods described herein may determine individual components of a dashed line based at least on identifying relationships across different portions of the dashed line. For instance, input data representing a road surface may be analyzed and a representation associated with a dashed line may be determined. In some instances, the representation may be generated based at least on intensity values associated with points corresponding to the input data. Then, based at least on the representation, information associated with one or more components of the dashed line may be determined. For instance, the representation may be indicative of the relationships across the different portions of the dashed line, and these relationships may be used to determine the information associated with the one or more components of the dashed line.

IPC Classes  ?

  • G06V 20/56 - Context or environment of the image exterior to a vehicle by using sensors mounted on the vehicle
  • G01S 17/89 - Lidar systems, specially adapted for specific applications for mapping or imaging
  • G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersectionsConnectivity analysis, e.g. of connected components
  • G06V 10/77 - Processing image or video features in feature spacesArrangements for image or video recognition or understanding using pattern recognition or machine learning using data integration or data reduction, e.g. principal component analysis [PCA] or independent component analysis [ICA] or self-organising maps [SOM]Blind source separation
  • G06V 10/88 - Image or video recognition using optical means, e.g. reference filters, holographic masks, frequency domain filters or spatial domain filters

8.

Universal Scale Metadata Layout for Matrix Multiply and Add (MMA)

      
Application Number 18606691
Status Pending
Filing Date 2024-03-15
First Publication Date 2025-09-18
Owner NVDIA Corporation (USA)
Inventor
  • Tyrlik, Maciej
  • Sembrant, Andreas
  • Tirumala, Ajay
  • Stiffler, Daniel
  • Patel, Manan

Abstract

This disclosure describes efficiently performing matrix multiply and add (MMA) operations using narrow operands. Narrow operand size (e.g., 8 bit/6 bit/4 bit operand) MMA operations utilize scale metadata in order to improve accuracy of the MMA operation. An efficient layout for scale metadata in narrow operand size MMA operations and its use are described. The proposed layout provides for efficient storing and efficient use of scale metadata.

IPC Classes  ?

9.

EFFICIENT EXECUTION OF ATOMIC INSTRUCTIONS FOR SINGLE INSTRUCTION, MULTIPLE THREAD (SIMT) ARCHITECTURES

      
Application Number 18604201
Status Pending
Filing Date 2024-03-13
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Gadre, Shirish
  • Johnson, Daniel Robert
  • Paranjape, Omkar
  • Rao, Poornachandra B.
  • Kenny, Matthew Alan

Abstract

a first set of threads having a same address corresponding to the shared memory is identified from a group of active threads associated with an instruction to update a shared memory. A first thread of the first set of threads is selected. The instruction is executed for the first thread using the same address to access the shared memory. Attempts to execute the instruction for remaining threads of the first set of threads are delayed until after the first thread is executed and until at least one of the remaining threads of the first set of threads is not guaranteed to fail execution of the instruction.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

10.

ENVIRONMENTAL TEXT PERCEPTION AND PARKING EVALUATION USING VISION LANGUAGE MODELS

      
Application Number 18791977
Status Pending
Filing Date 2024-08-01
First Publication Date 2025-09-18
Owner NVIDIA CORPORATION (USA)
Inventor
  • Pathak, Niral Lalit
  • Neerukonda, Chandana
  • Shetty, Rajath Bellipady
  • Avadhanam, Niranjan
  • Kumar, Ratin

Abstract

Some embodiments relate to environmental text perception using vision language models (VLMs). For example, an Advanced Driver Assistance System (ADAS) may identify candidate parking spaces, and a VLM may be used to evaluate parking signs and determine whether it is permissible and/or the cost to park in a candidate parking space. For example, frames from corresponding (e.g., front-facing, repeater, side pillar) camera(s) may be evaluated for corresponding parking signs (e.g., using a sign recognition DNN or a VLM). If a parking sign is detected, the image of the sign may be provided as input to a VLM with a textual prompt instructing the VLM to determine whether it is permissible to park at a corresponding location (and if so, the cost). The generated response may be provided to the ADAS to confirm or invalidate the candidate parking space, and a representation of the results may be provided to the driver.

IPC Classes  ?

  • B60W 50/14 - Means for informing the driver, warning the driver or prompting a driver intervention
  • G06Q 30/0283 - Price estimation or determination
  • G06V 20/58 - Recognition of moving objects or obstacles, e.g. vehicles or pedestriansRecognition of traffic objects, e.g. traffic signs, traffic lights or roads

11.

HARDWARE-BASED INTER-PROCESSING COMMUNICATION NETWORKS FOR MANAGED DEVICES

      
Application Number 18606893
Status Pending
Filing Date 2024-03-15
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Sampath, Varun
  • Basak, Abhishek
  • Jain, Rahul
  • Potnuru, Durga Prasad
  • Singh, Akash

Abstract

Disclosed are apparatuses, systems, and techniques that implement software-agnostic transport of messages to, from, and within managed devices. In one embodiment, a managed device has an intra-device network including a plurality of units, each unit associated with a unit controller. The managed device further includes a hub controller that receives data packet(s) jointly carrying a message from an external host. The controller identifies that the one or more first data packets are associated with a given unit and forwards the data packet(s) to the corresponding unit controller. The unit controller extracts the message from the data packet(s) and stores the message in a memory associated with the unit controller.

IPC Classes  ?

12.

DRIVER AND OCCUPANT MONITORING USING VISION LANGUAGE MODELS

      
Application Number 18791952
Status Pending
Filing Date 2024-08-01
First Publication Date 2025-09-18
Owner NVIDIA CORPORATION (USA)
Inventor
  • Neerukonda, Chandana
  • Pathak, Niral Lalit
  • Shetty, Rajath Bellipady
  • Kumar, Ratin
  • Avadhanam, Niranjan

Abstract

Some embodiments relate to driver or occupant monitoring using vision language models (VLMs). Any number of DNNs in a detection pipeline may be replaced with a VLM, and the VLM may be prompted to determine whether a corresponding feature is present in an image or sampled frames from a video. To facilitate using the VLM(s) to control one or more downstream actions, the VLM(s) may be prompted using structured inputs, and a designated output format for a corresponding structured output may be enforced in any suitable manner. As such, any number of VLMs may be used to perform any number of driver and/or occupant monitoring tasks (e.g., driver drowsiness detection, driver distraction detection, driver or occupant out-of-position detection, driver or occupant identification, seatbelt usage detection, occupant presence detection, occupant classification, child presence detection, gesture recognition, occlusion detection, and/or others).

IPC Classes  ?

  • G06V 20/59 - Context or environment of the image inside of a vehicle, e.g. relating to seat occupancy, driver state or inner lighting conditions
  • B60W 50/14 - Means for informing the driver, warning the driver or prompting a driver intervention
  • G06V 40/20 - Movements or behaviour, e.g. gesture recognition

13.

MATERIAL AGNOSTIC DENOISING

      
Application Number 18912355
Status Pending
Filing Date 2024-10-10
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Schied, Christoph Hermann
  • Keller, Alexander Georg

Abstract

In photorealistic image synthesis by light transport simulation, the colors of each pixel are computed by evaluating an integral of a high-dimensional function. In practice, the pixel colors are estimated by using Monte Carlo and quasi-Monte Carlo methods to sample light transport paths that connect light sources and cameras and summing up the contributions to evaluate the integral. Because of the sampling, images appear noisy when the number of samples is insufficient. Due to the lack of information, denoising the shaded images introduces artifacts, for example, blurred the images. Denoising before material shading enables real-time light transport simulation, producing high visual quality even for low sampling rates (avoiding the blurred shading). The light transport integral operator is evaluated by a neural network, requiring data from only a single frame.

IPC Classes  ?

14.

HYBRID QUANTUM-CLASSICAL SYSTEM FOR ENHANCED COMBINATORIAL OPTIMIZATION

      
Application Number 18602246
Status Pending
Filing Date 2024-03-12
First Publication Date 2025-09-18
Owner NVIDIA CORPORATION (USA)
Inventor
  • Seifoory, Hossein
  • Mentovich, Elad

Abstract

Systems, computer program products, and methods are described for a hybrid quantum-classical system for enhanced combinatorial optimization. An example system segments a received task into multiple sub-tasks. For each sub-task, the system accesses a database of pre-computed solutions through the classical computing unit to identify a suitable pre-computed solution. In scenarios where a pre-computed solution is not available for a sub-task, the classical computing unit transmits this sub-task to a quantum computing unit. The computing unit, utilizing a quantum optimization algorithm, computes a solution for the sub-task. This solution is then relayed back to the classical computing unit. The classical computing unit then implements each identified pre-computed and newly computed solution on the combinatorial optimization task.

IPC Classes  ?

  • G06N 10/60 - Quantum algorithms, e.g. based on quantum optimisation, or quantum Fourier or Hadamard transforms

15.

TECHNIQUES FOR ROBOT CONTROL USING STUDENT ACTOR MODELS

      
Application Number 18940682
Status Pending
Filing Date 2024-11-07
First Publication Date 2025-09-18
Owner NVIDIA CORPORATION (USA)
Inventor
  • Akinola, Iretiayo
  • Carius, Jan
  • Fox, Dieter
  • Narang, Yashraj Shyam
  • Xu, Jie

Abstract

Techniques for training a machine learning model to control a robot include performing, based on a first set of data, one or more training operations to generate a first trained machine learning model to control a robot and a trained evaluation model, and performing, based on a second set of data and first feedback generated by the trained evaluation model, one or more training operations to generate a second trained machine learning model to control the robot, where the second set of data is associated with a different set of sensor modalities than the first set of data.

IPC Classes  ?

  • B25J 9/16 - Programme controls
  • B25J 13/08 - Controls for manipulators by means of sensing devices, e.g. viewing or touching devices

16.

Synchronizing Memory Management Units in Multi-Dielet Processor Architectures

      
Application Number 18655693
Status Pending
Filing Date 2024-05-06
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Hossain, Hemayet
  • Deming, James
  • Wong, Raymond
  • Carlton, Stewart
  • Gandhi, Wishwesh
  • Patel, Piyush

Abstract

This disclosure describes supporting distributed graphics and compute engines in a multi-dielet parallel processing system, such as, for example, a multi-dielet graphics processing unit (GPU), architectures and synchronizing memory management in such architectures. Respective dielets each has a memory management unit (MMU). The processing of at least one memory-related message type is serialized by a designated MMU for messages originated at any dielet, and the processing of at least some memory-related message types is performed locally on the originating dielets.

IPC Classes  ?

  • G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
  • G06F 12/1009 - Address translation using page tables, e.g. page table structures

17.

GRAPHICAL FIDUCIAL MARKER IDENTIFICATION

      
Application Number 19225463
Status Pending
Filing Date 2025-06-02
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Milovanovic, Vukasin
  • D'Souza, Joy
  • Pereira, Rochelle
  • Min, Jianyuan

Abstract

In various examples, image data may be received that represents an image. Corner detection may be used to identify pixels that may be candidate corner points. The image data may be converted from a higher dimensional color space to a converted image in a lower dimensional color space, and boundaries may be identified within the converted image. A set of the candidate corner points may be determined that are within a threshold distance to one of the boundaries, and the set of the candidate corner points may be analyzed to determine a subset of the candidate corner points representative of corners of polygons. Using the subset of the candidate corner points, one or more polygons may be identified, and a filter may be applied to the polygons to identify a polygon as corresponding to a fiducial marker boundary of a fiducial marker.

IPC Classes  ?

  • G06T 7/13 - Edge detection
  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
  • G06T 19/00 - Manipulating 3D models or images for computer graphics

18.

THREE-DIMENSIONAL MULTI-CAMERA PERCEPTION SYSTEMS AND APPLICATIONS

      
Application Number 18898120
Status Pending
Filing Date 2024-09-26
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Tang, Zheng
  • Wang, Yizhou
  • Cetintas, Ibrahim Orcun
  • Pusegaonkar, Sameer Satish
  • Aiyer, Ganapathy Seshadri Cadungude
  • Wang, Shuo
  • Agrawal, Akshay
  • Biswas, Sujit
  • Meinhardt, Tim
  • Leal Taixe, Laura

Abstract

In various examples, three-dimensional multi-camera perception systems and applications is described herein. Systems and methods are disclosed herein that process image data generated using multiple cameras located throughout an environment in order to directly determine three-dimensional (3D) information associated with objects located within the environment. For instance, the image data may be processed using one or more feature extractors (e.g., one or more backbones) to determine multi-view image features associated with images represented by the image data. These multi-view image features, along with calibration data associated with the cameras, may then be processed using one or more spatio-temporal transformers (e.g., one or more spatial encoders, one or more temporal encoders, etc.) in order to determine 3D locations of objects within the environment.

IPC Classes  ?

  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
  • G06T 7/80 - Analysis of captured images to determine intrinsic or extrinsic camera parameters, i.e. camera calibration

19.

DEPTH-BASED VEHICLE ENVIRONMENT VISUALIZATION USING GENERATIVE AI

      
Application Number 18670416
Status Pending
Filing Date 2024-05-21
First Publication Date 2025-09-18
Owner NVIDIA CORPORATION (USA)
Inventor
  • Badki, Abhishek Haridas
  • Su, Hang
  • Kautz, Jan
  • Gallo, Orazio

Abstract

In various examples, systems and methods are disclosed relating to geometry estimation and dynamic object rendering for vehicle environment visualization. In embodiments, the environment surrounding an ego-machine may be visualized by extracting one or more depth maps from image data, converting the depth map(s) into a 3D surface topology of the surrounding environment, and/or texturizing the detected 3D surface topology with image data. Dynamic objects such as moving vehicles or pedestrians may be detected and masked from a first pass of texturization. Rigid dynamic objects may be visualized by warping corresponding depth values using corresponding trajectories, inserting or fusing the resulting warped 3D representation of each such object into the (e.g., texturized) 3D surface topology, and texturizing the warped 3D representation of each object using corresponding image data. Non-rigid dynamic objects may be represented as flat 2D surfaces and texturized with corresponding image data.

IPC Classes  ?

  • G06T 17/00 - 3D modelling for computer graphics
  • G06T 7/20 - Analysis of motion
  • G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects

20.

THREE-DIMENSIONAL (3D) HEAD POSE PREDICTION FOR AUTOMOTIVE SYSTEMS AND APPLICATIONS

      
Application Number 18603936
Status Pending
Filing Date 2024-03-13
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Sah, Shagan
  • Puri, Nishant
  • Sivaraman, Sakthivel
  • Kim, Dae Jin
  • Shetty, Rajath

Abstract

In various examples, head pose prediction for automotive occupant sensing systems and applications is presented. The systems and methods described herein provide for a machine learning model trained using a dataset that comprises ground truth head pose data computed using a registered head model of a training subject. While operating a vehicle, one or more cameras and a depth sensor capture synchronized images of the training subject. To compute a ground truth 3D head pose, angular deviations between a 3D point cloud and the registered head model may be computed to obtain a 3D ground truth head pose measurement. Using an extrinsic calibration transform, the head pose measurement may be mapped into the sensor coordinate frame. Training samples may be produced for training the machine learning model that comprise an optical image frame and the head pose measurement transposed into the frame of reference for that optical image frame.

IPC Classes  ?

  • G06T 7/70 - Determining position or orientation of objects or cameras
  • G06T 7/50 - Depth or shape recovery

21.

SCHEDULING AND PRIORITIZATION OF VISION LANGUAGE MODEL INFERENCE REQUESTS

      
Application Number 18792006
Status Pending
Filing Date 2024-08-01
First Publication Date 2025-09-18
Owner NVIDIA CORPORATION (USA)
Inventor
  • Pathak, Niral Lalit
  • Neerukonda, Chandana
  • Shetty, Rajath Bellipady
  • Avadhanam, Niranjan
  • Kumar, Ratin

Abstract

In some embodiments, the same vision language model (VLM) may be used to support different types of detection tasks (e.g., one foundational VLM supporting some or all detection tasks performed by an ego-machine, one VLM for interior sensing tasks and one for exterior sensing tasks, etc.), and an inference scheduler may be used to serve or handle inference requests for the VLM(s) to perform the different tasks. In some embodiments, the scheduler prioritizes inference requests based on safety (e.g., prioritizing inference requests to perform ADAS tasks such as pedestrian detection, bicycle detection, or trajectory planning over requests to perform driver or occupant monitoring tasks, prioritizing exterior sensing tasks over interior sensing tasks, etc.). As such, the scheduler may queue, manage, distribute inference requests from different detection applications to the VLM(s), and receive and return responses to corresponding detection task managers.

IPC Classes  ?

  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
  • G06V 10/776 - ValidationPerformance evaluation

22.

MACHINE LEARNING MODELS FOR RECONSTRUCTION AND SYNTHESIS OF DYNAMIC SCENES FROM VIDEO

      
Application Number 18602834
Status Pending
Filing Date 2024-03-12
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Acuna Marrero, David Jesus
  • Litany, Or
  • Kar, Amlan
  • Gojcic, Zan
  • Fidler, Sanja

Abstract

In various examples, systems and methods are disclosed relating to reconstruction and synthesis of dynamic scenes from video, such as to generate a four-dimensional (4D) representation of one or more scenes based on one or more videos (e.g., two-dimensional (2D) videos) of the one or more scenes. A system may determine, using a neural network and based on a three-dimensional (3D) representation of one or more scenes, a 4D representation of the one or more scenes, the 3D representation generated by a featurizer using a plurality of first image frames from video data of the one or more scenes. The system may determine, from the 4D representation, a target image having a target pose and a target time.

IPC Classes  ?

  • G06T 17/00 - 3D modelling for computer graphics
  • G06T 7/70 - Determining position or orientation of objects or cameras
  • G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersectionsConnectivity analysis, e.g. of connected components

23.

METHOD FOR FORWARD PROGRESS AND PROGRAMMABLE TIMEOUTS OF TREE TRAVERSAL MECHANISMS IN HARDWARE

      
Application Number 19223551
Status Pending
Filing Date 2025-05-30
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Muthler, Greg
  • Babich, Jr., Ronald Charles
  • Newhall, Jr., William Parsons
  • Nelson, Peter
  • Robertson, James
  • Burgess, John

Abstract

In a ray tracer, to prevent any long-running query from hanging the graphics processing unit, a traversal coprocessor provides a preemption mechanism that will allow rays to stop processing or time out early. The example non-limiting implementations described herein provide such a preemption mechanism, including a forward progress guarantee, and additional programmable timeout options that can be time or cycle based. Those programmable options provide a means for quality of service timing guarantees for applications such as virtual reality (VR) that have strict timing requirements.

IPC Classes  ?

  • G06T 15/06 - Ray-tracing
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06N 5/046 - Forward inferencingProduction systems
  • G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
  • G06T 1/60 - Memory management
  • G06T 17/00 - 3D modelling for computer graphics

24.

LANE GRAPH GENERATION USING NEURAL NETWORKS

      
Application Number 18603078
Status Pending
Filing Date 2024-03-12
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Deshmukh, Amala Sanjay
  • Nowruzi, Farzan
  • Cugunovs, Vadim
  • Grabner, Michael

Abstract

In various examples, various types of sensor data from multiple ego-machines are used to infer lanes and/or generate lane graphs for use in autonomous systems and applications. In some embodiments, one or more DNNs may be used to infer lane data indicating a representation of a lane shape using sensor data from various vehicles to represent a 3D environment. The inferred lane data may include cross-section indicators that indicate cross-sections of a lane and/or connection indicators that indicate a lane channel connecting two locations (e.g., two lane portions). The inferred lane data may be used to generate a lane graph that represents lanes on a road and, in some cases, lane dividers (e.g., polyline represented as a solid line, a dashed line, a double line, etc.). A lane graph may be used, for example, to model the environment around a vehicle, facilitate localization, provide guidance for autonomous driving, etc.

IPC Classes  ?

25.

LANE INFERENCE AND LANE GRAPH GENERATION FOR AUTONOMOUS SYSTEMS AND APPLICATIONS

      
Application Number 18603070
Status Pending
Filing Date 2024-03-12
First Publication Date 2025-09-18
Owner NVIDIA CORPORATION (USA)
Inventor
  • Deshmukh, Amala Sanjay
  • Nowruzi, Farzan
  • Cugonovs, Vadim
  • Grabner, Michael

Abstract

In various examples, various types of sensor data from multiple ego-machines are used to infer lanes and/or generate lane graphs for use in autonomous systems and applications. In some embodiments, one or more DNNs may be used to infer lane data indicating a representation of a lane shape using sensor data from various vehicles to represent a 3D environment. The inferred lane data may include cross-section indicators that indicate cross-sections of a lane and/or connection indicators that indicate a lane channel connecting two locations (e.g., two lane portions). The inferred lane data may be used to generate a lane graph that represents lanes on a road and, in some cases, lane dividers (e.g., polyline represented as a solid line, a dashed line, a double line, etc.). A lane graph may be used, for example, to model the environment around a vehicle, facilitate localization, provide guidance for autonomous driving, etc.

IPC Classes  ?

  • G06T 11/20 - Drawing from basic elements, e.g. lines or circles
  • G06T 7/11 - Region-based segmentation
  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
  • G06T 9/00 - Image coding

26.

Distributed Multi-Client Control Of Performance Telemetry Subsystem In A Multi-Die Chip

      
Application Number 18747404
Status Pending
Filing Date 2024-06-18
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Vaidya, Pranav
  • Kamalapurkar, Shounak
  • Smith, Gregory
  • Ranade, Abhijat Manohar
  • Ogletree, Thomas
  • Mcdonald, Timothy J.
  • Menezes, Alan
  • Joshi, Aditya
  • Ramachandran, Madhumitha
  • Issakov, Igor

Abstract

Computing system performance monitors provide on-chip control, selection, collection, coalescing and communication of behavior and other processing-indicating data of high performance single- and multi-die computing and processing systems, such as for use in multi-chip-module and/or multi-instanced graphics processing units (GPUs) and/or systems-on-chips (SOCs). Commands and data records can be forwarded between modules to abstract the processing system from profilers and other data report consumers. Quality of Service and security isolation for different command and data report streams is maintained.

IPC Classes  ?

  • H04L 45/00 - Routing or path finding of packets in data switching networks
  • H04L 45/74 - Address processing for routing
  • H04L 45/745 - Address table lookupAddress filtering

27.

MULTI-BENCHMARK PLATFORMS FOR EVALUATION OF MACHINE LEARNING MODELS

      
Application Number 19081997
Status Pending
Filing Date 2025-03-17
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Ficek, Aleksander
  • Peters Long, Eileen Margaret
  • Srihari, Nikhil
  • Watve, Rohit
  • Panguluri, Suseella
  • Spirin, Nikita Valeryevich
  • Polius, Yannick
  • Hud, Haribhau
  • Ahmed, Umair
  • Mahabaleshwarkar, Ameya Sunil
  • Murauyou, Anton
  • Ahamed A, Asif
  • Kakwani, Divyanshu
  • Lou, Jie
  • Vialard, Julien Veron
  • Nguyen, Khanh
  • Padovani, Otavio
  • Gloginic, Stefana
  • Barua, Sumeet Kumar
  • Singh, Varun
  • Zhang, Jiao

Abstract

Disclosed are devices, systems, and techniques for evaluation of machine learning models, pipelines of machine learning models, retrieval-augmented generation (RAG) systems, and/or other artificial intelligence systems. Example techniques include receiving, from a client device, an evaluation task to evaluate a language model (LM) using a plurality of evaluation benchmarks (EBs) associated with respective EB dataset and configuring, using an evaluation API, respective sets of evaluation jobs to implement the evaluation task. An individual set of evaluation jobs is configured to evaluate, using the corresponding EB dataset, performance of the LM to obtain a set of evaluation metrics. The techniques further include executing the sets of evaluation jobs to obtain respective sets of evaluation metrics and causing, using the evaluation API, a representation of the sets of evaluation metrics to be provided to the client device.

IPC Classes  ?

  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation

28.

UNIFIED CLOUD-BASED PLATFORMS FOR EVALUATION OF MACHINE LEARNING MODELS

      
Application Number 19081995
Status Pending
Filing Date 2025-03-17
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Ficek, Aleksander
  • Peters Long, Eileen Margaret
  • Srihari, Nikhil
  • Watve, Rohit
  • Panguluri, Suseella
  • Spirin, Nik
  • Polius, Yannick
  • Hud, Haribhau
  • Umair, Ahmed
  • Mahabaleshwarkar, Ameya Sunil
  • Murauyou, Anton
  • Ahamed A, Asif
  • Kakwani, Divyanshu
  • Lou, Jie
  • Vialard, Julien Veron
  • Nguyen, Khanh
  • Padovani, Otavio
  • Gloginic, Stefana
  • Barua, Sumeet Kumar
  • Singh, Varun
  • Zhang, Vivienne

Abstract

Disclosed are devices, systems, and techniques for evaluation of machine learning models, pipelines of machine learning models, retrieval-augmented generation (RAG) systems, and/or other artificial intelligence systems. Example techniques include receiving, from a client device, an evaluation task to evaluate a language model (LM) using a plurality of evaluation benchmarks (EBs) associated with respective EB dataset and configuring, using an evaluation API, respective sets of evaluation jobs to implement the evaluation task. An individual set of evaluation jobs is configured to evaluate, using the corresponding EB dataset, performance of the LM to obtain a set of evaluation metrics. The techniques further include executing the sets of evaluation jobs to obtain respective sets of evaluation metrics and causing, using the evaluation API, a representation of the sets of evaluation metrics to be provided to the client device.

IPC Classes  ?

  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 11/30 - Monitoring
  • G06N 20/00 - Machine learning
  • H04L 41/22 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks comprising specially adapted graphical user interfaces [GUI]

29.

MEMORY MANAGEMENT USING A REGISTER

      
Application Number 18604149
Status Pending
Filing Date 2024-03-13
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Choquette, Jack H.
  • Jones, Stephen Anthony Bernard
  • Tyrlik, Maciej Piotr
  • Edwards, Harold Carter
  • Patel, Manan

Abstract

A first request to allocate one or more memory blocks of a first plurality of memory blocks associated with a first memory is received by a processing device. A consecutive set of a first portion of bits of a first register with a first logical state is identified. The first logical state indicates that corresponding memory blocks of the one or more memory blocks are free. A first operation to adjust the consecutive set of the first portion of bits of the first register to a second logical state is performed. An allocation address comprising an index of the consecutive set of the first portion of bits of the first register is sent to the first request. The allocation address is useable to access the corresponding memory blocks.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

30.

PROGRAMMING INTERFACES FOR EVALUATION OF MACHINE LEARNING MODELS

      
Application Number 19040747
Status Pending
Filing Date 2025-01-29
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Gloginic, Stefana
  • Padovani, Otavio
  • Polius, Yannick
  • Barua, Sumeet Kumar
  • Watve, Rohit
  • Srihari, Nikhil
  • Panguluri, Suseella
  • Peters Long, Eileen Margaret
  • Spirin, Nik

Abstract

Disclosed are devices, systems, and techniques for training, deployment, inference, benchmarking, and evaluation of machine learning models. Example techniques include receiving a selection of a first task for a large language model (LLM) and instantiating an execution container including one or more compute backends. The example techniques further include receiving, via an evaluation API, task data into the execution container, the task data having one or more LLM prompts. The example techniques further include executing, using the compute backend(s), the first task in the execution container to generate a task output that includes one or more LLM responses to the LLM prompt(s) or a modification of parameters of the LLM based at least on the LLM prompt(s). The example techniques further include evaluating, using evaluation benchmarks accessed by the evaluation API, the task output to obtain metrics characterizing performance of the LLM and executing a second task using the LLM.

IPC Classes  ?

31.

LANGUAGE MODEL-BASED INTERFACE FOR SIMULATION SYSTEMS AND APPLICATIONS

      
Application Number 18951201
Status Pending
Filing Date 2024-11-18
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Lu, Hai Loc
  • Ouyang, Junliang

Abstract

In various examples, a language model may be trained and used as part of an interface for a simulation system. For instance, user inputs may be applied to the language model and the language model may be trained to generate code, make API calls, or perform any other operations to interact with and/or control various aspects of the simulation. In some examples, the language model may generate code for, among other things, creating and/or customizing a virtual environment associated with the simulation. For instance, the generated code may include, but is not limited to, code for rendering the virtual environment, code for rendering and simulating behaviors of virtual agents (e.g., pedestrians, vehicles, animals, etc.) and/or any other objects (e.g., road signs, buildings, trees, etc.) within the virtual environment, code for recreating and simulating real-world events from recorded sensor data, etc.

IPC Classes  ?

  • G06F 8/35 - Creation or generation of source code model driven
  • G06F 40/284 - Lexical analysis, e.g. tokenisation or collocates
  • G06F 40/40 - Processing or translation of natural language
  • G06N 20/00 - Machine learning

32.

METHOD AND APPARATUS FOR SUPPORTING DISTRIBUTED GRAPHICS AND COMPUTE ENGINES AND SYNCHRONIZATION IN MULTI-DIELET PARALLEL PROCESSOR ARCHITECTURES

      
Application Number 18606924
Status Pending
Filing Date 2024-03-15
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Milne, Timothy Ian
  • Kulkarni, Vaishali
  • Bhattacharya, Debajit
  • Maurya, Ashish Kumar
  • Tong, Tong
  • Ayachit, Vadiraj Alias Abhay
  • Wheeler, Chase Caldwell

Abstract

This disclosure describes supporting distributed graphics and compute engines in a multi-dielet processor, such as, for example, a multi-dielet graphics processing unit (GPU), architectures and synchronization in such architectures. Each multi-dielet processor includes a hardware-implemented remapping capability and/or a hardware-implemented memory barrier capability.

IPC Classes  ?

  • G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors

33.

ADDRESS TRANSLATION SERVICES TO ENABLE MEMORY COHERENCE

      
Application Number 18665382
Status Pending
Filing Date 2024-05-15
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Hossain, Hemayet
  • Gandhi, Wishwesh Anil
  • Deming, James Leroy
  • Mcknight, William Craig
  • Hairgrove, Mark
  • Sethi, Vikramjit
  • Molnar, Steven Edward

Abstract

A first virtual address is translated into a first physical address using a first translation agent associated with a first I/O device of a system. The first physical address is associated with an address space of the first I/O device. A first address translation request is sent to a second translation agent associated with a CPU of the system. The first address translation request includes the first physical address. A first address translation response is received from the second translation agent. The second address translation response includes a second physical address. the second physical address is associated with an address space of the system.

IPC Classes  ?

  • G06F 12/0815 - Cache consistency protocols
  • G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
  • G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
  • G06T 1/60 - Memory management

34.

DELAY LINE CALIBRATION BASED ON DERIVED REFERENCE SIGNALS

      
Application Number 18602754
Status Pending
Filing Date 2024-03-12
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Kashyap, Abhijith
  • Kumar, Virendra
  • Modaress-Razavi, Bobak
  • Wei, Hao-Yi
  • Katyal, Vipul

Abstract

Techniques for improving the accuracy of delay line calibration schemes. For example, an amount of offset may be determined between one or more first portions of a first clock signal and one or more second portions of a second clock signal that is delayed relative to the first clock signal. The first portion(s) may correspond to the second portion(s) based at least on the second clock signal being delayed relative to the first clock signal. In some examples, a value may be determined based at least on the amount of offset. The value may correspond to an amount to adjust the first clock signal to reduce the amount of offset. In some examples, a delay line may then be calibrated, based at least on the second value, to adjust the first clock signal.

IPC Classes  ?

  • H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • G06F 1/12 - Synchronisation of different clock signals
  • H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines

35.

MULTIMODAL LARGE LANGUAGE MODEL AGENT FOR AUTONOMOUS DRIVING

      
Application Number 18888639
Status Pending
Filing Date 2024-09-18
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Yu, Zhiding
  • Wang, Shihao
  • Lan, Shiyi
  • Shi, Min
  • Chang, Nai Chen
  • Kautz, Jan
  • Alvarez Lopez, Jose Manuel

Abstract

Multimodal large language models (MLLMs) have excellent reasoning capabilities and are used for autonomous driving applications. For real-world applications, understanding and navigating in three-dimensional (3D) space is necessary, particularly for autonomous vehicles (AVs) to make informed decisions, anticipate future states, and interact safely with the environment. An MLLM agent system includes a 3D projector model and an adapted LLM that extends understanding and reasoning capability from 2D to 3D. Another component of the MLLM agent system is development of a benchmark visual question-answering (VQA) training dataset for training the MLLM agent. The VQA tasks include scene description, traffic regulation, 3D grounding, counterfactual reasoning, decision making, and planning.

IPC Classes  ?

  • G06N 3/0895 - Weakly supervised learning, e.g. semi-supervised or self-supervised learning
  • G06N 5/04 - Inference or reasoning models

36.

Hardware assisted Page Migration in a Multi-Dielet Processing System

      
Application Number 18607525
Status Pending
Filing Date 2024-03-17
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Bhattacharya, Debajit
  • Maurya, Ashish Kumar
  • Sauvageau, Anthony
  • Milne, Timothy Ian
  • Kulkarni, Vaishali
  • Su, Yi

Abstract

A hardware mechanism at each dielet of a multi-dielet processing system is aware of engine page-table binds at all the dielets, thereby providing accurate traffic notifications to software (e.g., a unified virtual memory driver) for on-demand page-migration between system memory and GPU memory. The mechanism broadcasts binding information to access counters on each dielet so the access counters are able to correlate engines requesting memory access with bound virtual memory pages and generate corresponding informative notifications. A flexible multi-dielet counter clear capability enables software to clear access counters.

IPC Classes  ?

  • G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
  • G06F 12/0882 - Page mode

37.

MULTI-SENSOR SUBJECT TRACKING FOR MONITORED ENVIRONMENTS FOR REAL-TIME AND NEAR-REAL-TIME SYSTEMS AND APPLICATIONS

      
Application Number 18605121
Status Pending
Filing Date 2024-03-14
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Tang, Zheng
  • Biswas, Sujit
  • Aiyer, Ganapathy Seshadri Cadungude
  • Wang, Shuo
  • Agrawal, Akshay
  • Pusegaonkar, Sameer Satish

Abstract

In various examples, multi-sensor subject tracking for monitored environments for real-time and near-real-time systems and applications are provided. A location system performs multi-subject tracking using streaming data from multiple sensors. Subject tracking may be based on individual anchors and behavior states that are initialized for individual subjects using representations (e.g., behavior embeddings) derived from the streaming data. Clustering may be used to generate behavior clusters that individually represents a trackable subject. Behavior states for live anchors may identified based on continuity of trajectory and tracked by iteratively propagating their behavior states forward over time. Clusters lacking continuity of trajectory may be used to initialize new anchors, or matched to dormant anchors that may be reclassified as live anchors and propagated. Propagated behavior states may be updated using behavior data represented by the behavior embeddings.

IPC Classes  ?

  • G06T 7/20 - Analysis of motion
  • G06V 10/762 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using clustering, e.g. of similar faces in social networks
  • G06V 40/20 - Movements or behaviour, e.g. gesture recognition

38.

DIRECT CONNECT BETWEEN NETWORK INTERFACE AND GRAPHICS PROCESSING UNIT IN SELF-HOSTED MODE IN A MULTIPROCESSOR SYSTEM

      
Application Number 18605518
Status Pending
Filing Date 2024-03-14
First Publication Date 2025-09-18
Owner NVIDIA CORPORATION (USA)
Inventor
  • Gandhi, Wishwesh Anil
  • Bhattacharya, Debajit
  • Manyam, Ravi Kiran
  • Mehra, Karan
  • Cherabuddi, Prithvi Reddy

Abstract

Various embodiments include techniques for performing data transfer operations via a direct interconnect between a network interface and a graphics processor in a multiprocessor system that also includes a central processing unit (CPU). The CPU communicates with the graphics processor via a dedicated high-bandwidth interconnect to the memory in the graphics processor and a second interconnect to the graphics processor for various utility functions. The network interface communicates with the graphics processor via an interconnect to the memory in the graphics processor. The interconnect between the network interface and the graphics processor does not impact the throughput of the high-bandwidth interconnect from the CPU to the graphics processor, thereby improving CPU to graphics processor performance. Further, the interconnect between the CPU to the graphics processor does not impact the throughput of the interconnect from the network interface to the graphics processor, thereby improving network interface to graphics processor performance.

IPC Classes  ?

  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
  • G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation

39.

PERFORMANCE TESTING FOR STEREOSCOPIC IMAGING SYSTEMS AND ALGORITHMS

      
Application Number 18603916
Status Pending
Filing Date 2024-03-13
First Publication Date 2025-09-18
Owner Nvidia Corporation (USA)
Inventor Zhang, Jack Yusong

Abstract

Approaches presented herein provide for the testing of imaging algorithms and systems. In at least one embodiment, a stereoscopic test pattern can be obtained that includes a number of features that vary in width and separation, such as may comprise a set of radial elements that converge toward a center point. A stereoscopic image of an instance of the pattern can be analyzed, such as at a set of radial positions, to make various measurements, including a limit on the ability to distinguish between different features. A pair of synthetic images of the pattern can be generated in order to test aspects of a stereoscopic algorithm used to generate stereoscopic images, with such testing being separate from the physical system, and a physical object can be generated that includes a representation of the pattern in order to be able to test the physical stereoscopic imaging system.

IPC Classes  ?

  • H04N 13/239 - Image signal generators using stereoscopic image cameras using two 2D image sensors having a relative position equal to or related to the interocular distance
  • H04N 13/00 - Stereoscopic video systemsMulti-view video systemsDetails thereof
  • H04N 13/296 - Synchronisation thereofControl thereof

40.

DATA TRANSFER TECHNIQUE

      
Application Number 18634643
Status Pending
Filing Date 2024-04-12
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Garg, Rachit
  • Eryilmaz, Sukru Burc
  • Andersch, Michael
  • Parle, Apoorv
  • Hum, Herbert
  • Duan, Kefeng
  • Jiang, Jiang

Abstract

Apparatuses, systems, and techniques are to transfer data based, at least in part, on a computational graph. In at least one embodiment, a processor causes a compiler to generate instructions to prefetch one or more data values from dynamic random access memory (DRAM) into an in-processor cache based, at least in part, on a computational graph.

IPC Classes  ?

  • G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
  • G06F 12/1072 - Decentralised address translation, e.g. in distributed shared memory systems

41.

APPLICATION PROGRAMMING INTERFACE TO INDICATE DEVICE ATTRIBUTE

      
Application Number 18737820
Status Pending
Filing Date 2024-06-07
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Boissel, Raphael Dominique Pierre
  • Patel, Jalpa Mahendra
  • Kini, Vivek Belve
  • Tammana, Venkatesh
  • Misal, Sanket Narenda
  • Khodakovsky, Andrei
  • Middlebrook, Liam James
  • Chauhan, Jitenda Pratap Singh
  • Lentini, Christopher
  • Jones, James Roy
  • Juliano, Jeffrey
  • Vishnuswaroop Ramesh, Fnu
  • Bujak, Jakub

Abstract

Apparatuses, systems, and techniques to perform an application programming interface (API) to indicate whether one or more processors are able to be controlled by two or more drivers concurrently. An API is performed that will indicate whether a compute driver and a graphics driver can concurrently control a processor.

IPC Classes  ?

42.

FACILITATING CONTENT ACQUISITION VIA VIDEO STREAM ANALYSIS

      
Application Number 19223538
Status Pending
Filing Date 2025-05-30
First Publication Date 2025-09-18
Owner NVIDIA Corporation (USA)
Inventor
  • Hropak, Alexander
  • Fear, Andrew

Abstract

In various examples, one or more Machine Learning Models (MLMs) are used to identify content items in a video stream and present information associated with the content items to viewers of the video stream. Video streamed to a user(s) may be applied to an MLM(s) trained to detect an object(s) therein. The MLM may directly detect particular content items or detect object types, where a detection may be narrowed to a particular content item using a twin neural network, and/or an algorithm. Metadata of an identified content item may be used to display a graphical element selectable to acquire the content item in the game or otherwise. In some examples, object detection coordinates from an object detector used to identify the content item may be used to determine properties of an interactive element overlaid on the video and presented on or in association with a frame of the video.

IPC Classes  ?

  • G06V 20/40 - ScenesScene-specific elements in video content
  • A63F 13/537 - Controlling the output signals based on the game progress involving additional visual information provided to the game scene, e.g. by overlay to simulate a head-up display [HUD] or displaying a laser sight in a shooting game using indicators, e.g. showing the condition of a game character on screen
  • G06N 3/045 - Combinations of networks
  • H04L 65/611 - Network streaming of media packets for supporting one-way streaming services, e.g. Internet radio for multicast or broadcast

43.

ENVIRONMENTAL TEXT PERCEPTION AND TOLL EVALUATION USING VISION LANGUAGE MODELS

      
Application Number 18791995
Status Pending
Filing Date 2024-08-01
First Publication Date 2025-09-18
Owner NVIDIA CORPORATION (USA)
Inventor
  • Pathak, Niral Lalit
  • Neerukonda, Chandana
  • Shetty, Rajath Bellipady
  • Avadhanam, Niranjan
  • Kumar, Ratin

Abstract

A vision language model (VLM) may be used to evaluate signs that designate restricted or toll lanes, determine whether it is permissible (and/or the cost) to merge into a restricted or toll lane, and/or determine when to merge out of a restricted or toll lane based on the cost. Frames from one or more (e.g., front-facing) camera(s) may be evaluated for applicable signs (e.g., using a sign recognition DNN or a VLM). If detected, the (e.g., cropped) image of the sign may be provided as input to a VLM with a textual prompt instructing the VLM to determine whether to drive in the restricted or toll lane (e.g., whether it can be taken within budget) and/or what the cost would be. The generated response may be provided to an ADAS to trigger an initiation of a merge left or right or a determination to stay in the current lane.

IPC Classes  ?

  • G08G 1/16 - Anti-collision systems
  • G01C 21/34 - Route searchingRoute guidance
  • G06V 20/58 - Recognition of moving objects or obstacles, e.g. vehicles or pedestriansRecognition of traffic objects, e.g. traffic signs, traffic lights or roads

44.

DATA TRANSFER TECHNIQUE

      
Application Number CN2024081687
Publication Number 2025/189421
Status In Force
Filing Date 2024-03-14
Publication Date 2025-09-18
Owner NVIDIA CORPORATION (USA)
Inventor
  • Garg, Rachit
  • Eryilmaz, Sukru Burc
  • Andersch, Michael
  • Parle, Apoorv
  • Hum, Herbert
  • Duan, Kefeng
  • Jiang, Jiang

Abstract

Apparatuses, systems, and techniques are to transfer data based, at least in part, on a computational graph. In at least one embodiment, a processor causes a compiler to generate instructions to prefetch one or more data values from dynamic random access memory (DRAM) into an in-processor cache based, at least in part, on a computational graph.

IPC Classes  ?

45.

Systems and methods for aperture-specific cache operations

      
Application Number 18665392
Grant Number 12417181
Status In Force
Filing Date 2024-05-15
First Publication Date 2025-09-16
Grant Date 2025-09-16
Owner NVIDIA Corporation (USA)
Inventor
  • Holey, Anup
  • Gandhi, Wishwesh Anil
  • Kaushikkar, Sujoyita
  • Mehra, Karan
  • Robinson, Daniel Glenn
  • Kiminki, Sami Olavi Johannes
  • Waterman, Alexander Michael
  • Hairgrove, Mark
  • Smith, Jeff
  • Yin, Liang

Abstract

A processing device including a first cache is coupled to a system memory and a parallel processing unit (PPU) including a second cache. An operation to modify cache lines of the second cache associated with a first aperture of the system memory is received. A first subset of cache lines of the second cache is identified. The first subset of cache lines is associated with the first aperture of the system memory and is different from a second subset of cache lines of a second aperture of the system memory. The first subset of cache lines is modified as specified by the cache operation.

IPC Classes  ?

46.

Systems and methods for multicasting data

      
Application Number 18604184
Grant Number 12417177
Status In Force
Filing Date 2024-03-13
First Publication Date 2025-09-16
Grant Date 2025-09-16
Owner NVIDIA Corporation (USA)
Inventor
  • Lei, Ming Liang Milton
  • Schottmiller, Jeffery Michael
  • Patel, Manan
  • Ghoshal, Pritha
  • Fetterman, Michael Alan
  • Ohannessian, Jr., Robert
  • Kaushik, Praveen Kumar

Abstract

A first instruction to load a first data into a first register file associated with a first subpartition unit is received. A second instruction to load the first data into a second register file associated with a second subpartition unit is received. The first instruction and the second instruction are coalesced into a first entry of a request coalescer based on instruction identifiers. The first entry is associated with the first data. Responsive to a determination that the first data is available in the cache, the first data is multicast from the cache to the first register file and the second register file.

IPC Classes  ?

  • G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
  • G06F 12/0868 - Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack

47.

Fifth generation new radio signal processing

      
Application Number 16823146
Grant Number 12418897
Status In Force
Filing Date 2020-03-18
First Publication Date 2025-09-16
Grant Date 2025-09-16
Owner NVIDIA Corporation (USA)
Inventor
  • Banuli Nanje Gowda, Harsha Deepak
  • Gurfinkel, Steven Arthur

Abstract

Apparatuses, systems, and techniques to perform signal processing operations in a fifth generation (5G) new radio (NR) signal. In at least one embodiment, one or more processors process a 5G NR signals according to one or more graph nodes.

IPC Classes  ?

  • H04W 72/0446 - Resources in time domain, e.g. slots or frames
  • G06F 16/901 - IndexingData structures thereforStorage structures
  • H04B 7/26 - Radio transmission systems, i.e. using radiation field for communication between two or more posts at least one of which is mobile
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/0453 - Resources in frequency domain, e.g. a carrier in FDMA
  • H04W 74/04 - Scheduled access
  • H04W 84/04 - Large scale networksDeep hierarchical networks

48.

DEPTH ESTIMATION FOR AUTONOMOUS AND SEMI-AUTONOMOUS SYSTEMS AND APPLICATIONS

      
Application Number 19213186
Status Pending
Filing Date 2025-05-20
First Publication Date 2025-09-11
Owner NVIDIA Corporation (USA)
Inventor
  • Zhong, Yiran
  • Loop, Charles
  • Smolyanskiy, Nikolai
  • Chen, Ke
  • Birchfield, Stan
  • Popov, Alexander

Abstract

In various examples, methods and systems are provided for estimating depth values for images (e.g., from a monocular sequence). Disclosed approaches may define a search space of potential pixel matches between two images using one or more depth hypothesis planes based at least on a camera pose associated with one or more cameras used to generate the images. A machine learning model(s) may use this search space to predict likelihoods of correspondence between one or more pixels in the images. The predicted likelihoods may be used to compute depth values for one or more of the images. The predicted depth values may be transmitted and used by a machine to perform one or more operations.

IPC Classes  ?

  • G06T 7/55 - Depth or shape recovery from multiple images
  • G06T 7/70 - Determining position or orientation of objects or cameras
  • G06V 10/46 - Descriptors for shape, contour or point-related descriptors, e.g. scale invariant feature transform [SIFT] or bags of words [BoW]Salient regional features

49.

MOTION VECTOR OPTIMIZATION FOR MULTIPLE REFRACTIVE AND REFLECTIVE INTERFACES

      
Application Number 19217303
Status Pending
Filing Date 2025-05-23
First Publication Date 2025-09-11
Owner Nvidia Corporation (USA)
Inventor
  • Kozlowski, Pawel
  • Aizenshtein, Maksim

Abstract

Systems and methods relate to the determination of accurate motion vectors, for rendering situations such as a noisy Monte Carlo integration where image object surfaces are at least partially translucent. To optimize the search for “real world” positions, this invention defines the background as first path vertices visible through multiple layers of refractive interfaces. To find matching world positions, the background is treated as a single layer morphing in a chaotic way, permitting the optimized algorithm to be executed only once. Further improving performance over the prior linear gradient descent, the present techniques can apply a cross function and numerical optimization, such as Newton's quadratic target or other convergence function, to locate pixels via a vector angle minimization. Determined motion vectors can then serve as input for services including image denoising.

IPC Classes  ?

  • G06T 15/00 - 3D [Three Dimensional] image rendering
  • G06T 5/70 - DenoisingSmoothing
  • G06T 7/20 - Analysis of motion
  • G06T 7/70 - Determining position or orientation of objects or cameras

50.

NEURAL NETWORK BASED DETERMINATION OF GAZE DIRECTION USING SPATIAL MODELS

      
Application Number 19219696
Status Pending
Filing Date 2025-05-27
First Publication Date 2025-09-11
Owner NVIDIA Corporation (USA)
Inventor
  • Arar, Nuri Murat
  • Jiang, Hairong
  • Puri, Nishant
  • Shetty, Rajath
  • Avadhanam, Niranjan

Abstract

Systems and methods for determining the gaze direction of a subject and projecting this gaze direction onto specific regions of an arbitrary three-dimensional geometry. In an exemplary embodiment, gaze direction may be determined by a regression-based machine learning model. The determined gaze direction is then projected onto a three-dimensional map or set of surfaces that may represent any desired object or system. Maps may represent any three-dimensional layout or geometry, whether actual or virtual. Gaze vectors can thus be used to determine the object of gaze within any environment. Systems can also readily and efficiently adapt for use in different environments by retrieving a different set of surfaces or regions for each environment.

IPC Classes  ?

  • G06N 3/08 - Learning methods
  • G06F 18/21 - Design or setup of recognition systems or techniquesExtraction of features in feature spaceBlind source separation
  • G06F 18/214 - Generating training patternsBootstrap methods, e.g. bagging or boosting
  • G06N 20/00 - Machine learning
  • G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
  • G06V 10/774 - Generating sets of training patternsBootstrap methods, e.g. bagging or boosting
  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
  • G06V 10/94 - Hardware or software architectures specially adapted for image or video understanding
  • G06V 20/59 - Context or environment of the image inside of a vehicle, e.g. relating to seat occupancy, driver state or inner lighting conditions
  • G06V 20/64 - Three-dimensional objects
  • G06V 40/16 - Human faces, e.g. facial parts, sketches or expressions
  • G06V 40/18 - Eye characteristics, e.g. of the iris

51.

JOINT NEURAL DENOISING OF SURFACES AND VOLUMES

      
Application Number 19220272
Status Pending
Filing Date 2025-05-28
First Publication Date 2025-09-11
Owner NVIDIA Corporation (USA)
Inventor
  • Hofmann, Nikolai Till
  • Hasselgren, Jon Niklas Theodor
  • Munkberg, Carl Jacob

Abstract

Denoising images rendered using Monte Carlo sampled ray tracing is an important technique for improving the image quality when low sample counts are used. Ray traced scenes that include volumes in addition to surface geometry are more complex, and noisy when low sample counts are used to render in real-time. Joint neural denoising of surfaces and volumes enables combined volume and surface denoising in real time from low sample count renderings. At least one rendered image is decomposed into volume and surface layers, leveraging spatio-temporal neural denoisers for both the surface and volume components. The individual denoised surface and volume components are composited using learned weights and denoised transmittance. A surface and volume denoiser architecture outperforms current denoisers in scenes containing both surfaces and volumes, and produces temporally stable results at interactive rates.

IPC Classes  ?

52.

HARDWARE ACCELERATION FOR RAY TRACING PRIMITIVES THAT SHARE VERTICES

      
Application Number 19220495
Status Pending
Filing Date 2025-05-28
First Publication Date 2025-09-11
Owner NVIDIA Corporation (USA)
Inventor
  • Muthler, Gregory
  • Burgess, John
  • Kwong, Ian Chi Yan

Abstract

Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure and its underlying primitives are disclosed. For example, traversal speed is improved by grouping processing of primitives sharing at least one figure (e.g., a vertex or an edge) during ray-primitive intersection testing. Grouping the primitives for ray intersection testing can reduce processing (e.g., projections and transformations of primitive vertices and/or determining edge function values) because at least a portion of the processing results related to the shared feature in one primitive can be used to determine whether the ray intersects another primitive(s). Processing triangles sharing an edge can double the culling rate of the triangles in the ray/triangle intersection test without replicating the hardware.

IPC Classes  ?

  • G06T 15/06 - Ray-tracing
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06T 15/08 - Volume rendering
  • G06T 17/10 - Volume description, e.g. cylinders, cubes or using CSG [Constructive Solid Geometry]
  • G06T 17/20 - Wire-frame description, e.g. polygonalisation or tessellation

53.

APPLICATION PROGRAMMING INTERFACE TO INDICATE MEMORY ACCESS

      
Application Number 18596283
Status Pending
Filing Date 2024-03-05
First Publication Date 2025-09-11
Owner NVIDIA Corporation (USA)
Inventor
  • Ramos, Jesus
  • Vishnuswaroop Ramesh, Fnu
  • Kini, Vivek Belve
  • Thomason, Braxton
  • Iverson, Jeremy

Abstract

Apparatuses, systems, and techniques to perform a neural network to perform an API to cause storage to be reserved. In at least one embodiment, for example, an API causes storage to be reserved based, at least in part, on a flag indicating a memory pool to be allocated to a memory of a processor, such as a GPU or CPU. In at least one embodiment, as another example, a processor comprising one or more circuits performs an application programming interface (API) to indicate whether one or more graphics processing units (GPU) are to access GPU storage or host storage.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 9/54 - Interprogram communication

54.

DYNAMIC SHARING OF GRAPHICS PROCESSING UNIT (GPU) COMPUTATIONAL CAPABILITIES BASED ON PROCESSING DENSITY

      
Application Number 18597433
Status Pending
Filing Date 2024-03-06
First Publication Date 2025-09-11
Owner Nvidia Corporation (USA)
Inventor
  • Kass, Michael
  • Kim, Tae
  • Chalakov, Georgi M.

Abstract

Approaches presented herein provide systems and methods for dynamic allocation of processing units to increase computational density. Idle times between sequential processing tasks may be computed and, if the idle time exceeds a threshold capacity, additional sequential processing tasks may be allocated to a common processing unit. As a request, a first portion of a first sequential processing task may be executed, then a second portion of a second sequential processing task may be executed prior to executing a subsequent portion of the second sequential processing task. By using the idle time between portions of sequential processing tasks, output perform may be maintained while using additional processing capabilities that would otherwise remain idle.

IPC Classes  ?

  • G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
  • G06T 15/00 - 3D [Three Dimensional] image rendering

55.

BIDIRECTIONAL OBJECT TRACKING IN COMPUTER VISION APPLICATIONS

      
Application Number 18597451
Status Pending
Filing Date 2024-03-06
First Publication Date 2025-09-11
Owner NVIDIA Corporation (USA)
Inventor
  • Kale, Amit
  • Rupde, Bhushan
  • Purandare, Kaustubh

Abstract

Disclosed are apparatuses, systems, and techniques for implementing bidirectional tracking in computer vision applications. In one embodiment, the techniques include obtaining digital representations of an object depicted in video frames and for each of a forward direction (FD) of tracking and a reverse direction (RD) of tracking, obtaining, using (i) a current state of the object associated with an upstream video frame and (ii) the digital representation of the object for a downstream video frame, an updated state of the object associated with the downstream video frame. The techniques further include obtaining, using the updated state of the object for the FD and/or the updated state of the object for the RD, a bidirectional state of the object, and determining, using the bidirectional state of the object, a trajectory of the object across the video frames.

IPC Classes  ?

  • G06T 7/246 - Analysis of motion using feature-based methods, e.g. the tracking of corners or segments
  • G06T 7/277 - Analysis of motion involving stochastic approaches, e.g. using Kalman filters
  • G06T 7/60 - Analysis of geometric attributes
  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
  • G06V 10/74 - Image or video pattern matchingProximity measures in feature spaces
  • G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries

56.

SPEED DETERMINATION IN ROBOTICS SYSTEMS AND APPLICATIONS

      
Application Number 18597688
Status Pending
Filing Date 2024-03-06
First Publication Date 2025-09-11
Owner NVIDIA CORPORATION (USA)
Inventor
  • Liu, Wei
  • Goyal, Pulkit
  • Gulich, Lionel Federico
  • Okal, Billy Omondi
  • Pouya, Soha

Abstract

In various examples, a technique for generating speed change decisions for a mobile robot includes identifying, using one or more maps of a physical environment, one or more obstacles associated with one or more portions of a path of the mobile robot in the physical environment. The technique also includes generating, based at least on the one or more obstacles, one or more speed constraints, each speed constraint specifying a speed limit for a respective portion of the path. The technique further includes generating one or more speed change decisions specifying actions to be performed by the mobile robot to cause a speed profile of the mobile robot to satisfy the one or more speed constraints.

IPC Classes  ?

  • B25J 9/16 - Programme controls
  • B25J 13/08 - Controls for manipulators by means of sensing devices, e.g. viewing or touching devices

57.

SALIENCY-GUIDED PACKET LOSS MITIGATION FOR CONTENT STREAMING SYSTEMS AND APPLICATIONS

      
Application Number 18598777
Status Pending
Filing Date 2024-03-07
First Publication Date 2025-09-11
Owner Nvidia Corporation (USA)
Inventor
  • Su, Yuanhang
  • Mazumdar, Amrita
  • Bosnjakovic, Andrija
  • Zimmermann, Johannes

Abstract

Approaches presented herein provide systems and methods to selectively apply packet loss mitigation methods to one or more regions of a frame that have a sufficient importance value. The importance value may be determined by a saliency map generated for the frame that determine the most important content elements or regions of the frame. An importance value may be computed based on the saliency map and then, for areas of sufficient importance, selective mitigation methods may be used to reduce bandwidth, conserve compute resources, and provide error correction or duplication for important regions of the frame.

IPC Classes  ?

  • H04N 21/238 - Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidthProcessing of multiplex streams
  • H04N 21/234 - Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
  • H04N 21/24 - Monitoring of processes or resources, e.g. monitoring of server load, available bandwidth or upstream requests

58.

SILICON STRUCTURES TO MONITOR DEVICE CAPACITANCES

      
Application Number 18601230
Status Pending
Filing Date 2024-03-11
First Publication Date 2025-09-11
Owner NVIDIA Corp. (USA)
Inventor
  • Patel, Manish Umedlal
  • Srivastava, Kinshuk
  • Raja, Tezaswi

Abstract

A capacitive monitoring structure includes a ring oscillator and dynamically configurable capacitive load circuits coupled between stages of the ring oscillator. The oscillation frequency of the ring oscillator changes in response to settings applied to the capacitive load circuits to change a capacitance applied to the ring oscillator by the capacitive load circuits, where the capacitance may be one of a transistor drain capacitance, a transistor gate capacitance, and a Miller capacitance.

IPC Classes  ?

  • G01R 27/26 - Measuring inductance or capacitanceMeasuring quality factor, e.g. by using the resonance methodMeasuring loss factorMeasuring dielectric constants
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

59.

LOCAL TRANSFORM PROPAGATION IN ENVIRONMENT RECONSTRUCTION SYSTEMS AND APPLICATIONS

      
Application Number 18609296
Status Pending
Filing Date 2024-03-19
First Publication Date 2025-09-11
Owner Nvidia Corporation (USA)
Inventor
  • Schroeter, Derik
  • Wu, Mengxi
  • Liu, Tian

Abstract

Approaches presented herein provide for the matching and alignment of features in different instances of sensor data corresponding to an environment. At least one embodiment provides for accurate identification of matching lane dividers between two or more tracks obtained from sensor-equipped vehicles or machines. An initial transform can be determined using a seed area for tracks of data, where the seed area can be determined using landmarks, lane boundaries, or other such objects identified from the sensor data. The initial transform can be used to determine lane divider matches in the track data. If successfully evaluated, these lane divider matches from the seed areas can be propagated out in one or more tracking directions along a roadway to determine lane divider matches along entire stretches of roadway, including roads that pass through intersections or other relatively complex regions.

IPC Classes  ?

  • G06V 20/56 - Context or environment of the image exterior to a vehicle by using sensors mounted on the vehicle
  • G06V 10/74 - Image or video pattern matchingProximity measures in feature spaces

60.

SCHEDULING AND RESOURCE MANAGEMENT BASED ON APPLICATION PROFILING

      
Application Number 19215921
Status Pending
Filing Date 2025-05-22
First Publication Date 2025-09-11
Owner NVIDIA CORPORATION (USA)
Inventor Nakfour, Juana

Abstract

In various examples, each hosted application may be modeled with a corresponding application-specific resource consumption model that predicts a measure of that application's anticipated resource utilization at some future time based on an input representation of one or more features of the current state of an instance of the hosted application. For cloud gaming, those features may include the current level being played, current obstacles, user results playing the level or obstacles, metadata quantifying one or more aspects of the level or obstacles, game progress, etc. As such, application-specific models may be used to predict resource demands at a future time and schedule resource allocations accordingly. The present techniques may be used to manage and reallocate resources for applications such as game streaming applications, remote desktop applications, simulation applications (e.g., an autonomous or semi-autonomous vehicle simulation), virtual reality (VR) and/or augmented reality (AR) streaming applications, and/or other application types.

IPC Classes  ?

  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]

61.

NATURAL LANGUAGE PROCESSING APPLICATIONS USING LARGE LANGUAGE MODELS

      
Application Number 19217012
Status Pending
Filing Date 2025-05-23
First Publication Date 2025-09-11
Owner Nvidia Corporation (USA)
Inventor
  • Leary, Ryan
  • Cohen, Jonathan

Abstract

Approaches presented herein can provide for the performance of specific types of tasks using a large model, without a need to retrain the model. Custom endpoints can be trained for specific types of tasks, as may be indicated by the specification of one or more guidance mechanisms. A guidance mechanism can be added to or used along with a request to guide the model in performing a type of task with respect to a string of text. An endpoint receiving such a request can perform any marshalling needed to get the request in a format required by the model, and can add the guidance mechanisms to the request by, for example, prepending one or more text strings (or text prefixes) to a text-formatted request. A model receiving this string can process the text according to the guidance mechanisms. Such an approach can allow for a variety of tasks to be performed by a single model.

IPC Classes  ?

  • G06F 40/40 - Processing or translation of natural language
  • G06F 40/284 - Lexical analysis, e.g. tokenisation or collocates

62.

NATURAL LANGUAGE PROCESSING APPLICATIONS USING LARGE LANGUAGE MODELS

      
Application Number 19217029
Status Pending
Filing Date 2025-05-23
First Publication Date 2025-09-11
Owner Nvidia Corporation (USA)
Inventor
  • Leary, Ryan
  • Cohen, Jonathan

Abstract

Approaches presented herein can provide for the performance of specific types of tasks using a large model, without a need to retrain the model. Custom endpoints can be trained for specific types of tasks, as may be indicated by the specification of one or more guidance mechanisms. A guidance mechanism can be added to or used along with a request to guide the model in performing a type of task with respect to a string of text. An endpoint receiving such a request can perform any marshalling needed to get the request in a format required by the model, and can add the guidance mechanisms to the request by, for example, prepending one or more text strings (or text prefixes) to a text-formatted request. A model receiving this string can process the text according to the guidance mechanisms. Such an approach can allow for a variety of tasks to be performed by a single model.

IPC Classes  ?

  • G06F 40/40 - Processing or translation of natural language
  • G06F 40/284 - Lexical analysis, e.g. tokenisation or collocates

63.

PROCESSOR CLOCK SCALING TECHNIQUE

      
Application Number 18597271
Status Pending
Filing Date 2024-03-06
First Publication Date 2025-09-11
Owner NVIDIA Corporation (USA)
Inventor
  • Narayanaswamy, Sreedhar
  • Xu, Jun
  • Saini, Manish
  • Sitaraman, Krishna
  • Frid, Aleksandr

Abstract

Apparatuses, systems, and techniques to scale processor clocks. In at least one embodiment, one or more circuits are to scale one or more clocks of one or more cores based, at least in part, on a proximity of the one or more cores to each other.

IPC Classes  ?

  • G06F 1/08 - Clock generators with changeable or programmable clock frequency

64.

USING ONE OR MORE NEURAL NETWORKS TO GENERATE TEXT

      
Application Number 18597408
Status Pending
Filing Date 2024-03-06
First Publication Date 2025-09-11
Owner NVIDIA Corporation (USA)
Inventor
  • Pandey, Mayank
  • Mishra, Shivi
  • Sharma, Priyanshu
  • Kulkarni, Amey
  • Rao, Harshraj
  • Kumar, Prasun

Abstract

Apparatuses, systems, and techniques to cause one or more neural networks to summarize a text. In at least one embodiment, a processor is to cause one or more neural networks to generate one or more summaries of a first portion of a text based, at least in part, on one or more second portions of said text.

IPC Classes  ?

65.

REGIONAL PATH PLANNING IN ROBOTICS SYSTEMS AND APPLICATIONS

      
Application Number 18597682
Status Pending
Filing Date 2024-03-06
First Publication Date 2025-09-11
Owner NVIDIA CORPORATION (USA)
Inventor
  • Liu, Wei
  • Goyal, Pulkit
  • Gulich, Lionel Federico
  • Okal, Billy Omondi
  • Pouya, Soha

Abstract

In various examples, a technique for generating a path between a current location and a target waypoint is disclosed that includes receiving a route plan that is associated with a plurality of waypoints representing locations in a physical environment. The technique also includes identifying a search space that includes the route plan, and identifying a target waypoint of the plurality of waypoints—the target waypoint being in a portion of the search space between a current location of a mobile robot and an end waypoint of the route plan. A path between the current location of the mobile robot and the target waypoint may then be generated.

IPC Classes  ?

66.

HEALTH AND ERROR MONITORING OF SENSOR FUSION SYSTEMS

      
Application Number 18599546
Status Pending
Filing Date 2024-03-08
First Publication Date 2025-09-11
Owner NVIDIA Corporation (USA)
Inventor
  • Svensson, Daniel Per Olof
  • Hultberg, Andreas
  • Rahmathullah, Abu Sajana
  • Oh, Sangmin

Abstract

In various examples, systems and methods are disclosed relating to health and error monitoring of sensor fusion systems. Systems and methods are disclosed that aggregate results of monitoring and error checking in a sensor fusion system in a single checkpoint. A processor may include one or more circuits. The one or more circuits may receive perception data from one or more first sensors of a machine. The one or more circuits may receive position data from one or more second sensors of the machine. The one or more circuits may generate output data by performing fusion of at least the perception data and the position data. The one or more circuits may evaluate a plurality of criteria according to at least a subset of the perception data, the position data, and the output data. The one or more circuits may output an error signal according to the evaluation.

IPC Classes  ?

  • G06F 11/36 - Prevention of errors by analysis, debugging or testing of software
  • G06F 18/21 - Design or setup of recognition systems or techniquesExtraction of features in feature spaceBlind source separation
  • G06F 18/25 - Fusion techniques

67.

INFORMATION PRIORITIZATION IN WIRELESS NETWORKS

      
Application Number 18600240
Status Pending
Filing Date 2024-03-08
First Publication Date 2025-09-11
Owner NVIDIA Corporation (USA)
Inventor Lin, Xingqin

Abstract

Apparatuses, systems, and techniques of autonomously adjust priority of information to be transmitted by a UE device. In at least one embodiment, a UE device autonomously adjusts priority of information to be transmitted by adjusting prioritization parameters. In at least one embodiment, prioritization parameters are adjusted autonomously by a UE device that monitors packet statistics.

IPC Classes  ?

  • H04W 72/56 - Allocation or scheduling criteria for wireless resources based on priority criteria
  • H04W 28/08 - Load balancing or load distribution

68.

Fully cache coherent virtual partitions in multitenant configurations in a multiprocessor system

      
Application Number 18598997
Grant Number 12411761
Status In Force
Filing Date 2024-03-07
First Publication Date 2025-09-09
Grant Date 2025-09-09
Owner NVIDIA CORPORATION (USA)
Inventor
  • Rao S J, Adarsha
  • Deshpande, Sanjay R.
  • L, Raghuram
  • B K, Anirudh
  • Kumar, Harsh
  • Fang, Kun

Abstract

Various embodiments include techniques for processing memory operations in a computing system. The computing system includes a central processing unit (CPU) and an auxiliary processor, such as a parallel processing unit (PPU). The PPU can be divided into multiple partitions. Although the partitions are included in a single PPU, the CPU can track the partitions as if the partitions are independent devices rather than different portions of a single device. When two different partitions generate memory operations that access the same memory address in CPU memory address space, the two partitions employ two different data paths. The CPU can use path information for the two different paths to identify which partition generated each memory operation. As a result, the CPU can maintain data consistency and memory coherency in a system where a PPU is divided into multiple partitions.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 9/52 - Program synchronisationMutual exclusion, e.g. by means of semaphores
  • G06F 12/02 - Addressing or allocationRelocation
  • G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
  • G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array

69.

Audio noise removal using one or more neural networks

      
Application Number 16721881
Grant Number 12412590
Status In Force
Filing Date 2019-12-19
First Publication Date 2025-09-09
Grant Date 2025-09-09
Owner NVIDIA Corporation (USA)
Inventor
  • Dantrey, Ambrish
  • Ghosh, Angshuman
  • Nyayate, Mihir
  • Patait, Abhijit

Abstract

Apparatuses, systems, and techniques are presented to reduce noise in audio. In at least one embodiment, a sequence of neural networks is used to remove foreground and background noise from audio including a primary audio signal.

IPC Classes  ?

  • G10L 21/00 - Speech or voice signal processing techniques to produce another audible or non-audible signal, e.g. visual or tactile, in order to modify its quality or its intelligibility
  • G06N 3/044 - Recurrent networks, e.g. Hopfield networks
  • G06N 3/045 - Combinations of networks
  • G10L 15/16 - Speech classification or search using artificial neural networks
  • G10L 15/22 - Procedures used during a speech recognition process, e.g. man-machine dialog
  • G10L 21/0232 - Processing in the frequency domain
  • G10L 25/18 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the type of extracted parameters the extracted parameters being spectral information of each sub-band
  • G10L 25/84 - Detection of presence or absence of voice signals for discriminating voice from noise

70.

GRID-BASED LIGHT SAMPLING FOR RAY TRACING APPLICATIONS

      
Application Number 19202904
Status Pending
Filing Date 2025-05-08
First Publication Date 2025-09-04
Owner NVIDIA Corporation (USA)
Inventor
  • Boksansky, Jakub
  • Jukarainen, Paula Eveliina
  • Wyman, Christopher Ryan

Abstract

Devices, systems, and techniques to incorporate lighting effects into computer-generated graphics. In at least one embodiment, a virtual scene comprising a plurality of lights is rendered by subdividing the virtual area and stored, in a record corresponding to a subdivision of the virtual area, information indicative of one or more lights in the virtual area selected based on a stochastic model. Pixels near a subdivision are rendered based on the light information stored in the subdivision.

IPC Classes  ?

71.

INTELLIGENT REFRIGERANT-ASSISTED LIQUID-TO-AIR HEAT EXCHANGER FOR DATACENTER COOLING SYSTEMS

      
Application Number 19211240
Status Pending
Filing Date 2025-05-18
First Publication Date 2025-09-04
Owner NVIDIA Corporation (USA)
Inventor Heydari, Ali

Abstract

Systems and methods for cooling a datacenter are disclosed. In at least one embodiment, a liquid-to-air heat exchanger is associated with a fan wall and a refrigerant-based cooling system to provide air cooling and refrigerant-based cooling to cool secondary coolant or fluid received from at least one cold plate.

IPC Classes  ?

  • H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
  • G06N 3/04 - Architecture, e.g. interconnection topology

72.

PERFORMANCE OF RAY-TRACED SHADOW CREATION WITHIN A SCENE

      
Application Number 19212469
Status Pending
Filing Date 2025-05-19
First Publication Date 2025-09-04
Owner NVIDIA Corporation (USA)
Inventor
  • Story, Jon
  • Gruen, Holger Heinrich

Abstract

A ray (e.g., a traced path of light, etc.) is generated from an originating pixel within a scene being rendered. Additionally, one or more shadow map lookups are performed for the originating pixel to estimate an intersection of the ray with alpha-tested geometry within the scene. A shadow map stores the distance of geometry as seen from the point of view of the light, and alpha-tested geometry includes objects within the scene being rendered that have a determined texture and opacity. Further, the one or more shadow map lookups are performed to determine a visibility value for the pixel (e.g., that identifies whether the originating pixel is in a shadow) and a distance value for the pixel (e.g., that identifies how far the pixel is from the light). Further still, the visibility value and the distance value for the pixel are passed to a denoiser.

IPC Classes  ?

73.

IN-PLACE DATA MANAGEMENT WITHIN MEMORY BUFFERS

      
Application Number 18591882
Status Pending
Filing Date 2024-02-29
First Publication Date 2025-09-04
Owner Nvidia Corporation (USA)
Inventor
  • Viitanen, Timo Tapani
  • Lindqvist, Anders Jakob

Abstract

Approaches presented herein provide systems and methods for reading a portion of data from an unprocessed memory segment to a registry and changing a status identifier for the unprocessed memory segment indicative of the data being read to the registry. The data may then be written to a destination memory segment from the registry. If a corresponding status identifier for the destination memory segments meets a value indicative that the destination memory segment has not yet been read into the registry, it may be read into the registry before overwriting it, and recursively written into its own destination memory segment.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
  • G06T 1/60 - Memory management

74.

ASYNCHRONOUS RELEASE OPERATIONS IN A MULTIPROCESSOR SYSTEM

      
Application Number 18593817
Status Pending
Filing Date 2024-03-01
First Publication Date 2025-09-04
Owner NVIDIA CORPORATION (USA)
Inventor
  • Patel, Manan
  • Tanasic, Ivan
  • Marcovitch, Daniel
  • Parker, Michael Allen
  • Madugula, Srinivas Santosh Kumar
  • L, Raghuram
  • Gandhi, Wishwesh Anil
  • Giroux, Olivier

Abstract

Various embodiments include techniques for performing memory synchronization operations between processors in a multiprocessor computing system. A first processor transfers data by issuing memory operations to store the data to a shared memory. The first processor issues an asynchronous release operation to a load store unit. In response, the load store unit issues a memory synchronization operation to ensure that the data associated with the memory operations is visible in the shared memory. While the asynchronous release operation is pending, the first processor is able to issue further instructions and perform other operations. When the data associated with the memory operations is visible in the shared memory, the memory synchronization operation completes and the load store unit writes a flag to a separate memory location. Upon detecting that the flag has been written, a second thread, and/or other threads, can reliably read the data stored in the shared memory.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

75.

ACCELERATING GROUND TRUTH ANNOTATION USING ARTIFICIAL INTELLIGENCE

      
Application Number 18604129
Status Pending
Filing Date 2024-03-13
First Publication Date 2025-09-04
Owner Nvidia Corporation (USA)
Inventor
  • Skinner, James Michael
  • Xia, Tian
  • Lu, Yi
  • Wekel, Tilman

Abstract

Approaches presented herein provide for the acceleration of a human review process, such as the review of annotations generated by a human labeler. Annotations (at least partially) generated by a human reviewer can be provided as input to a machine learning model trained to infer a probability of the annotations including at least one error. Annotations with a low probability of including an error can be approved automatically, while annotations with a high probability (e.g., above a threshold) of including an error can be directed for human review. In order to keep the human reviewer engaged, artificial errors may be introduced at various times based on various engagement criteria.

IPC Classes  ?

  • G06N 20/00 - Machine learning
  • G06N 7/01 - Probabilistic graphical models, e.g. probabilistic networks

76.

LABEL-LOOPING PREDICTION FOR AUTOMATIC SPEECH RECOGNITION AND OTHER AI SYSTEMS

      
Application Number 18820028
Status Pending
Filing Date 2024-08-29
First Publication Date 2025-09-04
Owner NVIDIA Corporation (USA)
Inventor
  • Bataev, Vladimir
  • Xu, Hainan
  • Lavrukhin, Vitaly
  • Ginsburg, Boris

Abstract

Disclosed are apparatuses, systems, and techniques that use label-looping processing for efficient automatic speech recognition (ASR). The techniques include performing a plurality of iterations of an outer processing loop to identify content units (CUs) of a media item having multiple frames. An individual iteration of the outer processing loop includes updating, using a first neural network (NN) and identified non-blank CU, a state of the media item and performing one or more iterations of an inner processing loop. An individual iteration of the inner processing loop includes processing, using a second NN, the state of the media item and an individual frame to predict a CU associated with the individual frame. The iterations of the inner processing loop are performed until the predicted CU corresponds to a non-blank CU. The identified plurality of CUs is used to generate a representation of the media item.

IPC Classes  ?

  • G10L 15/16 - Speech classification or search using artificial neural networks

77.

MAGNETIC FLUX CANCELLATION INDUCTOR PAIRING

      
Application Number CN2024079107
Publication Number 2025/179501
Status In Force
Filing Date 2024-02-28
Publication Date 2025-09-04
Owner NVIDIA CORPORATION (USA)
Inventor
  • Gorla, Gabriele
  • Shu, Charlie J.
  • Wang, Chen
  • Jackson, Charles

Abstract

In various embodiments, an inductor package comprises a first inductor that is arranged in a first orientation and produces a first magnetic flux in a first direction; and a second inductor that is arranged in a second orientation and produces a second magnetic flux in a second direction that at least partially cancels the first magnetic flux, where the first direction is opposite the second direction. In some embodiments, a printed circuit board assembly comprises a printed circuit board (PCB) layer, a first inductor that is arranged on the PCB layer at a first orientation and produces a first magnetic flux in a first direction, and a second inductor that is arranged on the PCB layer at a second orientation and produces a second magnetic flux in a second direction that at least partially cancels the first magnetic flux.

IPC Classes  ?

  • H01F 17/04 - Fixed inductances of the signal type with magnetic core

78.

OBSTACLE TO PATH ASSIGNMENT FOR AUTONOMOUS SYSTEMS AND APPLICATIONS

      
Application Number 19191529
Status Pending
Filing Date 2025-04-28
First Publication Date 2025-09-04
Owner NVIDIA Corporation (USA)
Inventor
  • Sajjan, Neeraj
  • Kocamaz, Mehmet K.
  • Kwon, Junghyun
  • Oh, Sangmin
  • Park, Minwoo
  • Nister, David

Abstract

In various examples, one or more output channels of a deep neural network (DNN) may be used to determine assignments of obstacles to paths. To increase the accuracy of the DNN, the input to the DNN may include an input image, one or more representations of path locations, and/or one or more representations of obstacle locations. The system may thus repurpose previously computed information—e.g., obstacle locations, path locations, etc.—from other operations of the system, and use them to generate more detailed inputs for the DNN to increase accuracy of the obstacle to path assignments. Once the output channels are computed using the DNN, computed bounding shapes for the objects may be compared to the outputs to determine the path assignments for each object.

IPC Classes  ?

  • G05D 1/00 - Control of position, course, altitude or attitude of land, water, air or space vehicles, e.g. using automatic pilots
  • G06N 3/08 - Learning methods

79.

TRANSIENT CURRENT-MODE SIGNALING SCHEME FOR ON-CHIP INTERCONNECT FABRICS

      
Application Number 19193723
Status Pending
Filing Date 2025-04-29
First Publication Date 2025-09-04
Owner NVIDIA Corp. (USA)
Inventor
  • Liang, Jiale
  • Raja, Tezaswi
  • Satheesh, Suhas
  • Rasheed, Shalimar
  • Ajwani, Gaurav
  • Ranjith Kumar, Ram Kumar
  • Mehta, Miloni

Abstract

Circuits that include one or more transmission lines to propagate a signal through a serially-arranged plurality of repeaters, and one or more control circuits to propagate control pulses to the repeaters, wherein a timing and duration of the control pulses is configured to operate the repeaters in current-mode signaling (CMS) mode during a state transition of the signal at the repeaters and to operate the repeaters in voltage-mode signaling (VMS) mode otherwise.

IPC Classes  ?

  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
  • H03K 5/01 - Shaping pulses

80.

DENOISING DIFFUSION GENERATIVE ADVERSARIAL NETWORKS

      
Application Number 19207065
Status Pending
Filing Date 2025-05-13
First Publication Date 2025-09-04
Owner Nvidia Corporation (USA)
Inventor
  • Xiao, Zhisheng
  • Kreis, Karsten
  • Vahdat, Arash

Abstract

Apparatuses, systems, and techniques are presented to train and utilize one or more neural networks. A denoising diffusion generative adversarial network (denoising diffusion GAN) reduces a number of denoising steps during a reverse process. The denoising diffusion GAN does not assume a Gaussian distribution for large steps of the denoising process and applies a multi-model model to permit denoising with fewer steps. Systems and methods further minimize a divergence between a diffused real data distribution and a diffused generator distribution over several timesteps. Accordingly, various embodiments may enable faster sample generation, in which the samples are generated from noise using the denoising diffusion GAN.

IPC Classes  ?

81.

OVERVOLTAGE AND UNDERVOLTAGE DETECTOR

      
Application Number 19209610
Status Pending
Filing Date 2025-05-15
First Publication Date 2025-09-04
Owner NVIDIA Corporation (USA)
Inventor
  • Akkur, Abhishek
  • Raja, Tezaswi

Abstract

The disclosure provides a voltage detecting circuit that detects voltage increases and voltage decreases using a diode drop and voltage thresholds. The voltage detecting circuit, referred to as a voltage variation detector, uses the diode to maintain a differential between the voltage being monitored and a voltage threshold. When the diode is reversed bias, the voltage variation detector generates a detecting signal indicating the monitored voltage crossed the voltage threshold. In one example, the method includes: (1) detecting at least one transition of a voltage across a voltage threshold, wherein the detecting is based on a transistor diode being reversed biased, (2) generating a detection signal when the voltage crosses the voltage threshold, and (3) performing one or more actions in response to the detection signal.

IPC Classes  ?

  • G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
  • G01R 19/17 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values giving an indication of the number of times this occurs
  • H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage

82.

MAGNETIC FIELD CANCELLATION BASED ON WIRE ROUTING

      
Application Number CN2024079106
Publication Number 2025/179500
Status In Force
Filing Date 2024-02-28
Publication Date 2025-09-04
Owner NVIDIA CORPORATION (USA)
Inventor
  • Wang, Chen
  • Zheng, Ziyuan
  • Zhao, Mengli
  • Zhang, Cheng

Abstract

In various embodiments, an inductor package comprises a first portion of an inductor coil that runs substantially along a first axis and carries an electrical current along the first axis in a first direction to produce a first magnetic flux, and a second portion of the inductor coil that runs substantially along the first axis and carries the electrical current along the first axis in a second direction to produce a second magnetic flux that at least partially cancels the first magnetic flux, where the first direction is opposite the second direction.

IPC Classes  ?

  • G06F 1/16 - Constructional details or arrangements

83.

Neural network training method

      
Application Number 17141005
Grant Number 12406023
Status In Force
Filing Date 2021-01-04
First Publication Date 2025-09-02
Grant Date 2025-09-02
Owner NVIDIA Corporation (USA)
Inventor
  • Alvarez Lopez, Jose Manuel
  • Chawla, Akshay
  • Molchanov, Pavlo
  • Yin, Hongxu

Abstract

Apparatuses, systems, and techniques to generate images of objects. In at least one embodiment, one or more neural networks are trained to identify one or more objects within one or more images, and the one or more neural networks are used to generate an image of one or more objects.

IPC Classes  ?

84.

3D digital avatar generation from a single or few portrait images

      
Application Number 18185217
Grant Number 12406422
Status In Force
Filing Date 2023-03-16
First Publication Date 2025-09-02
Grant Date 2025-09-02
Owner NVIDIA Corporation (USA)
Inventor
  • Nagano, Koki
  • Seo, Jaewoo

Abstract

A system and method for generating a digital avatar from a two-dimensional input image in accordance with a machine learning models is provided. The machine learning models are generative adversarial networks trained to process a latent code into three-dimensional data and color data. A generative adversarial network (GAN) inversion optimization algorithm is run on the first machine learning model to map the input image to a latent code for the first machine learning model. The latent code is used to generate unstructured 3D data and color information. A GAN inversion optimization algorithm is then run on the second machine learning model to determine a latent code for the second machine learning model, based at least on the output of the first machine learning model. The latent code for the second machine learning model is then used to generate the data for the digital avatar.

IPC Classes  ?

  • G06T 13/40 - 3D [Three Dimensional] animation of characters, e.g. humans, animals or virtual beings
  • G06T 13/80 - 2D animation, e.g. using sprites

85.

GTC

      
Serial Number 99365107
Status Pending
Filing Date 2025-08-29
Owner NVIDIA Corporation ()
NICE Classes  ? 41 - Education, entertainment, sporting and cultural services

Goods & Services

Arranging and conducting educational conferences, seminars, classes, workshops, courses, webinars, exhibitions, and trade shows; Arranging and conducting educational conferences, seminars, classes, workshops, courses, webinars, exhibitions, and trade shows in the fields of technology, business, software development, hardware development, artificial intelligence, machine learning, deep learning, large language models (LLMs), natural language generation, statistical learning, supervised learning, un-supervised learning, predictive analytics, business intelligence, accelerated computing, edge computing, high performance computing, computer graphics hardware, graphics processing units (gpus), electronics, data science, autonomous machines, robotics, virtual reality, augmented reality, cybersecurity, data storage, cloud computing.

86.

NVIDIA GTC

      
Serial Number 99365109
Status Pending
Filing Date 2025-08-29
Owner NVIDIA Corporation ()
NICE Classes  ? 41 - Education, entertainment, sporting and cultural services

Goods & Services

Arranging and conducting educational conferences, seminars, classes, workshops, courses, webinars, exhibitions, and trade shows; Arranging and conducting educational conferences, seminars, classes, workshops, courses, webinars, exhibitions, and trade shows in the fields of technology, business, software development, hardware development, artificial intelligence, machine learning, deep learning, large language models (LLMs), natural language generation, statistical learning, supervised learning, un-supervised learning, predictive analytics, business intelligence, accelerated computing, edge computing, high performance computing, computer graphics hardware, graphics processing units (gpus), electronics, data science, autonomous machines, robotics, virtual reality, augmented reality, cybersecurity, data storage, cloud computing.

87.

MODEL-BASED PROCESSING TO REDUCE REACTION TIMES FOR CONTENT STREAMING SYSTEMS AND APPLICATIONS

      
Application Number 18800563
Status Pending
Filing Date 2024-08-12
First Publication Date 2025-08-28
Owner NVIDIA Corporation (USA)
Inventor
  • Patney, Anjul
  • Mazumdar, Amrita
  • Russell, Andrew Ian
  • Gnanasekaran, Kumaresan
  • Schneider, Seth
  • Brown, Rachel
  • Tarrazo, Roland
  • Goyal, Shishir
  • Banerjee, Ankan
  • Mawdsley, Jason
  • Bernal, Ariel Juan
  • Siman, Guillermo

Abstract

In various examples, model-based processing to reduce reaction times for content streaming systems and applications is described herein. Systems and methods are disclosed that use one or more machine learning models to process image data representative of frames of an application, such as a gaming application, in order to generate updated imaged data representative of one or more updated frames that help reduce reaction times for users. For instance, the machine learning model(s) may update one or more visual characteristics associated with the frames, such as a contrast, a brightness, and/or a saturation associated with the frames. As described herein, the machine learning model(s) may be trained to update the frames in order to reduce the reaction times of users, such as by using one or more loss functions that measure loss in predicted reactions times and/or loss associated with visual characteristics of frames.

IPC Classes  ?

  • G06T 19/20 - Editing of 3D images, e.g. changing shapes or colours, aligning objects or positioning parts
  • A63F 13/213 - Input arrangements for video game devices characterised by their sensors, purposes or types comprising photodetecting means, e.g. cameras, photodiodes or infrared cells

88.

TECHNIQUES FOR INTERPRETABLE CLASSIFICATION VIA MULTI-LEVEL CONCEPT PROTOTYPES

      
Application Number 18882563
Status Pending
Filing Date 2024-09-11
First Publication Date 2025-08-28
Owner NVIDIA CORPORATION (USA)
Inventor Wang, Chien-Yi

Abstract

One embodiment of a method for classifying data includes processing the data via a trained machine learning model that includes a plurality of layers, where each layer generates one or more corresponding features, generating a first distribution of features based on the one or more corresponding features generated by each layer included in the plurality of layers, and determining a first class for the data based on a comparison of the first distribution of features with one or more predefined distributions of features that are associated with one or more classes.

IPC Classes  ?

  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
  • G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries

89.

MACHINE-LEARNING-BASED ARCHITECTURE SEARCH METHOD FOR A NEURAL NETWORK

      
Application Number 18939300
Status Pending
Filing Date 2024-11-06
First Publication Date 2025-08-28
Owner NVIDIA Corporation (USA)
Inventor
  • Vahdat, Arash
  • Mallya, Arun Mohanray
  • Liu, Ming-Yu
  • Kautz, Jan

Abstract

In at least one embodiment, differentiable neural architecture search and reinforcement learning are combined under one framework to discover network architectures with desired properties such as high accuracy, low latency, or both. In at least one embodiment, an objective function for search based on generalization error prevents the selection of architectures prone to overfitting.

IPC Classes  ?

  • G06N 3/04 - Architecture, e.g. interconnection topology
  • G05B 13/02 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric
  • G06F 7/57 - Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups or for performing logical operations
  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
  • G06N 3/08 - Learning methods

90.

DISAGGREGATED SERVER ARCHITECTURE

      
Application Number 19062781
Status Pending
Filing Date 2025-02-25
First Publication Date 2025-08-28
Owner NVIDIA CORPORATION (USA)
Inventor
  • Mentovich, Elad
  • Albright, Ryan
  • Wells, Ryan
  • Yu, Lisa
  • Fields, Jr., James Stephen
  • Daley, James Bernard
  • Darbha, Rama
  • Gafni, Barak
  • Whidden, Nick

Abstract

Systems, devices, and methods for disaggregating networking components are provided. An example networking chassis includes a first disaggregated server device supported by the networking chassis that includes a first central processing unit (CPU) and a first graphics processing unit (GPU) coupled with the first CPU. The networking chassis further includes a first insertable switch module communicably coupled with the first disaggregated server device that includes first switching chipsets and a first fabric management controller coupled with the first switching chipsets. The first insertable switch module at least partially controls data transmission associated with the first disaggregated server device. The first GPU of the first disaggregated server device is isolated on the first disaggregated server device, supported on the first disaggregated server device in the absence of other GPUs, or is otherwise the only GPU on the first disaggregated server device so as to provide modularity in networking applications.

IPC Classes  ?

  • H05K 7/14 - Mounting supporting structure in casing or on frame or rack
  • G06F 1/18 - Packaging or power distribution
  • H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

91.

REGION-AWARE VISION LANGUAGE PROCESSOR

      
Application Number 19065367
Status Pending
Filing Date 2025-02-27
First Publication Date 2025-08-28
Owner NVIDIA Corp. (USA)
Inventor
  • Guo, Qiushan
  • De Mello, Shalini
  • Yin, Hongxu
  • Byeon, Wonmin
  • Cheung, Ka Chun
  • See, Simon Chong-Wee
  • Kautz, Jan
  • Liu, Sifei

Abstract

Visual language processors that include an image encoder configured to convert an image into a low-resolution feature map, a feature refinement network configured to upsample the low-resolution feature map into a high-resolution feature map, and a visual-language connector configured to map an image-level feature map and a region-level feature map both derived from the high-resolution feature map into an embedding space of a language encoder.

IPC Classes  ?

  • G06V 10/771 - Feature selection, e.g. selecting representative features from a multi-dimensional feature space
  • G06V 20/70 - Labelling scene content, e.g. deriving syntactic or semantic representations

92.

MULTICAST AND REFLECTIVE MEMORY BEHAVIOR FOR MEMORY MODEL CONSISTENCY

      
Application Number 19202282
Status Pending
Filing Date 2025-05-08
First Publication Date 2025-08-28
Owner NVIDIA Corporation (USA)
Inventor
  • Dearth, Glenn Alan
  • Hummel, Mark
  • Lustig, Daniel Joseph

Abstract

In various examples, a memory model may support multicasting where a single request for a memory access operation may be propagated to multiple physical addresses associated with multiple processing elements (e.g., corresponding to respective local memory). Thus, the request may cause data to be read from and/or written to memory for each of the processing elements. In some examples, a memory model exposes multicasting to processes. This may include providing for separate multicast and unicast instructions or shared instructions with one or more parameters (e.g., indicating a virtual address) being used to indicate multicasting or unicasting. Additionally or alternatively, whether a request(s) is processed using multicasting or unicasting may be opaque to a process and/or application or may otherwise be determined by the system. One or more constraints may be imposed on processing requests using multicasting to maintain a coherent memory interface.

IPC Classes  ?

  • G06F 12/1072 - Decentralised address translation, e.g. in distributed shared memory systems
  • G06F 12/02 - Addressing or allocationRelocation
  • G06F 12/10 - Address translation
  • G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
  • G06F 12/109 - Address translation for multiple virtual address spaces, e.g. segmentation
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

93.

Cooperative Group Arrays

      
Application Number 19205313
Status Pending
Filing Date 2025-05-12
First Publication Date 2025-08-28
Owner NVIDIA Corporation (USA)
Inventor
  • Palmer, Greg
  • Hirota, Gentaro
  • Krashinsky, Ronny
  • Long, Ze
  • Pharris, Brian
  • Dash, Rajballav
  • Tuckey, Jeff
  • Duluk, Jr., Jerome F.
  • Shah, Lacky
  • Durant, Luke
  • Choquette, Jack
  • Werness, Eric
  • Govil, Naman
  • Patel, Manan
  • Deb, Shayani
  • Navada, Sandeep
  • Edmondson, John
  • Bangalore Prabhakar, Prakash
  • Gandhi, Wish
  • Manyam, Ravi
  • Parle, Apoorv
  • Giroux, Olivier
  • Gadre, Shirish
  • Heinrich, Steve

Abstract

A new level(s) of hierarchy—Cooperate Group Arrays (CGAs)—and an associated new hardware-based work distribution/execution model is described. A CGA is a grid of thread blocks (also referred to as cooperative thread arrays (CTAs)). CGAs provide co-scheduling, e.g., control over where CTAs are placed/executed in a processor (such as a GPU), relative to the memory required by an application and relative to each other. Hardware support for such CGAs guarantees concurrency and enables applications to see more data locality, reduced latency, and better synchronization between all the threads in tightly cooperating collections of CTAs programmably distributed across different (e.g., hierarchical) hardware domains or partitions.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
  • G06F 9/54 - Interprogram communication

94.

THERMAL ENVIRONMENT EVALUATION AND COMPENSATION FOR COMPUTER COMPONENTS

      
Application Number 19205720
Status Pending
Filing Date 2025-05-12
First Publication Date 2025-08-28
Owner NVIDIA Corporation (USA)
Inventor
  • Lin, Qi
  • Haley, David
  • Plummer, Chad
  • Schulze, Hans
  • Moore, Darryl

Abstract

The disclosure provides a cooling solution that evaluates the thermal environment of a computer component based on transient thermal responses of the computer component. The transient thermal responses are generated by measuring the temperature rise of the computer component over a designated amount of time for multiple “good” assemblies and multiple “bad” assemblies to determine a duration and allowable temperature rise needed to set a pass/fail criteria for different failure modes of cooling devices. A cooling device may not be operating as designed due to damage, needed maintenance, missing thermal interface material (TIM), improper installation, etc. From the transient thermal responses, a thermal problem, such as a malfunctioning fan, can be determined and a corrective action can be performed.

IPC Classes  ?

  • G06F 1/20 - Cooling means
  • G01K 7/42 - Circuits effecting compensation of thermal inertiaCircuits for predicting the stationary value of a temperature
  • G01M 99/00 - Subject matter not provided for in other groups of this subclass
  • G05B 19/404 - Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by control arrangements for compensation, e.g. for backlash, overshoot, tool offset, tool wear, temperature, machine construction errors, load, inertia
  • H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

95.

IMAGE STITCHING WITH COLOR HARMONIZATION FOR SURROUND VIEW SYSTEMS AND APPLICATIONS

      
Application Number 19207445
Status Pending
Filing Date 2025-05-14
First Publication Date 2025-08-28
Owner NVIDIA CORPORATION (USA)
Inventor
  • Ren, Yuzhuo
  • Pajak, Dawid Stanislaw
  • Avadhanam, Niranjan
  • Dai, Guangli

Abstract

In various examples, color statistic(s) from ground projections are used to harmonize color between reference and target frames representing an environment. The reference and target frames may be projected onto a representation of the ground (e.g., a ground plane) of the environment, an overlapping region between the projections may be identified, and the portion of each projection that lands in the overlapping region may be taken as a corresponding ground projection. Color statistics (e.g., mean, variance, standard deviation, kurtosis, skew, correlation(s) between color channels) may be computed from the ground projections (or a portion thereof, such as a majority cluster) and used to modify the colors of the target frame to have updated color statistics that match those from the ground projection of the reference frame, thereby harmonizing color across the reference and target frames.

IPC Classes  ?

  • G06V 20/56 - Context or environment of the image exterior to a vehicle by using sensors mounted on the vehicle
  • G06T 7/90 - Determination of colour characteristics
  • G06T 15/20 - Perspective computation
  • G06V 10/10 - Image acquisition
  • G06V 10/25 - Determination of region of interest [ROI] or a volume of interest [VOI]
  • G06V 10/56 - Extraction of image or video features relating to colour

96.

ASYNCHRONOUS CONTROL OF PHASE SHIFT USING AN INJECTION-LOCKED-OSCILLATOR-BASED PHASE ROTATOR

      
Application Number 18584154
Status Pending
Filing Date 2024-02-22
First Publication Date 2025-08-28
Owner NVIDIA Corporation (USA)
Inventor
  • Huang, Yi-Chieh
  • Chen, Bo-Yu
  • Weng, Po-Shuan
  • Wei, Ying

Abstract

A circuit includes a phase selector to generate an injection clock signal having an injection phase based on a phase of a digitally controlled oscillator clock signal generated within a phase-locking feedback loop. An injection-locked oscillator (ILO), coupled to an output of the phase selector, generates an ILO clock signal that is convertible to provide a feedback clock signal of the circuit. Logic, coupled between an output of the ILO and the phase selector, to, at each predetermined number of cycles of the DCO clock signal, cause the phase selector to output a phase shift in the injection clock signal that causes the ILO clock signal to comprise a rotated phase, relative to the injection phase, and that prevents a glitch in the injection clock signal.

IPC Classes  ?

  • H03K 5/01 - Shaping pulses
  • H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
  • H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

97.

PARTITION-AWARE BROADCAST OPERATION FILTERING IN A MULTIPROCESSOR SYSTEM

      
Application Number 18584772
Status Pending
Filing Date 2024-02-22
First Publication Date 2025-08-28
Owner NVIDIA CORPORATION (USA)
Inventor
  • Streat, Lennard
  • Zhao, Yudong
  • Kulkarni, Vaishali
  • Milne, Timothy Ian
  • Maurya, Ashish Kumar
  • Bhattacharya, Debajit
  • Gandhi, Wishwesh Anil

Abstract

Various embodiments include techniques for processing broadcast operations in a computing system. Typically, broadcast operations are transmitted to all portions of a particular subsystem, such as all cache slices in a cache memory. As a result, a process that issues a broadcast operation can interfere with one or more other processes that access portions of the subsystem not assigned to the process. To prevent such interference, logic in the computing system filters broadcast operations so as to transmit the broadcast operation to only the relevant portions assigned to the process that issued the broadcast operation. The logic tracks acknowledgments from the relevant portions and, when all pending acknowledgments have been received, the logic transmits a single acknowledgement to the process that issued the broadcast operation. The logic is dynamically configurable such that the logic can change the portions of the subsystem assigned to each process as needed.

IPC Classes  ?

98.

DETERMINING EMOTIONAL STATES FOR SPEECH IN DIGITAL AVATAR SYSTEMS AND APPLICATIONS

      
Application Number 18587004
Status Pending
Filing Date 2024-02-26
First Publication Date 2025-08-28
Owner NVIDIA Corporation (USA)
Inventor
  • Fedorov, Ilia
  • Korobchenko, Dmitry

Abstract

In various examples, determining emotional states for speech in conversational artificial intelligence (AI) and/or digital avatar systems and applications is descried herein. Systems and methods are disclosed that use one or more machine learning models to determine one or more emotional states associated with speech, where the machine learning model(s) may be trained using various processes. For instance, in some examples, the machine learning model(s) may be trained during a first training process to determine probabilities for distributions of values, where the distributions model different emotional states. For example, a distribution may include a first value for angry, a second value for happy, a third value for sad, and/or so forth. Additionally, or alternatively, in some examples, the machine learning model(s) may be trained during a second training process to more precisely determine the actual emotional states (and/or the probabilities) based on training data representing human feedback.

IPC Classes  ?

  • G06T 13/20 - 3D [Three Dimensional] animation
  • G06N 7/01 - Probabilistic graphical models, e.g. probabilistic networks
  • G06T 13/40 - 3D [Three Dimensional] animation of characters, e.g. humans, animals or virtual beings
  • G10L 15/06 - Creation of reference templatesTraining of speech recognition systems, e.g. adaptation to the characteristics of the speaker's voice
  • G10L 25/57 - Speech or voice analysis techniques not restricted to a single one of groups specially adapted for particular use for comparison or discrimination for processing of video signals
  • G10L 25/63 - Speech or voice analysis techniques not restricted to a single one of groups specially adapted for particular use for comparison or discrimination for estimating an emotional state

99.

SUPPLEMENTING SENSOR DATA FOR PROCESSING USING AI SYSTEMS AND APPLICATIONS

      
Application Number 18587028
Status Pending
Filing Date 2024-02-26
First Publication Date 2025-08-28
Owner NVIDIA Corporation (USA)
Inventor
  • Rathi, Swapnil
  • Rupde, Bhushan
  • Purandare, Kaustubh

Abstract

In various examples, processing sensor data using rankings for AI systems and applications is described herein. Systems and methods are disclosed that determine rankings for sensor data, where the rankings may then be used to process the sensor data. For instance, a device that generates sensor data using a sensor may determine rankings for various portions of the sensor data, such as by analyzing the sensor data and/or related sensor data to detect configured events. For example, if the sensor data includes image data, then the device may determine a respective ranking for different groups of frames that are associated with different events. A system(s) that then use the rankings when processing the sensor data using one or more processing tasks. For example, the system(s) may determine which processing tasks to use for processing different portions of the sensor data based at least on the rankings.

IPC Classes  ?

  • G06V 10/96 - Management of image or video recognition tasks
  • G06V 20/50 - Context or environment of the image
  • H04N 19/46 - Embedding additional information in the video signal during the compression process

100.

PIXEL GENERATION TECHNIQUE

      
Application Number 18589214
Status Pending
Filing Date 2024-02-27
First Publication Date 2025-08-28
Owner NVIDIA Corporation (USA)
Inventor
  • Barnes, Levi Daniel
  • Sastry Kunigal, Kumara Narasimha
  • Luitjens, Justin Paul
  • Swanson, John Arthur
  • Pinzone, Benjamin Frank

Abstract

Apparatuses, systems, and techniques are to represent polygon data as pixels as part of a rasterization process. In at least one embodiment, a processor causes identification of pixels within a polygon based, at least in part, on one or more prefix sums of amounts of edges of pixels. covered by that polygon.

IPC Classes  ?

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