Embodiments herein describe a memory controller (MC) in a first integrated circuit (IC) that connect to circuitry in the same integrated circuit (e.g., horizontal direction) and to circuitry in a second IC in the vertical direction. That is, the first and second ICs can be stacked on each other where the MC in the first IC provides an interface for both circuitry in the first IC as well as circuitry in the second IC to communicate with a separate memory device. Thus, the MC includes data paths in both the X direction (e.g., within the same IC) and the Y direction (e.g., to an external IC). In this manner, the MC can provide an interface for circuitry in multiple ICs (or dies or chiplets) to the same external memory device.
A system for packing data includes a controller configured to receive compressed data. The compressed data includes data items and qualifier bits for the data items. The controller is configured to discard the data items designated as invalid by the qualifier bits. The controller is configured to generate data type bits specifying data type information for the data items designated as valid by the qualifier bits. The system includes a buffer. The controller is configured to store the data items designated as valid by the qualifier bits and the data type bits in the buffer. A system can include one or more decoders configured to decode encoded data and output literals, lengths, and distances.
A system includes a plurality of controller circuits. The system includes a plurality of target circuits. The system includes a communication bus communicatively linking the plurality of controller circuits with the plurality of target circuits. The communication bus includes a plurality of switches. Each switch of the plurality of switches is connected to a different one of the plurality of controller circuits.
Accelerated circuit design test coverage closure includes generating, by computer hardware, constraint ranges for input variables for a circuit design based on constraints for the input variables. A first value set for a verification testbench for the circuit design is generated. The first value set includes randomly generated values for the input variables constrained based on the constraint ranges. Whether the first value set is unique is detected by comparing the first value set with training value sets of a training corpus. In response to detecting that the first value set is unique, the first value is classified set by assigning a label selected from a plurality of labels to the first value set and adding the first value set to the training corpus.
The examples describe a chip package including an interposer including at least one embedded deep trench capacitor (eDTC) and at least one of an inductor, a T-coil, or a combination thereof and logic chips electrically connected to the interposer. The at least one eDTC is disposed in a different material layer of the interposer than the at least one of the inductor, the T-coil, or the combination thereof. The at least one of the inductor, the T-coil, or the combination thereof are disposed within a keep-out zone (KOZ). The at least one of the inductor, the T-coil, or the combination thereof are disposed in an upper layer of the interposer.
A hardware accelerator is described that includes an array of data processing engines (DPEs) which can execute multiple applications (or multiple different workloads) in the same column. For example, a column may include four DPEs where two of the DPEs execute a first application and the other two DPEs execute a second application, or one of the DPEs executes the first application and the other three DPEs execute the second application. This gives a programmer additionally flexibility to determine how to assign applications to the hardware accelerator.
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
7.
DETECTING AND CORRECTING SINGLE EVENT UPSETS IN STATIC RANDOM-ACCESS MEMORY CELLS
A memory circuit includes a memory cell including a plurality of inverter pairs. The plurality of inverter pairs include a first inverter pair and one or more reference inverter pairs. The plurality of inverter pairs are coupled by access transistors to same bit lines and to a same word line. The memory circuit includes a detector circuit coupled to the plurality of inverter pairs. The detector circuit is capable of generating an indicator signal in response to detecting a single-event upset (SEU) in the memory cell by detecting a mismatch in stored states among the plurality of inverter pairs of the memory cell. The memory circuit may include a correction circuit capable of correcting an output of the memory cell.
An apparatus and method for efficiently performing efficient data storage and data transfer of machine learning data. In various implementations, one of the multiple processing circuits of the computing system retrieves matrix of machine learning (ML) model weights (or weights). The processing circuit performs magnitude normalization across one or more channel dimensions of the matrix of weights. The processing circuit performs activation magnitude normalization across one of the channel dimensions of the input activation values. The processing circuit generates a pruning mask for the matrix of weights based on a combination of the weight magnitude normalization and the activation magnitude normalization.
An apparatus and method for efficiently performing efficient data storage and data transfer of machine learning data. In various implementations, one of the multiple processing circuits of the computing system retrieves matrix of machine learning (ML) model weights (or weights). The processing circuit generates the Kronecker product for each vector (row) of the retrieved query weights matrix. The processing circuit replaces, for each vector (row), each element of the vector (row) with a self-multiplication term. The processing circuit scales, for each vector (row), each element of the vector (row) where the scales are dependent on the denominator of the terms. The processing circuit performs these steps for each element of each vector (row) of the key weights matrix. The processing circuit generates the dot product of the transformed query weights matrix and the transformed key weights matrix.
G06F 17/17 - Function evaluation by approximation methods, e.g. interpolation or extrapolation, smoothing or least mean square method
G06F 7/78 - Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffersOverflow or underflow handling therefor
10.
OPTIMAL MEMORY CONFIGURATIONS IN A SILICON INTERPOSER FOR HIGH-SPEED DRAM
The examples describe a chip package including an interposer including at least one embedded deep trench capacitor (eDTC) and at least one of an inductor, a T-coil, or a combination thereof and logic chips electrically connected to the interposer. The at least one eDTC is disposed in a different material layer of the interposer than the at least one of the inductor, the T-coil, or the combination thereof. The at least one of the inductor, the T-coil, or the combination thereof are disposed within a keep-out zone (KOZ). The at least one of the inductor, the T-coil, or the combination thereof are disposed in an upper layer of the interposer.
An integrated circuit (IC) device includes functional circuitry and distributed management circuitry that includes multiple configuration interface manager (CIM) circuits that receive respective programming partitions as configuration packets over a first communication channel (e.g., a network-on-chip, or NoC), and perform management operations on respective regions of the functional circuitry in parallel with one another based on the respective configuration packets, including providing configuration parameters to the respective regions of the functional circuitry. The configuration packets may be streamed to the CIM circuits from a central manager and/or read by direct memory access (DMA) engines of the CIM circuits. The central manager may configure the CIM circuits and the NoC over a second communication channel (e.g., a global communication ring interconnect) during an initialization phase. The CIM circuits may include respective packet processors, random-access-memory, authentication circuitry, error detection circuitry, and interconnect circuitry having standardized bus-widths.
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
Embodiments herein describe a configurable engine that is embedded into the cache hierarchy of a processor. The configurable engine can enable efficient data sharing between the main memory, cache memories, and the core. The configurable engine can perform operations that are more efficient to be done in the cache hierarchy. In one embodiment, the configurable engine is controlled (or configured) by software (e.g., the operating system (OS)), adapting to each application domain. That is, the OS can configure the engine according to a data flow profile of a particular application being executed by the processor.
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 12/084 - Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
13.
DIRECT BROADCASTING OF CALCULATED SUMS BETWEEN ACCUMULATORS IN A MULTI-CORE SPATIAL ARCHITECTURE
An accumulator broadcast network is described that permits an accumulator in one core of a multi-core IC to transmit high-precision data to accumulators in multiple cores in parallel. That is, instead of a sending data to local memory and the broadcasting to different cores using shared memory or messaging protocols, the data stored in the accumulator registers can be directly transmitted to other accumulators.
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
Automated verification and generation of coverage data for a circuit design includes generating, by computer hardware, valid value ranges for coverpoint variables of a circuit design based on constraints for the coverpoint variables. A regression test is run on the circuit design using a verification testbench to generate test results and sampled values for the coverpoint variables. The sampled values of the coverpoint variables from the regression test are classified by a machine learning model based on the test results. Coverage data for the regression test is generated by the computer hardware by assigning the sampled values of the coverpoint variables to different ones of a plurality of bins based on the classifying.
An integrated circuit (IC) includes a clock modulation circuitry including a delay hierarchy circuitry coupled to the register, the delay hierarchy circuitry configured to receive a clock (CLK) signal, provide a delayed master clock (CLKM) signal to a master latch of the register, and provide a delayed slave clock (CLKS) signal to a slave latch of the register.
Embodiments herein describe using LUTs to map an input value to a non-linear output value as part of a non-linear activation function in a machine learning (ML) model. In one embodiment, two (or more) LUTs are used to approximate a non-linear activation function (e.g., GELU, SILU, Sigmoid, Tanh, etc.). The first LUT can define input ranges (e.g., -1 to 0, 0 to 1, 1 to 2, etc.) which have unequal numbers of splines, which can be determined using derivative analysis on the non-linear function. The first LUT can store pointers, corresponding to the splines, that point to entries in a second LUT. The entries in the second LUT contain coefficients to that can be used to calculate the non-linear output value.
A processing system includes a processor to access an input data array in an initial format from a memory and convert the input data array into an output data array in a target format based on an instruction specifying an element size in the input data array. The converting includes unpacking data of the input data array based on the element size to generate unpacked data and employing a look up table (LUT) and the unpacked data to convert to the output data array in the target format. The processor also includes a plurality of compute units to execute operations of an artificial intelligence (AI) model with the output data array.
Embodiments herein describe optimizing a netlist using machine learning (ML) models that predict which of a plurality of optimization strategies (e.g., a plurality of optimization algorithms) will provide the best results. The netlist can then be optimized using the optimization strategy. Doing so provides significant time and compute resources savings since the netlist can be optimized only once using the selected optimization strategy rather than having to be optimized using each of the plurality of optimization strategies. Moreover, the embodiments herein can permit the addition of more optimization strategies, which could not be considered earlier because of runtime constraints.
A photonics integrated circuit (PIC) assembly and method for fabricating the same are provided. In one example, the method includes aligning a first wafer comprising a plurality of photonics ICs with a second wafer comprising a plurality of optical couplers; bonding the first wafer to the second wafer such that each optical coupler of the plurality of optical couplers is aligned with a corresponding photonics IC of the plurality of photonics ICs; and singulating the photonics ICs, each singulated photonics IC bonded to one of the plurality of optical couplers to form an photonics IC assembly. In another example, a PIC assembly is provided that includes a photonics IC bonded an optical coupler. The photonics IC and the optical coupler having sidewalls aligned to form outer lateral sidewalls (boundaries) of the photonics IC assembly.
A system includes a plurality of ring oscillators, a controlled circuit, and a controller operably coupled to the plurality of ring oscillators and the controlled circuit. The controller is configured to operate one or more of the plurality of ring oscillators based on the controlled circuit and provide a voltage code to the controlled circuit based on analyzing oscillation behaviors of the one or more of the plurality of ring oscillators.
A trained machine learning model intercepts a subset of activation values of a generative artificial intelligence inference model executing at a processing system and classifies the subset of activation values as malicious based on the subset of activation values meeting one or more criteria. The trained machine learning model triggers an exception in response to the intercepted subset of activation values being classified as malicious.
Embodiments herein describe using LUTs to map an input value to a non-linear output value as part of a non-linear activation function in a machine learning (ML) model. In one embodiment, two (or more) LUTs are used to approximate a non-linear activation function (e.g., GELU, SILU, Sigmoid, Tanh, etc.). The first LUT can define input ranges (e.g., -1 to 0, 0 to 1, 1 to 2, etc.) which have unequal numbers of splines, which can be determined using derivative analysis on the non-linear function. The first LUT can store pointers, corresponding to the splines, that point to entries in a second LUT. The entries in the second LUT contain coefficients to that can be used to calculate the non-linear output value.
Plug and photonics IC (PIC) connection architectures and placement techniques are provided that provides improved placement accuracy. In one example, the plug and photonics IC (PIC) connection architecture includes a photonic integrated circuit (IC) assembly. The PIC assembly includes a photonic IC die and an optical coupler. The optical coupler has a top surface and a bottom surface. The bottom surface of the optical coupler is bonded to the photonic IC die. The top surface of the optical coupler has plug alignment structures disposed adjacent a lens of the optical coupler.
A photonics integrated circuit (PIC) assembly and method for fabricating the same are provided. In one example, the method includes aligning a first wafer comprising a plurality of photonics ICs with a second wafer comprising a plurality of optical couplers; bonding the first wafer to the second wafer such that each optical coupler of the plurality of optical couplers is aligned with a corresponding photonics IC of the plurality of photonics ICs; and singulating the photonics ICs, each singulated photonics IC bonded to one of the plurality of optical couplers to form an photonics IC assembly. In another example, a PIC assembly is provided that includes a photonics IC bonded an optical coupler. The photonics IC and the optical coupler having sidewalls aligned to form outer lateral sidewalls (boundaries) of the photonics IC assembly.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/42 - Coupling light guides with opto-electronic elements
25.
INTERCEPTION AND PREVENTION OF MALICIOUS ACTIONS OF ARTIFICIAL INTELLIGENCE MODELS
A trained machine learning model (225) intercepts a subset of activation values (230) of a generative artificial intelligence inference model (215) executing at a processing system (100) and classifies the subset of activation values as malicious based on the subset of activation values meeting one or more criteria. The trained machine learning model triggers an exception (250) in response to the intercepted subset of activation values being classified as malicious.
Levels of cross-correlation between pairs of original filters in the layers of a convolutional neural network (CNN) are determined and used in pruning the filters. The pruning includes, for one or more pairs of the pairs of original filters having a level of cross-correlation that satisfies a pruning threshold, determining a scale factor between first and second filters of the one or more pairs, and storing data that identify the first filter, the second filter, and the scale factor. The pruning further includes modifying the initial CNN into a modified CNN by removing the second filter of the one or more pairs and adjusting convolution logic of the CNN, and adding regeneration logic to the modified CNN. The regeneration logic generates an output channel corresponding to the second filter of the one or more pairs based on the scale factor and an output channel produced by the first filter.
Embodiments describe throttling cores in an IC based on the datatype. Government regulations or export control may indicate the maximum number of operations that can be performed in the IC. However, the IC may perform operations at different rates. For example, the maximum number of operations that an IC can perform in a given time period can be different depending on the datatypes—e.g., 200 Tera Operations per Second (TOPS) for INT4 datatypes but only 100 TOPS for INT8 datatypes. Embodiments herein perform throttling based on particular datatypes so the IC is not unnecessarily throttled.
Implementing a circuit design for a target integrated circuit includes receiving guide information including placement information for a circuit design from a prior implementation flow. A light incremental flow is performed on the circuit design using the guide information. The light incremental flow generates a placed and routed circuit design that re-uses at least a portion of the placement information from the prior implementation flow.
A system-on-chip (SoC) includes a request initiator device, a request target device, and an adaptable streaming interconnect (ASI) communicatively coupled to the request initiator device and the request target device. The ASI is configured to receive a posted request (PR) from the request initiator device, transmit the PR to the request target device, receive a posted request complete (PRC) from the request target device, and transmit the PRC to the request initiator device. The request initiator device is configured to enforce an ordering requirement of the PR based on the PRC.
High-speed and low modulation loss multi-ring modulators may be implemented in an integrated circuit (IC) device, and may include a throughput waveguide, multiple micro-ring modulators (MRMs) optically coupled to the throughput waveguide, and an inductor coupled to a signal pad and to N-type junctions of the MRMs. N junctions of the MRMs are coupled to one another, and P junctions of the MRMs are coupled to one another. The MRMs may be designed and/or tuned to resonate at the same wavelength. The N and P junctions may include lateral/horizontal junctions, vertical junctions, and/or interdigitated junctions. The IC device may further include a substrate and heater elements disposed adjacent to the MRMs, and a surface of the substrate facing the heater elements may have recesses aligned with the heater elements.
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
Embodiments herein describe an artificial intelligence (AI) engine including circuitry to divide a first operand into multiple groups, populate a lookup table (LUT) from multiple multiplications performed by the first operand with bit-groups of a second operand, and reuse the LUT across the bit-groups of the second operand. The first operand remains static for multiple cycles. In a first cycle, the first operand is used to pre-populate the LUT and, in subsequent cycles, the second operand is used to index the LUT. Indexing the LUT includes memory accesses configured to reduce power consumption.
Embodiments herein describe a system including a direct memory access (DMA) engine configured to receive first data stored in a local memory and an artificial intelligence (AI) engine configured to receive second data bypassing the DMA engine. The first data includes matrix-matrix instructions and the second data includes vector-matrix instructions. The second data is configured to be directly sent to the AI engine to avoid additional overhead of DMA data transfer latency, reduce memory bandwidth usage, and minimize power consumption.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 9/52 - Program synchronisationMutual exclusion, e.g. by means of semaphores
An adaptive voltage assist circuit includes a voltage comparison circuit with a first input configured to receive a supply voltage, and a second input configured to receive a threshold voltage. The supply voltage may be configured to be changed dynamically. The voltage comparison circuit is configured to generate at least one output signal indicating whether the supply voltage is above the threshold voltage. An assist logic circuit is configured to use the at least one output signal to generate a control signal indicating a voltage assist configuration for a memory circuit, such as read assist and/or write assist configurations. The memory circuit may be a volatile memory circuit, such as a static random-access memory (SRAM) circuit. The adaptive voltage circuit may be included in an integrated circuit that includes the memory circuit and additional circuits that operate using the supply voltage.
Embodiments herein describe an artificial intelligence (AI) engine including first functional circuitry configured to perform a first set of instructions that include a matrix operation and second functional circuitry configured to perform a second set of instructions that include a vector operation, where the second set of instructions are concurrently performed with the first set of instructions. The first set of instructions include instructions for an operation to perform based on two or more matrices and the second set of instructions include instructions for an operation to perform based on one or more vectors. The first set of instructions include instructions for an operation to perform based on a matrix and a vector and the second set of instructions include instructions for an operation to perform based on one or more vectors.
Embodiments herein describe an artificial intelligence (AI) engine including a register file and a multiplier configured to support a superset of a data type. The register file stores multiple variants of the data type. The AI engine includes logic to expand multiplication operations performed by the multiplier. The data type is a floating-point data type, where the superset of the data type includes a maximum value for a mantissa and a maximum value for an exponent.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
Embodiments herein describe a processor system that includes an integrated, adaptive accelerator. In one embodiment, the processor system includes multiple core complex chiplets that each contain one or processing cores for a host CPU. In addition the processor system includes an accelerator chiplet. The processor system can assign one or more of the core complex chiplets to the accelerator chiplet to form an IO device while the remaining core complex chiplets form the CPU for the host. In this manner, rather than the accelerator and the CPU having independent computer resources, the accelerator can be integrated into the processor system of the host so that hardware resources can be divided between the CPU and the accelerator depending on the needs of the particular application(s) executed by the host.
A chip package and method for fabricating the same are provided that includes embedded off-die inductors coupled in series. One of the off-die inductors is disposed in a redistribution layer formed on a bottom surface of an integrated circuit (IC) die. The other of the series connected off-die inductors is disposed in a substrate of the chip package. The substrate may be either an interposer or a package substrate.
A processor includes at least one processing elements. The at least one processing element is configured to generate a first optimized input matrix and a second optimized input matrix. The first optimized input matrix is generated based on copying elements of a column or row that includes a target value in a first input matrix to an unused column or row in the first input matrix, and scaling the elements prior or subsequent to copying elements. The second optimized input matrix is generated based on based on copying elements of a corresponding row or column in a second input matrix to an unused row or column in the second input matrix. The at least one processing element is further configured to generate an output matrix based on multiplying the first optimized input matrix and the second optimized input matrix, and perform one or more actions based on the output matrix.
Disclosed devices, systems, and methods may enhance communication protocols for low latency applications. Systems may include a device and a host interconnected by a high-performance interconnect and/or communication link. The device may comprise a transmitter, a receiver, and a control unit that may manage a credit-based flow control mechanism. In some aspects, the device may initiate a push write request, send a data header with an identifier (UQID) matching the push write request identifier (CQID), and transmit the data payload. The host may receive the push write request, match the UQID with the CQID, perform the write operation, and send a completion message back to the device. The method may involve ensuring sufficient credits before initiating the push write transaction, which may help prevent data loss and ensure reliable delivery. The push write mechanism may reduce the number of link traversals required for device-to-host memory writes, potentially lowering overall latency.
A device may include an array of data processing engines (DPEs) on a die and an event broadcast network. Each of the DPEs includes a core, a memory module, event logic in at least one of the core or the memory module, and an event broadcast circuitry coupled to the event logic. The event logic is capable of detecting an occurrence of one or more events in the core or the memory module. The event broadcast circuitry is capable of receiving an indication of a detected event detected by the event logic. The event broadcast network includes interconnections between the event broadcast circuitry of the DPEs. Detected events can trigger or initiate various responses, such as debugging, tracing, and profiling.
Disclosed devices, systems, and methods may enhance communication protocols for low latency applications. Systems may include a device and a host interconnected by a high-performance interconnect and/or communication link. The device may comprise a transmitter, a receiver, and a control unit that may manage a credit-based flow control mechanism. In some aspects, the device may initiate a push write request, send a data header with an identifier (UQID) matching the push write request identifier (CQID), and transmit the data payload. The host may receive the push write request, match the UQID with the CQID, perform the write operation, and send a completion message back to the device. The method may involve ensuring sufficient credits before initiating the push write transaction, which may help prevent data loss and ensure reliable delivery. The push write mechanism may reduce the number of link traversals required for device-to-host memory writes, potentially lowering overall latency.
Examples herein describe techniques for reducing the amount of memory used during weight sparsity. When decompressing the weights, the uncompressed weight data typically has many zero values. By knowing the location of these zero values (e.g., their indices in a weight matrix), the processor core can prune some of the activations (e.g., logically reduce the size of the activation matrix) which improves the efficiency of the processor core. In embodiments herein, the processor core includes logic for identifying the indices of the non-zero value after decompressing the compressed weights. These indices can then be used to prune the activations to improve the efficiency of the processor core.
A processor includes at least one processing elements. The at least one processing element is configured to generate a first optimized input matrix and a second optimized input matrix. The first optimized input matrix is generated based on copying elements of a column or row that includes a target value in a first input matrix to an unused column or row in the first input matrix, and scaling the elements prior or subsequent to copying elements. The second optimized input matrix is generated based on based on copying elements of a corresponding row or column in a second input matrix to an unused row or column in the second input matrix. The at least one processing element is further configured to generate an output matrix based on multiplying the first optimized input matrix and the second optimized input matrix, and perform one or more actions based on the output matrix.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
44.
MODEL LEVEL DEBUGGING OF MACHINE LEARNING DESIGNS ON NEURAL PROCESSING UNITS
Model level debugging of a machine learning design includes compiling the machine learning design for execution on target hardware using a compiler. Metadata for the machine is generated. The metadata specifies a mapping of buffers of the machine learning design to a plurality of memory levels of a memory architecture of the target hardware correlated with boundaries of the machine learning design. While running the machine learning design, debug data is dumped from the plurality of memory levels of the memory architecture based on the boundaries. The debug data is correlated with the boundaries of the machine learning design based on the metadata.
Devices, systems, and methods manage activity in die-to-die links. A link controller places a die-to-die link in a partially active state, with some lane groups active and others idle, adapting to changing conditions without full link retraining. Lane groups can independently enter an electrical idle state, reducing power consumption without interrupting data transmission over active lanes. Idle lanes can be retrained and reactivated without affecting active lanes. Control messages, may manage lane group states, ensuring synchronized transitions between active and idle states. This approach optimizes power management and maintains data transmission efficiency in die-to-die interconnects.
A flexible microscaling (MX) approach allows for the dynamic selection between multiple scale determination functions to compute a scaling factor that delivers lower deviation from an input data array (112, 302) when converting the input data array to an output data array (312) with reduced bit precision. The flexible MX approach includes selecting a first scale determination function from a plurality of scale determination functions (256-1, 256-2) based on a characteristic of an input data array having a first data format, computing a scaling factor (370) based on the first scale determination function, and converting the input data array into an output data array having a target data format based on the selected scaling factor. The output data array is then input to an artificial intelligence (AI) model for processing.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
A processing system is configured to generate a three-dimensional (3D) Gaussian map representing at least a portion of an environment surrounding the processing system. For example, a capture device of the processing device first captures a set of frames each including color data. The processing system then implements a visual odometry (VO) tracking model which samples patches from this set of frames so as to generate a point cloud and pose data representing the location and orientation of the patches within the environment. Further, the processing system implements a Gaussian Mapping model that generates a set of Gaussians from the point cloud which the processing system then uses to populate a 3D Gaussian map.
A flexible microscaling (MX) approach allows for the dynamic selection between multiple scale determination functions to compute a scaling factor that delivers lower deviation from an input data array when converting the input data array to an output data array with reduced bit precision. The flexible MX approach includes selecting a first scale determination function from a plurality of scale determination functions based on a characteristic of an input data array having a first data format, computing a scaling factor based on the first scale determination function, and converting the input data array into an output data array having a target data format based on the selected scaling factor. The output data array is then input to an artificial intelligence (AI) model for processing.
Embodiments herein relate to applying a Boolean matrix factorization operation to selected neurons, represented as truth tables, in LUT based neural networks. Applying the Boolean matrix factorization operation replaces the original truth table representing the neuron of the neural network with a simplified, approximated truth table derived from the original truth table. The neural network is then simulated, and the cost of the simulated result, as evaluated by a cost function which may for instance incorporate accuracy and resource cost, is compared to a cost threshold value to decide whether to replace the original neuron with its approximated representation.
High-level synthesis generation of multiplexer logic includes generating, using computer hardware, an intermediate representation of a design for an integrated circuit. The design is specified in high-level programming language source code. Selected logic within the intermediate representation is detected by the computer hardware and converted into a sparsemux node. A selected core is chosen from a plurality of cores to implement the sparsemux node. The computer hardware is capable of choosing the selected core based on a label encoding format and a default input of the sparsemux node. A circuit design is generated by the computer hardware. One or more operations of the selected core are scheduled based on a timing model corresponding to the selected core.
Alignment detection circuitry is disclosed that include a buffer configured to output a data stream of multiplexed groups of symbols from multiple data lanes and a set of correlators configured to determine physical link skew from one data lane of the multiple data lanes, wherein the physical link skew from the one data lane is known to equal the physical link skew on each data lane, assuming each data lane is transmitted over the same physical link. The alignment detection circuitry may also include anti¬ aliasing circuitry configured to extract a unique marker of the alignment marker to detect common marker aliasing by comparing the extracted unique marker to a known unique marker. Anti-aliasing circuitry may also be configured to use common marker detection status of adjacent data lanes of the multiple data lanes to detect common marker aliasing determined by a detection delay between the adjacent data lanes.
Calibration of wavelength division multiplexing (WDM) optical micro-ring modulators (MRMs) may include providing multiple optical signals to a waveguide having multiple MRMs, sweeping heater settings of each MRMs, from high to low, recording drop-port outputs of the first MRM for the corresponding heater settings, while other MRMs are rendered transparent, determining a percentage of the peak-drop port outputs and corresponding off-peak heater settings, discarding off-peak heater settings that are below a tracking margin threshold, and selecting calibrated heater settings for the MRMs from remaining ones of the off-peak heater settings of the respective MRMs. The calibrated heater settings may be selected based on a greedy placement method. Alternatively, additional data may be generated by determining remaining heater settings that cause collisions between adjacent pairs of MRMs, and selecting the calibrated heater settings based on an ordered placement or a sorted placement of the collision settings.
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
53.
TRANSFORM BLOCK FLOATING POINT VALUES TO OTHER BLOCK FLOATING POINT FORMATS
Embodiments herein describe an artificial intelligence (AI) engine including a register file including a block floating point configured to be converted to a block size that aligns with hardware capabilities by dividing the block floating point into multiple sub-blocks and replicating an exponent of the block floating point for each of the multiple sub-blocks. In one example, the block floating point includes 32 elements and the multiple sub-blocks are 4 sub-blocks with 8 elements each. In another example, the block floating point includes 32 elements and the multiple sub-blocks are 2 sub-blocks with 16 elements each.
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
54.
ADAPTIVE QUANTIZATION AND COMPRESSION FOR VARIABLE-LENGTH COLLECTIVE COMMUNICATION
A processing system dynamically and selectively quantizes or compresses variable-length input data for a collective operation to fit within a predetermined limit, executes the collective operation on the compressed data, and converts the data back to variable length results by dequantizing or decompressing the results of the collective operation.
Embodiments herein describe a sparse-dense-sparse (SDS) process that achieves a better pruning scheme that benefits from pruning-friendliness relative to one-shot pruning schemes. The SDS process performs a first pruning to generate a sparse ML model followed by reconstruction to generate a re-dense ML model, followed by a second pruning to generate another sparse ML model. By pruning a ML model and then re-constructing the ML model, the ML model can be made more pruning-friendly by performing data and/or weight regularization. As a result, performing the second pruning in the SDS process can result in a smoother weight distribution and lower perplexity relative to one-shot pruning.
Embodiments herein describe relaxation oscillator circuits for physical unclonable function (PUF) circuits and/or for providing clocks to multiple dies. The relaxation oscillator circuit generates a clock having a frequency that is based in part on random process variations of the passive components of the relaxation oscillator circuit. The relaxation oscillator circuit may be distributed amongst multiple dies of an integrated circuit device, to incorporate additional sources of randomness/entropy, enhance security, to provide clocks to the multiple dies. The relaxation oscillator circuits include differential and single-ended relaxation oscillator circuits. Resistive and/or capacitive components may be configurable, which may be useful for testing purposes, altering PUF codes, and/or generating time-multiplexed clocks.
H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
H03K 3/3565 - Bistables with hysteresis, e.g. Schmitt trigger
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
57.
Stress-reduced package substrate and method of forming the same
Disclosed herein is a package substrate and a method for fabricating the same. In one example, a package substrate includes a core having an outer edge and a first plurality of first interconnect layers disposed on the core. The first plurality of interconnect layers disposed on the core include an outermost dielectric layer disposed farthest from the core. The outermost dielectric layer has an edge that is recessed from the edge of the core.
Embodiments herein describe a hardware accelerator that includes multiple power or clock domains. For example, the hardware accelerator can include an array of data processing engines (DPEs) where different subsets of the DPEs (e.g., different columns, rows, or blocks) are disposed in different power or clock domains within the hardware accelerator. When one or more subsets of the DPEs are idle (e.g., the hardware accelerator has not assigned any tasks to those DPEs), the accelerator can deactivate the corresponding power or clock domain (or domains), which deactivates the DPEs in those domains while the DPEs in the other power or clock domains remain operational. As such, idle DPEs can be deactivated to conserve energy while DPEs with work can remain operational.
Embodiments herein describe a system including a plurality of network resources providing communication between a plurality of source end points and a plurality of destination end points, where a first source end point transmits data to a first destination end point by using information about a size, route, and timing of data exchanges to pre-allocate resources in the system for a predefined time frame and use a common time reference among the first end points and the second end points to commence transmission of the data at a time when an allocation time frame begins.
A modular and scalable high-performance compression system includes multiple compression units (CUs), each including a compression circuit, an input buffer, and a history buffer, and further including input circuitry that loads the input buffers and the history buffers with sub-blocks of data blocks. The compression circuits identify segments of the sub-blocks of the corresponding input buffers that match segments of the sub-blocks of the corresponding history buffers, and encode the identified segments based on positions/offsets of the matching segments within the history buffers. The system may include multiple selectable compression modes, and may compress multiple data blocks in parallel, based on the same or differing compression modes. The compression modes may include a high throughput mode and a high compression ratio mode, and may further include dynamic selection mode that selects a compression mode based on a compression ratio, available resources, and/or other criteria.
A multi-die ring oscillator with split entropy for security and physical unclonable function (PUF) applications includes a PUF circuit that includes a current source circuit that sources currents from a gated supply voltage and controls the currents based on an analog voltage, a voltage controller (e.g., a differential-input OTA) that controls the analog voltage based on first and second ones of the currents, and a ring oscillator that outputs a clock based on a third one of the currents, where a frequency of the clock is based on the third current and random variations of components of the PUF circuit. The voltage controller and the ring oscillator may be placed on a first die, and the current source circuit may be placed on a second die. The PUF circuit may be configurable to alter the clock frequency and/or to provide the clock with time-multiplexed frequencies.
G06F 21/73 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
62.
LANE ALIGNMENT FOR SYMBOL MULTIPLEXED WIRED COMMUNICATION SYSTEMS
Alignment detection circuitry is disclosed that include a buffer configured to output a data stream of multiplexed groups of symbols from multiple data lanes and a set of correlators configured to determine physical link skew from one data lane of the multiple data lanes, wherein the physical link skew from the one data lane is known to equal the physical link skew on each data lane, assuming each data lane is transmitted over the same physical link. The alignment detection circuitry may also include anti-aliasing circuitry configured to extract a unique marker of the alignment marker to detect common marker aliasing by comparing the extracted unique marker to a known unique marker. Anti-aliasing circuitry may also be configured to use common marker detection status of adjacent data lanes of the multiple data lanes to detect common marker aliasing determined by a detection delay between the adjacent data lanes.
Data spray techniques are used to implement fault resistant data detection using a plurality of data detectors. Each of the plurality of data detectors is coupled, at sequential times, to a lane of data bytes during transfers thereof from a data source to a data destination. Each data detector is individually associated with the lane of data bytes at sequential time slots representing each data byte transfer. All bits of the bytes being transferred on the lane are examined individually by the data detectors in determining if the data byte has been programmed for a security key code by detecting a certain logic state in at least one bit thereof. Associating each of the plurality of data detectors during data byte transfers improves security key detection by reducing the probability of a single defective data detector leading to an erroneous conclusion of the status of the data.
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
64.
DISTRIBUTED ON-CHIP KEY-VALUE STORE CIRCUIT ARCHITECTURE
An electronic system includes a key memory circuit capable of storing a plurality of keys and outputting an address for a key of the plurality of keys matched to a search key. The electronic system includes a memory manager circuit capable of tracking free memory addresses in the key memory circuit. The electronic system includes a state tracker circuit including a value memory circuit. The value memory circuit is capable of storing values of state information and is separate from the key memory circuit. The electronic system includes an insert-delete circuit capable of passing the address from the key memory circuit to the state tracker circuit, performing insert and delete operations on the key memory circuit, and providing free memory addresses of the key memory circuit to the memory manager circuit.
A method includes, for speculative decoding using a draft model that generates look ahead tokens for a target model, splitting an input dataset into a first set and a second set. The method also includes, using the first set, computing an expected number of look ahead tokens accepted by the target model per call based on a first value indicative of a quantity of look ahead tokens generated by the draft model per call to the target model, and modifying the quantity of look ahead tokens generated by the draft model to a second value based on the expected number of look ahead tokens accepted by the target model. Then, the method includes, with the second set, performing speculative decoding with a look ahead window size based on the second value.
Embodiments herein describe a system including a plurality of network resources providing communication between a plurality of source end points and a plurality of destination end points, where a first source end point transmits data to a first destination end point by using information about a size, route, and timing of data exchanges to pre-allocate resources in the system for a predefined time frame and use a common time reference among the first end points and the second end points to commence transmission of the data at a time when an allocation time frame begins.
Embodiments herein describe a system including a plurality of network resources providing data transmission between a first end point and a second end point by making a request for a network resource reservation to reserve resources on an end-to-end path during a time frame for the data transmission, selecting a routing table, populating the routing table with a limited number of entries, activating the data transmission at a start time of the time frame to an input port corresponding to the routing table, in response to activating the data transmission, forwarding data based on the entries, and determining an end time of the time frame to deactivate the data transmission from the first end point.
Machine learning (ML) tools for analyzing semiconductor yield analysis data, such as to infer information related to defects based on feature values of the yield diagnostic data, where the yield diagnostic data includes wafer-level test data, wafer-region based defect densities (DDs), and functional circuit block-based DDs. The wafer region based DDs are a function of numbers of defects within regions of the wafers and physical areas of the regions. The functional circuit block based DDs are a function of numbers of defects of functional circuit blocks and physical areas of the functional circuit blocks. The ML tools may include a supervised learning-based classification model, such as a gradient boosting classifier, an unsupervised outlier detection model, such as a hierarchical density-based spatial clustering of applications with noise model, an unsupervised clustering model, and/or an unsupervised associative model.
The embodiments herein describe techniques for performing ML compilation using a unified interface that combines different processors in a heterogeneous processing system which allows for intelligent partitioning of a ML model. Unlike prior solutions which rely on user preferences to assign the ML model, the unified interface can violate or break the user preferences when partitioning the ML model. The unified interface can receive information from the processors (e.g., a NPU, CPU, GPU, etc.) and determine the capabilities, current workload, power metrics, subgraphs of the ML model they can execute, and the like. With this information, the unified interface can intelligently choose when to violate or break the user-entered priority based instructions.
The embodiments herein describe techniques for performing ML compilation using a unified interface that combines different processors in a heterogeneous processing system which allows for intelligent partitioning of a ML model. Unlike prior solutions which rely on user preferences to assign the ML model, the unified interface can violate or break the user preferences when partitioning the ML model. The unified interface can receive information from the processors (e.g., a NPU, CPU, GPU, etc.) and determine the capabilities, current workload, power metrics, subgraphs of the ML model they can execute, and the like. With this information, the unified interface can intelligently choose when to violate or break the user-entered priority based instructions.
Optimizing timing margins across conditions is described. In one or more implementations, a computing system may include an interface circuitry configured to adjust a timing alignment of first and second signals between a central processing unit (CPU) of the system and a device coupled with the CPU and to measure and store one or more margins between the timing alignment and misalignments of the first and second signals. The interface circuitry may be configured to measure and store the timing margins at first and second conditions. The first and second conditions may be different voltages, temperatures, etc. The system may be configured to force the first and/or second condition. The system may be configured to calculate a coefficient from differences in between the margins and between the first and second conditions.
In-system electrical connectivity detection. In one or more implementations, a computing device includes a transmitter and a receiver in a package, the transmitter to transmit a signal to a separate device, the receiver to receive and measure a reflection of the transmitted signal, and the measured reflection for characterizing (e.g., testing or detecting) an electrical connection between the computing and separate devices. The computing device may characterize (e.g., detect a discontinuity in) the electrical connection by comparing a magnitude of the transmitted signal with a magnitude of the measured reflection. The computing device may be coupled with the separate device by multiple electrical connections, and the multiple electrical connections may be tested by corresponding transmitters and receivers.
A phase-locked loop circuit includes a phase-frequency detector circuit, a time amplifier circuit, a control circuit, and a variable oscillator circuit, such as a voltage-controlled oscillator. The phase-frequency detector is configured to generate a phase error output indicating a phase difference between a reference signal and a feedback signal generated using an output signal. The time amplifier is configured to extend the phase difference to generate an extended phase error output. The variable oscillator is configured to use one or more control signals generated by the control circuit using the extended phase error to adjust a frequency of the output signal. The control circuit may generate a proportional control signal using a switched-resistor circuit that includes a pull-up resistor and a pull-down resistor. The control circuit may generate an integral control signal using a capacitive-shared-integration circuit that includes passive integrating components.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
74.
METHOD FOR SCALABLE OPERATOR LOADING FOR PROGRAM MEMORY LIMITED ACCELERATORS
A method includes allocating, at least one boot image, and parsing programs comprising one or more operators. The method further includes determining a count corresponding to each operator included in each program and an estimated program memory consumption of each operator. The count corresponds to each operator and indicates a quantity of times each operator in each program is detected. The at least one boot image is populated with common operators based on a program memory size limit of an hardware accelerator circuitry of an IC device and an estimated program memory consumption of each common operator. The common operators are operators that are within a threshold count. The at least one boot image is populated with non-common operators based on the program memory size limit and an estimated program memory consumption of each non-common operator. The non-common operators are operators that are not within the threshold count.
Fine-grained preemption of a data flow architecture based neural processing unit (NPU) includes executing, by a controller, control-code that implements a first context in the NPU. In response to the controller detecting a preemption opcode in the control-code, detecting, by the controller, a second context awaiting execution by the neural processing unit. The second context has a priority that is greater than a priority of the first context. In response to detecting the second context, the NPU switches from executing the first context to implementing the second context.
A detector for detecting a periodic square wave (PSW) includes: an interface circuit configured to generate a serial bit stream (SBS) by sampling an input signal carrying the PSW; a decimation encoder circuit (DEC) coupled to the interface circuit and configured to generate, for every first number of bits in the SBS, a symbol in a symbol stream; a pulse width estimator (PWE) configured to generate, for each symbol generated by the DEC, an estimate of a width of a most recent pulse (MRP) in a sequence of bits in the SBS, where the sequence of bits correspond to a pre-determined number of most recent symbols generated by the DEC; and a state machine coupled to the PWE and configured to declare detection of the PSW in response to detecting that the estimate of the width of the MRP is within a pre-determined range for a pre-determined period of time.
Embodiments herein describe techniques for setting and using saliency values to modify how a ML model is trained. In one embodiment, different blocks of data (referred to herein as tiles) are assigned respective saliency values. After performing one or more iterations, a training application can modify the default saliency values assigned to the tiles to reflect the importance of the tile. In one embodiment, the training application evaluates a weight gradient that indicates how a weight (or weights) corresponding to each tile are modified and modifies the saliency values accordingly. The ML training system can then use the saliency values to affect future training iterations to reduce the time required to train the ML model or save power.
G06F 18/214 - Generating training patternsBootstrap methods, e.g. bagging or boosting
G06V 10/46 - Descriptors for shape, contour or point-related descriptors, e.g. scale invariant feature transform [SIFT] or bags of words [BoW]Salient regional features
G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries
78.
DETERMINISTIC JITTER DETECTION AND MITIGATION FOR FREQUENCY DIVIDER CIRCUITRY
A communication system includes correction circuitry. The correction circuitry includes detection circuitry and clock correction circuitry. The detection circuitry determines a first correction value based on a first rising edge and a second rising edge of a divided clock signal. The clock correction circuitry receives a first clock signal, a second clock signal and the first correction value, and generates a first adjusted clock signal and a second adjusted clock signal based on the first correction value. The first clock signal and the second clock signal. The first adjusted clock signal and the second adjusted clock signal are used by divider circuitry to generate the divided clock signal. A frequency of the divided clock signal is less than a frequency of the first clock signal and the second clock signal.
Fine-grained preemption of a data flow architecture based neural processing unit (NPU) includes executing, by a controller, control-code that implements a first context in the NPU. In response to the controller detecting a preemption opcode in the control-code, detecting, by the controller, a second context awaiting execution by the neural processing unit. The second context has a priority that is greater than a priority of the first context. In response to detecting the second context, the NPU switches from executing the first context to implementing the second context.
Command stream stitching for hardware acceleration includes generating, by a host processor, a stitched block representing a plurality of commands for a hardware accelerator. The host processor generates a stitched command from the plurality of commands. The stitched command references the stitched block. The hardware accelerator executes the stitched block in response to invoking the stitched command. The hardware accelerator generates a single notification directed to the host processor for the stitched command.
Techniques are described for the use of optical couplers with photonic integrated circuits (PICs). Some techniques include optically coupling one device (e.g., a package) to another via one or more optical couplers to, for instance, optically couple an on-chip waveguide to an off-chip optical fiber. Some techniques do not require careful alignment of a waveguide with a lens or other components, and are scalable to large numbers of optical paths. Moreover, some optical couplers herein may be fabricated with known (e.g., conventional) wafer-level processes.
A memory device includes memory cells, driver circuitry, and control circuitry. The driver circuitry is connected to the memory cells. The driver circuitry includes first sense amplifier circuitries connected to first memory cells of the memory cells. The second sense amplifier circuitries are connected to second memory cells of the memory cells. The control circuitry enables the first sense amplifier circuitries and disables the second sense amplifier circuitries based on a read command. First data associated with the first memory cells is output via the first sense amplifier circuitries based on the read command.
A unit cell circuitry for a digital-to-analog converter (DAC) circuitry includes cascode circuitry, switch circuitry, and capacitor circuitry. The cascode circuitry is connected to a first output node and a second output node of the unit cell circuitry. The switch circuitry is connected to the cascode circuitry. The capacitor circuitry includes one or more capacitors connected to the switch circuitry. The switch circuitry connects the capacitor circuitry to the cascode circuitry to inject a charge onto the cascode circuitry. The unit cell circuitry outputs a signal based on the injected charge.
Command stream stitching for hardware acceleration includes generating, by a host processor, a stitched block representing a plurality of commands for a hardware accelerator. The host processor generates a stitched command from the plurality of commands. The stitched command references the stitched block. The hardware accelerator executes the stitched block in response to invoking the stitched command. The hardware accelerator generates a single notification directed to the host processor for the stitched command.
Embodiments herein describe an integrated circuit (IC) including an integrated circuit including a first die and a second die including an inductor and disposed over the first die, where the second die is electrically coupled to the first die via hybrid bonds (MBs). The IC may include a metal layer disposed under a portion of the inductor. The IC may further include a shielding layer disposed within the first die. The IC may also include first metal strips disposed adjacent a head section of the inductor and second metal strips disposed over a leg section of the inductor. The inductor may include a head section constructed as a dual loop and a leg section constructed as a pair of legs, where the inductor is enclosed within isolation walls.
A metastable logic-based physical unclonable function (PUF) circuit with trimmable source degeneration and enhanced aging performance includes metastable logic that generates metastable states at first and second outputs, which settle into respective determinable logic states based on random process variations of elements of the metastable logic. The PUF circuit further includes compensation circuitry to compensate for load mismatches of the first and second outputs. The PUF circuit may further include trimmable (e.g., selectable) source degeneration resistors for controlling voltages of transistors of the metastable logic. Varying numbers of source degeneration resistors may be selected to control the determinable logic state and/or to evaluate the PUF circuit for stability. The source degeneration resistors may also serve a power gates to disable the PUF circuit when not in use, which may reduce age-related effects.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
87.
INDUCTOR DEGRADATION REDUCTION IN 3D STACKED INTEGRATION WITH HYBRID BOND
Embodiments herein describe an integrated circuit (IC) including an integrated circuit including a first die and a second die including an inductor and disposed over the first die, where the second die is electrically coupled to the first die via hybrid bonds (HBs). The IC may include a metal layer disposed under a portion of the inductor. The IC may further include a shielding layer disposed within the first die. The IC may also include first metal strips disposed adjacent a head section of the inductor and second metal strips disposed over a leg section of the inductor. The inductor may include a head section constructed as a dual loop and a leg section constructed as a pair of legs, where the inductor is enclosed within isolation walls.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/552 - Protection against radiation, e.g. light
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
88.
SYSTEMS AND METHODS FOR MANAGING ORDER OF COMMAND PROCESSING
A computer-implemented method for managing processing order for a plurality of commands can include in response to receiving each command of a plurality of commands in a receipt order, assigning each respective command of the plurality of commands to a respective processing queue of a plurality of processing queues to be processed, and setting, for each of the plurality of commands and in the receipt order, an identifier based on the respective queue assigned to each of the plurality of commands, and managing, based on the identifiers for each of the plurality of commands in the receipt order, an order of processing of each of the plurality of commands from the respective processing queue of the plurality of processing queues. Various other methods, systems, and computer-readable media are also disclosed.
Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
90.
CONTROL PROTOCOL TO ENABLE INDIVIDUAL THREADS TO ISSUE COMMANDS
Embodiments herein describe a method including posting a persistent work request (P-WR) to a memory space accessible by a control frontend (CFE), the P-WR including information about data chunks, ringing a doorbell in a control frontend (CFE), allowing the CFE to inspect the P-WR, allowing the CFE to set up virtual doorbells at specific addresses in the memory space, specifying a doorbell address range and completion flags associated with one or a set of data chunks, and allowing the CFE to set up a required data movement for each data chunk and provide completion status.
To enable an accelerator unit to perform one or more operators for a machine-learning model, a processing system is configured to generate a launch kernel using a dynamic operator dispatch mode. For example, a processing unit of the processing system first organizes an operator group of the machine-learning model into a series of nodes that represents the operators in the operator group. Based on this series of nodes, the processing unit retrieves and modifies pre-compiled operators from an operator library stored in a memory of the processing system. The processing unit then generates a launch kernel based on the modified pre-compiled operators.
Accelerated remote-direct-memory-access (RDMA) command construction for GPU-directed fine-grained communication, including interpreter logic that frees a host device and/or compute units of a data processing element (DPE), such as graphic processing unit (GPU), from managing execution of the WRs. The interpreter logic frees the host/DPE from managing execution of the WRs. The interpreter logic may access memory of the host/DPE (e.g., data, work request queues, completion queues, etc.), such as to retrieve the WRs and/or to write completion notifications, and/or the host/DPE may write the WRs to registers accessible to the interpreter logic.
Embodiments herein relate to training, calibrating, or preparing quantized neural networks for lossless low-precision accumulation with floating-point dot product operands. This includes an improvement in training low-precision floating-point neural networks for a certain accumulator bit width. The accumulator-aware weight quantization methodology yields floating-point weights that avoid arithmetic errors caused by overflow, underflow, and rounding, among other common problems when accumulated into low-precision accumulators during dot products with input activations of known data formats. This is implemented by imposing constraints on the values of the exponents and mantissas used to represent the weights of the neurons of the neural network.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. As a result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as CPU-to-CPU communication in the host. The dual domains in the peripheral I/O device can be leveraged for machine learning (ML) applications. While an I/O device can be used as an ML accelerator, these accelerators previously only used an I/O domain. In the embodiments herein, compute resources can be split between the I/O domain and the coherent domain where a ML engine is in the I/O domain and a ML model is in the coherent domain. An advantage of doing so is that the ML model can be coherently updated using a reference ML model stored in the host.
Systems and methods for dynamically selecting source code development tests using a trained machine learning (ML) model are disclosed. In certain embodiments, a plurality of data features is derived from information indicating a plurality of modifications to a source code repository. Based at least in part on the derived data features, an ML model is trained to identify correlations between the modifications and a plurality of historical source code development test results. Upon receiving an indication of one or more additional modifications to the source code repository, the trained ML model dynamically selects, from a plurality of source code development tests, a subset of source code development tests relevant to the additional modifications.
A processing unit executes a sequence of instructions comprising a branch instruction and selects a target branch predictor for the branch instruction from a plurality of branch predictors. The selection is based on a language model trained on a set of training instruction sequences that comprise branch instructions. The target branch predictor then determines the outcome of the branch instruction. The language model is trained to identify the branch instructions as having easy-to-predict outcomes or hard-to-predict outcomes based on sequence of instructions. Information generated by the language model is provided to a branch prediction unit, which uses the information to determine whether branch instructions are easy-to-predict or hard-to-predict.
Computer-implemented technology mapping of a circuit design includes, for a node of a circuit design, generating a plurality of regular cuts and a plurality of super cuts. A regular cut subset that is a subset of the plurality of regular cuts having M highest priorities and a super cut subset that is a subset of the plurality of super cuts having N highest priorities are generated. Each super cut that is incompatible with a cascaded lookup-table (LUT) circuit structure is discarding from the super cut subset. A cut from a group of cuts including the regular cut subset and the super cut subset is selected to implement a portion of the circuit design including the node.
A processing unit executes a sequence of instructions comprising a branch instruction and selects a target branch predictor for the branch instruction from a plurality of branch predictors. The selection is based on a language model trained on a set of training instruction sequences that comprise branch instructions. The target branch predictor then determines the outcome of the branch instruction. The language model is trained to identify the branch instructions as having easy-to-predict outcomes or hard-to-predict outcomes based on sequence of instructions. Information generated by the language model is provided to a branch prediction unit, which uses the information to determine whether branch instructions are easy-to-predict or hard-to-predict.
Embodiments herein relate to modifying the framework of an FFN module of a machine learning model. Modifications include an improved nonlinear function of that aims to decrease the number of hidden dimensions of the FFN module, thereby reducing the computational cost.
A circuit arrangement includes a plurality of cryptographic accelerators. Each cryptographic accelerator is configured to perform cryptographic operations according to a respective cryptographic protocol. A first memory is coupled to the cryptographic accelerators. A first processor is configured to specify, in response to requests to perform the cryptographic operations, parameters to the cryptographic accelerators according to the requests. The first processor is configured to identify, in the first memory, keys that are associated with the cryptographic accelerators, and signal the cryptographic accelerators to commence performing the cryptographic operations according to the parameters and using the associated keys.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
