An implementation may include a method for performing a binary multiplication including receiving a first at an input interface of a digital multiplier circuit in the computing system, receiving a second operand at the input interface of the digital multiplier circuit, generating, by the digital multiplier circuit, partial products by performing a AND operation with each of the N bits of the first operand and each of the bits of the second operand, and generating first modified partial products by modifying, by the digital multiplier circuit, most significant bits of the partial products, generating second modified partial products by modifying, by the digital multiplier circuit, one of the first modified partial product, generating, by the digital multiplier circuit, a product by summing the second modified partial products, and outputting the product from an output interface of the digital multiplier circuit.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
2.
EFFICIENT METHOD FOR THE LATCH TIMING ANALYSIS OF ELECTRONIC DESIGNS
Performing timing analysis of a circuit design includes building a timing graph of the circuit design, and determining delays of devices and wires of the circuit design based on the timing graph. Further, clock and arrival propagations for the circuit design are performed based on the delays of the devices and wires, latch loops are identified in the circuit design, and latch analysis on latches of the latch loops is performed. The timing analysis further includes performing arrival propagation for circuit elements of the circuit design impacted by the latch analysis performed on the latches of the latch loops, performing latch analysis on latches of the circuit design external to the latch loops, and performing required time and slack calculations on the circuit design.
Embodiments herein describe a circuit for detecting a single event upset (SEU). The circuit includes a latch including an output node, a first parity node, and a second parity node and correction circuitry configured to correct a single event upset (SEU) at the output node using the first and second parity nodes.
An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.
Embodiments herein describe a learnable transform block disposed before, or in between, the neural network layers to transform received data into a more computational-friendly domain while preserving discriminative features required for the neural network to generate accurate results. In one embodiment, during a training phase, an AI system learns parameters for the transform block that are then used during the inference phase to transform received data into the computational-friendly domain that has a reduced size input. The transformed data may require less compute resources or less memory usage to process by the underlying hardware device that hosts the neural network.
The disclosed device includes a processor and an interconnect connecting the processor to a memory. The interconnect includes an interconnect agent that can forward memory requests from the processor to the memory and receive requested data returned by the memory. The requested data can include information for a next memory request such that the interconnect agent can send, to the memory, a speculative memory request using information for the next memory request that was received in response to the memory request. Various other methods, systems, and computer-readable media are also disclosed.
A multi-chiplet system includes a first chiplet comprising a first transceiver and a first chiplet-to-chiplet (C2C) interface module, and a second chiplet comprising programmable logic circuitry and a second C2C interface module. The first transceiver is configured to generate a clock, which is transmitted from the first C2C interface module to the second C2C interface module, through a clock transmission wire, for data transfer between the first chiplet and the second chiplet.
Described herein are systems and methods for managing error detection in a message. A circuit can identify, based on an error detection configuration of the at least one circuit, a first portion of the message to be checked for errors before a second portion of the message is available to the at least one circuit, the first portion being less than all of the message to be checked for one or more errors. A circuit can analyze a number of bits of the first portion of the message using the at least one circuit and based on the error detection configuration. A circuit can, based on analyzing the first portion, determine whether the message includes the one or more errors. Various other methods, systems, and computer-readable media are also disclosed.
The disclosed device includes a processor and an interconnect connecting the processor to a memory. The interconnect includes an interconnect agent that can forward memory requests from the processor to the memory and receive requested data returned by the memory. The requested data can include information for a next memory request such that the interconnect agent can send, to the memory, a speculative memory request using information for the next memory request that was received in response to the memory request. Various other methods, systems, and computerreadable media are also disclosed.
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
An integrated circuit die stack and method thereof are described herein that is capable of detecting a physical tampering event. The integrated circuit die stack includes a first integrated circuit die including a sensor network that extends substantially across an entire top surface of the first integrated circuit die, and a second integrated circuit die stacked below the first integrated circuit die. The second integrated circuit die is configured to receive sensing signals generated by the sensor network via a plurality of through-silicon-vias coupled with the first integrated circuit die and the second integrated circuit die.
G11C 19/28 - Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
11.
PRUNING OF TECHNOLOGY-MAPPED MACHINE LEARNING-RELATED CIRCUITS AT BIT-LEVEL GRANULARITY
Embodiments herein describe pruning of technology-mapped machine learning-related circuits at bit-level granularity, including techniques to efficiently remove look-up tables (LUTs) of a technology-mapped netlist while maintaining a baseline accuracy of an underlying machine learning model. In an embodiment, a LUT output of a current circuit design is replaced with a constant value, and at least the LUT and LUTs within a maximum fanout-free cone (MFFC) are removed, to provide an optimized circuit design. The current circuit design or the optimized circuit design is selected as a solution based on corresponding training data-based accuracies and metrics (e.g., LUT utilization), and optimization criteria. If the optimized circuit design is rejected, inputs to the LUT may be evaluated for pruning. A set of solutions may be evaluated based on validation data-based accuracies and metrics of the corresponding circuit design. Solutions that do not meet a baseline accuracy may be discarded.
An integrated circuit die stack and method thereof are described herein that is capable of detecting a physical tampering event. The integrated circuit die stack includes a first integrated circuit die including a sensor network that extends substantially across an entire top surface of the first integrated circuit die, and a second integrated circuit die stacked below the first integrated circuit die. The second integrated circuit die is configured to receive sensing signals generated by the sensor network via a plurality of through-silicon-vias coupled with the first integrated circuit die and the second integrated circuit die.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
A multi-chiplet system includes a first chiplet comprising a first transceiver and a first chiplet-to-chiplet (C2C) interface module, and a second chiplet comprising programmable logic circuitry and a second C2C interface module. The first transceiver is configured to generate a clock, which is transmitted from the first C2C interface module to the second C2C interface module, through a clock transmission wire, for data transfer between the first chiplet and the second chiplet.
A circuit design emulation system having a plurality of integrated circuits (ICs) includes a first IC. The first IC includes an originator circuit configured to issue a request of a transaction directed to a completer circuit. The request is specified in a communication protocol. The first IC includes a completer transactor circuit coupled to the originator circuit and configured to translate the request into request data. The first IC includes a first interface circuit configured to synchronize the request data from an originator clock domain to a transceiver clock domain operating at a higher frequency than the originator clock domain. The first IC includes a first transceiver circuit configured to convey the request data over a communication link that operates asynchronously to the originator clock domain.
A disclosed semiconductor device includes (1) a silicon stack comprising a front-side Back-End-of-Line (BEOL) stack and a back side BEOL stack, the front-side BEOL stack comprising a plurality of signal routes and the back-side BEOL stack comprising a plurality of power delivery routes, and (2) a plurality of auxiliary power paths formed within the front-side BEOL stack and electrically coupled to the plurality of power delivery routes of the back-side BEOL stack via a plurality of programmable switches, the plurality of power delivery routes, the plurality of programmable switches, and the plurality of auxiliary power paths forming a programmable power delivery network (PDN). Various other apparatuses, systems, and methods of operation are also disclosed.
A system-on-chip (SoC) has programmable logic and a processor. A design tool generates configuration data to implement circuitry for emulation of a design-under-test (DUT) on the programmable logic and generates testbench executable code. The testbench executable code is configured to generate stimuli to the circuitry on the programmable logic. The processor can be configured to execute the testbench executable code and the programmable logic can be configured to implement the circuitry for emulation of the DUT.
An analog-to-digital converter (ADC) circuitry includes channels that are interleaved with each other to generate output digital signals from input analog signals. A first channel includes sub-ADC circuitry, amplitude detection circuitry, and correction circuitry. Random chopping is applied by chopping circuitry at the input of the sub-ADC circuitry while sampling. The sub-ADC circuitry outputs digital data corresponding to the chopping states. Gain mismatch within the chopping circuitry is mitigated by determining correction values via the amplitude detection circuitry and the correction circuitry and applying the correction values to the output of the sub-ADC circuitry. The amplitude detection circuitry determines an amplitude difference between data signals. The correction circuitry is coupled to the output of the amplitude detection circuitry. The correction circuitry generates the correction values based on the amplitude difference, and outputs the correction values to adjust the data signals.
Examples herein describe inductor circuitry including an inductor coil having a helical shape. The inductor coil includes a first turn and a second turn which are disposed within an isolation wall. The isolation wall extends above the inductor coil and below the inductor coil. The inductor circuitry includes an inductor leg which extends through an aperture of the isolation wall. The inductor leg includes a first portion which is disposed within the isolation wall and a second portion that is disposed outside of the isolation wall.
A disclosed semiconductor device includes (1) a silicon stack comprising a front-side Back-End-of-Line (BEOL) stack and a back side BEOL stack, the front-side BEOL stack comprising a plurality of signal routes and the back-side BEOL stack comprising a plurality of power delivery routes, and (2) a plurality of auxiliary power paths formed within the front-side BEOL stack and electrically coupled to the plurality of power delivery routes of the back-side BEOL stack via a plurality of programmable switches, the plurality of power delivery routes, the plurality of programmable switches, and the plurality of auxiliary power paths forming a programmable power delivery network (PDN). Various other apparatuses, systems, and methods of operation are also disclosed.
Scheduling kernels on a system with heterogeneous compute circuits includes receiving, by a hardware processor, a plurality of kernels and a graph including a plurality of nodes corresponding to the plurality of kernels. The graph defines a control flow and a data flow for the plurality of kernels. The kernels are implemented within different ones of a plurality of compute circuits coupled to the hardware processor. A set of buffers for performing a job for the graph are allocated based, at least in part, on the data flow specified by the graph. Different ones of the kernels as implemented in the compute circuits are invoked based on the control flow defined by the graph.
A transceiver circuit is disclosed. The transceiver circuit includes a transmitter driver circuit configured to drive a transmit antenna. The transceiver circuit also includes a receiver circuit configured to generate digital signals based on received signals. The transceiver circuit also includes a loopback data path circuit electrically connected to the transmitter driver circuit and to the receiver circuit, where the loopback data path circuit is configured to conditionally provide signals from the transmitter driver circuit to the receiver circuit according to one or more control signals. The transceiver circuit also includes a controller configured to generate the control signals.
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
H04B 1/48 - Transmit/receive switching in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter
H04B 17/14 - MonitoringTesting of transmitters for calibration of the whole transmission and reception path, e.g. self-test loop-back
Disclosed herein is a chip package assembly that includes a package substrate coupled with an integrated circuit die, a stiffener attached to a top surface of the package substrate, and a connector assembly integrated with the stiffener. Both the connector assembly and the stiffener are disposed at a peripheral area of the top surface. The connector assembly includes a bracket and a connector. The connector is configured to connect with one or more optical cables or electrical connectors. The bracket may be formed by a cavity in the stiffener. The bracket may be attached to the top surface of the package substrate. The stiffener may be coupled with the bracket directly or via the connector. Additionally, a frame coupled to the stiffener or a PCB board may be used to secure the bracket in place.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/043 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H05K 1/14 - Structural association of two or more printed circuits
23.
RECLAMATION OF MEMORY ECC BITS FOR ERROR TOLERANT NUMBER FORMATS
A method for operating a computing system includes determining a baseline accuracy of the computing system based on a baseline data transmission format comprising a baseline quantity of data bits and a baseline quantity of error correction (ECC) bits, determining sample accuracies of the computing system based on sample data transmission formats each including a quantity of data bits and a quantity of ECC bits that are different from the baseline quantity of data bits and the baseline quantity of ECC bits, and storing data in a memory device of the computing system using at least one data transmission format, wherein the at least one data transmission format is selected from a group of data transmission formats comprising the baseline data transmission format and the sample data transmission formats and the at least one data transmission is selected based on the baseline accuracy and the sample accuracies.
An integrated circuit device includes interconnect circuitry. The interconnect circuitry includes interleaving switch circuitries, network switch circuitries, and crossbar circuitries. The interleaving switch circuitries are coupled to requester devices. A first interleaving switch circuitry includes first ports. The first interleaving switch circuitry receives a first memory command, and outputs the first memory command via first communication lanes connected to a first port based on a memory address of the first memory command. The network switch circuitries are connected to the interleaving switch circuitries. A first network switch circuitry is connected to the first communication lanes and route the first memory command along the first communication lanes based on the memory address. A first crossbar circuitry of the crossbar circuitries receives the first memory command from the first communication lanes, and outputs the first memory command to a first memory device of the memory devices associated with the memory.
Embodiments herein describe using virtual destinations to route packets through a NoC (105). In one embodiment, instead of decoding an address into a target destination ID of the NoC (105), an ingress logic block (115) assigns packets for multiple different targets the same virtual destination ID. For example, these targets may be in the same segment or location of the NoC (105). Thus, instead of the ingress logic block (115) having to store entries in a lookup-table for each target, it can have a single entry for the virtual destination ID. The packets for the targets are then routed using the virtual destination ID to a decoder switch (140) in the NoC (105). This decoder switch (140) can then use the address in the packet (which is different than the destination ID) to select the appropriate target destination ID.
Generating low skew clock solutions for local clocks in an integrated circuit includes, for a circuit design, determining a plurality of delay ranges for respective clock pins of a local clock net. Each delay range of the plurality of delay ranges includes an upper bound delay and a lower bound delay. The upper bound delays of the plurality of delay ranges are allocated as setup constraints for the respective clock pins of the local clock net. The lower bound delays are allocated as hold constraints for the respective clock pins of the local clock net. The local clock net is routed using the setup constraints and the hold constraints.
Control set optimization for a circuit design includes generating, by a processor, Observability Don't Care (ODC) expressions for registers of the circuit design. Redundant reset pins of the registers of the circuit design are determined by the processor by iteratively checking, on a per-cube and a per-literal basis for each ODC expression, whether a value of a literal causes the ODC expression to evaluate to 1. A modified version of the circuit design is generated by the processor by connecting one or more reset pins of the set of redundant reset pins to one or more constants.
An integrated circuit device includes interconnect circuitry. The interconnect circuitry includes interleaving switch circuitries, network switch circuitries, and crossbar circuitries. The interleaving switch circuitries are coupled to requester devices. A first interleaving switch circuitry includes first ports. The first interleaving switch circuitry receives a first memory command, and outputs the first memory command via first communication lanes connected to a first port based on a memory address of the first memory command. The network switch circuitries are connected to the interleaving switch circuitries. A first network switch circuitry is connected to the first communication lanes and route the first memory command along the first communication lanes based on the memory address. A first crossbar circuitry of the crossbar circuitries receives the first memory command from the first communication lanes, and outputs the first memory command to a first memory device of the memory devices associated with the memory
Some examples described herein provide for display image data reliability and safety, for example end-to-end safety methods, apparatuses, and systems for display systems. One example includes a method, including replacing video frames from input video streams with a set of test frames. The method further includes generating an alpha-blended video stream based on the set of test frames and the input video streams. The method further includes generating and inserting cyclic redundancy check (CRC) information for the set of test frames into secondary data packets associated with the alpha-blended video stream. The method further includes processing the set of test frames and video frames by a display controller to generate an output video stream. The method further includes performing an error detection procedure for the set of test frames using the CRC information to detect an error associated with the set of video frames.
Some examples described herein provide for instruction glitch protection in an integrated circuit. In an example, a method includes generating a random number by the integrated circuit. The method also includes identifying, based at least in part on the generated random number, a sequence from a set of sequences stored in a memory of the integrated circuit, each sequence of the set of sequences corresponding to an order of execution for a plurality of tasks. The method further includes performing, by the integrated circuit, each task of the plurality of tasks in the order of execution corresponding to the identified sequence.
Embodiments herein describe using virtual destinations to route packets through a NoC. In one embodiment, instead of decoding an address into a target destination ID of the NoC, an ingress logic block assigns packets for multiple different targets the same virtual destination ID. For example, these targets may be in the same segment or location of the NoC. Thus, instead of the ingress logic block having to store entries in a lookup-table for each target, it can have a single entry for the virtual destination ID. The packets for the targets are then routed using the virtual destination ID to a decoder switch in the NoC. This decoder switch can then use the address in the packet (which is different than the destination ID) to select the appropriate target destination ID.
In one example, a micro device includes a housing; a chip package disposed in the housing; a noise producing component coupled to the housing. The micro device also includes a noise reduction system having a reference microphone for detecting a noise from the noise producing component and a controller configured to receive the noise from the reference microphone and generate a masking sound signal in response to the detected noise. A speaker is coupled to the housing for producing a masking sound corresponding to the masking sound signal, whereby the masking sound reduces the noise. In another example, the noise producing component comprises a fan.
G10K 11/178 - Methods or devices for protecting against, or for damping, noise or other acoustic waves in general using interference effectsMasking sound by electro-acoustically regenerating the original acoustic waves in anti-phase
Memory driver circuitry for driving a memory cell or cells of a memory device includes first driver path circuitry and selection circuitry. The first driver path circuitry includes driver circuitry that outputs a first signal and selection circuitry that receives the first signal and a second signal, and outputs a first selected signal. The first selected signal is a selected one of the first signal and the second signal. The selection circuitry of the memory driver circuitry receives a third signal and a fourth signal, and outputs a bias voltage signal to header circuitry of a memory cell. The bias voltage signal is a selected one of the third signal and the fourth signal. The third signal corresponds to the first selected signal.
Examples herein describe a scalable tweak engine and prefetching tweak values. Regarding the scalable tweak engine, it can be designed to accommodate different bus widths of data. The scalable tweak engine described herein includes multiple tweak calculators that can be daisy chained together to output multiple tweak values every clock cycle. These tweak values can be sent to multiple encryption cores so that multiple data blocks can be encrypted in parallel. Regarding prefetching tweak values, previous encryption engines incur a delay as the tweak value (e.g., a metadata value) for a data block is calculated. In the embodiments herein, the encryption engine can include an independent metadata engine that determines the metadata value for a subsequent data block while the current data block is being encrypted.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
A level shifter may include a first transistor stack including at least four transistors arranged from a first voltage source to ground, including second and third transistors coupled with bias voltage source, and a fourth transistor coupled with an input to receive an input signal at a second voltage or ground. The level shifter may include a second transistor stack comprising at least four transistors arranged from the first voltage source to ground, including second and third transistors coupled with the bias voltage source, and a fourth transistor to receive an inverse of the input signal. A first transistor of the first transistor stack is cross-coupled with a first transistor of the second transistor stack. A level shifter may include a first output coupled with the second transistor stack between the second and third transistors to provide a first output signal at the first voltage or ground.
A system for clock variation measurement includes a first clock counter circuit configured to generate a plurality of first counts of a first clock signal, a second clock counter circuit configured to generate a plurality of second counts of a second clock signal, a first synchronizer circuit configured to synchronize the plurality of first counts according to a third clock signal, and a second synchronizer circuit configured to synchronize the plurality of second counts according to the third clock signal. The system includes a difference circuit configured to generate a plurality of differences from respective count pairs as synchronized. The system includes a variation circuit configured to generate a variation signal indicating an amount of variation between the first clock signal and the second clock signal based, at least in part, on the plurality of differences.
A method for predicting voltage drop on a power delivery network of a 3D stacked device includes receiving a spatial power distribution map of a plurality of semiconductor dies of the 3D stacked device, receiving a spatial power source node location map for a plurality of power source nodes coupled to the 3D stacked device, dividing vertically the spatial power distribution map and the spatial power source node location map into overlapping windows, determining a voltage drop map in each of the windows based on the divided spatial power distribution map and the divided spatial power source node location map, and combining the voltage drop map in each of the windows to form a composite voltage drop map.
Some examples described herein provide for interconnect in chiplet systems, for example system-level techniques for error correction in chip-to-chip interfaces. In an example, a method of error correction includes receiving, at a first chiplet, a data message via a set of interconnect, and transmitting a first control message that requests retransmission of the data message based on detecting an error associated with receiving the data message. The method also includes transmitting one or more instances of a second control message that indicates an idle operation at the first chiplet until the first chiplet receives a third control message that triggers an end of a retransmission mode. The method also includes transmitting a fourth control message frame indicating the end of the retransmission mode, and receiving a retransmission of the data message from the second chiplet.
Embodiments herein describe a host that polls a network adapter to receive data from a network. That is, the host/CPU/application thread polls the network adapter (e.g., the network card, NIC, or SmartNIC) to determine whether a packet has been received. If so, the host informs the network adapter to store the packet (or a portion of the packet) in a CPU register (205). If the requested data has not yet been received by the network adapter from the network (210), the network adapter can delay (230) the responding to the request to provide extra time for the adapter to receive the data from the network.
G06F 13/12 - Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
G06F 13/22 - Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 13/366 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter
Embodiments herein describe a host that polls a network adapter to receive data from a network. That is, the host/CPU/application thread polls the network adapter (e.g., the network card, NIC, or SmartNIC) to determine whether a packet has been received. If so, the host informs the network adapter to store the packet (or a portion of the packet) in a CPU register. If the requested data has not yet been received by the network adapter from the network, the network adapter can delay the responding to the request to provide extra time for the adapter to receive the data from the network.
H04L 43/103 - Active monitoring, e.g. heartbeat, ping or trace-route with adaptive polling, i.e. dynamically adapting the polling rate
H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
A processor [102] employs a hardware signal monitor [110] to manage signaling for accelerators [103, 104]. The hardware signal monitor monitors designated memory addresses assigned to accelerator signals. In response to a memory write [112] to one of the designated memory addresses, the hardware signal monitor executes a set of one or more operations (referred to as a callback). The hardware signal monitor thereby enables improved and enhanced signaling features, such as asynchronous signaling between agents, inter-accelerator signaling, and inter-process signaling.
Embodiments herein describe techniques to build multi-die fieldprogrammable gate arrays (FPGAs) using chip-on-wafer (CoW) technology. In an embodiment, FPGA chiplets (i.e., dies) and an interposer substrate include respective hybrid bonding connectors. Metal layers of the interposer substrate are patterned to provide inter-die communications amongst the multiple dies via the hybrid bonding connectors, and the dies communicate with one another via the hybrid bonding connectors using a non-serialized protocol native to the FPGA. The dies may communicate with one another through edge-based hybrid bonding connectors (e.g., in a symmetrical fashion). The metal layers of the interposer substrate may also support intra-die communications (e.g., data, clocks, and/or controls) and/or provide power, clock(s), and/or configuration parameters to the dies via hybrid bonding connectors within central regions of the dies. The IC device may include more than 1000 tracks per millimeter (e.g., more than 1600, 2800, 3500, or greater).
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
Examples herein describe techniques for producing a three-dimensional (3D) die stack. The techniques include stacking a first die on top of a second die. The first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die. The techniques further include stacking a third die on top of the second die. The third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
44.
MULTI-HOST AND MULTI-CLIENT DIRECT MEMORY ACCESS SYSTEM HAVING A READ SCHEDULER
A direct memory access (DMA) system includes a read request circuit configured to receive read requests from a plurality of client circuits. The DMA system includes a response reassembly circuit configured to reorder read completion data received from a plurality of different hosts in response to the read requests. The DMA system includes a read scheduler circuit configured to schedule conveyance of the read completion data from the response reassembly circuit to the plurality of client circuits. The DMA system includes a data pipeline circuit including a plurality of data paths. The plurality of data paths are configured to convey the read completion data as scheduled by the read scheduler circuit to respective ones of the plurality of client circuits.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
Embodiments herein describe devices that indude an interposer with a stitch formed from overlapping exposure areas, which may result in the interposer having a total surface area that is greater than a maximum reticle field corresponding to the exposure areas. Two or more Integrated circuits (e.g., chiplets) can be disposed on the interposer. At least one of the integrated circuits is disposed over the stitch. The interposer can provide chip-to-chip connections between the integrated circuits.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
A memory device includes a first bit cell comprising a first inverter, the first inverter comprising a p-type transistor coupled to an n-type transistor, and header circuitry coupled to the first inverter and comprising a first header transistor and a second header transistor, the first header transistor having a gate configured to receive a bias voltage, the second header transistor having a gate configured to receive a reference voltage.
Embodiments herein describe techniques to build multi-die field-programmable gate arrays (FPGAs) using chip-on-wafer (CoW) technology. In an embodiment, FPGA chiplets (i.e., dies) and an interposer substrate include respective hybrid bonding connectors. Metal layers of the interposer substrate are patterned to provide inter-die communications amongst the multiple dies via the hybrid bonding connectors, and the dies communicate with one another via the hybrid bonding connectors using a non-serialized protocol native to the FPGA. The dies may communicate with one another through edge-based hybrid bonding connectors (e.g., in a symmetrical fashion). The metal layers of the interposer substrate may also support intra-die communications (e.g., data, clocks, and/or controls) and/or provide power, clock(s), and/or configuration parameters to the dies via hybrid bonding connectors within central regions of the dies. The IC device may include more than 1000 tracks per millimeter (e.g., more than 1600, 2800, 3500, or greater).
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A smart cache implementation for image warping is provided by dividing an output image into a plurality of blocks corresponding to initial coordinates in the output image; dividing an input image into at least a first and second regions of pixels, where the first region overlaps the second region; generating an unsorted remap vector of the plurality of blocks for image warping the input image; identifying a first and second subsets of blocks from the plurality of blocks that can be reconstructed using the first and second regions respectively; generating a region-based sorting, a line-based sorting of the region-based sorting, a column-based sorting of the line-based sorting based on the initial x-coordinates of the blocks in the unsorted remap vector, and a sorted remap vector by sorting the column-based sorting based on initial y-coordinates of the blocks in the unsorted remap vector.
Performance evaluation of a heterogeneous hardware platform includes implementing a traffic generator design in an integrated circuit. The traffic generator design includes traffic generator kernels including a traffic generator kernel implemented in a data processing array of the integrated circuit and a traffic generator kernel implemented in a programmable logic of the integrated circuit. The traffic generator design is executed in the integrated circuit. The traffic generator kernels implement data access patterns by, at least in part, generating dummy data. Performance data is generated from executing the traffic generator design in the integrated circuit. The performance data is output from the integrated circuit.
A method, system, and circuit arrangement involve synthesizing a circuit design specified in a register transfer level (RTL) specification into a netlist. The RTL specification includes an assert statement that specifies a conditional expression involving one or more signals specified in the circuit design to be checked during simulation, and the synthesizing includes synthesizing the assert statement into netlist elements. The design tool places and routes the netlist into a circuit design layout and generates implementation data from the layout.
Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface includes circuitry for performing multiple different C2C protocols to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocols. During runtime, the chip then uses the selected C2C protocol to communicate with the other chip in the C2C connection.
Disclosed circuit arrangements include a physically unclonable function (PUF) entropy source having passive circuit elements and active circuit elements. A first die has one or more metal layers and an active layer, and the passive circuit elements are disposed in the one or more metal layers. A second die has one or more metal layers and an active layer. The active circuit elements are coupled to the passive circuit elements and are disposed in the active layer of the second die, and the first die and the second die are in a stacked structure. The stacked structure has the one or more metal layers of the first die disposed between the active layer of the first die and the active layer of the second die.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
54.
PROCESS AND TEMPERATURE TRACKING ON-CHIP SUPPLY REGULATION FOR LOW JITTER APPLICATIONS
On chip integrated circuit supply voltage regulator has a reference voltage that varies, based on process and temperature conditions of the integrated circuit. Supply voltage is boosted up if the active transistor load devices operate in a Slow-Slow process condition and/or temperature rises. Higher supply voltage improves the system performance (jitter/delay) if the load network includes switching components. If the active transistor load devices operate in a Fast-Fast process condition then the supply voltage is reduced without loss of performance and a savings in power. The variable reference voltage is generated based on process and temperature conditions of the semiconductor integrated circuit devices (transistors). The voltage regulator will automatically have its variable reference voltage adjusted based upon the process condition fabrication and temperature of the areas of the integrated circuit where the active transistor load devices are located.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
55.
HIGH-LEVEL SYNTHESIS OF DESIGNS USING LOOP-AWARE EXECUTION INFORMATION
High-level synthesis of designs using loop-aware execution information includes generating, using computer hardware, an intermediate representation (IR) of a design specified in a high-level programming language. The design is for an integrated circuit. Execution information analysis is performed on the IR of the design generating analysis results for functions of the design. The analysis results of the design are transformed by embedding the analysis results in a plurality of regions of the IR of the design. Selected regions of the plurality of regions are merged based on the analysis results, as embedded, for the selected regions. The IR of the design is scheduled using the analysis results subsequent to the merging.
Some examples described herein provide for controlling output modulation amplitude for optoelectronic devices. In an example, a method includes transmitting a data pattern to an optical modulator device. The method also includes identifying, for each heater control value of a plurality of heater control values for a heater thermally coupled with the optical modulator device, an optical modulation amplitude corresponding to the heater control value based on a corresponding photodiode current value identified while transmitting the data pattern. The method also includes determining a maximum optical modulation amplitude for the optical modulator device based on a plurality of optical modulation amplitudes corresponding to the plurality of heater control values according to the identifying. The method also includes controlling the heater based at least in part on the determined maximum optical modulation amplitude that has been modified according to scaling maximum photodiode current values.
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
An integrated circuit (IC) device includes functional circuitry and data capture circuitry that stores a state of the functional circuitry in a buffer and outputs contents of the buffer to an external device based on a trigger. An embedded processor interacts with the functional circuitry based on a computer program, and initiates the trigger. The processor may initiate the trigger at a selectable break-point of the computer program and/or based on data generated by the functional circuitry. The processor may also output corresponding states of variables managed by the processor. The processor may initiate the trigger by asserting a predetermined value on a communication path between the processor and the functional circuitry, or over another communication path (e.g., an AXI debug hub) between the processor and the data capture circuitry. The processor may monitor/control the data capture circuitry through an API.
Embodiments herein describe techniques to extend a network-on-chip (NoC) across multiple IC dice in 3D. An integrated circuit (IC) device includes first and second vertically-stacked IC dice, and an inter-die bus that interfaces between the second die and a NoC packet switch (NPS) of the first die. The inter-die bus may include one or more driver circuits coupled to inter-die links of the inter-die bus. Communications over the inter-die links may be synchronous (e.g., packet-based) or asynchronous with the NPS (e.g., based on a point-to-point protocol, such as an AXI protocol). The inter-die bus may interface with a circuit block of the second IC device via a point-to-point (e.g., AXI) protocol or via a NPS of the second IC die. The IC device may include multiple inter-die buses, which may expand inter-die and intra-die routing options
A smart interrupt controller (SIC) routs an interrupt to a specific processor by dynamically changing the affinity of the interrupt based upon the processor power state and/or system load thereof. The SIC arbitrates interrupt servicing based on various parameters such as interrupt priority, interrupt affinity, processor load and processor power. Interrupt load sharing between selected processors increases overall computer system performance. Interrupt latency times decrease by avoiding unnecessary switching of processor power states from an inactive state to an active state by instead routing the interrupt to a different processor already in an active state. Interrupt latency times will decrease by routing the interrupt service request from a heavily loaded processor to one that is not so heavily loaded. Whereby active processor clock cycles are effectively utilized for interrupt servicing. Overall computer system power requirements will be reduced by eliminating unnecessary waking up of an inactive (sleeping) processor.
Methods and circuit arrangements for self-authentication of a data set by circuitry on a semi-conductor die include export circuitry and a non-volatile memory disposed on the semiconductor die. The export circuitry is configured to generate a public-private key pair and generate a signature from a data set and a private key of the key pair. The export circuitry is configured to store a version of a public key of the key pair in the non-volatile memory, destroy the private key, and output the data set to external storage.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
61.
METHODS AND APPARATUSES FOR WAVELENGTH LOCKING FOR OPTICAL WAVELENGTH DIVISON MULIPLEXED MICRO-RING MODULATORS
Some examples described herein provide for controlling output modulation amplitude for optoelectronic devices. In an example, a method includes transmitting a data pattern to an optical modulator device. The method also includes identifying, for each heater control value of a plurality of heater control values for a heater thermally coupled with the optical modulator device, an optical modulation amplitude corresponding to the heater control value based on a corresponding photodiode current value identified while transmitting the data pattern. The method also includes determining a maximum optical modulation amplitude for the optical modulator device based on a plurality of optical modulation amplitudes corresponding to the plurality of heater control values according to the identifying. The method also includes controlling the heater based at least in part on the determined maximum optical modulation amplitude that has been modified according to scaling maximum photodiode current values.
Embodiments herein describe techniques to extend a network-on-chip (NoC) across multiple IC dice in 3D. An integrated circuit (IC) device includes first and second vertically-stacked IC dice, and an inter-die bus that interfaces between the second die and a NoC packet switch (NFS) of the first die. The inter-die bus may include one or more driver circuits coupled to inter-die links of the inter-die bus. Communications over the inter-die links may be synchronous (e.g., packet-based) or asynchronous with the NFS (e.g., based on a point-to-point protocol, such as an AXI protocol). The inter-die bus may interface with a circuit block of the second IC device via a point-to-point (e.g., AXI) protocol or via a NFS of the second IC die. The IC device may include multiple inter-die buses, which may expand inter-die and intra-die routing options.
A digital processing engine is configured to receive input data from a memory. The input data comprises first input channels. The digital processing engine is further configured to convolve, with a convolution model, the input data. The convolution model comprises a first filter layer configured to generate first intermediate data having first output channels. A number of the first output channels is less than a number of the first input channels. The convolution model further comprises a second filter layer comprising shared spatial filters and is configured to generate second intermediate data by convolving each of the first output channels with a respective one of the shared spatial filters. Each of the shared spatial filters comprises first weights. The digital processing engine is further configured to generate output data from the second intermediate data and store the output data in the memory.
G06N 3/04 - Architecture, e.g. interconnection topology
G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersectionsConnectivity analysis, e.g. of connected components
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
An integrated circuit (IC) device includes functional circuitry and distributed management circuitry that includes multiple configuration interface manager (CIM) circuits that receive respective programming partitions as configuration packets over a first communication channel (e.g., a network-on-chip, or NoC), and perform management operations on respective regions of the functional circuitry in parallel with one another based on the respective configuration packets, including providing configuration parameters to the respective regions of the functional circuitry. The configuration packets may be streamed to the CIM circuits from a central manager and/or read by direct memory access (DMA) engines of the CIM circuits. The central manager may configure the CIM circuits and the NoC over a second communication channel (e.g., a global communication ring interconnect) during an initialization phase. The CIM circuits may include respective packet processors, random-access-memory, authentication circuitry, error detection circuitry, and interconnect circuitry having standardized bus-widths.
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
65.
GLOBAL PLACEMENT OF CIRCUIT DESIGNS USING A CALIBRATED SIMPLE TIMER
A design tool calibrates current delays of timing arcs in a current placement of a circuit design by determining respective delta-delays of the timing arcs. The current placement is represented by timing nodes connected by the timing arcs in a graph. The calibrating is based on a first timer model indicating arrival times at the timing nodes based on timing propagation without accounting for timing exceptions, and a reference timer indicating slacks that account for timing exceptions at the timing nodes. The design tool updates the current delays of the timing arcs using the delta-delays and delays from the first timer model and updates the current placement based on the current delays. The updating of the current delays and updating of the current placement are repeated in response to failure to satisfy placement convergence criteria.
Some examples described herein provide for controlling output modulation amplitude for optoelectronic devices. In an example, a method includes transmitting a first data pattern to an optical modulator device. The method also includes determining, while transmitting the first data pattern and for each heater control value of a plurality of heater control values for a heater, a photodiode current value associated with the optical modulator device to generate a plurality of photodiode current values corresponding to the plurality of heater control values. The method also includes determining a maximum optical modulation amplitude for the optical modulator device based at least in part on the plurality of photodiode current values corresponding to the plurality of heater control values. The method also includes controlling the heater for the optical modulator device based on the maximum optical modulation amplitude.
Driver circuitry for memory controller circuitry includes level shifter circuitry, inverter circuitry, and output circuitry. The level shifter circuitry receives an input data signal and outputs a first level shifted data signal and a second level shifted data signal based on the input data signal. The inverter circuitry is connected to the level shifter circuitry, receives the first level shifted data signal and the second level shifted data signal, and outputs a first inverted data signal via a first output node and a second inverted data signal via a second output node. The inverter circuitry includes mitigation circuitry coupled to the first output node and the second output node and alters one or more of the first inverted data signal and the second inverted data signal. The output circuitry outputs an output data signal based on the first inverted data signal and the second inverted data signal.
An integrated circuit (IC) device includes functional circuitry and distributed management circuitry that includes multiple configuration interface manager (CIM) circuits that receive respective programming partitions as configuration packets over a first communication channel (e.g., a network-on-chip, or NoC), and perform management operations on respective regions of the functional circuitry in parallel with one another based on the respective configuration packets, including providing configuration parameters to the respective regions of the functional circuitry. The configuration packets may be streamed to the CIM circuits from a central manager and/or read by direct memory access (DMA) engines of the CIM circuits. The central manager may configure the CIM circuits and the NoC over a second communication channel (e.g., a global communication ring interconnect) during an initialization phase. The CIM circuits may include respective packet processors, random-access-memory, authentication circuitry, error detection circuitry, and interconnect circuitry having standardized bus-widths.
Embodiments herein describe a self-reliant Network Interface Controller (NIC) that can perform the maintenance and control operations part of performing a distributed computation which relies on data received from multiple peers (or nodes) that are connected by a network. Rather than a CPU-driven adaptive compute where the CPU(s) in a host perform maintenance and control operations, the embodiments herein shift these operations to the NIC. The NIC can perform control operations such as determining when data has been received from remote peers, or a compute task has been completed and then inform the host CPU when the operation is complete.
G06F 13/366 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter
Embodiments herein describe a memory controller (MC) in a first integrated circuit (IC) that connect to circuitry in the same integrated circuit (e.g., horizontal direction) and to circuitry in a second IC in the vertical direction. That is, the first and second ICs can be stacked on each other where the MC in the first IC provides an interface for both circuitry in the first IC as well as circuitry in the second IC to communicate with a separate memory device. Thus, the MC includes data paths in both the X direction (e.g., within the same IC) and the Y direction (e.g., to an external IC). In this manner, the MC can provide an interface for circuitry in multiple ICs (or dies or chiplets) to the same external memory device.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
71.
Adding soft logic to flush a pipeline and reduce current ramp
An integrated circuit (IC) device includes a circuit comprising pipeline stages, and a controller circuitry configured to: load a static value into each of the pipeline stages based on a change in a clock enable (CE) signal, and sequentially deactivate each of the pipeline stages after a quantity of cycles of a reference clock signal that occur after the change of the CE signal, wherein the quantity of the cycles of the clock signal is based on a quantity of the pipeline stages.
Hardware event trace windowing for a data processing array includes executing a user design using a plurality of active tiles of a data processing array disposed in an integrated circuit. A trace start condition is detected subsequent to a start of execution of the user design. In response to the trace start condition, trace data is generated using one or more of the plurality of active tiles of the data processing array. A trace stop condition is detected during execution of the user design. In response to the trace stop condition, the generating the trace data by the one or more of the plurality of active tiles is discontinued.
Within an integrated circuit including a processor system and a data processing array, one or more kernels in the processor system are executed in response to a scheduling request from a host data processing system. The one or more kernels receive configuration data for implementing trace or profiling of a user design executable by a plurality of active tiles of the data processing array. Using the one or more kernels, selected tiles of the plurality of active tiles of the data processing array are configured with the configuration data to perform the trace or the profiling. Trace data or profiling data is generated through execution of the user design by the data processing array. The one or more kernels provide the trace data or the profiling data to the host data processing system.
A silicon-on-insulator (SOI) dense-wavelength-division-multiplexing (DWDM) device includes micro-ring modulators (MRMs) having radii under 5 micrometers. A 16-channel embodiment may provide a free spectral range of 3.2 THz, 200 GHz channel spacing, 41 GHz bandwidth, and a Q factor of 4500. PN junctions of rib ring waveguides (RWRs) may be perpendicular or parallel with a plane of the RWRs. On-chip inductive components may be used to match reactances of the PN junctions. The RWRs may be relatively wide and a rib bus waveguide may be relatively narrow (e.g., narrower than the RWRs). MRM outer slaps may be wider than inner slabs. Regions inside and outside of the RWRs, including slabs at optical coupling gaps may be doped to improve modulation efficiency. Regions of the rib bus waveguide distant from the optical coupling gaps may be undoped. Cavities may be provided below the MRMs and associated heater elements.
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
A congestion prediction machine learning model is trained to generate, prior to placement, a prediction value indicative of a congestion level likely to result from placement and routing of a netlist based on features of the netlist. In response to the prediction value indicating the congestion level is greater than a threshold, a design tool determines an implementation-flow action and performs the implementation-flow action to generate implementation data that is suitable for making an integrated circuit.
A memory controller includes driver circuitry, which includes main driver circuitry and hold driver circuitry. The main driver circuitry and hold driver circuitry are connected to an output node. The main driver circuitry comprises driver slice circuitries and outputs a first output signal to the output node based on a first input signal and a second input signal and a number of activated driver slice circuitries. The hold drive circuitry receive the first input signal and outputs a second output signal. The second output signal is delayed with reference to the first output signal by a first delay amount.
Embodiments herein describe an integrated circuit (IC) device that includes a multi-protocol, multi-cast, and multi-root network-on-chip (NoC) with dynamic resource allocation (DFxNoC). A DFxNoC may include a plurality of end-points (EPs) that include functional circuitry, first and second root devices, and a bus network that includes multi-port switch circuits and a network of fixed links amongst the multi-port switch circuits, the root devices, and the EPs, where the root devices output respective first and second clocks, and where the multi-port switch circuits are dynamically configurable to route the first and second clocks to respective first and second selectable sets of one or more of the EPs over the network of fixed links.
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
Disclosed methods and systems include debug circuitry registering candidate sample values in a plurality of sample periods while application circuitry is active. The candidate sample values indicate states of a plurality of candidate signals of the application circuitry. Sample values of first probed signals from each sample period are written to a sample memory using a mapping based on bit-widths of the first probed signals. The sample values of the first probed signals are selected from the candidate sample values. The mapping is updated based on bit-widths of second probed signals, and sample values of the second probed signals from each sample period are written to the sample memory using the mapping. The sample values of the second probed signals are selected from the candidate sample values.
A cascaded thin-oxide N-Well voltage steering circuit includes a reference voltage generator that outputs a reference voltage within a range of first and second supply voltages, a first voltage steering circuit that outputs a higher available one of the reference voltage and the second supply voltage as an interim voltage, and a second voltage steering circuit that outputs a higher available one of the first voltage and the interim voltage at an output of the second voltage steering circuit. The interim voltage is applied to N-wells of PMOS transistors of the first voltage steering circuit. The output of the second voltage steering circuit is applied to N-wells of PMOS transistors of the second voltage steering circuit. The output of the second voltage steering circuit may also be applied to N-wells of PMOS transistors of other circuitry. The cascaded thin-oxide N-Well voltage steering circuit may consist substantially of thin-oxide PMOS transistors.
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
80.
DATA PROCESSING ARRAY EVENT TRACE CUSTOMIZATION, OFFLOAD, AND ANALYSIS
Event trace includes implementing a design for a data processing array of a target integrated circuit (IC) by, at least in part, adding a trace data offload architecture to the design. One or more selected tiles of the data processing array used by the design as implemented in the target IC are configured to generate trace data based on user-specified runtime settings for performing a trace. During execution of the design by the data processing array, trace data as generated by the one or more selected tiles of the data processing array is conveyed to a memory of the target IC using the trace data offload architecture. A trace report is generated from the trace data using a data processing system coupled to the target IC.
A digital-to analog converter (DAC) includes an unary cell comprising unary slices, the unary slices are coupled in parallel, an intermediate significant bit (ISB) cell comprising ISB slices, the ISB slices are coupled in parallel, and a least significant bit (LSB) cell comprising LSB slices, the LSB slices are coupled in parallel, the unary cell, the ISB cell and the LSB cell each being coupled to each other, each of the unary slices comprising a set of cross-coupled capacitive elements including first capacitive elements having a first end coupled to a node positioned between a first pair of transistors and a second end coupled to a node positioned between a second pair of transistors, and second capacitive elements having a first end coupled to a node positioned between a third pair of transistors and a second end coupled to a node positioned between a fourth pair of transistors.
A 3D device includes a first semiconductor chip and a second semiconductor chip stacked vertically. The first semiconductor chip includes a first plurality of tiles. The second semiconductor chip includes a second plurality of tiles. A bus electrically couples each of the first plurality of tiles to a corresponding one of the second plurality of tiles based on assignments of the first plurality of tiles and the second plurality of tiles to tile-to-tile pairs that define a minimized sum of bus delays among each possible tile-to-tile pairs. In each tile-to-tile pair, a net electrically couples each of a first plurality of pins to a corresponding one of a second plurality of pins based on assignments of the first plurality of pins to the second plurality of pins that define a minimized sum of net delays among each possible pin-to-pin pairs.
A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.
Embodiments herein describe arranging TX and RX circuitry in ICs such that rotated and mirrored ICs are aligned when connected in a multiple-chip device. In one embodiment, the TX circuitry (e.g., TX physical layer or PHY) is arranged in one row while the RX circuitry (e.g., RX physical layer or PHY) is arranged in another row. As such, when an IC is rotated or mirrored, at least one TX PHY is aligned with a RX PHY on the other IC. As such, non-crossing chip-to-chip connections can be formed through the interposer.
Embodiments herein describe arranging TX and RX circuitry in iCs such that rotated and mirrored ICs are aligned when connected in a multiple-chip device. In one embodiment, the TX circuitry (e.g., TX physical layer or PHY) is arranged in one row while the RX circuitry (e.g., RX physical layer or PHY) is arranged in another row. As such, when an IC is rotated or mirrored, at least one TX PHY is aligned with a RX PHY on the other IC. As such, non-crossing chip-to-chip connections can be formed through the interposer.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
87.
DESCRIPTOR CACHE EVICTION FOR MULTI-QUEUE DIRECT MEMORY ACCESS
Evicting queues from a memory of a direct memory access system includes monitoring a global eviction timer. From a plurality of descriptor lists stored in a plurality of entries of a cache memory, a set of candidate descriptor lists is determined. The set of candidate descriptor lists includes one or more of the plurality of descriptor lists in a prefetch only state. An eviction event can be detected by detecting a first eviction condition including a state of the global eviction timer and a second eviction condition. In response to detecting the eviction event, a descriptor list from the set of candidate descriptor lists is selected for eviction. The selected descriptor list can be evicted from the cache memory.
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
88.
VARIABLE BUFFER SIZE DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT MEMORY ACCESS SYSTEM
Descriptor fetch for a direct memory access system includes, in response to receiving a first data packet, fetching a plurality of descriptors including a first descriptor and a specified number of prefetched descriptors. The plurality of descriptors specify different buffer sizes. In response to processing each data packet, selectively replenishing the plurality of fetched descriptors to the specified number of prefetched descriptors.
Descriptor fetch for a direct memory access system includes obtaining a descriptor for processing a received data packet. A determination is made as to whether the descriptor is a head descriptor of a chain descriptor. In response to determining that the descriptor is a head descriptor, one or more tail descriptors are fetched from a descriptor table specified by the head descriptor. A number of the tail descriptors fetched is determined based on a running count of a buffer size of the chain descriptor determined as each tail descriptor is fetched compared to a size of the data packet.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
90.
DIRECT MEMORY ACCESS SYSTEM WITH READ REASSEMBLY CIRCUIT
A direct memory access (DMA) system includes a plurality of read circuits and a switch coupled to a plurality of data port controllers configured to communicate with one or more data processing systems. The DMA system includes a read scheduler circuit coupled to the plurality of read circuits and the switch. The read scheduler circuit is configured to receive read requests from the plurality of read circuits, request allocation of entries of a data memory for the read requests, and submit the read requests to the one more data processing systems via the switch. The DMA system includes a read reassembly circuit coupled to the plurality of read circuits, the switch, and the read scheduler circuit. The read reassembly circuit is configured to reorder read completion data received from the switch for the read requests and provide read completion data, as reordered, to the plurality of read circuits.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
91.
CONTROL SET OPTIMIZATION FOR IMPLEMENTING CIRCUIT DESIGNS IN INTEGRATED CIRCUIT DEVICES
Implementing circuit designs in integrated circuit devices includes determining, using computer hardware, regular control sets, super control sets, and mega control sets for a circuit design. Control set optimization is performed on the circuit design. Performing control set optimization includes performing a clock-enable-only control set reduction for each super control set. Performing control set optimization includes performing a set/reset control set reduction and a clock-enable control set reduction for each mega control set. The circuit design is selectively modified by committing changes determined from the control set reductions to the circuit design on a per control set basis based on an improvement of a cost metric for each control set.
Offloading trace data from an integrated circuit (IC) can include receiving, by a high-speed debug port (HSDP) trace circuit, streams of trace data from a plurality of compute circuits of different compute circuit types. The compute circuits and the HSDP trace circuit are disposed in a same IC. Compute circuit type identifiers are included within the trace data. The compute circuit type identifiers specify the compute circuit type from which respective ones of the streams of the trace data originate. Debug trace packets (DTPs) are generated from the trace data and transmitted over a high-speed communication link to a trace data storage device (TDSD) external to the IC. Within the TDSD, trace data from the DTPs are stored in a memory of the TDSD.
Passive intermodulation (PIM) correction circuitry mitigates the effects of PIM within receiver circuitry. The PIM correction circuitry includes modeling circuitry, adapt circuitry, and compensation circuitry. The modeling circuitry receives one or more transmitter data signals. Further, the modeling circuitry generates output signals based on the one or more transmitter data signals, and a correction signal based on the output signals and correction coefficients. The correction signal is combined with an input signal to generate a corrected output signal. The adapt circuitry receives a first output signal of the output signals and the corrected output signal. The adapt circuitry correlates the first output signal with the corrected output signal to generate update values. The compensation circuitry receives the update values and generates updated correction coefficients based on the update values.
H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
94.
LOW LATENCY PHASE ALIGNMENT FOR PARALLEL DATA PATHS
Receiver circuitry for mitigating effects associated with the phase differences between a capture clock signal and the receipt of a data signal includes first data path circuitry, second data path circuitry, and phase alignment circuitry. The first data path circuitry receives a first data signal based on a capture clock signal. The second data path circuitry receives a second data signal based on the capture clock signal. The phase alignment circuitry adjusts the phase of a first launch clock signal and a second launch clock signal based on a first clock slip signal and a second clock slip signal, respectively. The phase alignment circuitry adjusts a phase of the capture clock signal relative to one of the first and the second launch clock signals based on a first adjustment value associated with the first data path circuitry and a second adjustment value associated with the second data path circuitry.
Embodiments herein describe assigning integrated circuits with defects as variants of the integrated circuit design. Each variant can deactivate different circuitry in the integrated circuit design. A location of the defect can be matched to a variant that has a deactivated region that covers the defect. The integrated circuit can then be assigned to that variant.
Embodiments herein describe various 2x2 configuration of integrated circuits (ICs), where the iCs can communicate with multipie neighboring ICs using chip-to- chip interfaces. As such, 2x2 configurations are improvements over other horizontal chip integration formats (such as 1x2, 1x3, and 1x4) where some of the ICs can directly communicate with only one other IC.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H05K 1/14 - Structural association of two or more printed circuits
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
An integrated circuit includes a high-speed debug port trace circuit. The high-speed debug trace circuit includes a plurality of input receiver circuits each configured to receive a stream of trace data. The plurality of input receiver circuits receive streams of trace data from a plurality of compute circuits of different compute circuit types. The plurality of compute circuits are within the integrated circuit. The high-speed debug trace circuit includes a stream selector circuit configured to perform multiple stages of arbitration among the plurality of streams of trace data to generate output trace data. The stream selector circuit inserts compute circuit type identifiers within the output trace data. Each compute circuit type identifier specifies a compute circuit type that originated each portion of trace data of the output trace data. The high-speed debug trace circuit includes an output transmitter circuit configured to output the output trace data.
Some examples described herein provide for an encrypted data quantization apparatus and method, for example a memory controller to quantize encrypted data using a cache. One or more embodiments includes obtaining a first set of plaintext data bits to be stored in a memory device using an encryption scheme. A memory address for encrypted data bits to be stored in the memory device is identified for a first subset of plaintext data bits. A second set of plaintext data bits associated with the memory address is obtained from a cache, if present. The second set of plaintext data bits are modified according to the first set of plaintext data bits to be stored in the memory device to generate a third set of plaintext data bits that are then encoded according to the encryption scheme for storage in the memory device.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
G06F 12/1009 - Address translation using page tables, e.g. page table structures
Embodiments herein describe various 2×2 configuration of integrated circuits (ICs), where the ICs can communicate with multiple neighboring ICs using chip-to-chip interfaces. As such, 2×2 configurations are improvements over other horizontal chip integration formats (such as 1×2, 1×3, and 1×4) where some of the ICs can directly communicate with only one other IC.
A 3D stacked device includes a plurality of semiconductor chips stacked in a vertical direction. The semiconductor chips each include a plurality of portions grouped into slivers according to the column they lie in. Each of the portions further includes a plurality of blocks grouped into sub-slivers and interconnected by inter-block bridges. A block that must be functional on the bottommost chip of the 3D stacked device is configured to bypass a neighboring nonfunctional block on the same chip by using a communication path of an inter-block bridge to a neighboring functional block that is in the same sub-sliver as the nonfunctional block but in a different chip. So long as only one of the blocks in a sub-sliver is nonfunctional, the inter-block bridges permit the other blocks in the sub-sliver to receive and route data.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
