Embodiments herein describe devices that indude an interposer with a stitch formed from overlapping exposure areas, which may result in the interposer having a total surface area that is greater than a maximum reticle field corresponding to the exposure areas. Two or more Integrated circuits (e.g., chiplets) can be disposed on the interposer. At least one of the integrated circuits is disposed over the stitch. The interposer can provide chip-to-chip connections between the integrated circuits.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
2.
MULTI-HOST AND MULTI-CLIENT DIRECT MEMORY ACCESS SYSTEM HAVING A READ SCHEDULER
A direct memory access (DMA) system includes a read request circuit configured to receive read requests from a plurality of client circuits. The DMA system includes a response reassembly circuit configured to reorder read completion data received from a plurality of different hosts in response to the read requests. The DMA system includes a read scheduler circuit configured to schedule conveyance of the read completion data from the response reassembly circuit to the plurality of client circuits. The DMA system includes a data pipeline circuit including a plurality of data paths. The plurality of data paths are configured to convey the read completion data as scheduled by the read scheduler circuit to respective ones of the plurality of client circuits.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
Examples herein describe techniques for producing a three-dimensional (3D) die stack. The techniques include stacking a first die on top of a second die. The first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die. The techniques further include stacking a third die on top of the second die. The third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die.
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
4.
BUILDING MULTI-DIE FPGAS USING CHIP-ON-WAFER TECHNOLOGY
Embodiments herein describe techniques to build multi-die fieldprogrammable gate arrays (FPGAs) using chip-on-wafer (CoW) technology. In an embodiment, FPGA chiplets (i.e., dies) and an interposer substrate include respective hybrid bonding connectors. Metal layers of the interposer substrate are patterned to provide inter-die communications amongst the multiple dies via the hybrid bonding connectors, and the dies communicate with one another via the hybrid bonding connectors using a non-serialized protocol native to the FPGA. The dies may communicate with one another through edge-based hybrid bonding connectors (e.g., in a symmetrical fashion). The metal layers of the interposer substrate may also support intra-die communications (e.g., data, clocks, and/or controls) and/or provide power, clock(s), and/or configuration parameters to the dies via hybrid bonding connectors within central regions of the dies. The IC device may include more than 1000 tracks per millimeter (e.g., more than 1600, 2800, 3500, or greater).
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p.ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A processor [102] employs a hardware signal monitor [110] to manage signaling for accelerators [103, 104]. The hardware signal monitor monitors designated memory addresses assigned to accelerator signals. In response to a memory write [112] to one of the designated memory addresses, the hardware signal monitor executes a set of one or more operations (referred to as a callback). The hardware signal monitor thereby enables improved and enhanced signaling features, such as asynchronous signaling between agents, inter-accelerator signaling, and inter-process signaling.
Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
A memory device includes a first bit cell comprising a first inverter, the first inverter comprising a p-type transistor coupled to an n-type transistor, and header circuitry coupled to the first inverter and comprising a first header transistor and a second header transistor, the first header transistor having a gate configured to receive a bias voltage, the second header transistor having a gate configured to receive a reference voltage.
Embodiments herein describe techniques to build multi-die field-programmable gate arrays (FPGAs) using chip-on-wafer (CoW) technology. In an embodiment, FPGA chiplets (i.e., dies) and an interposer substrate include respective hybrid bonding connectors. Metal layers of the interposer substrate are patterned to provide inter-die communications amongst the multiple dies via the hybrid bonding connectors, and the dies communicate with one another via the hybrid bonding connectors using a non-serialized protocol native to the FPGA. The dies may communicate with one another through edge-based hybrid bonding connectors (e.g., in a symmetrical fashion). The metal layers of the interposer substrate may also support intra-die communications (e.g., data, clocks, and/or controls) and/or provide power, clock(s), and/or configuration parameters to the dies via hybrid bonding connectors within central regions of the dies. The IC device may include more than 1000 tracks per millimeter (e.g., more than 1600, 2800, 3500, or greater).
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A smart cache implementation for image warping is provided by dividing an output image into a plurality of blocks corresponding to initial coordinates in the output image; dividing an input image into at least a first and second regions of pixels, where the first region overlaps the second region; generating an unsorted remap vector of the plurality of blocks for image warping the input image; identifying a first and second subsets of blocks from the plurality of blocks that can be reconstructed using the first and second regions respectively; generating a region-based sorting, a line-based sorting of the region-based sorting, a column-based sorting of the line-based sorting based on the initial x-coordinates of the blocks in the unsorted remap vector, and a sorted remap vector by sorting the column-based sorting based on initial y-coordinates of the blocks in the unsorted remap vector.
G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales
Performance evaluation of a heterogeneous hardware platform includes implementing a traffic generator design in an integrated circuit. The traffic generator design includes traffic generator kernels including a traffic generator kernel implemented in a data processing array of the integrated circuit and a traffic generator kernel implemented in a programmable logic of the integrated circuit. The traffic generator design is executed in the integrated circuit. The traffic generator kernels implement data access patterns by, at least in part, generating dummy data. Performance data is generated from executing the traffic generator design in the integrated circuit. The performance data is output from the integrated circuit.
A method, system, and circuit arrangement involve synthesizing a circuit design specified in a register transfer level (RTL) specification into a netlist. The RTL specification includes an assert statement that specifies a conditional expression involving one or more signals specified in the circuit design to be checked during simulation, and the synthesizing includes synthesizing the assert statement into netlist elements. The design tool places and routes the netlist into a circuit design layout and generates implementation data from the layout.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/31 - Saisie informatique, p.ex. éditeurs spécifiquement adaptés à la conception de circuits
G06F 30/323 - Traduction ou migration, p.ex. logique à logique, traduction de langage descriptif de matériel ou traduction de liste d’interconnections [Netlist]
12.
IIC WITH ADAPTIVE CHIP-TO-CHIP INTERFACE TO SUPPORT DIFFERENT CHIP-TO-CHIP PROTOCOLS
Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface includes circuitry for performing multiple different C2C protocols to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocols. During runtime, the chip then uses the selected C2C protocol to communicate with the other chip in the C2C connection.
High-level synthesis of designs using loop-aware execution information includes generating, using computer hardware, an intermediate representation (IR) of a design specified in a high-level programming language. The design is for an integrated circuit. Execution information analysis is performed on the IR of the design generating analysis results for functions of the design. The analysis results of the design are transformed by embedding the analysis results in a plurality of regions of the IR of the design. Selected regions of the plurality of regions are merged based on the analysis results, as embedded, for the selected regions. The IR of the design is scheduled using the analysis results subsequent to the merging.
G06F 30/323 - Traduction ou migration, p.ex. logique à logique, traduction de langage descriptif de matériel ou traduction de liste d’interconnections [Netlist]
14.
MULTI-DIE PHYSICALLY UNCLONABLE FUNCTION ENTROPY SOURCE
Disclosed circuit arrangements include a physically unclonable function (PUF) entropy source having passive circuit elements and active circuit elements. A first die has one or more metal layers and an active layer, and the passive circuit elements are disposed in the one or more metal layers. A second die has one or more metal layers and an active layer. The active circuit elements are coupled to the passive circuit elements and are disposed in the active layer of the second die, and the first die and the second die are in a stacked structure. The stacked structure has the one or more metal layers of the first die disposed between the active layer of the first die and the active layer of the second die.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
15.
PROCESS AND TEMPERATURE TRACKING ON-CHIP SUPPLY REGULATION FOR LOW JITTER APPLICATIONS
On chip integrated circuit supply voltage regulator has a reference voltage that varies, based on process and temperature conditions of the integrated circuit. Supply voltage is boosted up if the active transistor load devices operate in a Slow-Slow process condition and/or temperature rises. Higher supply voltage improves the system performance (jitter/delay) if the load network includes switching components. If the active transistor load devices operate in a Fast-Fast process condition then the supply voltage is reduced without loss of performance and a savings in power. The variable reference voltage is generated based on process and temperature conditions of the semiconductor integrated circuit devices (transistors). The voltage regulator will automatically have its variable reference voltage adjusted based upon the process condition fabrication and temperature of the areas of the integrated circuit where the active transistor load devices are located.
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
16.
METHODS AND APPARATUSES FOR WAVELENGTH LOCKING FOR OPTICAL WAVELENGTH DIVISION MULTIPLEXED MICRO-RING MODULATORS
Some examples described herein provide for controlling output modulation amplitude for optoelectronic devices. In an example, a method includes transmitting a data pattern to an optical modulator device. The method also includes identifying, for each heater control value of a plurality of heater control values for a heater thermally coupled with the optical modulator device, an optical modulation amplitude corresponding to the heater control value based on a corresponding photodiode current value identified while transmitting the data pattern. The method also includes determining a maximum optical modulation amplitude for the optical modulator device based on a plurality of optical modulation amplitudes corresponding to the plurality of heater control values according to the identifying. The method also includes controlling the heater based at least in part on the determined maximum optical modulation amplitude that has been modified according to scaling maximum photodiode current values.
G02F 1/01 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur
G02F 1/015 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des éléments à semi-conducteurs ayant au moins une barrière de potentiel, p.ex. jonction PN, PIN
An integrated circuit (IC) device includes functional circuitry and data capture circuitry that stores a state of the functional circuitry in a buffer and outputs contents of the buffer to an external device based on a trigger. An embedded processor interacts with the functional circuitry based on a computer program, and initiates the trigger. The processor may initiate the trigger at a selectable break-point of the computer program and/or based on data generated by the functional circuitry. The processor may also output corresponding states of variables managed by the processor. The processor may initiate the trigger by asserting a predetermined value on a communication path between the processor and the functional circuitry, or over another communication path (e.g., an AXI debug hub) between the processor and the data capture circuitry. The processor may monitor/control the data capture circuitry through an API.
Embodiments herein describe techniques to extend a network-on-chip (NoC) across multiple IC dice in 3D. An integrated circuit (IC) device includes first and second vertically-stacked IC dice, and an inter-die bus that interfaces between the second die and a NoC packet switch (NPS) of the first die. The inter-die bus may include one or more driver circuits coupled to inter-die links of the inter-die bus. Communications over the inter-die links may be synchronous (e.g., packet-based) or asynchronous with the NPS (e.g., based on a point-to-point protocol, such as an AXI protocol). The inter-die bus may interface with a circuit block of the second IC device via a point-to-point (e.g., AXI) protocol or via a NPS of the second IC die. The IC device may include multiple inter-die buses, which may expand inter-die and intra-die routing options
A smart interrupt controller (SIC) routs an interrupt to a specific processor by dynamically changing the affinity of the interrupt based upon the processor power state and/or system load thereof. The SIC arbitrates interrupt servicing based on various parameters such as interrupt priority, interrupt affinity, processor load and processor power. Interrupt load sharing between selected processors increases overall computer system performance. Interrupt latency times decrease by avoiding unnecessary switching of processor power states from an inactive state to an active state by instead routing the interrupt to a different processor already in an active state. Interrupt latency times will decrease by routing the interrupt service request from a heavily loaded processor to one that is not so heavily loaded. Whereby active processor clock cycles are effectively utilized for interrupt servicing. Overall computer system power requirements will be reduced by eliminating unnecessary waking up of an inactive (sleeping) processor.
Methods and circuit arrangements for self-authentication of a data set by circuitry on a semi-conductor die include export circuitry and a non-volatile memory disposed on the semiconductor die. The export circuitry is configured to generate a public-private key pair and generate a signature from a data set and a private key of the key pair. The export circuitry is configured to store a version of a public key of the key pair in the non-volatile memory, destroy the private key, and output the data set to external storage.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H04L 9/30 - Clé publique, c. à d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
21.
METHODS AND APPARATUSES FOR WAVELENGTH LOCKING FOR OPTICAL WAVELENGTH DIVISON MULIPLEXED MICRO-RING MODULATORS
Some examples described herein provide for controlling output modulation amplitude for optoelectronic devices. In an example, a method includes transmitting a data pattern to an optical modulator device. The method also includes identifying, for each heater control value of a plurality of heater control values for a heater thermally coupled with the optical modulator device, an optical modulation amplitude corresponding to the heater control value based on a corresponding photodiode current value identified while transmitting the data pattern. The method also includes determining a maximum optical modulation amplitude for the optical modulator device based on a plurality of optical modulation amplitudes corresponding to the plurality of heater control values according to the identifying. The method also includes controlling the heater based at least in part on the determined maximum optical modulation amplitude that has been modified according to scaling maximum photodiode current values.
Embodiments herein describe techniques to extend a network-on-chip (NoC) across multiple IC dice in 3D. An integrated circuit (IC) device includes first and second vertically-stacked IC dice, and an inter-die bus that interfaces between the second die and a NoC packet switch (NFS) of the first die. The inter-die bus may include one or more driver circuits coupled to inter-die links of the inter-die bus. Communications over the inter-die links may be synchronous (e.g., packet-based) or asynchronous with the NFS (e.g., based on a point-to-point protocol, such as an AXI protocol). The inter-die bus may interface with a circuit block of the second IC device via a point-to-point (e.g., AXI) protocol or via a NFS of the second IC die. The IC device may include multiple inter-die buses, which may expand inter-die and intra-die routing options.
A digital processing engine is configured to receive input data from a memory. The input data comprises first input channels. The digital processing engine is further configured to convolve, with a convolution model, the input data. The convolution model comprises a first filter layer configured to generate first intermediate data having first output channels. A number of the first output channels is less than a number of the first input channels. The convolution model further comprises a second filter layer comprising shared spatial filters and is configured to generate second intermediate data by convolving each of the first output channels with a respective one of the shared spatial filters. Each of the shared spatial filters comprises first weights. The digital processing engine is further configured to generate output data from the second intermediate data and store the output data in the memory.
G06V 10/44 - Extraction de caractéristiques locales par analyse des parties du motif, p.ex. par détection d’arêtes, de contours, de boucles, d’angles, de barres ou d’intersections; Analyse de connectivité, p.ex. de composantes connectées
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
An integrated circuit (IC) device includes functional circuitry and distributed management circuitry that includes multiple configuration interface manager (CIM) circuits that receive respective programming partitions as configuration packets over a first communication channel (e.g., a network-on-chip, or NoC), and perform management operations on respective regions of the functional circuitry in parallel with one another based on the respective configuration packets, including providing configuration parameters to the respective regions of the functional circuitry. The configuration packets may be streamed to the CIM circuits from a central manager and/or read by direct memory access (DMA) engines of the CIM circuits. The central manager may configure the CIM circuits and the NoC over a second communication channel (e.g., a global communication ring interconnect) during an initialization phase. The CIM circuits may include respective packet processors, random-access-memory, authentication circuitry, error detection circuitry, and interconnect circuitry having standardized bus-widths.
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
25.
GLOBAL PLACEMENT OF CIRCUIT DESIGNS USING A CALIBRATED SIMPLE TIMER
A design tool calibrates current delays of timing arcs in a current placement of a circuit design by determining respective delta-delays of the timing arcs. The current placement is represented by timing nodes connected by the timing arcs in a graph. The calibrating is based on a first timer model indicating arrival times at the timing nodes based on timing propagation without accounting for timing exceptions, and a reference timer indicating slacks that account for timing exceptions at the timing nodes. The design tool updates the current delays of the timing arcs using the delta-delays and delays from the first timer model and updates the current placement based on the current delays. The updating of the current delays and updating of the current placement are repeated in response to failure to satisfy placement convergence criteria.
Some examples described herein provide for controlling output modulation amplitude for optoelectronic devices. In an example, a method includes transmitting a first data pattern to an optical modulator device. The method also includes determining, while transmitting the first data pattern and for each heater control value of a plurality of heater control values for a heater, a photodiode current value associated with the optical modulator device to generate a plurality of photodiode current values corresponding to the plurality of heater control values. The method also includes determining a maximum optical modulation amplitude for the optical modulator device based at least in part on the plurality of photodiode current values corresponding to the plurality of heater control values. The method also includes controlling the heater for the optical modulator device based on the maximum optical modulation amplitude.
H04B 10/50 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs
H04B 10/508 - Génération d’impulsions, p.ex. génération de solitons
27.
DRIVER CIRCUITRY WITH REDUCED INTERSYMBOL INTERFERENCE JITTER
Driver circuitry for memory controller circuitry includes level shifter circuitry, inverter circuitry, and output circuitry. The level shifter circuitry receives an input data signal and outputs a first level shifted data signal and a second level shifted data signal based on the input data signal. The inverter circuitry is connected to the level shifter circuitry, receives the first level shifted data signal and the second level shifted data signal, and outputs a first inverted data signal via a first output node and a second inverted data signal via a second output node. The inverter circuitry includes mitigation circuitry coupled to the first output node and the second output node and alters one or more of the first inverted data signal and the second inverted data signal. The output circuitry outputs an output data signal based on the first inverted data signal and the second inverted data signal.
An integrated circuit (IC) device includes functional circuitry and distributed management circuitry that includes multiple configuration interface manager (CIM) circuits that receive respective programming partitions as configuration packets over a first communication channel (e.g., a network-on-chip, or NoC), and perform management operations on respective regions of the functional circuitry in parallel with one another based on the respective configuration packets, including providing configuration parameters to the respective regions of the functional circuitry. The configuration packets may be streamed to the CIM circuits from a central manager and/or read by direct memory access (DMA) engines of the CIM circuits. The central manager may configure the CIM circuits and the NoC over a second communication channel (e.g., a global communication ring interconnect) during an initialization phase. The CIM circuits may include respective packet processors, random-access-memory, authentication circuitry, error detection circuitry, and interconnect circuitry having standardized bus-widths.
Embodiments herein describe a self-reliant Network Interface Controller (NIC) that can perform the maintenance and control operations part of performing a distributed computation which relies on data received from multiple peers (or nodes) that are connected by a network. Rather than a CPU-driven adaptive compute where the CPU(s) in a host perform maintenance and control operations, the embodiments herein shift these operations to the NIC. The NIC can perform control operations such as determining when data has been received from remote peers, or a compute task has been completed and then inform the host CPU when the operation is complete.
G06F 13/38 - Transfert d'informations, p.ex. sur un bus
G06F 13/366 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée utilisant un arbitre d'interrogation centralisé
Embodiments herein describe a memory controller (MC) in a first integrated circuit (IC) that connect to circuitry in the same integrated circuit (e.g., horizontal direction) and to circuitry in a second IC in the vertical direction. That is, the first and second ICs can be stacked on each other where the MC in the first IC provides an interface for both circuitry in the first IC as well as circuitry in the second IC to communicate with a separate memory device. Thus, the MC includes data paths in both the X direction (e.g., within the same IC) and the Y direction (e.g., to an external IC). In this manner, the MC can provide an interface for circuitry in multiple ICs (or dies or chiplets) to the same external memory device.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
31.
ADDING SOFT LOGIC TO FLUSH A PIPELINE AND REDUCE CURRENT RAMP
An integrated circuit (IC) device includes a circuit comprising pipeline stages, and a controller circuitry configured to: load a static value into each of the pipeline stages based on a change in a clock enable (CE) signal, and sequentially deactivate each of the pipeline stages after a quantity of cycles of a reference clock signal that occur after the change of the CE signal, wherein the quantity of the cycles of the clock signal is based on a quantity of the pipeline stages.
Hardware event trace windowing for a data processing array includes executing a user design using a plurality of active tiles of a data processing array disposed in an integrated circuit. A trace start condition is detected subsequent to a start of execution of the user design. In response to the trace start condition, trace data is generated using one or more of the plurality of active tiles of the data processing array. A trace stop condition is detected during execution of the user design. In response to the trace stop condition, the generating the trace data by the one or more of the plurality of active tiles is discontinued.
Within an integrated circuit including a processor system and a data processing array, one or more kernels in the processor system are executed in response to a scheduling request from a host data processing system. The one or more kernels receive configuration data for implementing trace or profiling of a user design executable by a plurality of active tiles of the data processing array. Using the one or more kernels, selected tiles of the plurality of active tiles of the data processing array are configured with the configuration data to perform the trace or the profiling. Trace data or profiling data is generated through execution of the user design by the data processing array. The one or more kernels provide the trace data or the profiling data to the host data processing system.
A silicon-on-insulator (SOI) dense-wavelength-division-multiplexing (DWDM) device includes micro-ring modulators (MRMs) having radii under 5 micrometers. A 16-channel embodiment may provide a free spectral range of 3.2 THz, 200 GHz channel spacing, 41 GHz bandwidth, and a Q factor of 4500. PN junctions of rib ring waveguides (RWRs) may be perpendicular or parallel with a plane of the RWRs. On-chip inductive components may be used to match reactances of the PN junctions. The RWRs may be relatively wide and a rib bus waveguide may be relatively narrow (e.g., narrower than the RWRs). MRM outer slaps may be wider than inner slabs. Regions inside and outside of the RWRs, including slabs at optical coupling gaps may be doped to improve modulation efficiency. Regions of the rib bus waveguide distant from the optical coupling gaps may be undoped. Cavities may be provided below the MRMs and associated heater elements.
G02F 1/025 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des éléments à semi-conducteurs ayant au moins une barrière de potentiel, p.ex. jonction PN, PIN dans une structure de guide d'ondes optique
G02F 1/01 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur
A congestion prediction machine learning model is trained to generate, prior to placement, a prediction value indicative of a congestion level likely to result from placement and routing of a netlist based on features of the netlist. In response to the prediction value indicating the congestion level is greater than a threshold, a design tool determines an implementation-flow action and performs the implementation-flow action to generate implementation data that is suitable for making an integrated circuit.
G06F 30/31 - Saisie informatique, p.ex. éditeurs spécifiquement adaptés à la conception de circuits
G06F 30/323 - Traduction ou migration, p.ex. logique à logique, traduction de langage descriptif de matériel ou traduction de liste d’interconnections [Netlist]
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/392 - Conception de plans ou d’agencements, p.ex. partitionnement ou positionnement
36.
BOOSTED DRIVER CIRCUITRY OF A LOW VOLTAGE SUPPLY MEMORY CONTROLLER
A memory controller includes driver circuitry, which includes main driver circuitry and hold driver circuitry. The main driver circuitry and hold driver circuitry are connected to an output node. The main driver circuitry comprises driver slice circuitries and outputs a first output signal to the output node based on a first input signal and a second input signal and a number of activated driver slice circuitries. The hold drive circuitry receive the first input signal and outputs a second output signal. The second output signal is delayed with reference to the first output signal by a first delay amount.
Embodiments herein describe an integrated circuit (IC) device that includes a multi-protocol, multi-cast, and multi-root network-on-chip (NoC) with dynamic resource allocation (DFxNoC). A DFxNoC may include a plurality of end-points (EPs) that include functional circuitry, first and second root devices, and a bus network that includes multi-port switch circuits and a network of fixed links amongst the multi-port switch circuits, the root devices, and the EPs, where the root devices output respective first and second clocks, and where the multi-port switch circuits are dynamically configurable to route the first and second clocks to respective first and second selectable sets of one or more of the EPs over the network of fixed links.
H03K 17/56 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs
Event trace includes implementing a design for a data processing array of a target integrated circuit (IC) by, at least in part, adding a trace data offload architecture to the design. One or more selected tiles of the data processing array used by the design as implemented in the target IC are configured to generate trace data based on user-specified runtime settings for performing a trace. During execution of the design by the data processing array, trace data as generated by the one or more selected tiles of the data processing array is conveyed to a memory of the target IC using the trace data offload architecture. A trace report is generated from the trace data using a data processing system coupled to the target IC.
Disclosed methods and systems include debug circuitry registering candidate sample values in a plurality of sample periods while application circuitry is active. The candidate sample values indicate states of a plurality of candidate signals of the application circuitry. Sample values of first probed signals from each sample period are written to a sample memory using a mapping based on bit-widths of the first probed signals. The sample values of the first probed signals are selected from the candidate sample values. The mapping is updated based on bit-widths of second probed signals, and sample values of the second probed signals from each sample period are written to the sample memory using the mapping. The sample values of the second probed signals are selected from the candidate sample values.
G06F 30/33 - Vérification de la conception, p.ex. simulation fonctionnelle ou vérification du modèle
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
40.
Cascaded reference based thin-oxide only N-well steering circuit for contention solution in multi-supply designs
A cascaded thin-oxide N-Well voltage steering circuit includes a reference voltage generator that outputs a reference voltage within a range of first and second supply voltages, a first voltage steering circuit that outputs a higher available one of the reference voltage and the second supply voltage as an interim voltage, and a second voltage steering circuit that outputs a higher available one of the first voltage and the interim voltage at an output of the second voltage steering circuit. The interim voltage is applied to N-wells of PMOS transistors of the first voltage steering circuit. The output of the second voltage steering circuit is applied to N-wells of PMOS transistors of the second voltage steering circuit. The output of the second voltage steering circuit may also be applied to N-wells of PMOS transistors of other circuitry. The cascaded thin-oxide N-Well voltage steering circuit may consist substantially of thin-oxide PMOS transistors.
G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
41.
CROSS-COUPLED CAPACITIVE ELEMENTS IN HIGHSPEED DAC
A digital-to analog converter (DAC) includes an unary cell comprising unary slices, the unary slices are coupled in parallel, an intermediate significant bit (ISB) cell comprising ISB slices, the ISB slices are coupled in parallel, and a least significant bit (LSB) cell comprising LSB slices, the LSB slices are coupled in parallel, the unary cell, the ISB cell and the LSB cell each being coupled to each other, each of the unary slices comprising a set of cross-coupled capacitive elements including first capacitive elements having a first end coupled to a node positioned between a first pair of transistors and a second end coupled to a node positioned between a second pair of transistors, and second capacitive elements having a first end coupled to a node positioned between a third pair of transistors and a second end coupled to a node positioned between a fourth pair of transistors.
A 3D device includes a first semiconductor chip and a second semiconductor chip stacked vertically. The first semiconductor chip includes a first plurality of tiles. The second semiconductor chip includes a second plurality of tiles. A bus electrically couples each of the first plurality of tiles to a corresponding one of the second plurality of tiles based on assignments of the first plurality of tiles and the second plurality of tiles to tile-to-tile pairs that define a minimized sum of bus delays among each possible tile-to-tile pairs. In each tile-to-tile pair, a net electrically couples each of a first plurality of pins to a corresponding one of a second plurality of pins based on assignments of the first plurality of pins to the second plurality of pins that define a minimized sum of net delays among each possible pin-to-pin pairs.
A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.
Embodiments herein describe arranging TX and RX circuitry in ICs such that rotated and mirrored ICs are aligned when connected in a multiple-chip device. In one embodiment, the TX circuitry (e.g., TX physical layer or PHY) is arranged in one row while the RX circuitry (e.g., RX physical layer or PHY) is arranged in another row. As such, when an IC is rotated or mirrored, at least one TX PHY is aligned with a RX PHY on the other IC. As such, non-crossing chip-to-chip connections can be formed through the interposer.
Embodiments herein describe arranging TX and RX circuitry in iCs such that rotated and mirrored ICs are aligned when connected in a multiple-chip device. In one embodiment, the TX circuitry (e.g., TX physical layer or PHY) is arranged in one row while the RX circuitry (e.g., RX physical layer or PHY) is arranged in another row. As such, when an IC is rotated or mirrored, at least one TX PHY is aligned with a RX PHY on the other IC. As such, non-crossing chip-to-chip connections can be formed through the interposer.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
46.
PASSIVE INTERMODULATION MITIGATION COEFFICIENT DETERMINATION BASED ON RECEIVED DATA
Passive intermodulation (PIM) correction circuitry mitigates the effects of PIM within receiver circuitry. The PIM correction circuitry includes modeling circuitry, adapt circuitry, and compensation circuitry. The modeling circuitry receives one or more transmitter data signals. Further, the modeling circuitry generates output signals based on the one or more transmitter data signals, and a correction signal based on the output signals and correction coefficients. The correction signal is combined with an input signal to generate a corrected output signal. The adapt circuitry receives a first output signal of the output signals and the corrected output signal. The adapt circuitry correlates the first output signal with the corrected output signal to generate update values. The compensation circuitry receives the update values and generates updated correction coefficients based on the update values.
Receiver circuitry for mitigating effects associated with the phase differences between a capture clock signal and the receipt of a data signal includes first data path circuitry, second data path circuitry, and phase alignment circuitry. The first data path circuitry receives a first data signal based on a capture clock signal. The second data path circuitry receives a second data signal based on the capture clock signal. The phase alignment circuitry adjusts the phase of a first launch clock signal and a second launch clock signal based on a first clock slip signal and a second clock slip signal, respectively. The phase alignment circuitry adjusts a phase of the capture clock signal relative to one of the first and the second launch clock signals based on a first adjustment value associated with the first data path circuitry and a second adjustment value associated with the second data path circuitry.
Embodiments herein describe assigning integrated circuits with defects as variants of the integrated circuit design. Each variant can deactivate different circuitry in the integrated circuit design. A location of the defect can be matched to a variant that has a deactivated region that covers the defect. The integrated circuit can then be assigned to that variant.
Evicting queues from a memory of a direct memory access system includes monitoring a global eviction timer. From a plurality of descriptor lists stored in a plurality of entries of a cache memory, a set of candidate descriptor lists is determined. The set of candidate descriptor lists includes one or more of the plurality of descriptor lists in a prefetch only state. An eviction event can be detected by detecting a first eviction condition including a state of the global eviction timer and a second eviction condition. In response to detecting the eviction event, a descriptor list from the set of candidate descriptor lists is selected for eviction. The selected descriptor list can be evicted from the cache memory.
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
50.
VARIABLE BUFFER SIZE DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT MEMORY ACCESS SYSTEM
Descriptor fetch for a direct memory access system includes, in response to receiving a first data packet, fetching a plurality of descriptors including a first descriptor and a specified number of prefetched descriptors. The plurality of descriptors specify different buffer sizes. In response to processing each data packet, selectively replenishing the plurality of fetched descriptors to the specified number of prefetched descriptors.
Descriptor fetch for a direct memory access system includes obtaining a descriptor for processing a received data packet. A determination is made as to whether the descriptor is a head descriptor of a chain descriptor. In response to determining that the descriptor is a head descriptor, one or more tail descriptors are fetched from a descriptor table specified by the head descriptor. A number of the tail descriptors fetched is determined based on a running count of a buffer size of the chain descriptor determined as each tail descriptor is fetched compared to a size of the data packet.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
52.
DIRECT MEMORY ACCESS SYSTEM WITH READ REASSEMBLY CIRCUIT
A direct memory access (DMA) system includes a plurality of read circuits and a switch coupled to a plurality of data port controllers configured to communicate with one or more data processing systems. The DMA system includes a read scheduler circuit coupled to the plurality of read circuits and the switch. The read scheduler circuit is configured to receive read requests from the plurality of read circuits, request allocation of entries of a data memory for the read requests, and submit the read requests to the one more data processing systems via the switch. The DMA system includes a read reassembly circuit coupled to the plurality of read circuits, the switch, and the read scheduler circuit. The read reassembly circuit is configured to reorder read completion data received from the switch for the read requests and provide read completion data, as reordered, to the plurality of read circuits.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
53.
CONTROL SET OPTIMIZATION FOR IMPLEMENTING CIRCUIT DESIGNS IN INTEGRATED CIRCUIT DEVICES
Implementing circuit designs in integrated circuit devices includes determining, using computer hardware, regular control sets, super control sets, and mega control sets for a circuit design. Control set optimization is performed on the circuit design. Performing control set optimization includes performing a clock-enable-only control set reduction for each super control set. Performing control set optimization includes performing a set/reset control set reduction and a clock-enable control set reduction for each mega control set. The circuit design is selectively modified by committing changes determined from the control set reductions to the circuit design on a per control set basis based on an improvement of a cost metric for each control set.
Offloading trace data from an integrated circuit (IC) can include receiving, by a high-speed debug port (HSDP) trace circuit, streams of trace data from a plurality of compute circuits of different compute circuit types. The compute circuits and the HSDP trace circuit are disposed in a same IC. Compute circuit type identifiers are included within the trace data. The compute circuit type identifiers specify the compute circuit type from which respective ones of the streams of the trace data originate. Debug trace packets (DTPs) are generated from the trace data and transmitted over a high-speed communication link to a trace data storage device (TDSD) external to the IC. Within the TDSD, trace data from the DTPs are stored in a memory of the TDSD.
An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
Embodiments herein describe various 2x2 configuration of integrated circuits (ICs), where the iCs can communicate with multipie neighboring ICs using chip-to- chip interfaces. As such, 2x2 configurations are improvements over other horizontal chip integration formats (such as 1x2, 1x3, and 1x4) where some of the ICs can directly communicate with only one other IC.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H05K 1/14 - Association structurale de plusieurs circuits imprimés
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
57.
MEMORY CONTROLLER CRYPTOGRAPHIC DATA QUANTIZATION USING A CACHE
Some examples described herein provide for an encrypted data quantization apparatus and method, for example a memory controller to quantize encrypted data using a cache. One or more embodiments includes obtaining a first set of plaintext data bits to be stored in a memory device using an encryption scheme. A memory address for encrypted data bits to be stored in the memory device is identified for a first subset of plaintext data bits. A second set of plaintext data bits associated with the memory address is obtained from a cache, if present. The second set of plaintext data bits are modified according to the first set of plaintext data bits to be stored in the memory device to generate a third set of plaintext data bits that are then encoded according to the encryption scheme for storage in the memory device.
H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES
G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page
Embodiments herein describe various 2×2 configuration of integrated circuits (ICs), where the ICs can communicate with multiple neighboring ICs using chip-to-chip interfaces. As such, 2×2 configurations are improvements over other horizontal chip integration formats (such as 1×2, 1×3, and 1×4) where some of the ICs can directly communicate with only one other IC.
G06F 30/392 - Conception de plans ou d’agencements, p.ex. partitionnement ou positionnement
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
59.
REDUNDANCY SCHEME FOR ACTIVATING CIRCUITRY ON A BASE DIE OF A 3D stacked device
A 3D stacked device includes a plurality of semiconductor chips stacked in a vertical direction. The semiconductor chips each include a plurality of portions grouped into slivers according to the column they lie in. Each of the portions further includes a plurality of blocks grouped into sub-slivers and interconnected by inter-block bridges. A block that must be functional on the bottommost chip of the 3D stacked device is configured to bypass a neighboring nonfunctional block on the same chip by using a communication path of an inter-block bridge to a neighboring functional block that is in the same sub-sliver as the nonfunctional block but in a different chip. So long as only one of the blocks in a sub-sliver is nonfunctional, the inter-block bridges permit the other blocks in the sub-sliver to receive and route data.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
60.
EQUIPMENT DESIGN AND TESTING USING IN-SITU ON-DIE TIME-DOMAIN REFLECTOMETRY
Using “in-situ on-die time-domain reflectometry (TDR)” with data signal paths of integrated circuits, printed circuit boards, and data processing equipment and systems allows testing, verification and troubleshooting of data channel signal path impedance variations including the package, escape routing, socket, board, and cable/connectors provides fast characterization thereof. Operation of “in-situ on-die TDR” uses existing analog-to-digital converter (ADC) and data transmitter (TX) drivers of an integrated circuit to act as a TDR sampling head by performing a user interface-based TDR sampling with a step-waveform generated by an integrated circuit TX driver. Then sampling the step-waveform with the ADC of the integrated circuit using spline interpolation to obtain the over-sampled waveform. Once the sampled step-waveform is obtained, the TDR profile of the sampled data channels may be calculated. Large amounts of impedance variation data may thus be collected during either integrated circuit manufacturer or customer-built data communications channel testing.
Embodiments herein describe a solution for deterministic de-assertion of write and read resets of an asynchronous gearbox FIFO having unequal write and read data bit widths. Proposed approaches look for a stable region between read and write clock phases by sweeping one of the clock phases until the leading edges (phases) of both clocks are aligned then releasing the write and read resets deterministically based upon a change in cyclic behavior of detected logic levels of a reset beacon waveform.
G06F 5/06 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour modifier la vitesse de débit des données, c. à d. régularisation de la vitesse
A method of fabricating a chip package is provided, and a chip package fabricated using the same are provided. The method includes connecting a photonic die to a substrate of the chip package and attaching a protection apparatus to the substrate. The method also includes attaching a photonic connector to the photonic die. At least a portion of the photonic connector is disposed inside a housing of the protection apparatus. A fabrication process is performed on the chip package while the photonic connector is inside the housing. After processing, the photonic connector is removed from the housing.
An integrated circuit includes a high-speed debug port trace circuit. The high-speed debug trace circuit includes a plurality of input receiver circuits each configured to receive a stream of trace data. The plurality of input receiver circuits receive streams of trace data from a plurality of compute circuits of different compute circuit types. The plurality of compute circuits are within the integrated circuit. The high-speed debug trace circuit includes a stream selector circuit configured to perform multiple stages of arbitration among the plurality of streams of trace data to generate output trace data. The stream selector circuit inserts compute circuit type identifiers within the output trace data. Each compute circuit type identifier specifies a compute circuit type that originated each portion of trace data of the output trace data. The high-speed debug trace circuit includes an output transmitter circuit configured to output the output trace data.
An integrated circuit (IC) device includes a controller circuitry having an input connected to a photodiode of an optoelectronic circuitry and an output connected to a biasing circuitry, the biasing circuitry having an input connected to the output of the controller circuitry, the controller circuitry configured to transmit a transimpedance control signal code to the biasing circuitry configured to cause the biasing circuitry to offset a DC current component of the output of the photodiode.
An integrated circuit (IC) die includes a body having a dielectric layer and a plurality of contact pads formed on the dielectric layer. The IC die also includes a passivation layer disposed on the dielectric layer. The passivation layer has a plurality of openings exposing the plurality of contact pads. A plurality of inner under-bump-metallurgy (“UBM”) structures are disposed on a first portion of the plurality of openings, and a plurality of outer UBM structures are disposed on a second portion of the plurality of openings. The plurality of inner UBM structures have uniform spacing in a direction parallel to an edge of the body. The plurality of outer UBM structures are positioned around the plurality of inner UBM structures, and each of the plurality of outer UBM structures having a longitudinal axis directed toward a central area of the IC die.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A method for circuit die stacking can include providing a first circuit die having a first metal stack, wherein the first circuit die corresponds to a primary thermal source of an integrated circuit including the first circuit die. The method can additionally include providing a second circuit die of the integrated circuit, wherein the second circuit die has a second metal stack and is configured for connection to at least one of a package substrate or an additional die. The method can also include connecting the first metal stack to the second metal stack. Various other methods, systems, and computer-readable media are also disclosed.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p.ex. dissipateurs de chaleur
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
A method for providing backside power can include providing a first circuit die having a first metal stack. The method can also include connecting a second metal stack of a second circuit die to the first metal stack of the first circuit die, wherein a backside power delivery network is located in a passivation layer of at least one of the first circuit die or the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A method for die pair partitioning can include providing a first circuit die having a first metal stack. The method can additionally include positioning a second circuit die having a second metal stack in a manner that places a temperature sensor in a transistor layer of the second circuit die in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die. The method can also include connecting the first metal stack of the first circuit die to the second metal stack of the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.
H01L 23/34 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
A method for die pair partitioning can include providing a circuit die that has a metal stack and that includes a majority of logic transistors of an integrated circuit. The method can also include providing one or more additional circuit die that have one or more additional metal stacks of which at least one is connected to the metal stack of the circuit die and a majority of static random access memory and analog devices of the integrated circuit. The method can further include connecting at least one of the one or more additional metal stacks to the metal stack of the circuit die. Various other methods, systems, and computer-readable media are also disclosed.
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
70.
High-speed communication between integrated circuits of an emulation system
An emulation system can include a first integrated circuit (IC) including first circuitry and a first transceiver. The first circuitry is configured to emulate a first partition of a circuit design. The first circuitry is clocked by an emulation clock and the first transceiver is clocked by a transceiver clock asynchronous with the emulation clock. The transceiver clock has a higher frequency than the emulation clock. The emulation system can include a second IC configured to emulate a second partition of the circuit design. The second IC includes a second transceiver. The first transceiver is configured to generate multiplexed emulation data by multiplexing a plurality of nets that cross from the first partition to the second partition of the circuit design. The first transceiver is configured to send the multiplexed emulation data over a serial communication channel to the second transceiver. The multiplexed emulation data includes a clock signal of the first transceiver embedded therein.
G06F 30/331 - Vérification de la conception, p.ex. simulation fonctionnelle ou vérification du modèle par simulation avec accélération matérielle, p.ex. en utilisant les réseaux de portes programmables [FPGA] ou une émulation
Handling port resets in a multi-port system includes monitoring, using a plurality of firewall circuits, a plurality of controllers corresponding to different communication ports for a reset condition. The plurality of controllers are coupled to a direct memory access (DMA) system through a plurality of bridge circuits. A selected firewall circuit detects a reset condition on a selected controller coupled thereto. The selected controller is coupled to a selected bridge circuit of the plurality of bridge circuits. In response to detecting the reset condition, the selected firewall circuit implements a firewall operating mode. While operating in the firewall operating mode, the selected firewall circuit is configured to control operation of the selected bridge circuit thereby isolating the selected controller from the DMA system. Firewall operating mode of firewall circuits also may be initiated by a management processor in a proactive manner.
Embodiments herein describe connecting an ASIC to another integrated circuit (or die) using inter-die connections. In one embodiment, an ASIC includes a fabric sliver (e.g., a small region of programmable logic circuitry). Inter-die fabric extension connections are used to connect the fabric sliver in the ASIC to fabric (e.g., programmable logic) in the other integrated circuit. These connections effectively extend the fabric in the ASIC to include the fabric in the other integrated circuit. Hardened IP blocks in the ASIC can then use the fabric sliver and the inter-die extension connections to access computer resources in the other integrated circuit.
H03K 19/17736 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de routage
H03K 19/0175 - Dispositions pour le couplage; Dispositions pour l'interface
H03K 19/17796 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels pour l'adaptation des paramètres physiques pour la disposition physique des blocs
73.
PRE-PLACEMENT CLOCKING IDENTIFICATION AND RESOLUTION FOR CIRCUIT DESIGNS
Preplacement clock resolution for implementing a circuit design includes, prior to placement of the circuit design, determining, using computer hardware, pairs of clocks of the circuit design that clock synchronous inter-clock data paths. Using the computer hardware, a clock group is generated that includes clocks having a common ancestor clock node from the pairs of clocks. A clock delay group property is set, using the computer hardware, for the clocks of the clock group prior to placement. A placed version of the circuit design is generated using the computer hardware. The circuit design is placed using the clock delay group property as set for the clocks of the clock group.
Embodiments herein describe techniques for expressing the layers of a neural network in a software model. In one embodiment, the software model includes a class that describes the various functional blocks (e.g., convolution units, max-pooling units, rectified linear units (ReLU), and scaling functions) used to execute the neural network layers. In turn, other classes in the software model can describe the operation of each of the functional blocks. In addition, the software model can include conditional logic for expressing how the data flows between the functional blocks since different layers in the neural network can process the data differently. A compiler can convert the high-level code in the software model (e.g., C++) into a hardware description language (e.g., register transfer level (RTL)) which is used to configure a hardware system to implement a neural network accelerator.
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
Examples herein describe techniques for method of accessing encrypted data. The techniques include receiving, via a memory controller, a first memory request to a first memory region, where the first memory region is encrypted based on a first key, and incrementing, based on the first memory request, a first counter associated with the first key. The techniques further include, in response to determining that the first counter exceeds a first threshold, initiating a key rolling operation to cause the first memory region to be encrypted based on a second key. The techniques further include tracking an address range of the first memory region that has been encrypted based on the second key, and, in response to determining that an address of a second memory request is outside of the address range, causing the second memory request to be completed based on the first key.
A transmission system is disclosed including a driver circuit. The driver circuit includes multiplexer circuits that receive parallel data and operate as a differential pair. At least one of the multiplexer circuits is coupled to a first circuit node and a second circuit node of the driver circuit. The at least one the multiplexer circuits outputs serial data from the multiplexer circuits at the first and second circuit nodes. The first and second nodes are coupled to a differential output network. The first and second nodes are coupled to an inductor circuit. The first and second nodes are coupled to a cross-coupled circuit. The inductor circuit drains driver circuit current at the first circuit node. The second circuit node and the cross-coupled circuit steer driver circuit current at the first circuit node and the second circuit node.
Embodiments herein describe a configurable engine that is embedded into the cache hierarchy of a processor. The configurable engine can enable efficient data sharing between the main memory, cache memories, and the core. The configurable engine can perform operations that are more efficient to be done in the cache hierarchy. In one embodiment the configurable engine is controlled (or configured) by software (e.g., the operating system (OS)), adapting to each application domain. That is, the OS can configure the engine according to a data flow profile of a particular application being executed by the processor.
An integrated circuit (IC) device includes a controller circuitry having an input coupled to a photodiode of an optoelectronic circuitry and an output coupled to a heater of the optoelectronic circuitry, the controller circuitry configured to determine a center frequency of the optoelectronic circuitry based on a shape of an input signal received from the photodiode, and provide a heater signal to the heater based on the shape of the input signal and the center frequency of the optoelectronic circuitry.
A transformer includes a first inductor, facing in a first direction and a second inductor, facing in a second direction, the second direction opposite to the first. In one example the first and the second inductors are arranged such that the first inductor's legs extend to an area of the second inductor's head, and the second inductor's legs extend to an area of the first inductor's head.
H01F 27/00 - AIMANTS; INDUCTANCES; TRANSFORMATEURS; EMPLOI DE MATÉRIAUX SPÉCIFIÉS POUR LEURS PROPRIÉTÉS MAGNÉTIQUES - Détails de transformateurs ou d'inductances, en général
Embodiments herein describe techniques for converting multiple symbols into respective wire states in parallel. In one embodiment, the techniques can be used to convert symbols into wire states in parallel even when those wire states are dependent on previously determined wire states. That is, the dependency on previous wire states can be removed so that wire states can be determined in parallel.
Embodiments herein describe a configurable engine that is embedded into the cache hierarchy of a processor. The configurable engine can enable efficient data sharing between the main memory, cache memories, and the core. The configurable engine can perform operations that are more efficient to be done in the cache hierarchy. In one embodiment, the configurable engine is controlled (or configured) by software (e.g., the operating system (OS)), adapting to each application domain. That is, the OS can configure the engine according to a data flow profile of a particular application being executed by the processor.
G06F 12/0811 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec hiérarchies de mémoires cache multi-niveaux
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06F 12/084 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec mémoire cache partagée
G06F 12/1045 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p.ex. un répertoire de pages actives [TLB] associée à une mémoire cache de données
82.
METHOD AND SYSTEM FOR MITIGATING HOT CARRIER INJECTION EFFECT IN A SEMICONDUCTOR CIRCUIT
The Hot Carrier Injection effect is a phenomenon present in semiconductor devices, where charges are trapped in the gate oxide region and degrade the device. Hot carrier Injection (HCI) is one of the major problems in lower voltage technologies due to lower voltage tolerance limits of MOS devices. Due to this HCI effect, designing high voltage, wide range (i.e., supply voltage ranges: 3.3 v, 2.5 v, and 1.8 v) I/O buffers has become challenging. The HCI effect is common in input/output (I/O) buffers that use bias generation circuits for wide voltage ranges. Disclosed here are methods and systems employed to provide reliable bias generation in an I/O buffer or other semiconductor circuit. This limits the device drain to source voltage (Vds) in the bias circuits and I/O buffer so as to mitigate the hot carrier Injection (HCI) effect.
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
An integrated circuit (IC) device includes processor circuitry configured to output a first memory command having a first memory address, and in-line error correction control (ILECC) circuitry configured to receive the first memory command and output the first memory command to a memory device. The ILECC circuitry includes an error correction code (ECC) cache configured to store a first local ECC associated with the first memory command in a first cache line.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 12/0871 - Affectation ou gestion d’espace de mémoire cache
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
84.
System and method for secure deconstruction sensor in a heterogeneous integration circuitry
Some examples described herein provide for securely booting a heterogeneous integration circuitry apparatus. In an example, an apparatus (e.g., heterogeneous integration circuitry) includes a first portion and a second portion of one or more entropy sources on a first component and a second component, respectively. The apparatus also includes a key generation circuit communicatively coupled with the first portion and the second portion to generate a key encrypted key based on a first set of bits output by the first portion and a second set of bits output by the second portion. The apparatus also includes a key security circuit to generate, based on the key encrypted key and an encrypted public key stored at the apparatus, a plaintext public key to be used by a boot loader during a secure booting operation for the apparatus.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES
H04L 9/14 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité utilisant plusieurs clés ou algorithmes
H04L 9/30 - Clé publique, c. à d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
Some examples described herein relate to protecting an integrated circuit (IC) structure from imaging or access. In an example, an IC structure includes a semiconductor substrate, an electromagnetic radiation blocking layer, and a support substrate. The semiconductor substrate has a circuit disposed on a front side of the semiconductor substrate. The electromagnetic radiation blocking layer is disposed on a backside of the semiconductor substrate opposite from the front side of the semiconductor substrate. The support substrate is bonded to the semiconductor substrate. The electromagnetic radiation blocking layer is disposed between the semiconductor substrate and the support substrate.
An integrated circuit (IC) device includes functional circuits and multiple communication paths, which may include a first communication path through the functional circuits and a second communication path to permit the functional circuits to share information through a buffer and/or to bypass a subset of the functional circuits and a corresponding portion of the first communication path. The IC device may include a variety of protocol-specific interface circuits (ASIC and/or configurable circuitry) for respective IP blocks, and a controller that selectively directs traffic through the various communication paths. The controller may include a set of domain-specific OpCodes that link various subsets/combinations of the protocol-specific interface circuits as respective communication paths. The IC device may include multiple blocks of circuitry, each including a respective set of domain-specific circuitry (e.g., host-domain, network domain, RF domain, and/or data processing domain), and respective sets of OpCodes.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/24 - Circuits de protection ou de sécurité pour cellules de mémoire, p.ex. dispositions pour empêcher la lecture ou l'écriture par inadvertance; Cellules d'état; Cellules de test
Embodiments herein describe a memory system with a data width (W) that is split into N separate memories each of narrower width W/N. To protect a write enable (WE) signal, the WE signal is toggled and then stored in each of the N memories. For example, toggle circuits can have states that toggle each time the WE signal goes high, indicated that a received data word should be stored in the N memories. A fault on the WE input to any of the N memories results in its stored toggle bit being different from the toggle bits stored in the other N memories. This condition can then be detected upon any subsequent read by checking whether the toggled bits are equal. The memory system can also protect the address and control signals by generating parity bits that are stored in the N memories.
An interconnection circuitry of an accelerator device includes a multiplexer, a first plurality of buffers, a second plurality of buffers, and a demultiplexer. The multiplexer is coupled to first offload circuitry and received data therefrom. The first plurality of buffers has inputs coupled to outputs of the multiplexer. A second plurality of buffers has inputs coupled to outputs of the first plurality of buffers. The demultiplexer includes inputs coupled to outputs of the second plurality of buffers and outputs coupled to inputs of programmable logic.
A device includes a data processing engine (DPE) array having a plurality of data processing engines (DPEs) and a subsystem coupled to the DPE array. Each DPE of the plurality of DPEs is configurable to share data with one or more other DPEs of the plurality of DPEs using one or more of a plurality of data sharing techniques. The data sharing techniques include a core of a selected DPE accessing a memory module of an adjacent DPE via a memory interface of the selected DPE connected to a memory module of the adjacent DPE and the selected DPE accessing the memory module of a non-adjacent DPE using a DMA circuit and a stream switch of the selected DPE. The subsystem may be in a different die than the DPE array.
Globally placing a circuit design includes adjusting indicated capacity levels for placement bins associated with a target integrated circuit, based on first levels of demand for resources by instances in the circuit design in regions of the target IC. Region constraints restrict placement of the instances in the regions, and the regions include two or more two or more overlapping regions. Tracked levels of demand for resources in the placement bins are adjusted, after adjusting the indicated capacity levels, based on the indicated capacity levels, a target utilization level of the resources in the placement bins, and a current placement. The current placement of the instances is updated based on a density gradient of an electrostatics-based model of the tracked levels of demand, and repeating adjusting the tracked levels of demand and updating the current placement are repeated in response to the density gradient failing to satisfy a threshold.
G06F 30/392 - Conception de plans ou d’agencements, p.ex. partitionnement ou positionnement
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
91.
RETIMING SEQUENTIAL ELEMENTS HAVING INITITAL STATES
Retiming a circuit design can include determining whether or not an initial value specified for a candidate register can be removed based on an input logic cone to the candidate register and an output logic cone from the candidate register. The candidate register is a register in a critical path in the circuit design. The candidate register can be retimed into a retimed register in response to determining that the initial value specified for the candidate register can be removed. A new initial value for the retimed register can be derived based on initial values of registers in a logic cone of the retimed register, and the new initial value can be assigned to the retimed register.
An authentication device for a communication device includes key stream generator circuitry and hash function circuitry. The key stream generator circuitry receives a first input data stream and generates a first data stream output signal based on the first input data stream and an encryption key. The first input data stream is associated with a first data rate. The hash function circuitry receives the first data stream output signal from the key stream generator circuitry. The hash function circuitry includes first decimation circuitry and recursive circuitry. The first decimation circuitry receives the first data stream output signal, and combines adjacent data words of the first data stream output signal to generate a first decimated output signal having a second data rate. The second data rate is less than the first data rate. The recursive circuitry generates an authentication tag based on the first decimated output signal.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p.ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
94.
Memory controller with reduced latency transaction scheduling
A memory controller includes transaction queue circuitry, a first skip event, a second skip event, a third skip event, and scheduler circuitry. The transaction queue circuitry is configured to store a first transaction, a second transaction, and a third transaction. The first transaction received is by the transaction queue circuitry before the second transaction and the third transaction. The second transaction is received by the transaction queue circuitry before the third transaction. The first skip event counter is associated with the first transaction. The second skip event counter is associated with the second transaction. The third skip event counter is associated with the third transaction. The scheduler circuitry is configured to select the third transaction before selecting the first transaction, increase a value of the first skip event counter based on selecting the third transaction before the first transaction, and communicate the third transaction to a memory device.
An adaptable framework for circuit design simulation verification generates a simulation database for a circuit design and processed design data for the circuit design. The processed design data includes source files for the circuit design referenced by the simulation database. The simulation database and the processed design data are exported from a host integrated development environment (IDE). A template writer configured to generate a simulation script for the circuit design using the simulation database is provided. The simulation script is generated by executing the template writer. The simulation script is generated according to one or more user-specified parameters of the template writer using the simulation database and the processed design data as exported.
Examples herein describe techniques for performing parallel processing using a plurality of processing elements (PEs) and a controller for data that has data dependencies. For example, a calculation may require an entire row or column to be summed, or to determine its mean. The PEs can be assigned different chunks of a data set (e.g., a tensor set, a column, or a row) for processing. The PEs can use one or more tokens to inform the controller when they are done with partial processing of their data chunks. The controller can then gather the partial results and determine an intermediate value for the data set. The controller can then distribute this intermediate value to the PEs which then re-process their respective data chunks using the intermediate value to generate final results.
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
97.
PROGRAMMABLE HYBRID MEMORY AND CAPACITIVE DEVICE IN A DRAM PROCESS
A DRAM fabrication process for producing a semiconductor die adapted for having the ability to be both a hybrid memory and power supply capacitance. DRAM arrays on a semiconductor die may be individually selected to function as either a memory or as supplemental capacitance on a power distribution network serving circuits on one or more semiconductor dice in a three-dimensional active-on-active (AoA) stacked semiconductor die package configuration. Defective DRAM array trench capacitors can be repurposed to serve as supplemental capacitance on a power distribution network. DRAM array trench capacitors can be dynamically reassigned as supplemental capacitance when power supply monitors sense that additional power supply capacitance is needed.
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
A network interface device comprises at least one processor configured to validate at least a part of a context associated with a queue pair, the context being fetched from a memory on a host device.
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
99.
Modeling and compiling tensor processing applications for a computing platform using multi-layer adaptive data flow graphs
Modeling and compiling tensor processing applications using multi-layer adaptive data flow (ML-ADF) graphs, including folding the ML-ADF graph for temporal sharing of platform resources, computing schedules for runtime orchestration of kernel execution, memory reuse, tensor and sub-volume movement, and dataflow synchronization, and generating binary code for processors of the target computing platform and re-targetable controller code. The ML-ADF graph may represent: tensor processing of a layer of a neural network as data flow through the data nodes and distribution to compute tiles across memory hierarchy; data flow amongst layers of the neural network using connections amongst data nodes of the respective layers; and multi-dimension data partitioning and distribution using tiling parameters associated with ports of the data nodes.
A DRAM fabrication process for producing a semiconductor die adapted for having the ability to be both a hybrid memory and power supply capacitance. DRAM arrays on a semiconductor die may be individually selected to function as either a memory or as supplemental capacitance on a power distribution network serving circuits on one or more semiconductor dice in a three-dimensional active-on-active (AoA) stacked semiconductor die package configuration. Defective DRAM array trench capacitors can be repurposed to serve as supplemental capacitance on a power distribution network. DRAM array trench capacitors can be dynamically reassigned as supplemental capacitance when power supply monitors sense that additional power supply capacitance is needed.
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p.ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
