A memory module is operable in a computer system having a memory controller and a system bus and comprises memory devices organized in a plurality of groups, and circuits coupled to the memory devices. The circuits including circuitry configurable to receive from the memory controller a system clock and input control and address (C/A) signals, and to generate a module clock signal and module C/A signals in response to the system clock and input C/A signals. The circuits further include circuitry configurable to generate a plurality of local clock signals corresponding, respectively, to the plurality of groups of memory devices, and to output the plurality of local clock signals to respective groups of the memory devices. A respective local clock signal has a respective phase relationship with the module clock signal and is output to a corresponding group of the memory devices.
A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the nonvolatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.
A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
4.
MEMORY MODULE WITH TIMING-CONTROLLED DATA BUFFERING
A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to adjust the timing of at least one of the respective set of data signals by an amount based on at least one module control signal in a previous operation.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G11C 5/04 - Supports for storage elementsMounting or fixing of storage elements on such supports
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/20 - Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
G11C 8/12 - Group selection circuits, e.g. for memory block selection, chip selection, array selection
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
A system can include a host computer system and a host system bus coupled to the host computer system. One or more storage devices can be coupled to the host system bus and configured to store data. Additionally, a computational storage device (CSD) can be coupled to the host system bus and configured to receive a data write request comprising data from the host computer system. The CSD can further include a memory and an application processor. The application processor of the CSD can be configured to write the data of the data write request to the one or more storage devices in response to receiving the data write request.
A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 29/04 - Detection or location of defective memory elements
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G11C 29/44 - Indication or identification of errors, e.g. for repair
A memory module comprises dynamic random access memory (DRAM) devices arranged in ranks, and a module controller configurable to receive address and control signals for a memory operation, and to output first module control signals to the DRAM devices, causing a selected rank to output or receive data. The module controller is further configurable to output second module control signals to a plurality of data buffers coupled to the DRAM devices via module data lines. A respective data buffer includes data paths and logic configurable to, in response to the second module control signals, enable at least a subset of the data paths to receive and regenerate signals carrying a section of the data communicated from/to corresponding module data lines. The logic is further configurable to disable the data paths when the memory module is not communicating data with the memory controller.
A memory subsystem is operable with a memory controller of a host computer system via an interface. The memory subsystem comprises dynamic random access memory elements and a memory subsystem controller. The memory subsystem controller has an open drain output, and is configured to provide a first signaling interface via the open drain output during normal operations and a second signaling interface via the open drain output during an initialization operation. The second signaling interface is distinct from the first signaling interface and the initialization operation is distinct from any of the normal operations. The first signaling interface is used by the memory subsystem controller to indicate a parity error in response to a parity error having occurred during the normal operations. The second signaling interface is used by the memory subsystem controller to output a signal related to initialization operation sequences during the initialization operation.
A memory module comprises memory devices, a data module and a control module. The memory module is operable in a first mode in which at least some of the memory devices are accessed by a system memory controller in a computer system for memory read and/or write operations at a memory access speed, the control module is configured to register address and control signals associated with the memory read and/or write operations, and the data module is configured to propagate data signals between the at least some of the memory devices and the memory controller. The memory module is further operable in a second mode in which the memory devices are not accessed by the system memory controller for memory read or write operations, and the data module is configured to communicate data signals with at least some of the memory devices at the memory access speed.
A node in a network including a plurality of nodes comprises persistent memory; non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the UMA node, and a network interface for interfacing with other nodes. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on a local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes. Thus, a server in the UMA network can access the physical address spaces at other UMA nodes without going through the servers in the other UMA nodes.
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
G06F 12/109 - Address translation for multiple virtual address spaces, e.g. segmentation
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the nonvolatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.
A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G11C 29/44 - Indication or identification of errors, e.g. for repair
G11C 29/04 - Detection or location of defective memory elements
13.
MEMORY MODULE HAVING VOLATILE AND NON-VOLATILE MEMORY SUBSYSTEMS AND METHOD OF OPERATION
A memory module comprises dynamic random access memory (DRAM), Flash memory, and a module controller. The module controller is configured to receive data to be transferred from the DRAM to the Flash memory, compute first cyclic redundancy check (CRC) codes for the data, and write the data into the Flash memory. The module controller is further configured to read the data from the Flash memory, compute second CRC codes for the data read from the Flash memory, and transfer the data to the DRAM. The module controller is further configured to compare the second CRC codes with the first CRC codes to determine one or more erroneous data bits in the data read from the Flash memory, read a data segment of the data from the DRAM that include the one or more erroneous data bits, correct the one or more erroneous data bits in the data segment, and write the data segment back into the DRAM.
G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
G06F 12/0871 - Allocation or management of cache space
G06F 3/06 - Digital input from, or digital output to, record carriers
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/10 - Program control for peripheral devices
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
14.
Hybrid memory module having a volatile memory subsystem and a module controller configurable to provide data to accompany externally sourced data strobes to the volatile memory subsystem
A memory module according to some embodiments is operable in a computer system including a memory controller coupled to a memory channel. The memory module comprises a volatile memory subsystem, non-volatile (NV) memory subsystem and a module controller coupled to the volatile memory subsystem and the NV memory subsystem. The volatile memory subsystem includes dynamic random access memory (DRAM) devices and is configurable to communicate with the memory controller via the memory channel during memory read or write operations. The module controller is configured to output data strobe signals to accompany data from the volatile memory subsystem during a memory read operation and to output to accompany data strobes output by data buffers in response to data strobe signals from the memory controller during a system-initiated operation to transfer data from the NV memory subsystem to the volatile memory subsystem.
A memory module is operable in a computer system having a memory controller and a system bus and comprises memory devices organized in one or more ranks and in a plurality of groups, and circuits configurable to receive from the memory controller a system clock and input control and address (C/A) signals, and output registered C/A signals and buffer control signals. The memory module further comprises a plurality of buffer circuits. In response to the buffer control signals, each buffer circuit is configured to communicate first data/strobe signals with at least one memory device and to communicate second data/strobe signals with the memory controller.
The buffer circuit includes at least one delay circuit configured to delay at least one signal of the first data/strobe signals based on a first delay and a second delay. A respective local clock signal has a respective phase relationship with the module clock signal and is output to a corresponding group of the memory devices that includes at least one corresponding memory device in each of the one or more ranks.
A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
17.
Memory module having open-drain output for error reporting and for initialization
According to certain aspects, a memory subsystem is coupled to a memory controller of a host computer system via an interface. The memory subsystem comprises dynamic random access memory elements and a memory subsystem controller. During a normal memory read or write operation, the memory subsystem controller is configured to receive address and command signals associated with the memory read or write operations and to control the dynamic random access memory elements in accordance with the address and command signals. The memory subsystem controller is further configured to output via the open drain output a parity error signal in response to a parity error having occurred during the memory read or write operation. During an initialization operation, the memory subsystem controller is configured to output via the open train output a signal related to one or more parts of initialization operation sequences.
A memory module comprises a volatile memory subsystem including DRAM, a non-volatile memory subsystem including Flash memory, and a module control device. The Flash memory includes main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space. The module control device is configured to receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM and to, for each respective segment of data: select a respective set of pages in the DRAM; transfer respective data stored in the respective set of pages from the DRAM to a corresponding segment in the scratch Flash; and transfer the respective segment of data to the respective set of pages in the DRAM. Thus, data can be moved segment by segment between the DRAM and the Flash memory.
G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
G06F 12/0871 - Allocation or management of cache space
G06F 3/06 - Digital input from, or digital output to, record carriers
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/10 - Program control for peripheral devices
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
20.
Memory package having stacked array dies and reduced driver load
A DRAM packages comprises stacked array dies including at least a first array die and a stacked over at least the first array die, data terminals, via which the DRAM package receives or outputs data signals, first data interconnects between respective ones of the data terminals and the first array die, and second data interconnects distinct from the first data interconnects and between respective ones of the data terminals and the second array die. The DRAM package further comprises drivers configured to drive first data signals to the first array die via the first data interconnects and second data signals to the second array die via the second data interconnects. A first data signal is driven by one or more drivers having a first driver size, and a second data signal is driven by one or more drivers having a second driver size different from the first driver size.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
21.
Uniform memory access in a system having a plurality of nodes
The present application presents a Uniform Memory Access (UMA) network including a cluster of UMA nodes. A system in a UMA node comprises persistent memory; non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the respective UMA node, and a network interface for interfacing with the UMA network. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on a local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes. Thus, a server in the UMA network can access the physical address spaces at other UMA nodes without going through the servers in the other UMA nodes.
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
A storage device. In some embodiments the storage device includes a storage controller; a nonvolatile memory device connected to the storage controller through a first physical interface, and a processing circuit. The processing circuit may be connected, through a second physical interface, to the storage controller or to the nonvolatile memory device, the second physical interface being the same as the first physical interface.
A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
24.
COMPUTER MEMORY EXPANSION DEVICE AND METHOD OF OPERATION
A memory expansion device operable with a host computer system comprises a non-volatile memory subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. After indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.
In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
G06F 3/06 - Digital input from, or digital output to, record carriers
A memory module comprises dynamic random access memory (DRAM) devices arranged in ranks, and a module controller configurable to receive address and control signals for a memory operation, and to output first module control signals to the DRAM devices, causing a selected rank to output or receive N-bit-wide data. The module controller is further configurable to output second module control signals to a plurality of data buffers coupled to the DRAM devices via module data lines. Each respective data buffer includes a n-bit-wide (n
A memory module is operable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals and a system clock from the memory controller and to output a module clock, module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in one or more ranks, while the data buffer control signals, together with the module clock, are provided to a plurality of buffer circuits corresponding to respective groups of memory devices and are used to control data paths in the buffer circuits. The plurality of buffer circuits include clock regeneration circuits to regenerate clock signals with programmable delays from the module clock. The regenerated clock signals are provided to respective groups of memory devices so as to locally sync the buffer circuits with respective groups of memory devices.
A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.
A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G11C 5/04 - Supports for storage elementsMounting or fixing of storage elements on such supports
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
A memory module comprises a volatile memory subsystem, a non-volatile memory subsystem, and a module controller coupled to the volatile memory subsystem and to the non-volatile memory subsystem. The module controller is configurable to control data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller includes a data selection circuit configurable to pre-search data transferred from the non-volatile memory with respect to one or more search criteria before providing the pre-select data relevant to the one or more search criteria to the volatile memory subsystem.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0868 - Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.
G06F 13/36 - Handling requests for interconnection or transfer for access to common bus or bus system
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
G06F 3/06 - Digital input from, or digital output to, record carriers
Hybrid memory module having a volatile memory subsystem and a module controller sourcing read strobes to accompany read data from the volatile memory subsystem
A memory module according to some embodiments is operable in a computer system, and comprises a volatile memory subsystem and a module controller coupled to the volatile memory subsystem. The volatile memory subsystem is configurable to be coupled to a memory channel including a data bus, and includes dynamic random access memory (DRAM) devices. The memory module allows independent control of strobe paths and data paths between the DRAM devices and the data bus, and is configurable to perform a memory write operation during which write data is provided to the volatile memory subsystem together with write strobes transmitted via first strobe paths between the DRAM devices and the data bus, and a memory read operation during which read data from the volatile memory subsystem is output onto the data bus together with read strobes transmitted via second strobe paths between the module controller and the data bus.
A method of facilitating communication to an embedded computer in a computational storage device via a host includes receiving a message for transmission to an embedded process running at the embedded computer, determining that a destination address of the message corresponds to the embedded computer within the computational storage device, in response to the determination, forwarding the message to a host relay process associated with the embedded computer, and encapsulating the message to generate a proprietary command for transmission to the computational storage device.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
The present application presents a Uniform Memory Access (UMA) network including a cluster of UMA nodes each having at least one UMA memory unit and a server local to the at least one UMA memory unit. A respective UMA memory unit in a respective UMA node comprises persistent memory; non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the respective UMA node, and a network interface for interfacing with the UMA network. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on the local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes. Thus, a server in the UMA network can access the physical address spaces at other UMA nodes without going through the servers in the other UMA nodes.
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
35.
Memory module having an open-drain output for parity error and for training sequences
According to certain embodiments, a memory module is operable with a memory controller of a host system. The memory module includes a module controller configurable to receive address and control signals from the memory controller, and dynamic random access memory elements configurable to communicate data signals with the memory controller in accordance with the address and control signals. The module controller has an open-drain output and is configurable to drive the open-drain output with a first signal to indicate a parity error having occurred when the memory module is being accessed for a normal memory read or write operation. The module controller is further configurable to drive the open drain output with a second signal related to one or more training sequences when the memory module performs operations associated with the one or more training sequences and not associated with any normal memory read or write operations.
A storage device. In some embodiments, the storage device includes a storage interface, configured to be connected to a host computer, a processing circuit, and persistent storage media. The processing circuit may be configured to: read first data from the persistent storage media in response to a read command received through the storage interface; transmit second data through the storage interface, the second data being based on the first data; receive a write command, with third data, through the storage interface; write fourth data, based on the third data, to the persistent storage media; and perform a cryptographic operation on the first data or on the third data.
G06F 3/06 - Digital input from, or digital output to, record carriers
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
37.
System and method for outward communication in a computational storage device
A method of facilitating communication from an embedded computer in a computational storage device to a host or an external device includes receiving a message from an embedded user process for transmission to a user process running at either the host or the external device, determining that a destination address of the message corresponds to the host or the external device, in response to the determination, forwarding the message to an embedded relay process associated with the host or the external device, instructing a storage controller of the computational storage device about the message to be delivered, notifying a host relay process at the host of a presence of the message, receiving a send message request from the host in response to the notification, and in response to receiving the send message request, transmitting the message to the host.
A method of facilitating communication to an embedded computer in a computational storage device via a host includes receiving a message for transmission to an embedded process running at the embedded computer, determining that a destination address of the message corresponds to the embedded computer within the computational storage device, in response to the determination, forwarding the message to a host relay process associated with the embedded computer, and encapsulating the message to generate a proprietary command for transmission to the computational storage device.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
A method of computational storage device intercommunication includes receiving a notification from a first storage controller of a first computational storage device indicating a presence of a message, in response to receiving the notification, transmitting a send message request to the first storage controller of the first computational storage device, and receiving the message from the first storage controller, storing the message to a host memory and notifying a host pseudo network device driver of availability of the message, determining whether a destination address of the message corresponds to a host user process that is local to the host or to a second user process that is local to a second embedded computer of a second computational storage device, and providing the message to the host user process or to the second embedded computer associated with the destination address.
A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.
G06F 12/0871 - Allocation or management of cache space
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
A system and method for long term data retention in a flash memory. In some embodiments, the method includes transitioning the flash memory to a long term data retention state by re-storing first encoded data, the first encoded data being initially stored in the flash memory at a first code rate. The re-storing may include determining a second code rate, lower than the first code rate; reading the first encoded data from the flash memory; decoding the first encoded data at the first code rate to obtain first decoded data; encoding the first decoded data at the second code rate to form second encoded data; and storing the second encoded data in the flash memory.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G11C 29/04 - Detection or location of defective memory elements
H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
A memory module includes a plurality of DRAM packages mounted on a printed circuit board. Each DRAM package includes a control die, stacked array dies, and first and second die interconnects coupling the stacked array dies to the control die. The control die includes data signal conduits coupled to the first die interconnects and control signal conduits coupled to the second die interconnects. The control die is configured to receive control signals, and to control the data signal conduits in accordance with the control signals. Each of the DRAM packages is configurable to communicate a respective set of bits of a data signal between a selected die among the stacked array dies and the data conduits in response to the control signals.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
43.
Memory module with local synchronization and method of operation
A memory module-includes memory device groups, and a control circuit configurable to receive a system clock and input address and control (C/A) signals from a memory controller, and output a module clock, module C/A signals and data buffer control signals. The memory module further includes data buffers corresponding to respective memory device groups and configurable to receive the module clock and the data buffer control signals from the control circuit. A respective data buffer includes a n-bit wide data path and logic configured to control the data path in response to the data buffer control signals. The n-bit wide data path includes at least one programmable delay element controlled by the logic. The respective data buffer is further configurable to generate a respective local clock having a respective programmable delay from the module clock and to provide the respective local clock to a respective memory device group.
A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 3/06 - Digital input from, or digital output to, record carriers
G11C 5/04 - Supports for storage elementsMounting or fixing of storage elements on such supports
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
G11C 8/12 - Group selection circuits, e.g. for memory block selection, chip selection, array selection
G11C 7/20 - Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
G11C 29/04 - Detection or location of defective memory elements
45.
Hybrid memory system with configurable error thresholds and failure analysis capability
A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G11C 29/44 - Indication or identification of errors, e.g. for repair
G11C 29/04 - Detection or location of defective memory elements
A memory module is operable in a computer system to communicate data with a system memory controller via a system memory bus. The memory module comprises a plurality of memory devices mounted on a circuit board, a data module mounted on the circuit board and coupled between the plurality of memory devices and the system memory bus, and a control circuit mounted on the circuit board and coupled to the data module, the plurality of memory devices, and the system memory bus. The data module includes a plurality of data handlers in a plurality of integrated circuits. The memory module is operable in any of a plurality of modes, including a first mode and a second mode. The plurality of memory devices in the first mode is accessed by the system memory controller for normal memory read or write operations. The plurality of memory devices in the second mode communicate data signals with the data module while the memory module is not being accessed by the system memory controller for normal memory read or write operations.
A memory module comprises a volatile memory subsystem, a non-volatile memory subsystem, and a module control device. The module control device is configured to read data from the non-volatile memory subsystem in response to a set of signals received from the memory channel indicating a non-volatile memory access request to transfer the data from the non-volatile memory subsystem to the volatile memory subsystem, and to provide at least a portion of the data to the volatile memory subsystem in response to receiving a dummy write memory command including a memory address related to the non-volatile memory access request via the memory channel. The volatile memory subsystem is further configured to receive the dummy write memory command and to receive the at least a portion of the first data in response to the dummy write memory command.
G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
G06F 12/0871 - Allocation or management of cache space
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/10 - Program control for peripheral devices
48.
Method and apparatus for uniform memory access in a storage cluster
The present application presents a Uniform Memory Access (UMA) network including a cluster of UMA nodes each having at least one UMA memory unit and a server local to the at least one UMA memory unit. A respective UMA memory unit in a respective UMA node comprises persistent memory; non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the respective UMA node, and a network interface for interfacing with the UMA network. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on the local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes. Thus, a server in the UMA network can access the physical address spaces at other UMA nodes without going through the servers in the other UMA nodes.
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
49.
System and method for executing native client code in a storage device
A system and method for executing user-provided code securely on a solid state drive (SSD) to perform data processing on the SSD. In one embodiment, a user uses a security-oriented cross-compiler to compile user-provided source code for a data processing task on a host computer containing, or otherwise connected to, an SSD. The resulting binary is combined with lists of input and output file identifiers and sent to the SSD. A central processing unit (CPU) on the SSD extracts the binary and the lists of file identifiers. The CPU obtains from the host file system the addresses of storage areas in the SSD containing the data in the input files, reads the input data, executes the binary using a container, and writes the results of the data processing task back to the SSD, in areas corresponding to the output file identifiers.
G06F 13/10 - Program control for peripheral devices
G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
50.
Non-volatile memory storage for multi-channel memory system
A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.
A solid state drive with modular memory. The solid state drive may include a modular array of memory cards installed on a controller board, each memory card being connected to the controller board utilizing a respective connector. Redundant data, e.g., parity data, may be stored in the solid state drive, making it possible for a solid state drive controller on the controller board to restore the contents of a removed memory card (e.g., a memory card that has failed) on a replacement memory card installed in its place. The connector utilized to connect each memory card to the controller board may be an industry standard, commercial off the shelf connector, e.g., an M.2 connector; the functions of the conductors in the connector may be redefined, from the industry standard definitions, for the purposes of embodiments of the present invention.
A memory subsystem is operable with a system memory controller. The memory subsystem comprises memory devices mounted on a circuit board, a data module mounted on the circuit board; and a control module mounted on the circuit board to provide address and control signals to the memory devices. The memory subsystem is operable in any of a plurality of modes including a normal mode and a test mode. During the normal mode, the control module provides the address and control signals based on address and control signals from the system memory controller, and the data module enables data paths between the memory devices and the system memory controller. During the test mode, the control module generates the address and control signals, and the data module isolates the memory devices from the system memory controller.
According to certain aspects, a memory module is coupled to a memory controller of a host computer system via an interface. The memory module is operable in at least a second mode and a first mode. The memory module in the second mode is configured to perform training related to one or more training sequences initiated by the memory controller while the memory module is not accessed by the memory controller for memory read or write operations. The memory module in the first mode is configured to perform one or more memory read or write operations not associated with the one or more training sequences by communicating data signals with the memory module. The memory module has an open-drain output pin via which the memory module output a signal indicating a parity error having occurred while the memory module is performing a normal memory read or write operation, and via which the memory module output a signal related to the one or more training sequences.
A system and methods for in-storage on-demand data decompression. Compressed data are stored in a storage device connected to a host computer. When decompressed data are needed, the host computer sends a decompression command to the storage device indicating which data are to be decompressed, and instructing it how to decompress the data. The storage device decompresses the data and stores the decompressed data, making it available to the host.
A system and method for providing consistent performance in a storage device, such as a solid state drive. A threshold value for command execution time for a command in a category of command (e.g., a read command or a write command) and a command size, is stored in the storage device. When a host command in the category (e.g., a read command) and corresponding size is received, the storage device executes the command, and if it completes execution of the command in a time that is less than the threshold value, the solid state drive waits until an amount of time equal to the threshold value has elapsed before sending the command completion.
A computer system comprises a processor, a memory module and input/output devices. The memory module includes a circuit board, a volatile memory unit mounted on the circuit board, a non-volatile memory unit mounted on the circuit board and a control circuit mounted on the circuit board. The volatile memory unit comprises DRAM devices, and the non-volatile memory unit comprises flash memory. The processor is configured to execute an operating system (OS) and an application program and to present a memory address space to the application program. The memory address space including a memory mapped input/output (MMIO) space mapped to the I/O devices, a pseudo MMIO (PMMIO) space mapped to the non-volatile memory unit, and a DRAM space mapped to the volatile memory unit, the PMMIO space including a system main memory local storage (MMLS) area and a memory channel storage area, wherein the DRAM space is partitioned into memory pages, and the MCS space is partitioned into storage blocks.
A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data/strobe signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit includes a data path corresponding to each data signal line in the corresponding set of data/strobe signal lines, and a command processing circuit configured to decode module control signals from the module control circuit and to control the data path in accordance with the module control signals. The data path corresponding to the each data signal line includes at least one tristate buffer controlled by the command processing circuit and a delay circuit configured to delay a signal through the data path by an amount determined by the command processing circuit in response to at least one of the module control signals.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 8/12 - Group selection circuits, e.g. for memory block selection, chip selection, array selection
G11C 7/20 - Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
G11C 29/04 - Detection or location of defective memory elements
58.
System and method for executing data processing tasks using resilient distributed datasets (RDDs) in a storage device
A system and method of providing enhanced data processing and analysis in an infrastructure for distributed computing and large-scale data processing. This infrastructure uses the Apache Spark framework to divide an application into a large number of small fragments of work, each of which may be performed on one of a large number of compute nodes. The work may involve Spark transformations, operations, and actions, which may be used to categorize and analyze large amounts of data in distributed systems. This infrastructure includes a cluster with a driver node and a plurality of worker nodes. The worker nodes may be, or may include, intelligent solid state drives capable of executing data processing functions under the Apache Spark framework. The use of intelligent solid state drives reduces the need to exchange data with a central processing unit (CPU) in a server.
A system and method for combining the execution of a query with other operations, such as a data retention scan, in a storage device, when the execution of the query is not time-sensitive. The storage device may be connected to a host, and may operate during intervals of time in a power save mode. When a query is received by the host that is not time-sensitive, the query may be stored in the host or in the storage device until such time as the device would otherwise return to a normal operating mode, and then the query may be executed. Such delayed execution may enable the sharing of read operations for the query with read operations used, for example, for the execution of other queries or for a data retention scan.
A system and method for adaptive multiple read of NAND flash memory. A solid state drive may employ adaptive multiple-read to perform enhanced performance error correction using soft decisions without a performance penalty that otherwise might result from performing unnecessary reads. The soft decision error correcting algorithm may employ lookup tables containing log likelihood ratios. The method may include performing one or more read operations to obtain one or more raw data words for a code word, attempting to decode the code words using the one or more raw data words, and performing additional read operations when the decoding attempt fails. This process may be repeated until a decoding attempt succeeds.
H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
G11C 29/04 - Detection or location of defective memory elements
A memory module is operable to communicate data with a memory controller via a memory bus in response to memory commands received from the memory controller. The memory module comprises a plurality of memory integrated circuits arranged in ranks and including at least one first memory integrated circuit in a first rank and at least one second memory integrated circuit in a second rank, and further comprises a buffer coupled between the at least one first memory integrated circuit and the memory bus and between the at least one second memory integrated circuit and the memory bus. The memory module further comprises logic providing first control signals to the buffer to enable communication of a first data burst between the memory controller and the at least one first memory integrated circuit through the buffer in response to a first memory command, and providing second control signals to the buffer to enable communication of a second data burst between the at least one second memory integrated circuit and the memory bus through the buffer in response to a second memory command.
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 15/00 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
62.
Memory module and methods for handshaking with a memory controller
According to certain aspects, a memory module is coupled to a memory controller of a host computer system via an interface. The interface includes data, address and control signal pins and an output pin in addition to the data, address and control signal pins. The memory module receives a first command from the memory controller via the address and control signal pins, and enters a first mode in response to the first command. The memory module in the first mode responds to at least one initialization sequence, and sends a first output signal via the output pin to indicate a status of the at least one initialization sequence to the memory controller. The memory module enters a second mode in which the memory module performs memory operations including memory read/write operations according to an industry standard. During the read/write operations, the memory module communicates data with the memory controller via the data signal pins in response to second memory commands received via the address and control signal pins. The memory module may output a second output signal related to the read/write operations via the output pin.
A method of writing multi-stream host data to a storage device comprising a CPU, a multi-stream fast release buffer (FRB), and a non-volatile memory (NVM), includes: receiving a command to write the multi-stream host data to the NVM, the multi-stream host data being associated with a logical block number (LBN) and a new stream ID, recording a status of the active stream ID and retrieving a status of the new stream ID to determine a physical address in the NVM for storing one or more codewords (CWs) corresponding to the multi-stream host data, allocating space in a buffer of the FRB for storage of the multi-stream host data, organizing the multi-stream host data into the one or more CWs, and storing the one or more CWs into the allocated space in the buffer, transferring the one or more CWs from the buffer to the physical address in the NVM.
A system and methods for in-storage on-demand data decompression. Compressed data are stored in a storage device connected to a host computer. When decompressed data are needed, the host computer sends a decompression command to the storage device indicating which data are to be decompressed, and instructing it how to decompress the data. The storage device decompresses the data and stores the decompressed data, making it available to the host.
A memory module is configured to communicate with a memory controller. The memory module comprises DDR DRAM devices arranged in multiple ranks each of the same width as the memory module, and a module controller configured to receive and register input control signals for a read or write operation from the memory controller and to output registered address and control signals. The registered address and control signals selects one of the multiple ranks to perform the read or write operation. The module controller further outputs a set of module control signals in response to the input address and control signals. The memory module further comprises a plurality of byte-wise buffers controlled by the set of module control signals to actively drive respective byte-wise sections of each data signal associated with the read or write operation between the memory controller and the selected rank.
The present application presents a Uniform Memory Access (UMA) network including a cluster of UMA nodes each having at least one UMA memory unit and a server local to the at least one UMA memory unit. A respective UMA memory unit in a respective UMA node comprises persistent memory; non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the respective UMA node, and a network interface for interfacing with the UMA network. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on the local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes.
A memory module is operable in a computer system to communicate with a system memory controller via a command/address bus and a data bus. The memory module comprises a register device coupled to the command/address bus, and a plurality of DRAM packages coupled to the data bus and to the register device via a set of module control lines. Each respective DRAM package comprises stacked array dies and a control die. The control die includes data signal conduits and control signal conduits. In response to the memory module receiving a set of command/address signals from the system memory controller, the register device outputs control signals, and the control die configures the data signal conduits in accordance with the control signals to enable respective bits of one or more data signals to be communicated between a selected die among the stacked dies and the system memory controller.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
68.
Memory module with timing-controlled data paths in distributed data buffers
A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device mounted on the module board to receive command signals from the memory controller and to output module command signals and module control signals, and memory devices mounted on the module board to perform a first memory operation in response to the module command signals. The memory module further comprises a plurality of buffer circuits distributed across a surface of the module board. Each respective buffer circuit is associated with a respective set of the memory devices and includes logic that is configured to obtain timing information based on signals received by the each respective buffer circuit during a second memory operation prior to the first memory operation and to control timing of the data and strobe signals through the each respective buffer circuit in accordance with the timing information.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 3/06 - Digital input from, or digital output to, record carriers
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
69.
Flash channel calibration with multiple lookup tables
A system and method for generating lookup tables for use in an adaptive multiple-read system for reading flash memory. Successive different attempts are made to decode previously stored data using error correction codes, the attempts differing, for example, with respect to the combination of raw data words used for each attempt, each raw data word having been obtained by reading a code word of data using a different word line voltage. When a decoding attempt succeeds, log likelihood ratios are calculated from counts of flipped bits, i.e., bits in the raw data read from the memory having a different value than the corresponding bits in the decoded data.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
H03M 13/05 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
H03M 13/45 - Soft decoding, i.e. using symbol reliability information
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
70.
System and method for supporting atomic writes in a flash translation layer
A method for memory-efficient backup of a logical-to-physical (LtoP) table in a storage device having a processor, a volatile memory, and a non-volatile memory, includes retrieving and subsequently processing, by the processor, a plurality of flushed zone segments stored in a first block stripe of the non-volatile memory in an order opposite to an order of storage of the plurality of flushed zone segments in the first block stripe in the non-volatile memory, wherein the processing of the plurality of flushed zone segments includes identifying a retrieved flushed zone segment of the plurality of flushed zone segments differing from all previously retrieved plurality of flushed zone segments, and writing the identified retrieved flushed zone segment of the plurality of flushed zone segments to a second block stripe of the non-volatile memory.
A system and method for combining the execution of a query with other operations, such as a data retention scan, in a storage device, when the execution of the query is not time-sensitive. The storage device may be connected to a host, and may operate during intervals of time in a power save mode. When a query is received by the host that is not time-sensitive, the query may be stored in the host or in the storage device until such time as the device would otherwise return to a normal operating mode, and then the query may be executed. Such delayed execution may enable the sharing of read operations for the query with read operations used, for example, for the execution of other queries or for a data retention scan.
A memory module is operable with a memory controller of a host computer system. The memory module includes a module controller having an open drain output. The module controller generates a parity error signal and drives the parity error signal to the memory controller of the host system via the open drain output while the memory module operates in a first mode, the parity error signal indicating a parity error having occurred in the memory module while the memory module operates in the first mode. The module controller is configured to cause the memory module to enter a second mode in response to a command from the memory controller of the host system. The module controller generates a notification signal indicating at least one status of one or more training sequences while the memory module is in the second mode and outputs the notification signal to the memory controller of the host system via the open drain output while the memory module is in the second mode.
A system and method for comparing a character from a search space simultaneously to each of a set of search characters. The set of search characters may correspond to a regular expression. In one embodiment, the search space character is encoded to a short binary presentation (e.g., to an 8-bit representation), which is then converted to a long binary representation one bit of which is set, at a first position in the long binary representation corresponding to the value of the short representation. Each character of the set of search characters is similarly encoded and converted to a respective long binary representation. If the bit in one of the long binary representations corresponding to the set of search characters is set, it indicates that the search character matches the corresponding character of the set of search characters.
A system and method for providing consistent performance in a storage device, such as a solid state drive. A threshold value for command execution time for a command in a category of command (e.g., a read command or a write command) and a command size, is stored in the storage device. When a host command in the category (e.g., a read command) and corresponding size is received, the storage device executes the command, and if it completes execution of the command in a time that is less than the threshold value, the solid state drive waits until an amount of time equal to the threshold value has elapsed before sending the command completion.
A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in a computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the memory channel. The module controller reads first data from the non-volatile memory subsystem and reads second data from the volatile memory subsystem in response to a NV access request received via the memory channel, and causes at least a portion of the first data to be written into the volatile memory subsystem in response to a dummy write memory command received via the C/A bus. The module control device includes status registers accessible by the computer system via the memory channel.
A method of restoring user data in a modular solid-state drive including memory channels coupled to respective ones of non-volatile memory cards, the method including: upon physical replacement of a defunct memory card of the non-volatile memory cards with a new non-volatile memory card, and power on of the modular solid-state drive, retrieving a firmware segment and a system segment of the modular solid-state drive from unaffected memory channels of the memory channels not coupled to the new non-volatile memory card; rebuilding a firmware of the modular solid-state drive based on the retrieved firmware segment; rebuilding a data mapping table associated with the non-volatile memory cards based on the retrieved system segment; and restoring full integrity of the user data originally stored on the non-volatile memory cards based on the rebuilt data mapping table and data from the unaffected memory channels.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
A solid state drive with modular memory. The solid state drive may include a modular array of memory cards installed on a controller board, each memory card being connected to the controller board utilizing a respective connector. Redundant data, e.g., parity data, may be stored in the solid state drive, making it possible for a solid state drive controller on the controller board to restore the contents of a removed memory card (e.g., a memory card that has failed) on a replacement memory card installed in its place. The connector utilized to connect each memory card to the controller board may be an industry standard, commercial off the shelf connector, e.g., an M.2 connector; the functions of the conductors in the connector may be redefined, from the industry standard definitions, for the purposes of embodiments of the present invention.
A multi-rank memory module is operable in a memory system with a memory controller. The memory module according to one embodiment comprises at least one module board, memory devices organized in three ranks, and at least one register device providing control/address signals to the memory devices. Arrangement of the ranks on the at least one module board are made to balance memory device loadings on the C/A signals, and data/strobe signal hubs are designed to provide better alignment of different data bits in a data signal and to reduce reflection from discrete components disposed near an edge of the module board, resulting in improved signal quality and integrity.
An apparatus is provided that includes a plurality of array dies and at least two die interconnects. The first die interconnect is in electrical communication with a data port of a first array die and a data port of a second array die and not in electrical communication with data ports of a third array die. The second die interconnect is in electrical communication with a data port of the third array die and not in electrical communication with data ports of the first array die and the second array die. The apparatus includes a control die that includes a first data conduit configured to transmit a data signal to the first die interconnect and not to the second die interconnect, and at least a second data conduit configured to transmit the data signal to the second die interconnect and not to the first die interconnect.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
G06F 3/06 - Digital input from, or digital output to, record carriers
A memory module or a storage device comprises a volatile memory subsystem, a non-volatile memory subsystem, and a controller coupled to the volatile memory subsystem and to the non-volatile memory subsystem. The memory module or storage device further comprises a data selection circuit that pre-search data from the non-volatile memory with respect to one or more search criteria received from a computer system to pre-select data relevant to the one or more search criteria for loading into the volatile memory subsystem.
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0868 - Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
G06F 13/10 - Program control for peripheral devices
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from the memory controller and to output module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in groups, each group including at least one memory device, while the data buffer control signals are provided to a plurality of buffer circuits to control data paths in the buffer circuits, a respective buffer circuit corresponding to a respective group of memory devices. The plurality of buffer circuits are distributed across a surface of the memory module such that each data buffer control signal arrives at the plurality of buffer circuits at different points in time. The plurality of buffer circuits include clock regeneration circuits to regenerate a clock signal received from the module control device and to provide regenerated clock signals to respective groups of memory devices.
A system and method of providing enhanced data processing and analysis in a storage device, such as a solid state drive (SSD). The SSD includes flash memory and an SSD controller capable of executing searches on the data in the flash memory without returning all of the data to be searched to a host CPU outside of the SSD. Other processing capabilities incorporated into the SSD may include encryption and decryption, compression and decompression, and in-line indexing of data. The SSD efficiently processes queries through the use of an internal data buffer and a data engine configured to search partial data.
G06F 12/14 - Protection against unauthorised use of memory
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 17/30 - Information retrieval; Database structures therefor
G06F 3/06 - Digital input from, or digital output to, record carriers
85.
Systems and methods for performing single and multi threaded searches and complex pattern matching in a solid state drive
System and methods for enhanced data processing and analysis in a storage device, such as a solid state drive (SSD) include an SSD having a data storage and a controller. The data storage stores a plurality of data sets. The controller has a pattern buffer and a data engine. The controller receives a query, processes the query to extract a pattern, loads the pattern into the pattern buffer, and accesses the data storage. The data engine searches a data subset from the data storage for instances of the pattern using a rolling window method. The controller generates a result from the search.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 17/30 - Information retrieval; Database structures therefor
G06F 12/14 - Protection against unauthorised use of memory
G06F 3/06 - Digital input from, or digital output to, record carriers
A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from the memory controller and to output module command signals and module control signals. The module command signals are provided to memory devices organized in groups, each group including at least one memory device, while the module control signals are provided to a plurality of buffer circuits to control data paths in the buffer circuits. The plurality of buffer circuits are associated with respective groups of memory devices and are distributed across a surface of the memory module such that each module control signal arrives at the plurality of buffer circuits at different points in time. The plurality of buffer circuits are configured to align read data signals received from the memory devices such that the read data signals are transmitted to the memory controller from the memory module substantially aligned with each other and in accordance with a read latency parameter of the memory system.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 3/06 - Digital input from, or digital output to, record carriers
A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller reads first data from the non-volatile memory subsystem in response to a Flash access request received via the memory channel, and causes at least a portion of the first data to be written into the volatile memory subsystem in response to a dummy write memory command received via the C/A bus. The module control device includes status registers accessible by the computer system via the memory bus.
G06F 12/0871 - Allocation or management of cache space
G06F 13/10 - Program control for peripheral devices
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
88.
System and method for executing native client code in a storage device
A system and method for executing user-provided code securely on a solid state drive (SSD) to perform data processing on the SSD. In one embodiment, a user uses a security-oriented cross-compiler to compile user-provided source code for a data processing task on a host computer containing, or otherwise connected to, an SSD. The resulting binary is combined with lists of input and output file identifiers and sent to the SSD. A central processing unit (CPU) on the SSD extracts the binary and the lists of file identifiers. The CPU obtains from the host file system the addresses of storage areas in the SSD containing the data in the input files, reads the input data, executes the binary using a container, and writes the results of the data processing task back to the SSD, in areas corresponding to the output file identifiers.
G06F 13/10 - Program control for peripheral devices
G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
89.
System and method for management of garbage collection operation in a solid state drive
A method of garbage collection in a storage device including a central processing unit (CPU), a self-organized fast release buffer (FRB), and a non-volatile memory, the method including receiving a command to perform garbage collection in a first block stripe of the non-volatile memory from the CPU, the command including a second block stripe to write to and valid logical block numbers (LBNs) corresponding to a first codewords (CWs) stored in the first block stripe, allocating space in a buffer memory of the FRB for storage of the first CWs, storing the first CWs into the allocated space in the buffer memory, transferring a second CWs to a plurality of physical addresses in the second block stripe of the non-volatile memory, and sending the valid LBNs and the plurality of physical addresses to the CPU to update a logical-to-physical table, wherein the second CWs is based on the first CWs.
A method of writing host data to a storage device including a central processing unit (CPU), a self-organized fast release buffer (FRB), and a non-volatile memory, the storage device being in communication with a host, the method including receiving a command from the CPU to write the host data to a location in the non-volatile memory, the host data being associated with a first plurality of codewords (CWs), allocating space in a buffer memory of the FRB for storage of the first CWs, storing the first CWs into the allocated space in the buffer memory, extracting data from the stored first CWs, organizing the extracted data and the host data into a second plurality of CWs, transferring a second CWs to a physical addresses in the non-volatile memory, and sending the plurality of physical addresses to the CPU to update a logical-to-physical table.
A method of reading host data from a storage device including a central processing unit (CPU), a self-organized fast release buffer (FRB), and a non-volatile memory, the storage device being in communication with a host, the method including receiving, by the FRB, a command to read host data stored in the non-volatile memory from the CPU, the host data being stored in the non-volatile memory as one or more codewords (CWs), allocating space, by the FRB, in a buffer memory of the FRB for storage of the one or more CWs, storing, by the FRB, the one or more CWs into the allocated space in the buffer memory, extracting, by the FRB, the host data from the stored one or more CWs, and transferring, by the FRB, the host data to the host.
Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Data stored in a volatile memory subsystem is backed up redundantly into first and second channels of a non-volatile memory subsystem. The data is retrieved from the volatile memory subsystem upon detection of a trigger condition indicative of real or imminent power loss or reduction and multiple copies are stored in dedicated non-volatile memory channels. The stored copies may be error checked and corrected, and re-written if necessary. The redundantly backed up data can be subsequently retrieved from the non-volatile memory subsystem, error-corrected, and an error-free copy communicated to the volatile memory subsystem.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/16 - Error detection or correction of the data by redundancy in hardware
A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
95.
Programmable data write management system and method for operating the same in a solid state drive
A method of writing host data to a storage device including a central processing unit (CPU), a self-organized fast release buffer (FRB), and a non-volatile memory, the storage device being in communication with a host, the method including receiving a command to write the host data to the non-volatile memory from the CPU, the host data being associated with a logical block number (LBN), allocating space in a buffer memory of the FRB for storage of the host data, organizing the host data into one or more codewords (CWs), storing the one or more CWs into the allocated space in the buffer memory, transferring the one or more CWs from the buffer memory to a physical address in the non-volatile memory, and sending the LBN and the physical address to the CPU to update a logical-to-physical table.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
A system and method for operating a solid state drive (SSD) within power limitations while maintaining SSD performance. In one embodiment a power management integrated circuit (PMIC) is used to measure power consumption, and a built-in self-test (BIST) procedure is used to exercise the storage device, and to calibrate the power consumed by various SSD operations. The results are stored in a power consumption cost table. In one embodiment, a procedure to dynamically adjust the power consumption cost table is employed. A power credit allocation scheme is used, along with the power consumption cost table, to track and limit the power consumed by the SSD in operation.
A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.
G06F 5/10 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
G06F 12/0871 - Allocation or management of cache space
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
98.
Power efficient method for cold storage data retention management
A system and method for storing infrequently accessed data with reduced power consumption. In one embodiment, a solid state drive (SSD) includes flash memory and environmental data logging circuitry. The SSD is shut off or operated in a sleep mode to reduce power consumption, and turned on or transitioned to an active mode as needed when data on the SSD is to be accessed, or when a calculation, based on a number of erase cycles previously performed in the flash memory and on a temperature history of the SSD indicates that a data refresh may be needed to prevent data corruption in the SSD, due to data retention limitation of the nonvolatile memory in the SSD.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
99.
System and method for supporting atomic writes in a flash translation layer
A method of maintaining and updating a logical-to-physical (LtoP) table in a storage device including a processor, a volatile memory, and a non-volatile memory, the storage device being in communication with a host utilizing atomic writes, the method including receiving, by the processor, data for storing at a plurality of physical addresses in the non-volatile memory, the data being associated with a plurality of logical addresses of the host, storing, by the processor, the plurality of physical addresses in an atomic segment in the volatile memory, storing, by the processor, one or more of zones of the LtoP table in the non-volatile memory, the one or more zones of the LtoP table corresponding in size to the atomic segment, and updating the one or more zones of the LtoP table with the plurality of physical addresses in the atomic segment.
A method of maintaining and updating a logical-to-physical (LtoP) table in a storage device including a processor, a volatile memory, and a non-volatile memory, the storage device being in communication with a host, the method including receiving, by the processor, data for storing at a physical address in the non-volatile memory, the data being associated with a logical address of the host, storing, by the processor, the physical address in a first LtoP zone of a plurality of LtoP zones of the LtoP table, the LtoP table being stored in the volatile memory, adding, by the processor, the first LtoP zone to a list of modified zones, and storing, by the processor, a second LtoP zone of the plurality of LtoP zones in the non-volatile memory when a size of the list of modified zones exceeds a threshold.
