Abstract

An electronic device includes an Integrated Circuit (IC) and a package including a die-attach pad for connecting the IC. The IC includes (i) a measurement circuit configured to measure an electrical characteristic of the die-attach pad, and (ii) a security control circuit configured to initiate a responsive action responsively to detecting a deviation of the measured electrical characteristic of the die-attach pad from an initial measurement of the electrical characteristic.

IPC Classes  ?

• G06F 21/87 - Secure or tamper-resistant housings by means of encapsulation, e.g. for integrated circuits
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G06F 21/55 - Detecting local intrusion or implementing counter-measures

Abstract

An integrated circuit formed with interconnected electronic elements includes at least: i) functional elements which perform IC operations; ii) at least one countermeasure (CM) for detecting fault injection attacks upon the IC and outputting an alert signal when a FI attack is detected; and iii) at least one attack emulator which emulates FI attacks on the IC by applying stimuli to the plurality of functional elements in accordance with at least one control signal. An integrated circuit formed with interconnected electronic elements includes at least: i) functional elements which perform IC operations; ii) at least one countermeasure (CM) for detecting fault injection attacks upon the IC and outputting an alert signal when a FI attack is detected; and iii) at least one attack emulator which emulates FI attacks on the IC by applying stimuli to the plurality of functional elements in accordance with at least one control signal. The IC may include other elements such as power supply elements, oscillators, interface elements and so forth.

IPC Classes  ?

• G06F 11/26 - Functional testing
• G06F 11/00 - Error detectionError correctionMonitoring
• G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
• G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences

Abstract

An analog-to-digital conversion circuit configured to convert an input voltage into a digital code includes a trigger controller, a comparison circuit, a successive approximation controller, and an initial voltage scanning controller. The trigger controller enables the first enable signal and the second enable signal in sequence. The comparison circuit selects a successive approximation code or a scan code to generate a conversion voltage and compares the conversion voltage with the input voltage to generate a comparison result. The successive approximation controller updates the successive approximation code based on the enabled first enable signal and the comparison result. The initial voltage scanning controller sets the initial value based on the digital code, and updates the scan code based on the enabled second enable signal and the comparison result.

IPC Classes  ?

• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Abstract

A control chip including a communication interface, a serial interface, and a control logic is provided. The communication interface is configured to receive an access package. The serial interface includes a first pin and a second pin. The first and second pins operate in an alternate function mode. The control logic is coupled to the serial interface. In response to the access package having a read operation code, the control logic uses the first pin to output the read operation code and read information to a slave device and sets the first pin to operate in a general-purpose input-output (GPIO) mode. The slave device provides read data according to the read information. The control logic uses the second pin to receive the read data.

IPC Classes  ?

• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation

Abstract

When a developer edits a lighting effect file played by single one or multiple light emitting units of a sounding and lighting device, a lighting effect editing device and method provided by the present disclosure enable the developer to simultaneously determine whether playing single one lighting effect file once, playing single one lighting effect file repeatedly, playing a concatenation of multiple lighting effect files once, playing a concatenation of multiple lighting effect files repeatedly, playing a mixture of multiple lighting effect files once, playing multiple lighting effect files simultaneously once, playing multiple lighting effect files simultaneously repeatedly, playing multiple concatenation lighting effect files simultaneously once or playing multiple concatenation lighting effect files simultaneously repeatedly generates a flicker frequency not meeting a predetermined specification. In addition, when there exists the flicker frequency not meeting the predetermined specification, the developer may be notified of a location of a corresponding sampling time point.

IPC Classes  ?

• H05B 47/165 - Controlling the light source following a pre-assigned programmed sequenceLogic control [LC]

Abstract

A secure adder includes a mask generator, a secure carry-lookahead adder, and a verification circuit. The mask generator generates a first mask value, a second mask value, a third mask value, first masked data, and second masked data. The secure carry-lookahead adder performs an operation on the first masked data and the second masked data to generate a sum output according to the first mask value, the second mask value, and the third mask value. The verification circuit includes a secure carry-save adder and a comparator. The secure carry-save adder generates sum data and carry data according to the first mask value, the second mask value, the third mask value, the first masked data, the second masked data, and the sum output. The comparator generates a verification output according to the relationship between the sum data and the carry data.

IPC Classes  ?

• G06F 7/508 - AddingSubtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
• G06F 7/502 - Half addersFull adders consisting of two cascaded half adders

Abstract

A storage circuit including a memory and a control circuit is provided. The memory includes a memory block and a backup block. The memory block stores a plurality of data sets. The control circuit receives an erase request. In response to the erase request selecting at least one of the data sets, the control circuit erases the backup block, copies all data sets that are not selected by the erase request to the backup block from the memory block, and activates the backup block to replace the memory block. After activating the backup block, the control circuit accesses the backup block in response to an access request pointing to the memory block.

IPC Classes  ?

• G06F 12/02 - Addressing or allocationRelocation

Abstract

An integrated circuit (IC) includes a thermal memory device, a fault injection (FI) detector and a security control circuit. The thermal memory device includes (i) a thermal storage zone and (ii) a heating element configured to heat the thermal storage zone in response to write operations. The FI detector is configured to detect attempts to inject faults into the IC. The security control circuit is configured to perform a write operation to the thermal memory device in response to an attempt detected by the FI detector, to identify a sequence of the attempts that meets a density criterion, by reading the thermal memory device, and initiate a responsive action upon identifying the sequence.

IPC Classes  ?

• G06F 21/55 - Detecting local intrusion or implementing counter-measures

Abstract

A class-D amplifier includes an output driver stage and a current sensing circuit connected. The current sensing circuit includes: an operational amplifier having a positive input terminal and a negative input terminal; a positive input replica transistor, where a source of the positive input replica transistor is connected to the positive input terminal, a drain and a gate of the positive input replica transistor is connected to the drain and the gate of a first n-type output transistor, respectively; and a negative input replica transistor, where a source of the negative input replica transistor is connected to the negative input terminal, a drain and a gate of the negative input replica transistor is connected to the drain and the gate of the second n-type output transistor, respectively.

IPC Classes  ?

• G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03F 3/45 - Differential amplifiers

Abstract

An electronic circuit applied to communication between a controller and a memory array includes a timer and a delay-locked loop. The timer counts a counting time based on a selection signal generated by the controller to generate a first enable signal. The delay-locked loop delays an output clock signal by a delay time based on a clock signal generated by the controller and the first enable signal to generate the delay clock signal. When the controller performs a read operation on the memory array, the memory array outputs the output clock signal and a data signal. The controller samples the data signal using the delay clock signal.

IPC Classes  ?

• H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
• H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Abstract

A charge controller for a buck circuit is illustrated. The charge controller compares a reference voltage and multiple feedback voltages of multiple output voltages to generate multiple comparison signals, wherein a pulse-frequency modulation buck module outputs the output voltages at multiple voltage output terminals through a single inductor and multiple switches, and each of the switches is disposed between the single inductor and the corresponding voltage output terminal. Then, the charge controller determines a charging order of the voltage output terminals based on the comparison signals, and is arranged to generate multiple switching signals and a start signal based on a zero-current detection signal of the single inductor and the charging order, wherein the switching signals are arranged to control the switches, and the start signal is arranged to enable the pulse-frequency modulation buck module to charge one of the voltage output terminals.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices

Abstract

A memory system including a memory; an encoding management circuit; and a memory access instruction decoding unit is provided. The memory access instruction decoding unit is configured to receive an instruction from a bus, identify a bad block in the memory, determine whether the instruction indicates access to the bad block. When the instruction indicates writing data to the bad block, the memory access instruction decoding unit outputs an address of the bad block and the data to the encoding management circuit to trigger the encoding management circuit to update the encoding management circuit. When the instruction indicates reading the bad block, the memory access instruction decoding unit outputs the address to and trigger the encoding management circuit to output simulation data of the bad block, wherein the encoding management circuit obtains the simulation data based on the address.

IPC Classes  ?

• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

Abstract

A clock filter system and a clock filter switching method. The clock filter system includes a plurality of clock filters for respectively outputting a plurality of individual clock signals; a bypass circuit for outputting a bypass enable signal; a plurality of clock enable circuits for respectively outputting a plurality of enable signals; a feedback logic circuit for performing an inverse OR (NOR) operation on the bypass enable signal and the plurality of enable signals to generate a feedback signal; a plurality of clock control circuits for respectively generating and outputting a plurality of control signals according to the feedback signal and the plurality of enable signals to respectively control the plurality of individual clock signals to be turned on or turned off. When switching clock filters, a source individual clock signal and a target individual clock signal are controlled to be turned on at different times.

IPC Classes  ?

• H03K 5/125 - Discriminating pulses
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

A control chip including a first processing circuit, a second processing circuit, and a storage circuit. The first processing circuit provides a learning procedure and learning data. The second processing circuit is configured to execute the learning procedure. The storage circuit stores the learning procedure and the learning data. In response to an access request pointing to the learning procedure, the storage circuit determines whether the access request is a correct access request. In response to the access request being a correct access request, the storage circuit provides the learning procedure to the second processing circuit. In response to the access request pointing to the learning data, the storage circuit determines whether the access request is provided from the second processing circuit. In response to the access request being provided from the second processing circuit, the storage circuit provides the learning data to the second processing circuit.

IPC Classes  ?

• G05B 19/042 - Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
• H10B 20/00 - Read-only memory [ROM] devices

Abstract

A control device includes a storage unit, a key generation unit and a processing unit. The storage unit stores a control device certificate and a programming device certificate. The key generation unit generates a first private key. The key generation unit also generates a first public key according to the first private key. The processing unit receives the control device certificate and the programming device certificate according to the first public key and a device identification code. The processing unit stores the control device certificate and the programming device certificate in the storage unit.

IPC Classes  ?

• H04L 9/14 - Arrangements for secret or secure communicationsNetwork security protocols using a plurality of keys or algorithms
• H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system

Abstract

A processing circuit is provided. The processing circuit includes an image-providing device, an adjustment device, a resistive memory, and a control circuit. The image-providing device is configured to provide a target image. The adjustment device adjusts the scale of a template image to generate a sample image according to the setting information. The resistive memory includes a storage region and a computation circuit. The storage region stores the target image. The computation circuit computes the sample image and the target image to generate a plurality of computation results. The control circuit finds a matching position that matches the sample image in the target image according to the computation results.

IPC Classes  ?

• G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries
• G06T 3/40 - Scaling of whole images or parts thereof, e.g. expanding or contracting
• G06T 7/11 - Region-based segmentation
• H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters

Abstract

An encryption and decryption device includes a ShiftRow/InvShiftRow unit, a SubBytes/InvSubBytes unit, a dual ShiftRow/InvShiftRow unit, an encoder, a decoder, and a first verification unit. The ShiftRow/InvShiftRow unit performs a row shift/inverse row shift operation on result data to generate an input state array. The subbytes/invsubbytes unit performs a transformation on the input state array to generate an output state array. The dual ShiftRow/InvShiftRow unit performs the row shift/inverse row shift operation on dual output data to generate a dual input state array. The encoder encodes the dual input state to generate encoded data. The decoder decodes the encoded data to generate decoded data. The first verification unit verifies the mapping relationship of the decoded data and the output state array to generate a first verification signal.

IPC Classes  ?

• H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems

Abstract

A control chip is provided. A storage circuit includes a memory and a control circuit. The memory includes a first region and a second region. The first region stores command streams. The second region stores parameters. The control circuit accesses the memory. A neural-network processing unit (NPU) receives a destination block and performs a destination command stream corresponding to the destination block. In response to the destination command stream pointing to the second region, the control circuit or the NPU determines whether the destination command stream has access authority. In response to the destination command stream not having access authority, the control circuit does not read the second region. In response to the destination command stream having access authority, the control circuit reads the second region and provides the destination parameter stored in the second region to the NPU.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A dual mode power integrated circuit and power converter circuit using the same are disclosed. The power integrated circuit can be used for driving a power converter with high side PMOSFET or NMOSFET, wherein the power integrated circuit includes a high side switch driver circuit which is disposed on the isolated area and a high side power provider circuit is also disposed on the isolated area. When the PMOSFET is adopted on the high side, the source terminal voltage of the PMOSFET is input to the high side power provider circuit for generating the operation voltage of the high side switch driver circuit. When the NMOSFET is adopted on the high side, the bootstrap circuit is adopted.

IPC Classes  ?

• H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit

Abstract

A control device coupled to an oscillator circuit and including a first output circuit, a synchronizer circuit, a hysteresis circuit, a stable circuit, and a second output circuit is provided. The first output circuit activates an oscillator circuit according to an activation signal so that the oscillator circuit generates an input clock. The synchronizer circuit synchronizes the activation signal to generate a synchronization signal. The synchronization signal is synchronized with the input clock. The hysteresis circuit directs the first output circuit to disable the oscillator circuit according to the synchronization signal. The stable circuit enables a transmission signal according to the input clock. When the transmission signal is enabled, the second output circuit uses the input clock as an output clock.

IPC Classes  ?

• H03K 3/014 - Modifications of generator to ensure starting of oscillations
• H03K 3/037 - Bistable circuits
• H03K 3/356 - Bistable circuits
• H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines

Abstract

A microcontroller unit (MCU) with a controller area network (CAN) function. The MCU provides a CAN controller for the CAN function, to generate a transmission signal (CANTX) in digital form. The MCU also has a digital signal remapping circuit inside, which remaps the CANTX signal into a first chip output and a second chip output. The MCU has a first pin that outputs the first chip output to drive a differential positive signal line (CANH) of the CAN function. The MCU has a second pin that outputs the second output to drive a differential negative signal line (CANL) of the CAN function.

IPC Classes  ?

• H04L 12/40 - Bus networks

Abstract

A switching circuit coupled to a first oscillator circuit and a second oscillator is provided. The first oscillator circuit generates a first clock signal according to a first enable signal. The second oscillator generates a second clock signal according to a second enable signal. The switching circuit uses the first or second clock signal as an output clock according to a detection signal. The switching circuit includes a first D-type flip-flop and a second D-type flip-flop. The first D-type flip-flop includes a first reset terminal receiving the first enable signal. The second D-type flip-flop includes a second reset terminal receiving the second enable signal.

IPC Classes  ?

• G06F 1/08 - Clock generators with changeable or programmable clock frequency

Abstract

A class-D amplifier includes a pulse width modulation (PWM) signal generator configured to generate an input signal, a p-type output transistor and an n-type output transistor connected in series with the p-type output transistor at an output terminal, and an output monitor connected to the output terminal and configured to detect a duty cycle of an output signal at the output terminal. The amplifier includes a pre-driver circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is connected to the PWM signal generator to receive the input signal, the second input terminal is connected to the output monitor to receive the duty cycle, the first output terminal is connected to a gate of the p-type output transistor, and the second output terminal is connected to a gate of the n-type output transistor.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers

Abstract

A method for reducing influence of noise on a signal line, a decoding circuit and a power provider are disclosed. The method includes steps of: dividing an analog signal to be decoded into levels; determining the level of the analog signal and acquiring the current level of the analog signal to be decoded to obtain a current level number; updating a highest level variable when the current level number is greater than the highest level variable; updating a lowest level variable when the current level number is smaller than the lowest level variable; and outputting an edge detection pulse and setting the highest level variable and the lowest level variable equal to the current level number when the difference between the highest level variable and the lowest level variable is greater than a noise tolerance value.

IPC Classes  ?

• H03K 5/1252 - Suppression or limitation of noise or interference
• H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

Abstract

An encryption/decryption device includes a SubBytes/InvSubBytes unit, a MixColumns/InvMixColumns unit, a first verification unit, and a controller. The SubBytes/InvSubBytes unit performs a transformation on the input state array to generate an output state array. The MixColumns/InvMixColumns unit performs a mix column operation/inverse mix column operation on the output state array to generate a mix-column/inverse mix-column array. The mix column operation/inverse mix column operation includes a binary-field multiplication calculation. The first verification unit determines whether the output state array and the mix-column/inverse mix-column array meet a mapping relationship to generate a verification signal. The controller determines whether the binary field multiplication calculation performed by the MixColumns/InvMixColumns unit is correct based on the first verification signal.

IPC Classes  ?

• G06F 17/16 - Matrix or vector computation

Abstract

A digital DC-DC voltage conversion apparatus is used to convert an input voltage into an output voltage for a digital core circuit and generate an output current for the digital core circuit. The digital DC-DC voltage conversion apparatus includes a direct charging path current supply unit. The direct charging path current supply unit includes a direct charging switch and a direct charging path controller electrically connected to the direct charging switch. A control end of the direct charging switch receives a direct charging switch control signal, and the direct charging path controller generates direct charging switch control signal to control the direct charging switch to generate a direct charging path current to the digital core circuit. In this way, the digital DC-DC voltage conversion apparatus can faster track an operation current of the digital core circuit.

IPC Classes  ?

• G05F 1/59 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load

Abstract

A secure control circuit protects data stored in a memory is provided. A setting circuit provides a first activation signal and protection information. The protection information points to a confidential area of the memory. A processing circuit provides a second activation signal and access information. An arbiter determination circuit determines whether the access information points to the confidential area according to the protection information in response to the first activation signal being in a first level. In response to the second activation signal not being in a specific level and the access information points to the confidential area, the arbiter determination circuit directs an access circuit to access the confidential area. In response to the second activation signal being in the specific level and the access information points to the confidential area, the arbiter determination circuit directs the access circuit to stop accessing the confidential area.

IPC Classes  ?

• G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A class-D amplifier includes: a p-type output transistor; an n-type output transistor connected in series with the p-type output transistor; and a drive circuit connected to a gate of the p-type output transistor and a gate of the n-type output transistor. The drive circuit receives an input signal, generates a p-type output transistor control signal applied to the gate of the p-type output transistor, and generates an n-type output transistor control signal applied to the gate of the n-type output transistor. When the input signal becomes logic high, the n-type output transistor control signal becomes logic low fast, while the p-type output transistor control signal becomes logic low gradually. When the input signal becomes logic low, the p-type output transistor control signal becomes logic high fast, while the n-type output transistor control signal becomes logic high gradually.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers

Abstract

The present disclosure provides a power control method for a microcontroller unit (MCU) and a power control system using the same. The power control method includes after a triggering event of switching CPU frequency occurs, controlling, through a power controller, a low dropout linear regulator (LDO) to output a preset voltage and triggering a clock controller to switch a first central processing unit (CPU) frequency; after the clock controller switches the first CPU frequency, counting, through a clock counter, a number of times of occurrence of a CPU clock within a period to obtain a second CPU frequency; and determining, through the power controller, a corresponding voltage of the second CPU frequency and controlling the LDO to output the corresponding voltage.

IPC Classes  ?

• G06F 1/324 - Power saving characterised by the action undertaken by lowering clock frequency
• G06F 1/08 - Clock generators with changeable or programmable clock frequency
• G06F 1/3234 - Power saving characterised by the action undertaken
• G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage

Abstract

A level shifter is disclosed. The input circuit receives an input signal operating within a first voltage range that is defined by a first voltage level. A pull-up circuit is coupled between a second voltage line and the input circuit. The second voltage line supplies a second voltage level. The second voltage level is higher than the first voltage level. A first connection node between the pull-up circuit and the input circuit serves as an output terminal of the level shifter. An acceleration circuit coupled to the first connection node accelerates the low-to-high transition at the output terminal. The acceleration controller for the acceleration circuit includes a first series of pulse generation transistors driven by first driving signals which have time differences therebetween, so that the acceleration controller enables the acceleration circuit in a pulse manner. The first driving signals are derived from the input signal.

IPC Classes  ?

• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• H03K 19/017 - Modifications for accelerating switching in field-effect transistor circuits

Abstract

An electronic device includes an immutable memory, a counter, and a processor. The immutable memory stores a first public key and a second public key in advance, and the first public key and the second public key are unmodifiable. The counter has an anti-rollback protection and counts a counting value. When the counting value is a first value, the processor selects a first public key corresponding to the first value. When the counting value is a second value, the processor selects the second public key corresponding to the second value. When the counting value is a third value, the processor selects the first public key and the second public key. The first value and the second value are in a first state, and the third value is in a second state, where the first state and the second state are different.

IPC Classes  ?

• H04L 9/08 - Key distribution

Abstract

A control device includes a first memory, a second memory, a processing circuit and an input-output interface. The first memory stores a secure-bootloader program code. The second memory stores a first specific program code. The processing circuit performs the secure-bootloader program code to execute a first legality verification on the first specific program code. When the first specific program code passes the first legality verification, the processing circuit performs the first specific program code to generate a verification signal. The input-output interface is configured to output the verification signal to an external device and receives a response signal from the external device. The processing circuit executes a second legality verification on the reply signal. When the reply signal does not pass the second legality check, the processing circuit ignores a request from the external device.

IPC Classes  ?

• G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• G06F 11/36 - Prevention of errors by analysis, debugging or testing of software

Abstract

An encryption device is provided herein, which includes a memory array and a memory control device. The memory array is configured to store lock data. The memory control device determines whether the lock data is equal to a predetermined value according to an operation instruction. When the memory control device determines that the lock data is equal to the predetermined value, the memory control device performs a logic operation on the write data and an output key to generate encrypted write data, and writes the encrypted data into the memory array as ciphertext.

IPC Classes  ?

• G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
• G06F 21/60 - Protecting data
• G06F 21/64 - Protecting data integrity, e.g. using checksums, certificates or signatures

Abstract

A microcontroller circuit including a detection circuit, a storage circuit, an error counter circuit, a comparison circuit, and a processing circuit is provided. The detection circuit enables a trigger signal and outputs error information in response to the occurrence of an error event. The storage circuit stores the error information. The error counter circuit adjusts the count value according to the number of times that the trigger signal is enabled by the detection circuit. The comparison circuit enables an interruption signal in response to the count value reaching a threshold value. The processing circuit performs a specific operation according to the interruption signal.

IPC Classes  ?

• G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
• G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result

Abstract

A peripheral device including a universal serial bus (USB) interface, a storage circuit, and a command parser is provided. The USB interface is configured to be coupled to an external host and to receive file data from the external host. The file data includes a self-defining command and update data. The storage circuit is configured to store a file allocation table and a root directory. The command parser analyzes the self-defining command to generate an analysis result and operates according to the analysis result. In response to the self-defining command being an update command, the command parser performs an update operation.

IPC Classes  ?

• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
• G06F 13/38 - Information transfer, e.g. on bus

Abstract

A high-voltage device includes: a diode; a junction field-effect transistor (JFET) adjoining the diode and electrically coupled to the diode; a high-voltage junction termination (HVJT) element electrically connected with the diode and the junction field-effect transistor, wherein the high-voltage junction termination element is a ring shape from top view, and a high-side region and a low-side region are respectively defined inside the ring shape and outside the ring shape; and a first deep well region encircling the high-side region. The first deep well region includes: a first segment disposed in the high-voltage junction termination element; and a second segment disposed in the junction field-effect transistor. The first segment includes a well region and a doped region in the well region. The second segment includes only the well region.

IPC Classes  ?

• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/66 - Types of semiconductor device
• H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
• H01L 29/861 - Diodes

Abstract

An LED driving apparatus, a microcontroller, and a control method for an LED module are provided. The LED driving apparatus includes a power supply module, a switch module, and a control module. The power supply module is configured to supply power to the LED module, in which the power supply module determines whether to trigger an overcurrent protection based on whether an output current exceeds a threshold current. The control module is configured to receive an overcurrent detection signal to control a conduction state of the switch module, so as to affect the current amount of the LED module. When the overcurrent detection signal indicates the output current exceeds the threshold current, the control module outputs a first control signal based on the overcurrent detection signal to control the switch module, to prevent the overcurrent protection from being triggered.

IPC Classes  ?

• H05B 45/30 - Driver circuits
• H05B 45/46 - Details of LED load circuits with an active control inside an LED matrix having LEDs disposed in parallel lines
• H05B 45/50 - Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDsCircuit arrangements for operating light-emitting diodes [LED] responsive to LED lifeProtective circuits

Abstract

An attack-detection (A-DET) circuit in an integrated circuit includes a main detector and a spike detection circuit. The main detector is configured to, while activated, detect an abnormal level of a power supply input of the integrated circuit. The spike detection circuit is configured to detect a transition on the power supply input and to send an activation indication to the main detector responsively the detected transition.

IPC Classes  ?

• G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering

Abstract

A semiconductor structure includes a first well, a second well, a first doping region, a second doping region, a field oxide layer, a third well, and a fourth well. The first well is N-type. The second well is P-type, adjacent to the first well and in contact with the first well at an interface. The first doping region is N-type and deposited in the first well. The second doping region is P-type and deposited in the second well. The field oxide layer is formed in the first well and deposited between the first doping region and the second doping region. The third well is N-type, formed in the first well, and deposited below the field oxide layer. The fourth well is N-type, formed in the first well, and deposited below the field oxide layer.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A micro-controller including a secure world, a non-secure world, and a processing circuit is provided. The secure world includes a key management device, a decryption circuit, and a first memory. The key management device stores a secret key. The decryption circuit utilizes the secret key to decrypt an encrypted model to generate a decrypted model. The first memory stores the decrypted model. The non-secure world includes a second memory and a third memory. The second memory stores the encrypted model. The third memory stores an inference result. The processing circuit provides input data to the decrypted model. The decrypted model generates the inference result according to the input data.

IPC Classes  ?

• H04L 9/08 - Key distribution

Abstract

A micro-controller including a non-secure world, a secure world, and a processing circuit is provided. The non-secure world stores a neural network model including an encrypted operator and an un-encrypted operator. The secure world stores a key and includes a decryption circuit. In a non-secure mode, the processing circuit interprets the un-encrypted operator. In a secure mode, the processing circuit directs the decryption circuit to use the key to decrypt the encrypted operator to generate a decrypted result. In the secure mode, the processing circuit interprets the decrypted result to generate second output data and stores the second output data in the non-secure world.

IPC Classes  ?

• G06F 21/55 - Detecting local intrusion or implementing counter-measures
• H04L 9/08 - Key distribution

Abstract

A control chip including a detection circuit, a management circuit, and a main core circuit is provided. The detection circuit enables a first wake-up signal in response to a specific event occurring. The management circuit determines whether a wake-up condition is satisfied in response to the first wake-up signal being enabled. In response to the wake-up condition being satisfied, the management circuit enables a second wake-up signal. The main core circuit enters a normal mode from a sleep mode according to the second wake-up signal. In response to the specific event not occurring, the management circuit and the main core circuit operate in the sleep mode. In response to the wake-up condition not being satisfied, the main core circuit operates in the sleep mode.

IPC Classes  ?

• G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices

Abstract

A control chip coupled to a sensing circuit and including a first memory, an accessing circuit, a second memory, and a processing circuit is provided. The first memory includes a first storage area and a second storage area. The first storage area stores sensing data provided by the sensing circuit. The second storage area stores processing parameters. The accessing circuit reads continuous data of the first storage area according to a first access command to generate first read data and reads at least one processing parameter of the second storage area according to a second access command to generate second read data. The second memory stores the first and second read data. The processing circuit reads the second memory and processes the first read data according to the second read data to generate first processed data. The processing circuit stores the first processed data in the second memory.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A delay calibration circuit includes a first delay chain, a second delay chain, and a calibration circuit. The first delay chain includes a plurality of first delay units and delays a clock signal with a first delay to generate a first delay signal. The supply current for each of the first delay units is a first current. The second delay chain includes a plurality of second delay units and a third delay unit. The second delay units delay a first signal with a second delay to generate a second delay signal. The third delay unit delays the second delay signal to generate the third delay signal. The supply current for each unit in the second delay chain is a second current. The calibration circuit adjusts a current ratio of the second current to the first current based on the second delay signal and the third delay signal.

IPC Classes  ?

• H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
• H03K 3/037 - Bistable circuits
• H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
• H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter

Abstract

A device for detection of a clipped ringing signal includes a ringing generator, a ringing signal adjusting-and-driving section, and a voltage-detection and clipping-judgment section. The ringing signal adjusting-and-driving section receives a ringing signal from the ringing generator. The ringing signal adjusting-and-driving section also receives a gain adjusting signal. The ringing signal adjusting-and-driving section outputs the ringing signal to a subscriber loop after adjusting the gain thereof according to the gain adjusting signal. The voltage-detection and clipping-judgment section is coupled to the subscriber loop to detect the loop voltage waveform of the subscriber loop, and to determine that the ringing signal is clipped when the loop voltage waveform is discontinuous. When the ringing signal is clipped, the voltage-detection and clipping-judgment section sends the gain adjusting signal to drive the ringing signal adjusting-and-driving section to attenuate the gain of the ringing signal.

IPC Classes  ?

• H04Q 1/36 - Pulse-correcting arrangements, e.g. for reducing effects due to interference
• H04M 1/654 - Telephone line monitoring circuits therefor, e.g. ring detectors
• H04M 19/02 - Current supply arrangements for telephone systems providing ringing current or supervisory tones, e.g. dialling tone or busy tone

Abstract

An oscillation circuit includes: a current mirror circuit outputting a reference current; a charging and discharging circuit charging a first charge storage element by using one of the reference currents or discharging the first charge storage element, to generate a first control voltage; an output stage circuit including a first switch transistor controlled by the first control voltage to output a first oscillation signal; a first resistor; a second resistor; and a diode circuit. The first resistor and the second resistor have same directional temperature drifts, a first resistance of the first resistor is greater than a second resistance of the second resistor, and a first resistance drift of the first resistor with a temperature variation is smaller than a second resistance drift of the second resistor with the temperature variation, such that the effect of the temperature variation on a frequency accuracy is reduced.

IPC Classes  ?

• H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
• H03K 3/037 - Bistable circuits

Abstract

An entropy maintaining method for a true random number generator and a true random number generator thereof are provided. The true random number generator includes a plurality of first ring oscillation output circuits. The entropy maintaining method includes providing at least one second ring oscillation output circuit in the true random number generator, the at least one second ring oscillation output circuit initially disabled; after the true random number generator is operated, recording logic of generated random bit signals every preset time; counting the logic of the random number bit signal to obtain a statistic value; and determining, according to the statistic value, whether the at least one second ring oscillation output circuit is operated in combination with the plurality of first ring oscillation output circuits to generate the random bit signals.

IPC Classes  ?

• G06F 7/58 - Random or pseudo-random number generators
• H03K 3/03 - Astable circuits

Abstract

The present disclosure provides a digital low-dropout regulator (DLDO) and an electronic device using the same. The DLDO includes a voltage comparator circuit, a switch control circuit, a power switch module, and an asynchronous clock generation circuit. The voltage comparator circuit compares a reference voltage with the output voltage to output a comparison result signal. The switch control circuit generates a switch control signal based on the comparison result signal. The power switch module is controlled by the switch control signal to switch between the on state and the off state, thereby adjusting the output voltage. The asynchronous clock generation circuit generates a reference clock signal that is asynchronous with the system clock signal used in the load circuit and has a higher clock frequency. This allows the switch control circuit to update the switch control signal based on the reference clock signal.

IPC Classes  ?

• G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Abstract

A method for emulating electrically-erasable programmable read-only memory and a flash memory system are disclosed. The flash memory system includes a control circuit and a flash memory. Each unit of the flash memory is divided into a data field and an address field. A plurality of units are allocated as a first page. When the control circuit receives an instruction to read a specific storage unit of the sector, it determines, starting from an initial unit of an initial page, whether the address field of the unit has been written; when the address field has been written, finding a next address according to the address field until a target unit with an address field that has not been written is found. The control circuit reads the data field of the target unit.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

An analog-to-digital converter (ADC) circuit including a receiving circuit and a delta-sigma ADC is provided. The receiving circuit receives a first analog input and a second analog input, and uses the first or second analog input as an output signal according to a control signal. The delta-sigma ADC converts the output signal to input data. The delta-sigma ADC over-samples the input data to generate a plurality of sampling results and stores the sampling results. The delta-sigma ADC generates output data according to the sampling results.

IPC Classes  ?

• H03M 3/00 - Conversion of analogue values to or from differential modulation

Abstract

A touch device and an operation method for the touch device are provided. The touch device includes touch keys, controllers, and a processing circuit. The controllers group selected touch keys among the touch keys into at least one touch key group. Each of the at least one touch key group includes at least two selected touch keys. When the selected touch keys of a first touch key group among the at least one touch key group are simultaneously touched, the processing circuit sequentially provides touch driving signals to the first touch key group and receives touch sensing signal groups corresponding to the touch driving signals. When the touch sensing signal groups all indicate that the selected touch keys of the first touch key group are simultaneously touched, the processing circuit determines that the touch on the first touch key group is a valid touch.

IPC Classes  ?

• G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
• G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

Abstract

An asynchronous bridge with command prefetching, including a command prefetcher as well as a command receiver. The command receiver receives a first command from a first-clock computing device. The first command is issued to operate a second-clock computing device. The command prefetcher prefetches a second command from the first-clock computing device before the first-clock computing device receives notice of execution completion of the first command. In this manner, when the command receiver receives the second command (that the first-clock computing device formally issues to operate the second-clock computing device), the second-clock computing device already operates in response to the prefetched second command.

IPC Classes  ?

• G06F 13/40 - Bus structure
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation

Abstract

A signal conversion device for converting a single-ended input voltage into a differential input voltage having a positive input voltage and a negative input voltage is provided. During a sampling phase, a holding phase, and a common-mode voltage generation phase, a capacitor related to the positive input voltage is electrically connected to the single-ended input voltage, and a capacitor related to the negative input voltage is electrically connected to a preset voltage. During a single-ended to differential phase, the capacitor related to the positive input voltage is electrically connected to the preset voltage, and the capacitor related to the negative input voltage is electrically connected to the single-ended input voltage. Hence, the common-mode voltage is not related to a capacitance ratio, and the capacitors does not need to be designed as switching capacitors with multiple switches. No complex control is required, and the parasitic effect of the circuit can be reduced.

IPC Classes  ?

• H03K 5/01 - Shaping pulses

Abstract

A low power mode control module for a crystal oscillator which performs the following steps: detecting whether an oscillation output signal of the crystal oscillator is output stably; when the oscillation output signal of the crystal oscillator is output stably, comparing at least one of an oscillation input signal and the oscillation output signal with an amplitude control signal to determine whether to adjust the amplitude control signal; when the amplitude control signal does not need to be adjusted, generating an upper bound reference voltage and a lower bound reference voltage associated with the amplitude control signal; and according to whether the oscillation output signal exceeds a reference voltage range of the upper reference voltage and the lower reference voltage, generating a low power mode control output signal associated with a crystal oscillator enable signal for enabling the crystal oscillator.

IPC Classes  ?

• H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
• H03B 5/04 - Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature

Abstract

A packaged integrated circuit including an input-output pin, a first chip and a second chip is provided. The first chip includes a first voltage converter circuit, a second voltage converter circuit, and a data transmission circuit. The first voltage converter circuit, the second voltage converter circuit, and the data transmission circuit are connected in parallel between an internal pin and the input-output pin. The second chip enables the first voltage converter circuit, the second voltage converter circuit, or the data transmission circuit based on the operation mode of the internal pin.

IPC Classes  ?

• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

A bus slave device and an interrupt request determination method thereof are provided. The bus slave device sets interrupt request groups and interrupt request numbers to slave devices, respectively. A master device receives an interrupt request through an alarm pin, and each of the slave devices send interrupt request through the alarm pin, and an alarm detection module detects whether the alarm pin is at a low level. A selecting module selects an interrupt mode which is one of a level mode and a pulse mode. An interrupt request module sends or terminates the interrupt request. The master device configures the interrupt request group and the interrupt request number corresponding to the slave devices through the control module to generate a master device receiving signal, and transmits the master device receiving signal to the master device through the data pin and the clock pin.

IPC Classes  ?

• G06F 13/24 - Handling requests for interconnection or transfer for access to input/output bus using interrupt

Abstract

A micro-controller for executing over-the-air updated firmware is provided to access an external memory. The external memory stores a first program code and a second program code. The micro-controller includes a bus, a control circuit, and a management circuit. The control circuit sends an access command to the bus. The management circuit receives an access command through the bus and reads a recorded value. In response to that the recorded value matches a preset value, the management circuit maps the first program code to a specific mapped memory space of a system memory space. In response to that the recorded value does not match the preset value, the management circuit maps the second program code to the specific mapped memory space.

IPC Classes  ?

• G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities

Abstract

An Attack Resilient Computation Circuit (ARCC) in an integrated circuit (IC) includes a first computation stage, a second computation stage, and security circuitry. The first computation stage is configured to process one or more signals so as to produce one or more outputs, the first computation stage having multiple signal propagation paths. The second computation stage is configured to receive and process the outputs of the first computation stage. The security circuitry is configured to generate a synchronization signal indicating that propagation of the signals in the first computation stage has completed, and to inhibit the second processing stage from processing the outputs of the first processing stage for a time interval derived from the synchronization signal.

IPC Classes  ?

• G06F 21/55 - Detecting local intrusion or implementing counter-measures
• G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information

Abstract

A control chip providing power to a sink device and including a connection port, an encoder, a decoder, and a control circuit is provided. The connection port provides an output voltage and an inquiry signal to the sink device, and receives an acknowledgement signal provided by the sink device. The encoder generates the inquiry signal. The decoder decodes the acknowledgement signal to generate a decoded result. In a compensation mode, the control circuit obtains an actual voltage received by the sink device according to the decoded result and adjusts the output voltage according to the actual voltage received by the sink device. In a setting mode, the control circuit obtains a protect-point voltage of the sink device according to the decoded result and adjusts the output voltage according to the protect-point voltage of the sink device to prevent the output voltage from being higher than the protect-point voltage.

IPC Classes  ?

• G06F 1/26 - Power supply means, e.g. regulation thereof
• G06F 1/3234 - Power saving characterised by the action undertaken
• G06F 13/38 - Information transfer, e.g. on bus
• G06F 13/40 - Bus structure

Abstract

A dynamic protection circuit including an adjustment circuit, a detection circuit, a control circuit, and a counter circuit is provided. The adjustment circuit adjusts an output voltage based on a predetermined value. The detection circuit detects whether the output voltage is higher than an upper-limit value or lower than a lower-limit value. The control circuit changes the predetermined value and disables the detection circuit while the predetermined value is being changed. The counter circuit starts to adjust a count value in response to the detection circuit being disabled. In response to the counter circuit adjusting the count value, the control circuit adjusts the upper-limit value and the lower-limit value to be proportional to the output voltage. In response to the count value being equal to a target value, the counter circuit enables the detection circuit.

IPC Classes  ?

• H03K 17/0814 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
• H03K 21/02 - Input circuits
• H03K 21/38 - Starting, stopping, or resetting the counter

Abstract

A method includes providing one or more signals to an electronic device for performing a test procedure that involves programming a One-Time Programmable (OTP) memory in the electronic device. A verification is made as to whether connection of the one or more signals to the electronic device is stable, by performing a sequence of one or more iterations, each iteration including (i) determining, from among a set of scratchpad addresses in the OTP memory, an address that is available for programming, (ii) writing a test value to the address, and then (iii) reading the test value from the address. If the read test value differs from the written test value, re-tuning of the connection of the one or more signals is initiated. Only when the connection is verified as stable by the sequence of iterations, the OTP memory is programmed in accordance with the test procedure.

IPC Classes  ?

• G11C 29/54 - Arrangements for designing test circuits, e.g. design for test [DFT] tools
• G06F 12/02 - Addressing or allocationRelocation

Abstract

A control circuit including a storage circuit, a register, and a write protection logic circuit is provided. The storage circuit stores data, an enable-set value and a mode-set value. The register stores a protection-set value. The write protection logic circuit determines whether to change at least one of the enable-set value, the mode-set value, and the protection-set value according to the mode-set value after receiving a write command. In response to the mode-set value matching a pre-determined value, the write protection logic circuit changes at least one of the enable-set value, the mode-set value, and the protection-set value according to the protection-set value. In response to the mode-set value not matching the pre-determined value, the write protection logic circuit does not change the enable-set value and the mode-set value.

IPC Classes  ?

• G11C 16/22 - Safety or protection circuits preventing unauthorised or accidental access to memory cells
• G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, a channel layer, a barrier layer, a gate electrode, a dielectric layer, a source electrode, a drain electrode, and a diode structure. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate electrode is disposed on the barrier layer. The dielectric layer is disposed on the gate electrode. The source electrode and the drain electrode are disposed on opposite sides of the gate electrode and in contact with the channel layer, respectively. The diode structure is disposed on the dielectric layer and is electrically connected to the source electrode.

IPC Classes  ?

• H01L 29/861 - Diodes
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/40 - Electrodes
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

Abstract

An embodiment of the invention provides a data authentication device. The data authentication device may include a main memory, a backup memory, a platform control hub (PCH) and an embedded controller (EC). The main memory may be configured to store data. The backup memory may be configured to back up the data stored in the main memory. The PCH is coupled to the main memory and generates a write command to write a first data image to the main memory, wherein the first data image comprises updated data and a digital signature. The EC is coupled to the main memory, the backup memory and the PCH and obtains the first data image from the PCH. When the EC detects a write command, the EC may perform an authentication for the updated data based on the first data image or a second data image corresponding to the first data image.

IPC Classes  ?

• G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• G06F 21/64 - Protecting data integrity, e.g. using checksums, certificates or signatures

Abstract

A low-dropout regulator with an automatic adjustment stability compensation circuit is provided. The low-dropout regulator includes an analog positive power supply; a compensation circuit; a PMOS; an error amplifier; a reference voltage; a load capacitance; a soft start circuit; a first resistor; and a second resistor. The drain of the PMOS is connected to one end of the first resistor and a node is formed at the connection to output voltage; the gate of the PMOS is connected to the output of the error amplifier and compensation circuit; the other end of the first resistor is connected in series with the second resistor, and the other end of the second resistor is grounded; the non-inverting input end of the error amplifier is connected to the reference voltage, and the inverting input end is connected to the one of the two resistors.

IPC Classes  ?

• G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices

Abstract

A microcontroller circuit is provided. The microcontroller circuit includes a memory, a check module, and a processor. The memory includes a main memory block and a backup memory block. The main memory block has a boot setting and the backup memory block has a backup boot setting. The check module includes a register. The processor is configured to determine whether the backup memory block of the memory has been backed up according to the register of the check module in response to a boot signal, and to compare the boot setting with the backup boot setting when the backup memory block of the memory has been backed up. When the boot setting is different from the backup boot setting, the processor is configured to perform a boot initialization procedure according to the backup boot setting.

IPC Classes  ?

• G06F 9/4401 - Bootstrapping

Abstract

A rail-to-rail input stage circuit including a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first processing circuit, a second processing circuit, a first voltage adjustment circuit, and a second voltage adjustment circuit is provided. The first P-type transistor and the first N-type transistor are coupled to a first input terminal. The second P-type transistor and the second N-type transistor are coupled to a second input terminal. In response to the voltage of the first terminal being higher than a first threshold value, the first voltage adjustment circuit controls the operation of the first processing circuit. In response to the voltage of the first terminal being lower than a second threshold value, the second voltage adjustment circuit controls the operation of the second processing circuit.

IPC Classes  ?

• H03F 3/45 - Differential amplifiers
• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 1/08 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements

Abstract

An Integrated Circuit (IC), designed for debugging by Focused Ion Beam (FIB) editing, includes functional circuitry, a network of Basic FIB elements (BFEs), and routing circuitry. The functional circuitry includes functional nodes. Each of the BFEs includes a respective metal pad configured to be connected to one of the functional nodes using FIB editing. The routing circuitry is configured to route one or more selected BFEs for analysis.

IPC Classes  ?

• H01J 37/305 - Electron-beam or ion-beam tubes for localised treatment of objects for casting, melting, evaporating, or etching
• H01J 37/30 - Electron-beam or ion-beam tubes for localised treatment of objects
• H01J 37/304 - Controlling tubes by information coming from the objects, e.g. correction signals

Abstract

An analog-to-digital conversion circuit is provided. The analog-to-digital conversion circuit includes an analog-to-digital converter (ADC) and a debounce controller. The ADC is configured to sequentially convert an analog input signal into a plurality of conversion bits in response to a plurality of cycles of a clock signal. The debounce controller is configured to sequentially receive the conversion bits in response to each of the cycles of the clock signal. In each of the cycles, the debounce controller is configured to integrate the received conversion bits into conversion data and to determine whether the conversion data exceeds a normal range. When the conversion data exceeds the normal range, the debounce controller is configured to provide an abort signal to the analog-to-digital converter, so that the analog-to-digital converter stops converting the analog input signal.

IPC Classes  ?

• H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise

Abstract

A light strip unplugging protection method includes: providing a light strip, wherein the light strip includes a plug including a power pin and a control pin; providing a socket corresponding to the plug, wherein the socket includes a power pin holder and at least one light strip control pin holder for electrically connecting with the power pin and the light strip control pin respectively; using a pulse-width modulation signal to drive the light strip on the light strip control pin holder to control the current passing therethrough; and when the pulse-width modulation signal is in a first state, detecting voltage or current of the light strip control pin holder; determining whether the light strip is unplugged according to the voltage or current; and when it is determined that the light strip is unplugged, power voltage on the power pin holder is turned off.

IPC Classes  ?

• H05B 45/50 - Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDsCircuit arrangements for operating light-emitting diodes [LED] responsive to LED lifeProtective circuits
• F21V 23/06 - Arrangement of electric circuit elements in or on lighting devices the elements being coupling devices
• G01R 31/69 - Testing of releasable connections, e.g. of terminals mounted on a printed circuit board of terminals at the end of a cable or a wire harnessTesting of releasable connections, e.g. of terminals mounted on a printed circuit board of plugsTesting of releasable connections, e.g. of terminals mounted on a printed circuit board of sockets, e.g. wall sockets or power sockets in appliances
• H05B 45/10 - Controlling the intensity of the light
• H05B 45/325 - Pulse-width modulation [PWM]

Abstract

A sensing device and a manufacturing method thereof are provided. The sensing device includes a substrate, a first electrode layer, a first sensing layer, a first dielectric layer, a second electrode layer, a second sensing layer, a second dielectric layer, and a capping layer. The first electrode layer is disposed on the substrate. The first sensing layer is disposed on the first electrode layer and has a plurality of holes. The first dielectric layer is disposed on the first sensing layer. The second electrode layer is disposed on the first dielectric layer. The second sensing layer is disposed on the second electrode layer. A material of the second sensing layer is different from a material of the first sensing layer. The second dielectric layer is disposed on the second sensing layer. The capping layer is disposed on the substrate.

IPC Classes  ?

• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/528 - Layout of the interconnection structure

Abstract

A microcontroller, an electronic device, and a method for encrypting transmission data using the same are provided. The microcontroller includes a processing circuit, a storage circuit, and a data scrambling circuit. The processing circuit is arranged to access a raw data to control the operation of the microcontroller. The storage circuit is coupled to the processing circuit and configured to store a characteristic parameter of the microcontroller. The data scrambling circuit is coupled to the storage circuit and the processing circuit, and arranged to generate a transformation matrix according to at least one of the characteristic parameters and a random-number value. When the microcontroller sends data, the data scrambling circuit swaps the bit addresses of a plurality of data units in the raw data, to convert the raw data into a scramble data.

IPC Classes  ?

• G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits

Abstract

A sensing device and a sensing method are provided. The sensing device includes a substrate, a first unit, a second unit, a third unit, and a fourth unit. The first unit and the second unit are disposed on the substrate and connected to each other in series. The third unit and the fourth unit are disposed on the substrate and connected to each other in series. Of the first unit, the second unit, the third unit, and the fourth unit, two are reference resistors, and the other two are a first sensing unit and a second sensing unit configured to capture volatile organic compounds. At least one of the first sensing unit and the second sensing unit has different capture degrees for polar gas and nonpolar gas of the volatile organic compounds and/or has different capture degrees for protic gas and aprotic gas of the volatile organic compounds.

IPC Classes  ?

• G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups

Abstract

The present disclosure relates to a firmware switching method for system security and an electrical device using the same. The firmware switching method use a safety protection circuit between the central process unit (CPU) and the security circuit block. When the firmware is updated and malfunction is occurred and the backup firmware is restored, the safety protection circuit is activated to blank the necessary signal for accessing the security circuit block from the CPU. Therefore, even if user made a command to access the security circuit block, the security circuit block is unable to be accessed since the necessary signal is blanked. Thus, even if the firmware is operated at an older version, it also maintains the system security and gives developers more time to modify firmware.

IPC Classes  ?

• G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• G06F 21/55 - Detecting local intrusion or implementing counter-measures
• G06F 21/56 - Computer malware detection or handling, e.g. anti-virus arrangements

Abstract

A microcontroller including a processing circuit, a function-controlling circuit and a first functional module is provided. The processing circuit is arranged to provide a first enabling signal in an operation mode, and stop providing the first enabling signal in a low power-consumption mode. The function-controlling circuit is electrically connected to the processing circuit, and arranged to generate a first signal in response to the first enabling signal. The first functional module electrically is connected to the function-controlling circuit, and arranged to enable a first function based on the first signal. When the first functional module receives a first triggering event, the first functional module sends a first enabling request to the function-controlling circuit. The function-controlling circuit generates the first signal in response to the first enabling request in the low power-consumption mode, so that the first functional module enables the first function.

IPC Classes  ?

• G06F 1/32 - Means for saving power
• G06F 1/3234 - Power saving characterised by the action undertaken

Abstract

A referential voltage generating device includes a bandgap-voltage generating unit, a control-comparison unit, a difference current generating unit and a referential voltage generating unit. The bandgap-voltage generating unit generates a second proportional to absolute temperature (PTAT) current and a bandgap-voltage based on a first PTAT current and a complementary to an absolute temperature (CTAT) voltage, both of which are generated in the bandgap-voltage generating unit. The control-comparison unit generates a PTAT voltage based on the second PTAT current, and generates a control voltage based on a difference voltage value between the PTAT voltage and the bandgap voltage. The difference current generating unit generates the difference current based on the control voltage, wherein the difference current is proportional to an absolute voltage value of the control voltage. The referential voltage generating unit generates a referential voltage based on the bandgap voltage and the differential current.

IPC Classes  ?

• G05F 3/26 - Current mirrors

Abstract

A circuit receives an input clock pulse signal characterized by a first frequency and a first pulse width, and produces an output pulse signal characterized by a second frequency that is half of the first frequency and a second pulse width that is equal to the first pulse width. The circuit also includes a first D-flipflop, a first inverter, a first Schmitt trigger, and a first AND gate. The first D-flipflop includes a clock input terminal for receiving the input clock pulse signal and an output terminal for producing a first data output. The first inverter couples the output terminal and a data input terminal of the first D-flipflop. A first Schmitt trigger receives the input clock pulse signal and provides a first delayed input clock signal. The first AND gate receives the first data output and the first delayed input clock signal, and provides the output pulse signal.

IPC Classes  ?

• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
• H03K 3/037 - Bistable circuits
• H03K 5/1252 - Suppression or limitation of noise or interference
• H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
• H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
• H03K 21/00 - Details of pulse counters or frequency dividers

Abstract

A full-bridge circuit module with an over-temperature protection mechanism for driving an inductive load includes a full-bridge circuit and a comparator module. When the over-temperature protection mechanism is triggered, four switching transistors of the full-bridge circuit are turned off, and two body diodes of corresponding twos of the four switching transistors which are electrically connected to each other via the inductive load are conductive to form a load current flowing through the inductive load. When the load current causes a first output voltage of a first output terminal of the full bridge circuit to drop to a first comparison voltage and causes a second output voltage of a second output terminal of the full bridge circuit to reach a second comparison voltage, the comparator module controls the corresponding twos of the four switching transistors which are electrically connected to each other via the inductive load to be turned on.

IPC Classes  ?

• H02P 25/062 - Linear motors of the induction type
• H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage
• H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit

Abstract

A ramp voltage signal generated by an equivalent series resistance compensation circuit in prior art is not linear, and average amplitude and maximum amplitude of the ramp voltage signal changes with an input voltage and a turn-on time. It results in a comparison result or compensation value generated by a comparator of the constant-frequency turn-on circuit will change accordingly and is difficult to control. Thus, it is difficult to design the stability of the system. The embodiments of the present disclosure design an equivalent series resistance compensation circuit including hardware circuits. Through functions of these hardware circuits, a ramp voltage signal of which average amplitude and a maximum amplitude are constant is generated, thereby solving problems encountered in the prior art.

IPC Classes  ?

• H03K 3/0233 - Bistable circuits
• H02M 1/00 - Details of apparatus for conversion
• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

Abstract

A direct memory access device has a first channel combination/separation unit, a second channel combination/separation unit and a data processing device. The first channel combination/separation unit selectively combines/separates channels of data received by the direct memory access device. The second channel combination/separation unit selectively combines/separates channels of data processed by the data processing device. The data are then output by the direct memory access device. The data processing device receives a data output by the first channel combination/separation unit. The data processing device is used to selectively perform at least one of amplification/down-scale process, data bit number adjustment process and shifting process on its received data, and output the data to the second channel combination/separation unit. A sequence and each number of the above-mentioned multiple processes are determined by control selection commands.

IPC Classes  ?

• G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal

Abstract

A micro-controller circuit including a central processing unit (CPU), a plurality of function circuits, a management circuit, and a driving circuit is provided. The CPU is in a first power domain. The function circuits are in a second power domain. In response to the first power domain being powered-off, the function circuits operate normally to generate an event trigger signal. The management circuit reads a look-up table to provide at least one management signal in response to the first power domain being powered-off and the event trigger signal is enabled. The driving circuit adjusts at least one driving signal according to the management signal and provides the driving signal to at least one of the function circuits.

IPC Classes  ?

• G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system

Abstract

A memory address generation device for a test mode comprises row and column address random number counters and a control unit. The row address random number counter receives a counting signal to update a first count value, generates a row address random number based on the first count value, and outputs a row address to the memory. The column address random number counter receives the counting signal to update a second count value, generates a column address random number based on the second count value, and outputs a column address to the memory. The control unit controls the test mode and sets the first/second count value. A difference value between the currently and previously generated row addresses is greater than or equal to 2, and a difference value between the currently and previously generated column addresses is greater than or equal to 2.

IPC Classes  ?

• G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
• G06F 12/02 - Addressing or allocationRelocation

Abstract

A gain control device comprises a sign bit identification device and a gain determination device. The sign bit identification device is used to receive a data, identify a sign bit, and obtain a position of a time slot corresponding to the sign bit. Also, the data comprises a plurality of bits, wherein the most significant bit of the bits is designed to be a sign bit which is used to represent a positive or negative value of the data. The gain determination device is electrically connected to the sign bit identification device, and the gain determination device is used to determine a gain value for amplifying the data based on the position of the time slot corresponding to the sign bit identified through the sign bit identification device.

IPC Classes  ?

• H03G 3/30 - Automatic control in amplifiers having semiconductor devices
• H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only

Abstract

An embodiment of the invention provides a fault-attack analysis device. The first encoder performs a first encoding operation on the first output result corresponding to the normal round calculation to generate a first encoding result. The first decoder performs a first decoding operation on the first encoding result to generate a first decoding result. The second encoder performs a second encoding operation on the second output result corresponding to the redundant round calculation to generate a second encoding result. The second decoder performs a second decoding operation on the second encoding result to generate a second decoding result. The second encoding operation and the second decoding operation are based on binary field addition. The comparison circuit compares the first decoding result to the second decoding result to perform a fault-attack analysis.

IPC Classes  ?

• G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
• G06F 21/60 - Protecting data
• G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits

Abstract

A motion-detection system including a camera and a storage device is provided. The camera captures a color image and transmits the color image to a pre-processor. In a low-power mode, the pre-processor retrieves the luminance value of each pixel in the color image to generate a luminance image and performs resolution reduction on the luminance image to generate an input image. The motion-identifying device identifies a motion-object block within the input image and calculates the amount of movement of the motion-object block. When the amount of movement reaches an identification threshold, the motion-detection system enters a normal mode from the low-power mode. In the normal mode, when an object-identifying model determines that an object in the motion-object block is not a predefined object, the motion-detection system enters the low-power mode.

IPC Classes  ?

• H04N 23/65 - Control of camera operation in relation to power supply
• G06T 7/223 - Analysis of motion using block-matching
• H04N 23/61 - Control of cameras or camera modules based on recognised objects
• H04N 23/84 - Camera processing pipelinesComponents thereof for processing colour signals

Abstract

A multi-processor device comprises more than two processors. The multi-processor device can make the two processors running different operating systems (for example, Linux, real-time operating system (RT OS) or non-operating system (non-OS)) share one peripheral controller by allocating transmit descriptions, receive descriptions, transmit buffers corresponding to the transmit descriptions and receive buffers corresponding to the receive descriptions of the two processors in a shared memory. The peripheral device can process the data associated with the two processors. In one embodiment, the peripheral controller can be an Ethernet controller, and the peripheral device is an Ethernet network card.

IPC Classes  ?

• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 9/54 - Interprogram communication

Abstract

A control chip coupled to a central processing unit (CPU) and including a selection circuit, a buffer circuit, a calculation circuit, and a motion judgment circuit is provided. The selection circuit selects some of the first image macro-blocks of a first image frame and some of the second image macro-blocks of a second image frame. The buffer circuit stores the selected first and second image macro-blocks. The calculation circuit accesses the buffer circuit and calculates the differences between the selected first and second image macro-blocks to generate a calculated result. The motion judgment circuit determines whether the first and second image frames are the same according to the calculated result. In response to the second image frame not being the same as the first image frame, the motion judgment circuit wakes up the CPU so that the CPU enters a normal mode from a low-power mode.

IPC Classes  ?

• G06T 7/223 - Analysis of motion using block-matching
• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
• H04N 23/80 - Camera processing pipelinesComponents thereof

Abstract

A control device includes a storage module and a control module. The storage module includes a plurality of registers. The control module sets the buffer width of the registers, the used number of the registers and the occupied number that a horizontal line signal occupies the registers according to the horizontal resolution. The control module receives the horizontal line signal. The control module assigns a plurality of pixels of the horizontal line signal to the registers. The control module sequentially outputs pixels of the horizontal line signal from the registers.

IPC Classes  ?

• G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals

Abstract

A micro-controller circuit including a sensor circuit, a processing circuit, a storage circuit, and an adjustment circuit is provided. The sensor circuit senses a physical parameter to generate sense information. The processing circuit performs an operation on the sense information to generate a processed signal. The storage circuit stores the processed signal and predetermined information. The adjustment circuit utilizes a machine learning method to process the processed signal stored in the storage circuit to generate a learning result. In response to the learning result not matching the predetermined information, the adjustment circuit adjusts the predetermined information.

IPC Classes  ?

• G05B 19/042 - Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors

Abstract

A secure boot device includes a counter, a storage device and a comparator. The counter receives a clock. When the processor performs a verification of a firmware for the first time, the counter counts a first verification time taken by the processor to perform the verification of the firmware for the first time based on the clock to generate a first-time verification count value. When the processor performs the verification of the firmware for the non-first time, the counter counts a second verification time taken by the processor to perform the verification of the firmware at least once for the non-first time based on the clock to generate a count value. The storage device stores the first-time verification count value. The comparator is electrically connected to the counter and the storage device. When the processor performs the verification of the firmware for the non-first time, the comparator compares the count value with the first-time verification count value, and generates a comparison result. The comparison result is used to indicate whether the processor executes the firmware.

IPC Classes  ?

• G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities

Abstract

A control method executing a power-off detection operation is provided. An operation voltage provided by a power circuit is detected. In response to the operation voltage being equal to the first detection value, the count value is adjusted. In response to the operation voltage being equal to the second detection value, the first detection value, the second detection value, and the count value are calculated to generate a first slope. A first power-off speed at which the operation voltage drops to the reset voltage is estimated according to the first slope. In a test mode, the first power-off speed is output to a test machine. The test machine determines whether the power circuit is working normally according to the first power-off speed.

IPC Classes  ?

• G06F 1/30 - Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
• G06F 1/14 - Time supervision arrangements, e.g. real time clock
• G06F 1/28 - Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A resistance tracking circuit coupled to a comparator circuit is provided. The comparator circuit generates a first current and a second current according to a first control signal and a second control signal. A variable resistor generates a first reference voltage according to the first current. A capacitor generates the output voltage according to the second current. The resistance tracking circuit includes a first conversion circuit which generates the second control signal according to a third control signal, and a copy circuit including a current circuit, a second conversion circuit, and a comparator. The third current circuit generates a third current according to the first control signal. The third current is equal to the first current. The second conversion circuit provides a second reference voltage according to the third current. The comparator compares the first reference voltage and the second reference voltage to generate the third control signal.

IPC Classes  ?

• H03K 3/0231 - Astable circuits
• H03K 3/011 - Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
• H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

Abstract

An embodiment of the invention provides a data transmission device. The data transmission device includes a first bus master control circuit, a second bus master control circuit, a storage circuit, a first control circuit and a second control circuit. The first bus master control circuit processes data transmissions associated with a peripheral device. The second bus master control circuit processes data transmissions associated with a system memory. The storage circuit stores information and instructions for data transmission. The first control circuit controls the first bus master control circuit according to the information and the instructions. The second control circuit controls the second bus master control circuit according to the information and the instructions.

IPC Classes  ?

• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

Abstract

A calibration device, method and electronic device using the same provided by embodiments of the present disclosure only need to measure frequency values of two temperatures, then calculate frequency drift rates of various configuration combinations, and select the configuration combination with the smallest frequency drift rate to set configuration values of a trimming module. Thus, the test time can be reduced. In one embodiment, a simple heating device can be directly disposed on the chip package structure of the electronic device, so it is not necessary to use an external heating device for heating, and the environmental space required for placing the external heating device can be reduced.

IPC Classes  ?

• H03L 1/02 - Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
• H03B 5/04 - Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature

Abstract

A touch-sensing circuit and a touch-judging method are provided. The touch-sensing circuit controls the charging process or the discharging process of a sensing capacitor by a charge-discharge control unit. The first comparator and the second comparator are connected to the sensing capacitor to compare whether the voltage level of the sensing capacitor is higher than the preset high voltage or lower than the preset low voltage. The crossing detection unit receives the output pulse of the comparator and samples the first duration before the output pulse has a state transition and the second duration after the output pulse has the state transition. When the second duration is greater than the first duration, a switching signal is sent to the charge-discharge control unit to switch between the charging and discharging processes.

IPC Classes  ?

• G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
• G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means

Abstract

A mainboard device and an update method of the basic input-output system thereof are provided. The mainboard device includes a flash memory, a universal serial bus (USB) port, and a microprocessor. The code of the basic input-output system is stored in the flash memory. The USB port is connected to an external USB device, wherein the external USB device includes a supply power and stores an update code. The microprocessor includes a power-switching device coupled to the system power and the USB port. When the power-switching device detects that the system power does not provide power and the USB port is provided with the supply power, the microprocessor provides power to the flash memory based on the supply power, and the microprocessor accesses the update code of the external USB device to perform an update operation on the code in the flash memory.

IPC Classes  ?

• G06F 1/26 - Power supply means, e.g. regulation thereof
• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation

Abstract

A security processing device for handling attacks including an attack detector, a programing time controller, a non-volatile memory device and a processing unit. The attack detector is used to detect whether an attack event occurs, and generate an attack trigger signal when the attack event occurs. The programing time controller is electrically connected to the attack detector, and used to update a first flag value when receiving the attack trigger signal. The non-volatile memory device is electrically connected to the program time controller, and used to store the first and the second flag values. The processing unit is electrically connected to the program time controller. When the security processing device is reset or boot-up, the programing time controller updates the second flag value and adjusts a time of a first instruction processed through the processing unit based on the first flag value and the second flag value.

IPC Classes  ?

• G06F 21/55 - Detecting local intrusion or implementing counter-measures
• G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
• G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities

Abstract

A method for automatically setting addresses suitable for an RS485 system is provided. The RS485 system includes a host device and a plurality of slave devices. The method includes the following stages. The host device confirms that there are no addresses of the slave devices in a database. The slave devices are turned on in sequence. The slave devices calculate their own respective power-on times. The slave device enter an idle state during the period associated with the power-on time. Only one of the slave devices sends the power-on time to the host device when said slave device leaves the idle state. The host device sets the address of said slave device according to the power-on time when said slave device leaves the idle state.

IPC Classes  ?

• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
• G06F 13/38 - Information transfer, e.g. on bus

Abstract

A comparator testing circuit and a testing method are provided. The comparator testing circuit includes a switching circuit, a comparator, and a determination circuit. The switching circuit receives a first signal, a second signal, and a switching signal, and outputs one of the first signal and the second signal as a first input signal and the other of the first signal and the second signal as a second input signal according to the switching signal. The comparator compares the first input signal with the second input signal to generate an output signal. The determination circuit determines whether the comparator is abnormal based on the switching signal and the output signal to generate an exception flag.

IPC Classes  ?

• H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• H03K 3/037 - Bistable circuits
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

A touch detection circuit detects whether a key is being touched and includes a comparator, a compensation capacitor, and a voltage control circuit. The comparator includes an inverting input, a non-inverting input, and an output terminal. The compensation capacitor is coupled to the inverting input. The voltage control circuit provides an output voltage to the non-inverting input. In a calibration mode, the voltage control circuit adjusts the output voltage according to the voltage level of the output terminal.

IPC Classes  ?

• H03K 17/00 - Electronic switching or gating, i.e. not by contact-making and -breaking
• G06F 3/023 - Arrangements for converting discrete items of information into a coded form, e.g. arrangements for interpreting keyboard generated codes as alphanumeric codes, operand codes or instruction codes
• G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
• H03K 17/96 - Touch switches