Abrégé

A frequency adjustment device includes a microprocessor, a buffer, and a frequency adjustment circuit. The microprocessor is configured to receive a memory access signal. The buffer is disposed inside the microprocessor. The buffer is configured to output an input pointer signal and an output pointer signal according to the memory access signal, the input pointer signal, and the output pointer signal. The frequency adjustment circuit is disposed inside the microprocessor. The frequency adjustment circuit is configured to output a first current threshold according to the input pointer signal and the output pointer signal. The frequency adjustment circuit is further configured to output a threshold trimming signal to a time register according to a setting threshold signal and the first current threshold.

Classes IPC  ?

• H03L 7/24 - Commande automatique de fréquence ou de phaseSynchronisation utilisant un signal de référence directement appliqué au générateur

Abrégé

A fan driving device and method thereof for cooling a data processing system are provided. The fan driving device comprises a fan driving module and a machine learning module. The fan driving module outputs a driving voltage to rotate the fan. The machine learning module predicts a temperature of the data processing system after a preset time based on the number of instructions or instruction type of instructions executed or to be executed by the data processing system, and determines the driving voltage based on the temperature. The machine learning module is trained using the number of instructions, instruction type, a driving voltage and fan speed relationship table, and a fan speed and temperature relationship table.

Classes IPC  ?

• F04D 27/00 - Commande, p. ex. régulation, des pompes, des installations ou des systèmes de pompage spécialement adaptés aux fluides compressibles
• F04D 29/66 - Lutte contre la cavitation, les tourbillons, le bruit, les vibrations ou phénomènes analoguesÉquilibrage
• G05B 13/02 - Systèmes de commande adaptatifs, c.-à-d. systèmes se réglant eux-mêmes automatiquement pour obtenir un rendement optimal suivant un critère prédéterminé électriques

Abrégé

A voltage conversion device and a method capable of adjusting a voltage conversion rate based on an input voltage are provided. The voltage conversion device includes a charge pump circuit, an operating voltage generation module, and a processing module. The charge pump circuit converts the input voltage into an output voltage based on an operating voltage and a clock signal, and the voltage conversion rate of the charge pump circuit is dynamically adjustable. The operating voltage generation module is connected to the output voltage, includes a Zener diode, and generates the operating voltage based on a conduction state of the Zener diode. The processing module is connected to the operating voltage generation module, detects a first current flowing through the Zener diode, and adjusts the voltage conversion rate of the charge pump circuit based on the first current.

Classes IPC  ?

• H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande

Abrégé

Adaptive current limiters for capacitive loads (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a signal emitting system includes a signal processing unit, an amplifier, and an emitter. The signal processing unit can determine a delta limit based on (i) system parameters and (ii) a representative magnitude corresponding to a sample of a source signal, one or more samples of a conditioned signal, or a combination thereof. The signal processing unit can further determine a ratio of (i) the delta limit to (ii) a difference between a sample of the source signal and a previous sample of the source signal, and apply a lowpass filter to the source signal to obtain a filtered signal, with filter coefficients based on the ratio. The amplifier can generate an amplified signal based on the filtered signal, and the emitter can emit an output signal based on the amplified signal.

Classes IPC  ?

• H04R 3/00 - Circuits pour transducteurs
• H03F 3/20 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C
• H04R 3/04 - Circuits pour transducteurs pour corriger la fréquence de réponse
• H04R 17/00 - Transducteurs piézo-électriquesTransducteurs électrostrictifs

Abrégé

An electronic device includes a logic controller, a time digital converter, and a clock adjustment circuit. The logic controller receives a clock signal and generates a first signal and a second signal according to the clock signal. The first signal leads the second signal by a first time difference. The time digital converter includes a plurality of delay circuits, receives the first signal and the second signal, and enables the second signal to catch up with the first signal in a second time difference through the delay circuits. The clock adjustment circuit adjusts the frequency of the clock signal according to the sum of the first time difference and the second time difference respectively calculated in the previous and subsequent periods of the clock signal.

Classes IPC  ?

• G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
• G06F 1/12 - Synchronisation des différents signaux d'horloge
• G06F 1/14 - Dispositions pour le contrôle du temps, p. ex. horloge temps réel

Abrégé

A control circuit including a processing circuit, a function circuit, a voltage regulator, and a monitoring circuit is provided. The voltage regulator uses a switching signal to adjust the operating voltage provided to the processing circuit and the function circuit. The monitoring circuit determines the total current of the processing circuit and the function circuit according to the switching signal. In response to the total current of the processing circuit and the function circuit being higher than a heavy threshold value, the monitoring circuit directs the function circuit to operate in an energy-saving mode. In response to the total current of the processing circuit and the function circuit being lower than a light threshold value, the monitoring circuit directs the function circuit to operate in a performance mode.

Classes IPC  ?

• G06F 1/3296 - Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
• G06F 1/3206 - Surveillance d’événements, de dispositifs ou de paramètres initiant un changement de mode d’alimentation

Abrégé

A malware detection apparatus includes a processor and an accelerator processor. The accelerator processor is electrically connected to the processor. The processor operates in a first mode or a second mode, a first authority of the first mode is higher than a second authority of the second mode. The accelerator processor is triggered by the processor under the first mode to read a code block in an untrusted region, use an interpretation model to determine whether a software program corresponding to the code block is malware based on the code block, and generate an interpretation result to the processor.

Classes IPC  ?

• G06F 21/56 - Détection ou gestion de programmes malveillants, p. ex. dispositions anti-virus

Abrégé

A current source circuit including a current mirror, a bias resistor, a first transistor, a second transistor and a first current source is provided. The current mirror is coupled between a supply voltage terminal, a first node, and a second node and outputs a first current and a second current to the first node and the second node respectively. The bias resistor is coupled between the first node and a third node and controls the first current according to a voltage difference between the first node and the third node. The first transistor is coupled between the third node and a reference voltage terminal. The second transistor is connected between the second node and the reference voltage terminal. The first current source outputs a third current to the second node to generate a fourth current. The third current has negative temperature coefficient.

Classes IPC  ?

• G05F 3/26 - Miroirs de courant

Abrégé

A convolution accelerator performing the convolution operations of a plurality of convolution layers on data stored in a storage circuit is provided. The convolution accelerator includes a plurality of convolution calculation circuits, a detection circuit, and a control circuit. A convolution operation is performed in response to one of the convolution calculation circuits being turned on. The detection circuit detects the access state of the storage circuit within a fixed time interval to generate a detection signal. The control circuit dynamically adjusts the number of convolution calculation circuits to be turned on for the convolution operations of each of the convolution layers according to the detection signal.

Classes IPC  ?

• G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
• G06N 3/0464 - Réseaux convolutifs [CNN, ConvNet]

Abrégé

An interface controller is electrically connected between a data storage device and a bus system. The interface controller is configured to read and buffer first data of a data block or second data of an associated data block related to the data block from the data storage device, and to transmit the buffered first data or second data to the bus system. The interface controller is further configured to utilize a prediction model to predict whether the data block is associated with one of a plurality of other data blocks. If the data block is associated with one of the plurality of other data blocks, and all of the first data of the data block has been read by the interface controller, the interface controller reads the second data of the associated data block from the data storage device.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A system and method for improving power using efficiency are provided. The method includes periodically providing load data corresponding to load states of multiple peripheral units to a neural network unit. Based on the load data, the neural network unit calculates a power operation prediction score. An operation mode is then determined according to the prediction score to control activation and deactivation of the peripheral units. A clock rate is further adjusted according to the operation mode.

Classes IPC  ?

• G06F 1/3206 - Surveillance d’événements, de dispositifs ou de paramètres initiant un changement de mode d’alimentation
• G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]

Abrégé

A side channel attack prevention apparatus includes a controller and a machine learning module. When a sensitive data processing device and/or an encryption and decryption device of the electronic device is operating, the controller uses a power waveform adjustment manner to change a power waveform of the electronic device. The machine learning module acquires the power waveform during operation of the encryption and decryption device and/or the sensitive data processing device of the electronic device and determines a confidence that the power waveform has a specific characteristic. The power waveform adjustment manner is one selected by the controller from power waveform adjustment manners that have not been selected previously among a plurality of power waveform adjustment manners, and, when the confidence is greater than or equal to a threshold value, the controller reselects one power waveform adjustment manner from the power waveform adjustment manners that have not been selected previously.

Classes IPC  ?

• H04L 9/00 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité
• G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p. ex. pour empêcher l'ingénierie inverse
• G06F 21/81 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur en agissant sur l’alimentation, p. ex. en branchant ou en débranchant l’alimentation, les fonctions de mise en veille ou de reprise

Abrégé

A control chip disposed in a motherboard and including a first detection pin, a second detection pin, a first control pin, a second control pin, a detection circuit and a determination circuit is provided. The first detection pin is coupled to a first external device including a first light-emitting circuit. The second detection pin is coupled to a second external device including a second light-emitting circuit. The first and second control pins are respectively coupled to the first and second light-emitting circuits. The detection circuit detects the voltages of the first and second detection pins to generate a first detection signal and a second detection signal. In response to the first external device having been coupled to the motherboard and the second external device having been coupled to the motherboard, the determination circuit controls the lighting effects displayed by the first and second light-emitting circuits.

Classes IPC  ?

• H05B 45/14 - Commande de l'intensité de la lumière à l'aide d'une rétroaction électrique provenant de LED ou de modules de LED
• G06F 13/12 - Commande par programme pour dispositifs périphériques utilisant des matériels indépendants du processeur central, p. ex. canal ou processeur périphérique
• H05K 1/181 -

Abrégé

A method for reducing network packet load is provided. The method is implemented by a device and includes receiving network packets from an Ethernet physical layer into a receiving slot. The method includes determining whether a packet count of the network packets in the receiving slot exceeds an intermediate threshold. The method includes filtering out first network packets from media access control addresses recorded in a blacklist according to the blacklist when the packet count exceeds the intermediate threshold value.

Classes IPC  ?

• H04L 9/40 - Protocoles réseaux de sécurité

Abrégé

An electronic device is disclosed. The device includes a storage module configured to store a plurality of instructions, a controller configured to load and parse a first instruction, and a timing module. When the first instruction is a logic instruction, the controller selects and parses a second instruction according to the first instruction. When the first instruction is a trigger instruction, the controller outputs a first signal indicating a time period and a second signal indicating a peripheral module. The timing module receives the signals, counts to obtain a count value associated with the time period, compares the count value with the time period to generate a time trigger signal, and outputs a target trigger signal to trigger the peripheral module to operate.

Classes IPC  ?

• G06F 1/3234 - Économie d’énergie caractérisée par l'action entreprise
• G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions

Abrégé

A game system is provided. The game system includes a display device, an input device, a processing device, and a microcontroller. The display device is configured to display a first game screen. The input device is configured to receive a game operation. The processing device is configured to generate a second game screen based on the first game screen and the game operation. The microcontroller is connected to the processing device, the display device, and the input device. The microcontroller is configured to generate a game suggestion based on the first game screen and the game operation through the artificial intelligence (AI) module. The display device is further configured to display a third game screen including the second game screen and the game suggestion. The game suggestion is superimposed on the second game screen.

Classes IPC  ?

• A63F 13/53 - Commande des signaux de sortie en fonction de la progression du jeu incluant des informations visuelles supplémentaires fournies à la scène de jeu, p. ex. en surimpression pour simuler un affichage tête haute [HUD] ou pour afficher une visée laser dans un jeu de tir
• A63F 13/67 - Création ou modification du contenu du jeu avant ou pendant l’exécution du programme de jeu, p. ex. au moyen d’outils spécialement adaptés au développement du jeu ou d’un éditeur de niveau intégré au jeu en s’adaptant à ou par apprentissage des actions de joueurs, p. ex. modification du niveau de compétences ou stockage de séquences de combats réussies en vue de leur réutilisation
• A63F 13/837 - Tirs à la cible

Abrégé

A method for determining a quantity corresponding to peripheral modules for reducing gate count, executed in a development stage of a SoC, and the method has steps: (A) selecting an estimated quantity corresponding to first peripheral modules; (B) dispose the first peripheral module in the SoC based on the estimated quantity corresponding to first peripheral modules; (C) obtaining an activation status and a peripheral setting parameter and performance parameter set of each of the first peripheral modules; (D) using a trained machine learning model to calculate a first processing timing of data transmission of each of the first peripheral modules based on the activation status and the peripheral setting parameter and performance parameter set of each of the first peripheral modules; (E) using an inference unit to determine whether to reduce the estimated quantity based on the first processing timing of data transmission of each of the first peripheral modules.

Classes IPC  ?

• G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
• G06F 115/02 - Conception de systèmes sur une puce [SoC]

Abrégé

Power-on reset (POR) circuits with brownout detection, including small form factor and/or low-power/low-voltage POR circuits, are disclosed herein. In one embodiment, a POR circuit includes at least one current mirror and an inverter having an input coupled to the at least one current mirror. A voltage at the input of the inverter is based at least in part on (i) a current produced by the at least one current mirror and (ii) a power supply voltage. The POR circuit is configured to generate a power-on reset bar signal based at least in part on the output of the inverter. In some embodiments, the POR circuit can further include a Schmitt-trigger buffer coupled to the output of the inverter to provide hysteresis to the power-on reset bar signal.

Classes IPC  ?

• H03K 17/22 - Modifications pour assurer un état initial prédéterminé quand la tension d'alimentation a été appliquée

Abrégé

A test device including a storage circuit and a processing circuit is provided. The storage circuit stores a machine learning model. In a training mode, the processing circuit loads the machine learning model and inputs wafer acceptance test (WAT) sample data of a sample wafer into the machine learning model to train the machine learning model to predict the process factor of each sample die of the sample wafer. In a test mode, the processing circuit inputs WAT data of a wafer to be tested into the machine learning model to predict the process factor of each die of the wafer to be tested. In the test mode, the processing circuit converts the process factor of each die of the wafer to be tested to generate a trim value and provides the trim value to a function circuit of a corresponding die of the wafer to be tested.

Classes IPC  ?

• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement

Abrégé

A test method is provided. In a training period, a plurality of WAT sample data of a plurality of sample wafers are received, and a CP operation is performed on the sample wafers to generate a plurality of CP sample data. The machine learning model calculates the WAT sample data and the CP sample data to generate a correlation. In a test period, the product information and the WAT measurement data of a wafer to be tested are input to the machine learning model. The machine learning model determines at least one key parameter from the WAT measurement data according to the correlation. The machine learning model adjusts the testing sequence of a plurality of test items according to the key parameter. The wafer to be tested is tested according to the adjusted testing sequence of the plurality of test items.

Classes IPC  ?

• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

Abrégé

A computer system for optimizing a temperature adjustment mechanism of a ring oscillator (RC) is provided. The computer system includes a storage unit and a processing unit. The storage unit stores an RC characteristic data set. The RC characteristic data set includes one or more characteristics of each of a plurality of RCs and an optimal temperature coefficient set of the each RC. The characteristics of the each RC include a temperature-frequency relationship of the RC. The processing unit loads program instructions from the storage unit to receive one or more target characteristics of a target RC, and to determine a target temperature coefficient set of the target RC based on the RC characteristic data set and the target characteristics. The target characteristics include a temperature-frequency relationship of the target RC.

Classes IPC  ?

• H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p. ex. alimentation, charge, température
• G06F 1/20 - Moyens de refroidissement
• G06F 1/3234 - Économie d’énergie caractérisée par l'action entreprise
• H03L 1/02 - Stabilisation du signal de sortie du générateur contre les variations de valeurs physiques, p. ex. de l'alimentation en énergie contre les variations de température uniquement

Abrégé

A target yield correction method is provided. A plurality of yields of a plurality of first products in a plurality of wafers and a plurality of sizes of the first products in the wafers are obtained. The yields are divided into a plurality of groups according to sizes of the first products. The yields of each group are averaged to generate an average yield. The average yields and the sizes are calculated to generate a plurality of defect density values. The defect density values are input into a machine learning model to remove at least one defect density value that does not meet a predetermined standard. A baseline curve is generated according to the remaining defect density values. The baseline curve and the sizes are calculated to generate a plurality of target yields. Each target yield corresponds to one of the sizes.

Classes IPC  ?

• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

Abrégé

A control circuit including a plurality of processing circuits and a calculation circuit is provided. The calculation circuit detects which of the processing circuits are turned on and includes a machine learning module. The machine learning module predicts the sum of the power consumption values of the turned-on processing circuits according to a power-consumption profile. In response to the sum of the power consumption values of the turned-on processing circuits being higher than a threshold value, the calculation circuit adjusts behaviors of the turned-on processing circuits to reduce the sum of the power consumption values of the turned-on processing circuits.

Classes IPC  ?

• G06F 1/3296 - Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
• G05B 13/02 - Systèmes de commande adaptatifs, c.-à-d. systèmes se réglant eux-mêmes automatiquement pour obtenir un rendement optimal suivant un critère prédéterminé électriques

Abrégé

A control chip coupled to an external chip and including an interface control circuit, a first memory, a second memory, and a processing circuit is provided. The interface control circuit outputs data to the external chip according to the transmission setting value. The first memory stores the performance status and the interface setting value. The second memory stores predetermined data. The processing circuit dynamically adjusts the transmission setting value according to the performance status, the interface setting value, and the predetermined data to modify the transmission efficiency.

Classes IPC  ?

• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
• G06N 5/04 - Modèles d’inférence ou de raisonnement

Abrégé

A prediction method for predicting the yield of a batch of wafers is provided. During a training period, a plurality of wafer acceptance test (WAT) sample data of a plurality of first wafers are received, a wafer probe (CP) test is performed on the first wafers to generate a plurality of CP sample data, and the WAT sample data and the CP sample data are input into a machine learning model. The machine learning model calculates the WAT sample data and the CP sample data to generate a correlation. During a prediction period, WAT measurement data is input into a trained machine learning model. The trained machine learning model predicts the yield of the batch of wafers according to the correlation and the WAT measurement data.

Classes IPC  ?

• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
• G06N 20/00 - Apprentissage automatique

Abrégé

An electronic device includes an offset calibration module, an analog-to-digital converter module, a host, and an operational amplifier. The offset calibration module is configured to measure an operating voltage and a temperature and to determine whether it stores offset error information associated with the operating voltage and temperature. The operational amplifier has a negative input electrically connected to the offset calibration module, a positive input electrically connected to the analog-to-digital converter module, and an output electrically connected to the host. When the offset error information is stored, the offset calibration module outputs the offset error information to the operational amplifier, and the analog-to-digital converter module performs a normal analog-to-digital conversion based on a trigger signal to output a raw value to the operational amplifier. The operational amplifier then outputs a result value to the host.

Classes IPC  ?

• H03M 1/10 - Calibrage ou tests

Abrégé

A control circuit including a detection circuit, a sampling circuit, and an operational circuit is provided. The detection circuit collects first external information to generate a first detection signal. The sampling circuit has a first sampling rate and samples the first detection signal to generate a first sampled signal. The operational circuit inputs the first sampled signal to an inference model to generate an inference result, and determines whether the first predetermined condition is satisfied according to the inference result. In response to the first predetermined condition being satisfied, the operational circuit adjusts the first sampling rate from the first predetermined value to the second predetermined value. In response to the first predetermined condition not being satisfied, the operational circuit maintains the first sampling rate at the first predetermined value.

Classes IPC  ?

• G05B 13/02 - Systèmes de commande adaptatifs, c.-à-d. systèmes se réglant eux-mêmes automatiquement pour obtenir un rendement optimal suivant un critère prédéterminé électriques

Abrégé

A computer system for supporting multi-language file processing is provided. The computer system includes a storage unit and a processing unit. The storage unit stores a graphical user interface (GUI) program and a file. The processing unit loads the GUI program from the storage unit to perform the following steps. The processing unit receives a filename expressed in a first language and encoded with a first character encoding standard, and generates an alias expressed in a second language using the same encoding. The processing unit links the alias name to the file so that both the filename and the alias name refer to the file. The processing unit converts the alias name to follow the second character encoding standard, so as to enforce low-level processing that follows the second character encoding standard on the file to which the alias name refers.

Classes IPC  ?

• G06F 40/126 - Encodage de caractères

Abrégé

A universal serial bus (USB) power delivery device is provided, including a bit detector, a start of packet (SOP) cycle counter, a reset detector, and a flag generator. The bit detector receives and detects an input data signal, and enables a preamble confirmation signal in response to a preamble byte in the input data signal. The SOP cycle counter starts counting and enables an SOP enable signal in response to the preamble confirmation signal being disabled. The reset detector receives and determines whether the input data signal includes codes related to a hard reset, to output an invalid hard reset signal and a K code confirmation signal. The flag generator receives the SOP enable signal, the invalid hard reset signal, the K code confirmation signal, and a reset enable signal, to output an invalid hard reset flag to an event recorder.

Classes IPC  ?

• G06F 1/26 - Alimentation en énergie électrique, p. ex. régulation à cet effet

Abrégé

A power reduction device includes a first master controller, a processor, and a power manager. The power manager includes a model acceleration algorithm. The first master controller is configured to output a first active transmission signal. The model acceleration algorithm is configured to control the clock source of the processor or the power supply of the processor to reduce the power consumption of the processor according to the first active transmission signal.

Classes IPC  ?

• G06F 1/324 - Économie d’énergie caractérisée par l'action entreprise par réduction de la fréquence d’horloge

Abrégé

The present invention provides a semiconductor device having two independent power domains: a first power domain and a second power domain. Different clock signals are applied to the respective circuits which are provided in the first and second power domains. The first and second power domains have a first storage unit and a second storage unit, respectively. When the semiconductor device enters a power-saving mode, the parameter of the first storage unit is maintained in the second storage unit, and then the first power domain is turned off. In the power-saving mode, the timing of each device in the second power domain is driven by the second clock signal, so as to solve the problem of clock domain crossing between different power domains. Therefore, the second power domain may use a second storage unit with a lower processing speed than the first storage unit.

Classes IPC  ?

• G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
• G06F 1/3237 - Économie d’énergie caractérisée par l'action entreprise par désactivation de la génération ou de la distribution du signal d’horloge
• G06F 1/3246 - Économie d’énergie caractérisée par l'action entreprise par mise hors tension initiée par logiciel

Abrégé

A keyboard security device includes a keyboard control module for outputting typing information when the keyboard is in use; an audio signal control module for outputting a first raw audio signal when a microphone module is activated; an intelligent learning module for generating an additional audio signal based on the typing information received from the keyboard control module and the first raw audio signal received from the audio signal control module, and outputting the additional audio signal; and a sound mixing module for, in response to a trigger signal, mixing a second raw audio signal received from the audio signal control module with the additional audio signal received from the intelligent learning module, to generate a mixed audio signal and output the mixed audio signal. The first raw audio signal corresponds to the typing information.

Classes IPC  ?

• G06F 21/83 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs de saisie de données, p. ex. claviers, souris ou commandes desdits claviers ou souris
• G06F 3/023 - Dispositions pour convertir sous une forme codée des éléments d'information discrets, p. ex. dispositions pour interpréter des codes générés par le clavier comme codes alphanumériques, comme codes d'opérande ou comme codes d'instruction
• G06F 3/16 - Entrée acoustiqueSortie acoustique

Abrégé

An electronic device includes a power-supply input, a protected circuit and a voltage sense circuit, The protected circuit is configured to draw current from the power-supply input, thereby obtaining from the power-supply input an operational voltage waveform. The voltage sense circuit is configured to receive, from the power-supply input, a sense voltage waveform that differs from the operational voltage waveform, via a second electrical connection that is separate from the first electrical connection, and to detect a security attack on the protected circuit responsively to the sense voltage waveform.

Classes IPC  ?

• G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p. ex. pour empêcher l'ingénierie inverse
• G06F 21/56 - Détection ou gestion de programmes malveillants, p. ex. dispositions anti-virus

Abrégé

A driving system for a buzzer is provided. The driving system includes a driving unit and a boost unit. The driving unit receives an analog audio and outputs a driving voltage to the buzzer according to the analog audio. The boost unit is electrically connected to the driving unit, generates a working voltage by boosting an input voltage and transmits the working voltage to the driving unit. The driving system generates the driving voltage through an analog signal to improve an output audio quality of the buzzer.

Classes IPC  ?

• H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs
• G10K 9/122 - Dispositifs dans lesquels le son est produit par la vibration d'un diaphragme ou un élément analogue, p. ex. cornes de brume, avertisseurs de véhicule ou vibreurs fonctionnant électriquement utilisant des moyens d'entraînement piézo-électriques

Abrégé

A buzzer driving system includes a filter circuit and a driving circuit. The filter circuit is configured to filter an audio playback signal and output an analog playback signal. The driving circuit is electrically connected to the filter circuit and configured to output a driving voltage to the buzzer based on the analog playback signal. The driving system generates the driving voltage in an analog form to enhance the output audio quality of the buzzer.

Classes IPC  ?

• H03G 3/00 - Commande de gain dans les amplificateurs ou les changeurs de fréquence
• H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs

Abrégé

A buzzer driving system with a signal compensation function for a buzzer is provided. The buzzer driving system includes a control module and a filter module. The control module has a neural network unit configured to generate a filter coefficient corresponding to a frequency response of the buzzer based on frequency spectrum data of the buzzer. The filter module is configured to receive an audio playback signal and filter the audio playback signal according to the filter coefficient to generate an output signal. The buzzer driving system realizes signal compensation of the buzzer by adjusting the filter coefficient, thereby preventing distortion of the output audio signal.

Classes IPC  ?

• G10K 9/122 - Dispositifs dans lesquels le son est produit par la vibration d'un diaphragme ou un élément analogue, p. ex. cornes de brume, avertisseurs de véhicule ou vibreurs fonctionnant électriquement utilisant des moyens d'entraînement piézo-électriques
• G01R 23/16 - Analyse de spectreAnalyse de Fourier

Abrégé

A buzzer driving system is electrically connected to a buzzer and includes a driving unit, a boost unit, and a gain estimation unit. The driving unit includes a gain control circuit that adjusts the gain of an audio signal based on a gain factor and outputs a driving voltage to the buzzer based on the adjusted audio signal. The boost unit is electrically connected to the driving unit and boosts an input voltage to generate a working voltage for the driving unit. The gain estimation unit is electrically connected to both the driving unit and the boost unit and is configured to generate a plurality of stepwise voltages based on the working voltage. The gain estimation unit sequentially compares the input voltage with each of the stepwise voltages to generate an estimated gain. The gain factor used by the gain control circuit is determined based on this estimated gain.

Classes IPC  ?

• H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs
• G10K 9/122 - Dispositifs dans lesquels le son est produit par la vibration d'un diaphragme ou un élément analogue, p. ex. cornes de brume, avertisseurs de véhicule ou vibreurs fonctionnant électriquement utilisant des moyens d'entraînement piézo-électriques

Abrégé

A successive-approximation register analog-to-digital converter includes a first digital-to-analog converter, a comparator, a successive-approximation controller, and a calibration controller. The first digital-to-analog converter generates a difference voltage based on an input voltage and a digital code. The digital code corresponds to a sum of the input voltage and the difference voltage. When the difference voltage exceeds a threshold, the comparator sets a comparison signal to an enabled state. The successive-approximation controller adjusts the digital code based on the comparison signal, so that the digital code corresponds to the input voltage. The calibration controller executes a calibration process to determine a delay time from the digital code changing to the comparison signal switching from a disabled state to the enabled state.

Classes IPC  ?

• H03M 1/10 - Calibrage ou tests

Abrégé

A data rearrangement system is provided. The system includes a data-encoding device and a data-decoding device. The data-encoding device is configured to receive one or more data streams from one or more end devices. The data-encoding device is configured to generate a data-encoding pattern based on quality of service (QoS) information, scheduling policy, and transmission information of the data streams using a neural network model. The data-encoding device is configured to encode the data streams to generate an encoded data stream with an encoder, according to the data-encoding pattern. The data-encoding device is configured to transmit the data-encoding pattern and the encoded data stream to the data-decoding device. The data-decoding device is configured to restore the data stream according to the data-encoding pattern and the encoded data stream.

Classes IPC  ?

• H04L 47/2441 - Trafic caractérisé par des attributs spécifiques, p. ex. la priorité ou QoS en s'appuyant sur la classification des flux, p. ex. en utilisant des services intégrés [IntServ]
• H03M 7/28 - Structures programmables, c.-à-d. dans lesquelles le convertisseur de code contient un dispositif permettant à l'opérateur de modifier le procédé de conversion
• H04L 41/14 - Analyse ou conception de réseau

Abrégé

A clock control method for a slave device and a microprocessor system using the same are disclosed. The clock control method for a slave device comprises connecting a microprocessor and a plurality of slave devices via a bus; controlling a clock signal to enable or disable for one of the plurality of slave devices through a corresponding one of a plurality of clock gating circuits; pre-decoding an instruction output by the microprocessor to the bus to obtain an address of the instruction; finding a specific slave device corresponding to the address from the plurality of slave devices; and when one of the plurality of clock gating circuits corresponding to the specific slave device is not enabled, enabling the one of the plurality of clock gating circuits so that the specific slave device operates normally to receive the instruction.

Classes IPC  ?

• G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
• G06F 1/14 - Dispositions pour le contrôle du temps, p. ex. horloge temps réel

Abrégé

A differential signal generation circuit is provided. A PMOS transistor pair provides a first current to a current modulator circuit. A first current control circuit is coupled to the PMOS transistor pair in parallel. When the PMOS transistor pair is turned off, the first current control circuit provides the first current to the current adjustment circuit. An NMOS transistor pair provides a second current to the current modulator circuit. A second current control circuit is coupled to the NMOS transistor pair in parallel. When the NMOS transistor pair is turned off, the second current control circuit provides the second current to the current modulator circuit. The current modulator circuit sets the static current of a first output terminal to be equal to the static current of a second output terminal.

Classes IPC  ?

• H03F 3/45 - Amplificateurs différentiels
• H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire

Abrégé

A data transmission controller including a first master, a second master, a first slave, a second slave, a plurality of channels, a direct memory access (DMA) controller, a first command converter, and a second command converter is provided. The channels are coupled to the first or second master. The DMA controller is configured to receive a plurality of first commands, and to transmit the first commands to the channels corresponding to different data flow directions in order to transmit the first commands to the first or second master. The first and second command converters are respectively connected to the first and second slave, and are respectively connected to the second and first master through the channels. The first and second command converters are configured to convert original commands into a plurality of second commands with DMA mode.

Classes IPC  ?

• G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle

Abrégé

A network-packet filtering system is provided. The system includes one or more end hosts and a network-packet filtering device communicable with the end hosts and an external network. Each end host obtains its host-performance vector by executing a first neural network model based on its system-performance information. The network-packet filtering device determines whether to drop a packet from the external network or to pass the packet by executing a second neural network model based on the host-performance vectors and the packet.

Classes IPC  ?

• H04L 9/40 - Protocoles réseaux de sécurité

Abrégé

A level shifter circuit including a bias-voltage generation circuit, a charge-discharge balancer circuit, a first high-voltage NMOS transistor, a second high-voltage NMOS transistor, a low-voltage processing circuit, and a high-voltage processing circuit is provided. The bias-voltage generation circuit generates a stable voltage. The charge-discharge balancer circuit generates a first control voltage and a second control voltage based on the stable voltage, a first processed signal, and a second processed signal. The first high-voltage NMOS transistor receives the first control voltage and a third processed signal. The second high-voltage NMOS transistor receives the second control voltage and a fourth processed signal. The low-voltage processing circuit processes an input signal to provide the first, second, third, and fourth processed signals. The high-voltage processing circuit generates an output signal based on the drain voltage of the first high-voltage NMOS transistor and the drain voltage of the second high-voltage NMOS transistor.

Classes IPC  ?

• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
• H03K 17/0412 - Modifications pour accélérer la commutation sans réaction du circuit de sortie vers le circuit de commande par des dispositions prises dans le circuit de commande

Abrégé

A system includes: a microphone configured to receive an acoustic signal; an ADC configured to convert the acoustic signal into a digital form; and a processor configured to: trim a window of the digital form; locate positive-bound zero-crossings or negative-bound zero-crossings; locate local maxima or local minima between each of the two neighboring positive-bound zero-crossings or between each of the two neighboring negative-bound zero-crossings; identify an overall maximum; determine at least one valid sample range; determine an amplitude threshold; screen the local maxima or the local minima based on the at least one valid sample range and the amplitude threshold to identify a first set of local maxima or a first set of local minima; select a second number of top local maxima or a second number of bottom local minima; expand the first set of lags; calculate normalized autocorrelations; and determine an approximated maximum normalized autocorrelation.

Classes IPC  ?

• G10L 25/06 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par le type de paramètres extraits les paramètres extraits étant des coefficients de corrélation
• G10L 25/09 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par le type de paramètres extraits les paramètres extraits étant des taux de passage par zéro
• G10L 25/90 - Détermination de la hauteur tonale des signaux de parole

Abrégé

An oscillator device includes a control circuit and an oscillator circuit. The control circuit receives a first input signal and a second input signal, and generates a first control signal and a second control signal. The oscillator circuit is coupled to the control circuit. The oscillator circuit receives the first control signal and the second control signal, and generates a first oscillating signal and a second oscillating signal according to the first control signal and the second control signal.

Classes IPC  ?

• H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p. ex. alimentation, charge, température

Abrégé

A self-calibration digital-to-analog converter (DAC) and a calibration method for DAC are provided. The circuit includes a resistor circuit, a buffer amplifier, a fine-tuning circuit, and a correction switching circuit. In normal operation mode, the resistor circuit receives the common voltage for conversion. In correction mode, the circuit performs self-correction in a sampling time and a comparison time. During the sampling time, the resistor circuit receives the reference voltage and first correction data, and the buffer amplifier input samples the voltage. During the comparison time, the resistor circuit receives the common connection voltage and second correction data, and the fine-tuning circuit adjusts the correction data until the buffer amplifier output voltage flips and records the correction value corresponding to the second correction data. With this self-correction mechanism, the circuit can output theoretically correct digital-to-analog conversion results under the reference voltage and common connection voltage.

Classes IPC  ?

• H03M 1/10 - Calibrage ou tests

Abrégé

A micro-controller system including a central processing unit, a peripheral device, and an interrupt pre-processor is provided. The interrupt pre-processor is connected between the central processing unit and the peripheral device. When the central processing unit is powered down, the interrupt pre-processor is configured to receive an interrupt signal from the peripheral device and output a wake-up signal to activate the central processing unit when the number of times that the interrupt pre-processor receives the interrupt signal from the peripheral device is higher than or equal to the first predetermined number.

Classes IPC  ?

• G06F 1/3215 - Surveillance de dispositifs périphériques
• G06F 13/32 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant la combinaison d'interruption et de transfert par rafale

Abrégé

A fan driving chip for detecting a type of a fan electrically connected to the fan driving chip and driving the fan is provided. The fan driving chip includes: a first specific chip pin adapted for receiving a signal from the fan; a second specific chip pin; a chip control module electrically connected to the first specific chip pin and the second specific chip pin. When detecting that the signal includes specific data with a specific pattern, the chip control module determines that the fan is a smart fan capable of supporting a specific function, and triggers an exchange of at least one acknowledgement signal with the fan through the first specific chip pin and the second specific chip pin to control a rotation speed and the specific function of the fan, wherein a specific effect of the specific function is a function other than fan rotation.

Classes IPC  ?

• G06F 1/20 - Moyens de refroidissement

Abrégé

A low battery voltage protection method for a microcontroller system and a microcontroller system using the same are provided. The low battery protection method and the microcontroller system are used to prevent continuous battery drain by setting time thresholds and a count threshold. In an embodiment, when a low-voltage power-on reset voltage is not exceeded within a first preset time, the microcontroller system is forced to enter a sleep mode to prevent power consumption by an analog block. In another embodiment, when the low-voltage power-on reset voltage is exceeded, but a reset count of the microcontroller system exceeds a preset value within a second preset time, the microcontroller system is also forced to enter the sleep mode to prevent a digital block from continuously loading data, which could lead to battery failure.

Classes IPC  ?

• G06F 1/26 - Alimentation en énergie électrique, p. ex. régulation à cet effet
• G05F 1/569 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p. ex. courant, tension, facteur de puissance à des fins de protection
• H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires

Abrégé

An analog-to-digital converter (ADC) circuit including a programmable gain amplifier (PGA), a buffer, a delta sigma ADC, and a bandwidth control circuit is provided. The PGA is configured to receive and amplify an input signal to generate an amplification signal. The buffer is configured to receive the amplification signal and output a corresponding buffered signal. The delta sigma ADC is configured to receive the amplification signal and the buffered signal, and output a corresponding digital signal. The bandwidth control circuit is configured to generate a first control signal and a second control signal, wherein the first control signal is output to the PGA to control the bandwidth of the PGA, and the second control signal is configured to enable or disable the buffer.

Classes IPC  ?

• H03M 3/00 - Conversion de valeurs analogiques en, ou à partir d'une modulation différentielle

Abrégé

The preferred embodiment of the present disclosure relates to a sound wake-up device and a sound wake-up method, for waking up a functional circuit. The sound wake-up method includes: converting external sound into a sound electrical signal; sampling the sound electrical signal, and converting the sound electrical signal in a time domain into a sound spectrum signal in a frequency domain; obtaining a high-frequency part of the sound spectrum signal and calculating a high-frequency energy of the high-frequency part; obtaining a mid-frequency part of the sound spectrum signal and calculating a mid-frequency energy of the mid-frequency part; obtaining a low-frequency part of the sound spectrum signal and calculating a low-frequency energy of the low-frequency part; and determining whether to wake up the functional circuit based on respective magnitudes of the high-frequency energy, the mid-frequency energy, and the low-frequency energy.

Classes IPC  ?

• G06F 1/3206 - Surveillance d’événements, de dispositifs ou de paramètres initiant un changement de mode d’alimentation
• G06F 1/3296 - Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
• H04R 5/04 - Circuits

Abrégé

The preferred embodiment of the present disclosure relates to a sound output device and an audio data interruption protection method thereof for driving a speaker equipment. The sound output device includes: a First-In-First-Out (FIFO) buffer configured to receive and output audio data; a buffer circuit configured to temporarily store the received audio data; and a pop noise protection device. The pop noise protection device is configured to receive the audio data from the buffer circuit to drive the speaker equipment. When the pop noise protection device receives an underflow notification from the FIFO buffer, the pop noise protection device obtains the last audio data from the buffer circuit and gradually reduces volume of the last audio data to avoid the occurrence of pop noise. This design effectively prevents sudden pops of noise caused by interruptions of the audio data, protecting the speaker equipment and the hearing of users.

Classes IPC  ?

• H04R 3/00 - Circuits pour transducteurs

Abrégé

A pulse generation circuit is provided. The pulse generation circuit includes a reference voltage generator, a pulse generator, a comparator, a voltage regulator, a voltage-controlled oscillator (VCO), and a frequency divider. The reference voltage generator generates a reference signal. The pulse generator generates a pulse signal according to the frequency division signal. The comparator receives and compares the reference signal and the pulse signal to output a comparison signal. When the pulse signal and the reference signal have the same voltage level, the comparator outputs the comparison signal with a low logic level. The voltage regulator receives the comparison signal and the frequency division signal outputs a voltage signal correspondingly. The VCO receives the voltage signal and outputs an oscillation signal correspondingly, and the frequency divider divides the oscillation signal to generate the frequency division signal.

Classes IPC  ?

• H03K 3/0231 - Circuits astables

Abrégé

Embodiments of the present disclosure provide an electronic device. The electronic device includes a memory, a storage device, and a control device. The memory is configured to store a bootloader and an image. The storage device is powered by a battery dedicated to the storage device. The control device is configured to read and execute the bootloader to perform the following operations: determining whether the storage device stores a first hash value of the image; when the storage device stores the first hash value of the image, verifying the first hash value; and when the verification of the first hash value is successful, executing a firmware in the image.

Classes IPC  ?

• H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système

Abrégé

The preferred embodiment of the present disclosure relates to an adaptive power setting and protection method in power transmission and a power supply system using the same. The method includes: providing a power and signal transmission line between a power source and a power sink; providing a corresponding output voltage according to a power request transmitted by the power sink from the power and signal transmission line; detecting an output current by the power source; receiving a feedback voltage from the power sink through the power and signal transmission line; limiting the output current when a ratio of the output current to the feedback voltage exceeds a specification; and increasing the output voltage to perform voltage compensation according to the feedback voltage when the ratio of the output current to the feedback voltage does not exceed the specification.

Classes IPC  ?

• H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries

Abrégé

A system includes a memory and processor. The memory is configured to store a machine learning (ML) model that is trained to estimate values of frequencies added (FA) in sparse input signals that have been derived from respective input audio signals, the sparse input signals being indicative of one or more FA in the corresponding input audio signals. The processor is configured to (i) receive an input audio signal, (ii) derive from the input audio signal a sparse input signal indicative of the FA in the input audio signal, and (iii) estimate the values of the FA in the input audio signal by applying the trained ML model to the sparse input signal.

Classes IPC  ?

• G10L 25/18 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par le type de paramètres extraits les paramètres extraits étant l’information spectrale de chaque sous-bande
• G10L 25/09 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par le type de paramètres extraits les paramètres extraits étant des taux de passage par zéro
• G10L 25/30 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par la technique d’analyse utilisant des réseaux neuronaux
• H04R 3/00 - Circuits pour transducteurs
• H04R 3/04 - Circuits pour transducteurs pour corriger la fréquence de réponse

Abrégé

The preferred embodiment of the present disclosure relates to a decoding method for reducing the influence of noise power signal line and a decoding circuit. The method includes: dividing an analog signal to be decoded into a plurality of levels; performing an edge detection according to the levels to obtain a first edge detection signal; setting the levels which is smaller than a lower level to the lower level and performing the edge detection to obtain the second edge detection signal; setting the levels which is greater than a higher level to the higher level and performing the edge detection to obtain a third edge detection signal; decoding the first, the second, the third edge detection signal to obtain an optimum edge detection signal.

Classes IPC  ?

• H03M 7/30 - CompressionExpansionÉlimination de données inutiles, p. ex. réduction de redondance
• H03H 11/04 - Réseaux sélectifs en fréquence à deux accès
• H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité

Abrégé

A level shifter is provided, including high-voltage side circuit, bias voltage generating circuit, capacitor, and first to fourth N-type transistors (NTs). The high-voltage side circuit is coupled between a voltage source and first and second output terminals. The bias voltage generating circuit provides bias voltage to a first node. The first NT is coupled between the first output terminal and a second node. A control terminal of the first NT is coupled to the first node. The second NT is coupled between the second node and ground. A control terminal of the second NT is coupled to first input terminal. The third and fourth NTs are coupled in series between the second output terminal and the ground. The control terminals of the third and fourth NTs are coupled to second input terminal. The first and second input terminals respectively receive first and second input signals that are phase-inverted.

Classes IPC  ?

• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ

Abrégé

A circuit for battery detection including a power-on reset (POR) block, an analog-to-digital converter (ADC) circuit, a switch circuit, and a logic control circuit is provided. The POR block is coupled to a node and is configured to output an output voltage with logic high level or logic low level when the node has a battery voltage higher or lower than a preset value, respectively. The switch circuit is coupled to the logic control circuit and the ADC circuit. The logic control circuit is coupled to the POR block and is configured to generate a control signal with the logic low level when the output voltage is at the logic low level, so that the switch circuit disconnects the ADC circuit and the node, and the ADC circuit does not read the battery voltage.

Classes IPC  ?

• G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
• G01R 31/364 - Connexions pour bornes de batteries, munies de dispositions de mesure intégrées

Abrégé

A drawing-based unlocking method is provided. The method is implemented by a device. The method includes training a recognition model. The method includes using the recognition model to identify whether a drawing style of a drawing belongs to an owner of the device when receiving the drawing that is input by a user. The method includes unlocking the device when the drawing style belongs to the owner. The method includes not unlocking the device when the drawing style does not belong to the owner.

Classes IPC  ?

• H04M 1/72463 - Interfaces utilisateur spécialement adaptées aux téléphones sans fil ou mobiles avec des moyens permettant d’adapter la fonctionnalité du dispositif dans des circonstances spécifiques pour limiter la fonctionnalité du dispositif
• G06N 3/0464 - Réseaux convolutifs [CNN, ConvNet]
• G06N 3/08 - Méthodes d'apprentissage

Abrégé

The class-D amplifier includes an output driver stage configured to output an output signal at an output node. The class-D amplifier also includes a current sensing circuit coupled to the output node of the output driver stage, and the current sensing circuit may include: a peak detector coupled to the output node of the output driver stage configured to capture a peak value of the output signal, and a current sensor coupled to the peak detector and configured to receive the peak value of the output signal and generate a sense current based on the peak value of the output signal.

Classes IPC  ?

• H03F 3/217 - Amplificateurs de puissance de classe DAmplificateurs à commutation

Abrégé

An electronic device includes an Integrated Circuit (IC) and a package including a die-attach pad for connecting the IC. The IC includes (i) a measurement circuit configured to measure an electrical characteristic of the die-attach pad, and (ii) a security control circuit configured to initiate a responsive action responsively to detecting a deviation of the measured electrical characteristic of the die-attach pad from an initial measurement of the electrical characteristic.

Classes IPC  ?

• G06F 21/87 - Boîtiers fiables ou inviolables par encapsulation, p. ex. de circuits intégrés
• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
• G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures

Abrégé

An integrated circuit formed with interconnected electronic elements includes at least: i) functional elements which perform IC operations; ii) at least one countermeasure (CM) for detecting fault injection attacks upon the IC and outputting an alert signal when a FI attack is detected; and iii) at least one attack emulator which emulates FI attacks on the IC by applying stimuli to the plurality of functional elements in accordance with at least one control signal. An integrated circuit formed with interconnected electronic elements includes at least: i) functional elements which perform IC operations; ii) at least one countermeasure (CM) for detecting fault injection attacks upon the IC and outputting an alert signal when a FI attack is detected; and iii) at least one attack emulator which emulates FI attacks on the IC by applying stimuli to the plurality of functional elements in accordance with at least one control signal. The IC may include other elements such as power supply elements, oscillators, interface elements and so forth.

Classes IPC  ?

• G06F 11/26 - Tests fonctionnels
• G06F 11/00 - Détection d'erreursCorrection d'erreursContrôle de fonctionnement
• G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
• G06F 11/263 - Génération de signaux d'entrée de test, p. ex. vecteurs, formes ou séquences de test

Abrégé

A control chip including a communication interface, a serial interface, and a control logic is provided. The communication interface is configured to receive an access package. The serial interface includes a first pin and a second pin. The first and second pins operate in an alternate function mode. The control logic is coupled to the serial interface. In response to the access package having a read operation code, the control logic uses the first pin to output the read operation code and read information to a slave device and sets the first pin to operate in a general-purpose input-output (GPIO) mode. The slave device provides read data according to the read information. The control logic uses the second pin to receive the read data.

Classes IPC  ?

• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation

Abrégé

An analog-to-digital conversion circuit configured to convert an input voltage into a digital code includes a trigger controller, a comparison circuit, a successive approximation controller, and an initial voltage scanning controller. The trigger controller enables the first enable signal and the second enable signal in sequence. The comparison circuit selects a successive approximation code or a scan code to generate a conversion voltage and compares the conversion voltage with the input voltage to generate a comparison result. The successive approximation controller updates the successive approximation code based on the enabled first enable signal and the comparison result. The initial voltage scanning controller sets the initial value based on the digital code, and updates the scan code based on the enabled second enable signal and the comparison result.

Classes IPC  ?

• H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p. ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
• H03M 1/12 - Convertisseurs analogiques/numériques
• H03M 1/38 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p. ex. du type à approximations successives

Abrégé

When a developer edits a lighting effect file played by single one or multiple light emitting units of a sounding and lighting device, a lighting effect editing device and method provided by the present disclosure enable the developer to simultaneously determine whether playing single one lighting effect file once, playing single one lighting effect file repeatedly, playing a concatenation of multiple lighting effect files once, playing a concatenation of multiple lighting effect files repeatedly, playing a mixture of multiple lighting effect files once, playing multiple lighting effect files simultaneously once, playing multiple lighting effect files simultaneously repeatedly, playing multiple concatenation lighting effect files simultaneously once or playing multiple concatenation lighting effect files simultaneously repeatedly generates a flicker frequency not meeting a predetermined specification. In addition, when there exists the flicker frequency not meeting the predetermined specification, the developer may be notified of a location of a corresponding sampling time point.

Classes IPC  ?

• H05B 47/165 - Commande de la source lumineuse en suivant une séquence programmée pré-assignéeCommande logique [LC]

Abrégé

A secure adder includes a mask generator, a secure carry-lookahead adder, and a verification circuit. The mask generator generates a first mask value, a second mask value, a third mask value, first masked data, and second masked data. The secure carry-lookahead adder performs an operation on the first masked data and the second masked data to generate a sum output according to the first mask value, the second mask value, and the third mask value. The verification circuit includes a secure carry-save adder and a comparator. The secure carry-save adder generates sum data and carry data according to the first mask value, the second mask value, the third mask value, the first masked data, the second masked data, and the sum output. The comparator generates a verification output according to the relationship between the sum data and the carry data.

Classes IPC  ?

• G06F 7/508 - AdditionSoustraction en mode parallèle binaire, c.-à-d. ayant un circuit de maniement de chiffre différent pour chaque position avec génération simultanée de retenue pour plusieurs étages ou propagation simultanée de retenue sur plusieurs étages utilisant des circuits à retenue anticipée
• G06F 7/502 - Semi-additionneursAdditionneurs complets composés de deux semi-additionneurs en cascade

Abrégé

A storage circuit including a memory and a control circuit is provided. The memory includes a memory block and a backup block. The memory block stores a plurality of data sets. The control circuit receives an erase request. In response to the erase request selecting at least one of the data sets, the control circuit erases the backup block, copies all data sets that are not selected by the erase request to the backup block from the memory block, and activates the backup block to replace the memory block. After activating the backup block, the control circuit accesses the backup block in response to an access request pointing to the memory block.

Classes IPC  ?

• G06F 12/02 - Adressage ou affectationRéadressage

Abrégé

An integrated circuit (IC) includes a thermal memory device, a fault injection (FI) detector and a security control circuit. The thermal memory device includes (i) a thermal storage zone and (ii) a heating element configured to heat the thermal storage zone in response to write operations. The FI detector is configured to detect attempts to inject faults into the IC. The security control circuit is configured to perform a write operation to the thermal memory device in response to an attempt detected by the FI detector, to identify a sequence of the attempts that meets a density criterion, by reading the thermal memory device, and initiate a responsive action upon identifying the sequence.

Classes IPC  ?

• G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures

Abrégé

A class-D amplifier includes an output driver stage and a current sensing circuit connected. The current sensing circuit includes: an operational amplifier having a positive input terminal and a negative input terminal; a positive input replica transistor, where a source of the positive input replica transistor is connected to the positive input terminal, a drain and a gate of the positive input replica transistor is connected to the drain and the gate of a first n-type output transistor, respectively; and a negative input replica transistor, where a source of the negative input replica transistor is connected to the negative input terminal, a drain and a gate of the negative input replica transistor is connected to the drain and the gate of the second n-type output transistor, respectively.

Classes IPC  ?

• G01R 19/00 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe
• H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
• H03F 3/217 - Amplificateurs de puissance de classe DAmplificateurs à commutation
• H03F 3/45 - Amplificateurs différentiels

Abrégé

An electronic circuit applied to communication between a controller and a memory array includes a timer and a delay-locked loop. The timer counts a counting time based on a selection signal generated by the controller to generate a first enable signal. The delay-locked loop delays an output clock signal by a delay time based on a clock signal generated by the controller and the first enable signal to generate the delay clock signal. When the controller performs a read operation on the memory array, the memory array outputs the output clock signal and a data signal. The controller samples the data signal using the delay clock signal.

Classes IPC  ?

• H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
• H03K 5/133 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés utilisant une chaîne de dispositifs actifs de retard
• H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge

Abrégé

A charge controller for a buck circuit is illustrated. The charge controller compares a reference voltage and multiple feedback voltages of multiple output voltages to generate multiple comparison signals, wherein a pulse-frequency modulation buck module outputs the output voltages at multiple voltage output terminals through a single inductor and multiple switches, and each of the switches is disposed between the single inductor and the corresponding voltage output terminal. Then, the charge controller determines a charging order of the voltage output terminals based on the comparison signals, and is arranged to generate multiple switching signals and a start signal based on a zero-current detection signal of the single inductor and the charging order, wherein the switching signals are arranged to control the switches, and the start signal is arranged to enable the pulse-frequency modulation buck module to charge one of the voltage output terminals.

Classes IPC  ?

• H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
• H02M 1/088 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques pour la commande simultanée de dispositifs à semi-conducteurs connectés en série ou en parallèle

Abrégé

A memory system including a memory; an encoding management circuit; and a memory access instruction decoding unit is provided. The memory access instruction decoding unit is configured to receive an instruction from a bus, identify a bad block in the memory, determine whether the instruction indicates access to the bad block. When the instruction indicates writing data to the bad block, the memory access instruction decoding unit outputs an address of the bad block and the data to the encoding management circuit to trigger the encoding management circuit to update the encoding management circuit. When the instruction indicates reading the bad block, the memory access instruction decoding unit outputs the address to and trigger the encoding management circuit to output simulation data of the bad block, wherein the encoding management circuit obtains the simulation data based on the address.

Classes IPC  ?

• G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11

Abrégé

A control device includes a storage unit, a key generation unit and a processing unit. The storage unit stores a control device certificate and a programming device certificate. The key generation unit generates a first private key. The key generation unit also generates a first public key according to the first private key. The processing unit receives the control device certificate and the programming device certificate according to the first public key and a device identification code. The processing unit stores the control device certificate and the programming device certificate in the storage unit.

Classes IPC  ?

• H04L 9/14 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité utilisant plusieurs clés ou algorithmes
• H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système

Abrégé

A clock filter system and a clock filter switching method. The clock filter system includes a plurality of clock filters for respectively outputting a plurality of individual clock signals; a bypass circuit for outputting a bypass enable signal; a plurality of clock enable circuits for respectively outputting a plurality of enable signals; a feedback logic circuit for performing an inverse OR (NOR) operation on the bypass enable signal and the plurality of enable signals to generate a feedback signal; a plurality of clock control circuits for respectively generating and outputting a plurality of control signals according to the feedback signal and the plurality of enable signals to respectively control the plurality of individual clock signals to be turned on or turned off. When switching clock filters, a source individual clock signal and a target individual clock signal are controlled to be turned on at different times.

Classes IPC  ?

• H03K 5/125 - Discrimination d'impulsions
• H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON

Abrégé

A control chip including a first processing circuit, a second processing circuit, and a storage circuit. The first processing circuit provides a learning procedure and learning data. The second processing circuit is configured to execute the learning procedure. The storage circuit stores the learning procedure and the learning data. In response to an access request pointing to the learning procedure, the storage circuit determines whether the access request is a correct access request. In response to the access request being a correct access request, the storage circuit provides the learning procedure to the second processing circuit. In response to the access request pointing to the learning data, the storage circuit determines whether the access request is provided from the second processing circuit. In response to the access request being provided from the second processing circuit, the storage circuit provides the learning data to the second processing circuit.

Classes IPC  ?

• G05B 19/042 - Commande à programme autre que la commande numérique, c.-à-d. dans des automatismes à séquence ou dans des automates à logique utilisant des processeurs numériques
• G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
• H10B 20/00 - Dispositifs de mémoire morte [ROM]

Abrégé

A processing circuit is provided. The processing circuit includes an image-providing device, an adjustment device, a resistive memory, and a control circuit. The image-providing device is configured to provide a target image. The adjustment device adjusts the scale of a template image to generate a sample image according to the setting information. The resistive memory includes a storage region and a computation circuit. The storage region stores the target image. The computation circuit computes the sample image and the target image to generate a plurality of computation results. The control circuit finds a matching position that matches the sample image in the target image according to the computation results.

Classes IPC  ?

• G06V 10/75 - Organisation de procédés de l’appariement, p. ex. comparaisons simultanées ou séquentielles des caractéristiques d’images ou de vidéosApproches-approximative-fine, p. ex. approches multi-échellesAppariement de motifs d’image ou de vidéoMesures de proximité dans les espaces de caractéristiques utilisant l’analyse de contexteSélection des dictionnaires
• G06T 3/40 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement
• G06T 7/11 - Découpage basé sur les zones
• H04N 25/772 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des convertisseurs A/N, V/T, V/F, I/T ou I/F

Abrégé

An encryption and decryption device includes a ShiftRow/InvShiftRow unit, a SubBytes/InvSubBytes unit, a dual ShiftRow/InvShiftRow unit, an encoder, a decoder, and a first verification unit. The ShiftRow/InvShiftRow unit performs a row shift/inverse row shift operation on result data to generate an input state array. The subbytes/invsubbytes unit performs a transformation on the input state array to generate an output state array. The dual ShiftRow/InvShiftRow unit performs the row shift/inverse row shift operation on dual output data to generate a dual input state array. The encoder encodes the dual input state to generate encoded data. The decoder decodes the encoded data to generate decoded data. The first verification unit verifies the mapping relationship of the decoded data and the output state array to generate a first verification signal.

Classes IPC  ?

• H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES

Abrégé

A control chip is provided. A storage circuit includes a memory and a control circuit. The memory includes a first region and a second region. The first region stores command streams. The second region stores parameters. The control circuit accesses the memory. A neural-network processing unit (NPU) receives a destination block and performs a destination command stream corresponding to the destination block. In response to the destination command stream pointing to the second region, the control circuit or the NPU determines whether the destination command stream has access authority. In response to the destination command stream not having access authority, the control circuit does not read the second region. In response to the destination command stream having access authority, the control circuit reads the second region and provides the destination parameter stored in the second region to the NPU.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A dual mode power integrated circuit and power converter circuit using the same are disclosed. The power integrated circuit can be used for driving a power converter with high side PMOSFET or NMOSFET, wherein the power integrated circuit includes a high side switch driver circuit which is disposed on the isolated area and a high side power provider circuit is also disposed on the isolated area. When the PMOSFET is adopted on the high side, the source terminal voltage of the PMOSFET is input to the high side power provider circuit for generating the operation voltage of the high side switch driver circuit. When the NMOSFET is adopted on the high side, the bootstrap circuit is adopted.

Classes IPC  ?

• H02M 1/088 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques pour la commande simultanée de dispositifs à semi-conducteurs connectés en série ou en parallèle
• H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
• H03K 17/081 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande

Abrégé

A microcontroller unit (MCU) with a controller area network (CAN) function. The MCU provides a CAN controller for the CAN function, to generate a transmission signal (CANTX) in digital form. The MCU also has a digital signal remapping circuit inside, which remaps the CANTX signal into a first chip output and a second chip output. The MCU has a first pin that outputs the first chip output to drive a differential positive signal line (CANH) of the CAN function. The MCU has a second pin that outputs the second output to drive a differential negative signal line (CANL) of the CAN function.

Classes IPC  ?

• H04L 12/40 - Réseaux à ligne bus

Abrégé

A control device coupled to an oscillator circuit and including a first output circuit, a synchronizer circuit, a hysteresis circuit, a stable circuit, and a second output circuit is provided. The first output circuit activates an oscillator circuit according to an activation signal so that the oscillator circuit generates an input clock. The synchronizer circuit synchronizes the activation signal to generate a synchronization signal. The synchronization signal is synchronized with the input clock. The hysteresis circuit directs the first output circuit to disable the oscillator circuit according to the synchronization signal. The stable circuit enables a transmission signal according to the input clock. When the transmission signal is enabled, the second output circuit uses the input clock as an output clock.

Classes IPC  ?

• H03K 3/014 - Modifications du générateur pour assurer le démarrage des oscillations
• G06F 1/04 - Génération ou distribution de signaux d'horloge ou de signaux dérivés directement de ceux-ci
• H03L 3/00 - Démarrage des générateurs

Abrégé

A switching circuit coupled to a first oscillator circuit and a second oscillator is provided. The first oscillator circuit generates a first clock signal according to a first enable signal. The second oscillator generates a second clock signal according to a second enable signal. The switching circuit uses the first or second clock signal as an output clock according to a detection signal. The switching circuit includes a first D-type flip-flop and a second D-type flip-flop. The first D-type flip-flop includes a first reset terminal receiving the first enable signal. The second D-type flip-flop includes a second reset terminal receiving the second enable signal.

Classes IPC  ?

• G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable

Abrégé

An encryption/decryption device includes a SubBytes/InvSubBytes unit, a MixColumns/InvMixColumns unit, a first verification unit, and a controller. The SubBytes/InvSubBytes unit performs a transformation on the input state array to generate an output state array. The MixColumns/InvMixColumns unit performs a mix column operation/inverse mix column operation on the output state array to generate a mix-column/inverse mix-column array. The mix column operation/inverse mix column operation includes a binary-field multiplication calculation. The first verification unit determines whether the output state array and the mix-column/inverse mix-column array meet a mapping relationship to generate a verification signal. The controller determines whether the binary field multiplication calculation performed by the MixColumns/InvMixColumns unit is correct based on the first verification signal.

Classes IPC  ?

• G06F 17/16 - Calcul de matrice ou de vecteur

Abrégé

A method for reducing influence of noise on a signal line, a decoding circuit and a power provider are disclosed. The method includes steps of: dividing an analog signal to be decoded into levels; determining the level of the analog signal and acquiring the current level of the analog signal to be decoded to obtain a current level number; updating a highest level variable when the current level number is greater than the highest level variable; updating a lowest level variable when the current level number is smaller than the lowest level variable; and outputting an edge detection pulse and setting the highest level variable and the lowest level variable equal to the current level number when the difference between the highest level variable and the lowest level variable is greater than a noise tolerance value.

Classes IPC  ?

• H03K 5/1252 - Suppression ou limitation du bruit ou des interférences
• H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale la caractéristique étant l'amplitude

Abrégé

A class-D amplifier includes a pulse width modulation (PWM) signal generator configured to generate an input signal, a p-type output transistor and an n-type output transistor connected in series with the p-type output transistor at an output terminal, and an output monitor connected to the output terminal and configured to detect a duty cycle of an output signal at the output terminal. The amplifier includes a pre-driver circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is connected to the PWM signal generator to receive the input signal, the second input terminal is connected to the output monitor to receive the duty cycle, the first output terminal is connected to a gate of the p-type output transistor, and the second output terminal is connected to a gate of the n-type output transistor.

Classes IPC  ?

• H03F 3/217 - Amplificateurs de puissance de classe DAmplificateurs à commutation

Abrégé

A digital DC-DC voltage conversion apparatus is used to convert an input voltage into an output voltage for a digital core circuit and generate an output current for the digital core circuit. The digital DC-DC voltage conversion apparatus includes a direct charging path current supply unit. The direct charging path current supply unit includes a direct charging switch and a direct charging path controller electrically connected to the direct charging switch. A control end of the direct charging switch receives a direct charging switch control signal, and the direct charging path controller generates direct charging switch control signal to control the direct charging switch to generate a direct charging path current to the digital core circuit. In this way, the digital DC-DC voltage conversion apparatus can faster track an operation current of the digital core circuit.

Classes IPC  ?

• G05F 1/59 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de réglage final pour une charge unique

Abrégé

A secure control circuit protects data stored in a memory is provided. A setting circuit provides a first activation signal and protection information. The protection information points to a confidential area of the memory. A processing circuit provides a second activation signal and access information. An arbiter determination circuit determines whether the access information points to the confidential area according to the protection information in response to the first activation signal being in a first level. In response to the second activation signal not being in a specific level and the access information points to the confidential area, the arbiter determination circuit directs an access circuit to access the confidential area. In response to the second activation signal being in the specific level and the access information points to the confidential area, the arbiter determination circuit directs the access circuit to stop accessing the confidential area.

Classes IPC  ?

• G06F 21/76 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits intégrés à application spécifique [ASIC] ou les dispositifs programmables, p. ex. les réseaux de portes programmables [FPGA] ou les circuits logiques programmables [PLD]
• G06F 21/00 - Dispositions de sécurité pour protéger les calculateurs, leurs composants, les programmes ou les données contre une activité non autorisée

Abrégé

A class-D amplifier includes: a p-type output transistor; an n-type output transistor connected in series with the p-type output transistor; and a drive circuit connected to a gate of the p-type output transistor and a gate of the n-type output transistor. The drive circuit receives an input signal, generates a p-type output transistor control signal applied to the gate of the p-type output transistor, and generates an n-type output transistor control signal applied to the gate of the n-type output transistor. When the input signal becomes logic high, the n-type output transistor control signal becomes logic low fast, while the p-type output transistor control signal becomes logic low gradually. When the input signal becomes logic low, the p-type output transistor control signal becomes logic high fast, while the n-type output transistor control signal becomes logic high gradually.

Classes IPC  ?

• H03F 3/217 - Amplificateurs de puissance de classe DAmplificateurs à commutation

Abrégé

The present disclosure provides a power control method for a microcontroller unit (MCU) and a power control system using the same. The power control method includes after a triggering event of switching CPU frequency occurs, controlling, through a power controller, a low dropout linear regulator (LDO) to output a preset voltage and triggering a clock controller to switch a first central processing unit (CPU) frequency; after the clock controller switches the first CPU frequency, counting, through a clock counter, a number of times of occurrence of a CPU clock within a period to obtain a second CPU frequency; and determining, through the power controller, a corresponding voltage of the second CPU frequency and controlling the LDO to output the corresponding voltage.

Classes IPC  ?

• G06F 1/324 - Économie d’énergie caractérisée par l'action entreprise par réduction de la fréquence d’horloge
• G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
• G06F 1/3234 - Économie d’énergie caractérisée par l'action entreprise
• G06F 1/3296 - Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement

Abrégé

A level shifter is disclosed. The input circuit receives an input signal operating within a first voltage range that is defined by a first voltage level. A pull-up circuit is coupled between a second voltage line and the input circuit. The second voltage line supplies a second voltage level. The second voltage level is higher than the first voltage level. A first connection node between the pull-up circuit and the input circuit serves as an output terminal of the level shifter. An acceleration circuit coupled to the first connection node accelerates the low-to-high transition at the output terminal. The acceleration controller for the acceleration circuit includes a first series of pulse generation transistors driven by first driving signals which have time differences therebetween, so that the acceleration controller enables the acceleration circuit in a pulse manner. The first driving signals are derived from the input signal.

Classes IPC  ?

• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
• H03K 19/017 - Modifications pour accélérer la commutation dans les circuits à transistor à effet de champ

Abrégé

An electronic device includes an immutable memory, a counter, and a processor. The immutable memory stores a first public key and a second public key in advance, and the first public key and the second public key are unmodifiable. The counter has an anti-rollback protection and counts a counting value. When the counting value is a first value, the processor selects a first public key corresponding to the first value. When the counting value is a second value, the processor selects the second public key corresponding to the second value. When the counting value is a third value, the processor selects the first public key and the second public key. The first value and the second value are in a first state, and the third value is in a second state, where the first state and the second state are different.

Classes IPC  ?

• H04L 9/40 - Protocoles réseaux de sécurité
• H04L 9/08 - Répartition de clés

Abrégé

A control device includes a first memory, a second memory, a processing circuit and an input-output interface. The first memory stores a secure-bootloader program code. The second memory stores a first specific program code. The processing circuit performs the secure-bootloader program code to execute a first legality verification on the first specific program code. When the first specific program code passes the first legality verification, the processing circuit performs the first specific program code to generate a verification signal. The input-output interface is configured to output the verification signal to an external device and receives a response signal from the external device. The processing circuit executes a second legality verification on the reply signal. When the reply signal does not pass the second legality check, the processing circuit ignores a request from the external device.

Classes IPC  ?

• G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
• G06F 11/36 - Prévention d'erreurs par analyse, par débogage ou par test de logiciel

Abrégé

An encryption device is provided herein, which includes a memory array and a memory control device. The memory array is configured to store lock data. The memory control device determines whether the lock data is equal to a predetermined value according to an operation instruction. When the memory control device determines that the lock data is equal to the predetermined value, the memory control device performs a logic operation on the write data and an output key to generate encrypted write data, and writes the encrypted data into the memory array as ciphertext.

Classes IPC  ?

• G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p. ex. les mémoires adressables directement
• G06F 21/60 - Protection de données
• G06F 21/64 - Protection de l’intégrité des données, p. ex. par sommes de contrôle, certificats ou signatures

Abrégé

A microcontroller circuit including a detection circuit, a storage circuit, an error counter circuit, a comparison circuit, and a processing circuit is provided. The detection circuit enables a trigger signal and outputs error information in response to the occurrence of an error event. The storage circuit stores the error information. The error counter circuit adjusts the count value according to the number of times that the trigger signal is enabled by the detection circuit. The comparison circuit enables an interruption signal in response to the count value reaching a threshold value. The processing circuit performs a specific operation according to the interruption signal.

Classes IPC  ?

• G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
• G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat

Abrégé

A peripheral device including a universal serial bus (USB) interface, a storage circuit, and a command parser is provided. The USB interface is configured to be coupled to an external host and to receive file data from the external host. The file data includes a self-defining command and update data. The storage circuit is configured to store a file allocation table and a root directory. The command parser analyzes the self-defining command to generate an analysis result and operates according to the analysis result. In response to the self-defining command being an update command, the command parser performs an update operation.

Classes IPC  ?

• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
• G06F 13/38 - Transfert d'informations, p. ex. sur un bus

Abrégé

A high-voltage device includes: a diode; a junction field-effect transistor (JFET) adjoining the diode and electrically coupled to the diode; a high-voltage junction termination (HVJT) element electrically connected with the diode and the junction field-effect transistor, wherein the high-voltage junction termination element is a ring shape from top view, and a high-side region and a low-side region are respectively defined inside the ring shape and outside the ring shape; and a first deep well region encircling the high-side region. The first deep well region includes: a first segment disposed in the high-voltage junction termination element; and a second segment disposed in the junction field-effect transistor. The first segment includes a well region and a doped region in the well region. The second segment includes only the well region.

Classes IPC  ?

• H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
• H01L 21/225 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p. ex. une couche d'oxyde dopée
• H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
• H01L 29/861 - Diodes

Abrégé

An LED driving apparatus, a microcontroller, and a control method for an LED module are provided. The LED driving apparatus includes a power supply module, a switch module, and a control module. The power supply module is configured to supply power to the LED module, in which the power supply module determines whether to trigger an overcurrent protection based on whether an output current exceeds a threshold current. The control module is configured to receive an overcurrent detection signal to control a conduction state of the switch module, so as to affect the current amount of the LED module. When the overcurrent detection signal indicates the output current exceeds the threshold current, the control module outputs a first control signal based on the overcurrent detection signal to control the switch module, to prevent the overcurrent protection from being triggered.

Classes IPC  ?

• H05B 45/30 - Circuits de commande
• H05B 45/46 - Détails des circuits de charge à LED avec un contrôle actif à l'intérieur d'une matrice de LED les diodes étant disposées parallèlement
• H05B 45/50 - Circuits pour faire fonctionner des diodes électroluminescentes [LED] réagissant aux dysfonctionnements des LED ou à un comportement indésirable des LEDCircuits pour faire fonctionner des diodes électroluminescentes [LED] sensibles à la vie des LEDCircuits de protection

Abrégé

An attack-detection (A-DET) circuit in an integrated circuit includes a main detector and a spike detection circuit. The main detector is configured to, while activated, detect an abnormal level of a power supply input of the integrated circuit. The spike detection circuit is configured to detect a transition on the power supply input and to send an activation indication to the main detector responsively the detected transition.

Classes IPC  ?

• G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p. ex. pour empêcher l'ingénierie inverse