The application relates to a manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure. The method comprises a step of producing the wafer having a crystal orientation identifier and a certain thickness. The method further comprises a step of thinning the produced wafer from the certain thickness to a desired thickness of the wafer in order to obtain the thinned wafer. The method further comprises a step of providing a surface passivation layer having a certain layer thickness on a front surface of the thinned wafer. The method further comprises a step of polishing the passivation layer from the certain layer thickness to a desired final layer thickness of the passivation layer so that the polished front surface of the wafer enables active layer bonding in order to form the hybrid substrate structure.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
B24B 49/12 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation involving optical means
B24B 51/00 - Arrangements for automatic control of a series of individual steps in grinding a workpiece
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
2.
MANUFACTURE METHOD OF A HIGH-RESISTIVITY SILICON HANDLE WAFER FOR ENABLING A FORMATION OF A HYBRID SUBSTRATE STRUCTURE
A manufacture method (100) of a high-resistivity silicon handle wafer (230) for enabling a formation of a hybrid substrate structure (336). The method comprises producing the wafer (212) having a crystal orientation identifier (210), thinning the produced wafer to obtain a thinned wafer (222), providing a surface passivation layer (229) on a front surface (221) of the thinned wafer, and polishing the passivation layer so that the polished front surface (232) of the wafer enables active layer bonding in order to form the hybrid substrate structure. The step of thinning comprises a controlled single-side, fixed abrasive grinding of the produced, crystal orientation identifier-comprised wafer (218) with a chuck arrangement, which eliminates at least majority of an effect of non-circular asymmetry caused by the identifier, in order to manufacture the wafer with a desired submicron total thickness variation for enabling the formation of the hybrid substrate structure.
The application relates to a high-resistivity silicon substrate (100) with a reduced radio frequency loss for a radio frequency integrated passive device. The sub- strate comprising a bulk zone (110) comprising high-resistivity bulk silicon and a preserved sub-surface lattice damage zone (120b) comprising fractured silicon above the bulk zone. The lattice damage zone is processed into the substrate and the preserved lattice damage zone is configured to achieve the RF loss reduction of the substrate by suppressing a parasitic surface conduction.
b) comprising fractured silicon above the bulk zone. The lattice damage zone is processed into the substrate and the preserved lattice damage zone is configured to achieve the RF loss reduction of the substrate by suppressing a parasitic surface conduction.
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
The invention relates to a method for depositing one or more polycrystalline silicon layers (230c) on a substrate (210) by a chemical vapour deposition in a reactor, which method comprises adjusting a deposition temperature between 605 °C-800 °C in a process chamber of the reactor, and depositing the one or more polycrystalline silicon layers on the substrate by using a silicon source gas comprising SiH4 or SiH2CI2, and a dopant gas comprising BCI3.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
C30B 28/14 - Production of homogeneous polycrystalline material with defined structure directly from the gas state by chemical reaction of reactive gases
An implementation of a Czochralski-type crystal growth has been shown and embodied. More particularly, a furnace with suitable insulation and flow arrangement is shown to improve the cost-efficiency of production of crystals. That is achieved by the shown new hot-zone structure, gas flows and the growth process which can decrease the power consumption, increase the lifetime of hot-zone parts and improve the productivity, e.g., by giving means for opening the hot-zone and easily adapting the hot-zone to a new crystal diameter.
An implementation of a Czochralski-type crystal growth has been shown and embodied. More particularly, a furnace with suitable insulation and flow arrangement is shown to improve the cost-efficiency of production of crystals. That is achieved by the shown new hot-zone structure, gas flows and the growth process which can decrease the power consumption, increase the lifetime of hot-zone parts and improve the productivity, e.g., by giving means for opening the hot-zone and easily adapting the hot-zone to a new crystal diameter.
C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
An implementation of a Czochralski-type crystal growth has been shown and embodied. More particularly, a furnace with suitable insulation and flow arrangement is shown to improve the cost-efficiency of production of crystals. That is achieved by the shown new hot-zone structure, gas flows and the growth process which can decrease the power consumption, increase the lifetime of hot-zone parts and improve the productivity, e.g., by giving means for opening the hot-zone and easily adapting the hot-zone to a new crystal diameter.
It is shown in the invention a method for manufacturing a semiconductor wafer structure with an active layer for impurity removal, which method comprises phases of depositing a first layer on a first wafer surface for providing an active layer, an optional phase of preparation for said first layer for next phase, growing thermal oxide layer on a second wafer, bonding said first and second wafers into a stack, annealing the stack for a crystalline formation in said thermal oxide layer as a second layer, and thinning said first wafer to a pre-determined thickness. The invention concerns also a wafer manufactured according to the method, chip that utilizes such a wafer structure and an electronic device utilizing such a chip.
patents
