Abstract

A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.

IPC Classes  ?

• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
• H10D 84/01 - Manufacture or treatment
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

A semiconductor device includes an insulating structure, a first electrical fuse element, a second electrical fuse element, a first spacer, a second spacer and an epitaxial structure. The insulating structure is disposed in a substrate. The first electrical fuse element and the second electrical fuse element are disposed at two sides of the insulating structure. Each of the first electrical fuse element and the second electrical fuse element includes a semiconductor layer disposed on the substrate and a mask layer disposed on the semiconductor layer. The first spacer partially covers a sidewall of the semiconductor layer of the first electrical fuse element adjacent to the insulating structure. The second spacer partially covers a sidewall of the semiconductor layer of the second electrical fuse element adjacent to the insulating structure. The epitaxial structure is disposed above the insulating structure and electrically connects the two semiconductor layers.

IPC Classes  ?

• H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections

Abstract

A semiconductor device includes a first memory gate, a second memory gate, a select gate and an inner spacer. The first memory gate is disposed on a substrate. The second memory gate is disposed on the substrate. The select gate is disposed on the substrate and between the first memory gate and the second memory gate. The inner spacer is disposed on a side surface of the select gate, in which each of the first memory gate and the second memory gate includes a capping layer disposed at a top end thereof, each of the capping layers has a curved side surface facing the select gate, and a top end of the inner spacer is adjacent to a bottom end of each of the capping layers.

IPC Classes  ?

• H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Abstract

A test method for a wafer is provided. First, data of an optical characteristic of a test key of the wafer is acquired using an optical scatterometer. The wafer has chip areas and a frame area surrounding and separating the chip areas. The test key is disposed in the frame area. Then, the data is compared with corresponding data of a standard sample without a crack, and a difference between the data and the corresponding date is obtained. It is determined that a crack is formed in the test key and a crack condition in the chip areas does not meet a criterion of the wafer when the difference is larger than a tolerance. It is determined that the crack condition in the chip areas meets the criterion of the wafer when the difference is smaller than or equal to the tolerance.

IPC Classes  ?

• G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined
• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

IPC Classes  ?

• H10N 50/80 - Constructional details
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment

Abstract

A semiconductor device includes a first wafer, a second wafer, a dielectric layer and a first metal structure. The first wafer includes a first substrate and a first interconnection layer disposed on the first substrate. The second wafer includes a second substrate and a second interconnection layer. The second substrate includes a buried oxide layer and a semiconductor layer disposed on the buried oxide layer. The second interconnection layer is disposed on the semiconductor layer, in which the second interconnection layer is bonded with the first interconnection layer. The dielectric layer is disposed on the buried oxide layer. The first metal structure is disposed through the dielectric layer, in which an end of the first metal structure physically contacts the buried oxide layer, and the buried oxide layer is grounded through the first metal structure.

IPC Classes  ?

• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 23/498 - Leads on insulating substrates
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

IPC Classes  ?

• H10N 50/80 - Constructional details
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10D 48/40 - Devices controlled by magnetic fields
• H10N 50/01 - Manufacture or treatment
• H10N 50/10 - Magnetoresistive devices

Abstract

A method for fabricating a semiconductor device includes the steps of first forming an active device having a gate structure and a source/drain region on a substrate, forming an interlayer dielectric (ILD) layer on the active device, removing part of the ILD layer to form a contact hole on the active device without exposing the active device and the bottom surface of the contact hole is higher than a top surface of the gate structure, and then forming a metal layer in the contact holt to form a floating contact plug.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

An operation method and an operation device for operating a real-time discussion window are provided. The operation method for operating the real-time discussion window includes the following steps. A discussion topic is obtained from an initiator. A participant candidate list is provided. The participant candidate list includes a plurality of non-player characters. A participant suggestion list is provided from the candidate list according to the discussion topic. At least one of the non-player characters is added into the real-time discussion window according to a selection result of the initiator. At least one relevant technical person is invited into the real-time discussion window. The discussion topic is discussed in the real-time discussion window. A discussion report is automatically generated according to the discussion content in the real-time discussion window.

IPC Classes  ?

• G06Q 10/1093 - Calendar-based scheduling for persons or groups
• G06N 3/0895 - Weakly supervised learning, e.g. semi-supervised or self-supervised learning

Abstract

A method of fabricating a semiconductor device is disclosed. A semiconductor substrate is provided. A high-voltage well and a pre-recessed region are formed in the semiconductor substrate. A drift region is formed in the high-voltage well. A recessed channel region is formed adjacent to the drift region. A heavily doped drain region is formed in the drift region and spaced apart from the recessed channel region. An isolation structure is formed between the recessed channel region and the heavily doped drain region in the drift region. The isolation structure overlaps with the pre-recessed region. A buried gate dielectric layer is formed on the recessed channel region. A top surface of the buried gate dielectric layer is lower than a top surface of the heavily doped drain region. A gate is formed on the buried gate dielectric layer.

IPC Classes  ?

• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 30/01 - Manufacture or treatment
• H10D 30/60 - Insulated-gate field-effect transistors [IGFET]
• H10D 30/65 - Lateral DMOS [LDMOS] FETs
• H10D 64/01 - Manufacture or treatment
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates

Abstract

A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ; forming a passivation layer around the MTJ; forming a second SOT layer on the first SOT layer and the passivation layer; and patterning the second SOT layer and the passivation layer.

IPC Classes  ?

• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment
• H10N 50/80 - Constructional details

Abstract

An HEMT includes a first III-V compound layer, a second III-V compound layer, and a III-V compound cap layer. The second III-V compound layer is disposed on the first III-V compound layer. The III-V compound cap layer covers and contacts the second III-V compound layer. The composition of the III-V compound cap layer and the second III-V compound layer are different from each other. A first opening is disposed in the III-V compound cap layer. A first insulating layer includes two first insulating parts and two second insulating parts. The two first insulating parts cover a top surface of the III-V compound cap layer, and the two second insulating parts respectively contact two sidewalls of the first opening. A second opening is disposed between the two first insulating parts and between the two second insulating parts. A gate electrode is disposed in the second opening.

IPC Classes  ?

• H10D 30/01 - Manufacture or treatment
• H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
• H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs

Abstract

An interposer with an MIM capacitor includes a substrate. A redistribution layer is disposed on the substrate. A first copper pillar, a second copper pillar and a third copper pillar are disposed on the redistribution layer. The first copper pillar and the third copper pillar respectively electrically connect to the redistribution layer. An MIM capacitor covers and contacts the first copper pillar and the second copper pillar. A first bonding bump is disposed directly on the third copper pillar and electrically connects to the third copper pillar. A second bonding bump is disposed directly on the second copper pillar and electrically connects to the MIM capacitor.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/498 - Leads on insulating substrates
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

IPC Classes  ?

• H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
• H10D 1/00 - Resistors, capacitors or inductors
• H10D 1/66 - Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

IPC Classes  ?

• H10N 50/80 - Constructional details
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment
• H10N 50/85 - Materials of the active region

Abstract

A three-dimensional structure with an FD-SOI transistor includes a handler wafer, a first device layer and a second device layer stacked in sequence from bottom to top. The first device layer includes a first SOI layer, a first FD-SOI transistor and a first back gate. The first SOI layer includes a first front side and a first back side. The first FD-SOI transistor is disposed on the first front side. The first back gate is disposed on the first back side. The second device layer includes a second SOI layer, a second FD-SOI transistor and a second back gate. The second SOI layer includes a second front side and a second back side. The second FD-SOI transistor is disposed on the second front side. The second back gate is disposed on the second back side.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 21/764 - Air gaps
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A magnetic memory device includes a substrate, a patterned conductive layer, and a magnetic tunnel junction (MTJ) structure. The substrate includes a memory area and a circuit area. The patterned conductive layer includes a first conductive pattern and a second conductive pattern that are separated from each other. The first conductive pattern is disposed in the memory area, and the second conductive pattern is disposed in the circuit area. The MTJ structure is disposed on the first conductive pattern and electrically contact with the first conductive pattern.

IPC Classes  ?

• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• G01R 33/09 - Magneto-resistive devices
• H10N 50/01 - Manufacture or treatment
• H10N 50/20 - Spin-polarised current-controlled devices
• H10N 50/85 - Materials of the active region

Abstract

The invention provides a laterally diffused metal-oxide-semiconductor (LDMOS), which comprises a substrate, a plurality of fin structures on the substrate, a gate structure on the substrate and spanning the fin structures, and a gate contact layer on the gate structure, wherein the gate contact layer is electrically connected with a dummy contact structure.

IPC Classes  ?

• H10D 30/65 - Lateral DMOS [LDMOS] FETs
• H10D 30/01 - Manufacture or treatment
• H10D 64/00 - Electrodes of devices having potential barriers

Abstract

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a passivation layer around the MTJ, and a second SOT layer on the first SOT layer and the passivation layer. Preferably, the first SOT layer and the second SOT layer are made of same material.

IPC Classes  ?

• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment
• H10N 50/80 - Constructional details

Abstract

Provided are a multiple-level interconnect structure having a scatterometry test layer and a manufacturing method thereof. The multiple level interconnect structure includes a patterned reflective layer, a bulk reflective layer and a patterned test layer. The patterned reflective layer is disposed on a substrate and includes a first reflective pattern and a second reflective pattern separated from each other. The bulk reflective layer is disposed on the patterned reflective layer. The patterned test layer is disposed on the bulk reflective layer.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

An MIM capacitor disposed in a modified dual damascene structure includes a dielectric layer, and a first modified dual damascene structure is disposed in the dielectric layer. The first modified dual damascene structure includes a trench and a hole, and the hole connects to the trench. The hole includes a funnel profile. An MIM capacitor is disposed in the first modified dual damascene structure and a first copper layer is disposed in the first modified dual damascene structure and is located on the MIM capacitor.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A method for forming a semiconductor structure is disclosed. A substrate having a front surface and a rear surface is provided. A plurality of trenches extending into the substrate from the front surface of the substrate is formed. A polishing stop structure is formed at a bottom of each of the plurality of trenches. The plurality of trenches is filled with a gap-filling material layer. The rear surface of the substrate is subjected to a polishing process to remove a portion of the substrate from the rear surface until the polishing stop structure is exposed.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

An automatic calibration method and an automatic calibration equipment for a testing probe set used in a semiconductor process are provided. The automatic calibration method of the test probe set used in the semiconductor manufacturing process includes the following steps. A preliminary correction offset is analyzed according to an empirical needle mark of the test probe set. A relative position between the test probe set and a wafer to be tested are preliminarily adjusted according to the preliminary correction offset. The test probe set is used to perform a test procedure on the wafer to be tested. Whether the offset of the test probe set is within a predetermined specification is determined. If the offset of the test probe set exceeds the predetermined specification, the relative position between the test probe set and the wafer to be tested is further adjusted.

IPC Classes  ?

• G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
• G01R 1/067 - Measuring probes
• G01R 31/319 - Tester hardware, i.e. output processing circuits

Abstract

A semiconductor device includes a semiconductor substrate of a first conductivity type; a well region of the first conductivity type in the semiconductor substrate; and a fin disposed on the semiconductor substrate within the well region. The fin extends along a first direction. The fin includes a first portion and a second portion that is contiguous with the first portion. The first portion includes a counter-doping region having dopants of a second conductivity type. A gate extends over the fin along a second direction. The gate overlaps with the first portion of the fin and does not overlap with the second portion of the fin.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 27/146 - Imager structures
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS

Abstract

The invention provides a semiconductor layout pattern, which comprises a substrate, a plurality of gate metal frames arranged on the substrate, a plurality of source/drain patterns and a plurality of gate patterns extending along an X direction and located in each gate metal frame, and the source/drain patterns and the plurality of gate patterns are alternately arranged along a Y direction, wherein any two adjacent gate metal frames are partially overlapped with each other, and the overlapping part of the two gate metal frames is defined as an overlapping line.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/8234 - MIS technology
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

Abstract

A manufacturing method of an OTP memory capacitor structure is provided. The OTP memory capacitor structure includes a semiconductor substrate, a bottom electrode, a capacitor insulating layer and a metal electrode stack structure. The bottom electrode is provided on the semiconductor substrate. The capacitor insulating layer is provided on the bottom electrode. The metal electrode stack structure includes a metal layer, an insulating sacrificial layer and a capping layer stacked in sequence. The metal layer is provided on the capacitor insulating layer and is used as a top electrode. The insulating sacrificial layer is provided between the metal layer and the capping layer. By the provision of the insulating sacrificial layer, the bottom electrode formed first can be prevented from being damaged by subsequent etching and other processes, so that the OTP memory capacitor structure has better electrical characteristics.

IPC Classes  ?

• H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• H10D 1/00 - Resistors, capacitors or inductors
• H10D 1/68 - Capacitors having no potential barriers

Abstract

A MOS capacitor includes a substrate of a first conductivity type including a fin surrounded by an isolation region. The fin protrudes from a top surface of the isolation region. A counter-doping region of a second conductivity type is disposed in the fin and serves as a first electrode plate of the MOS capacitor. A capacitor dielectric layer covers a sidewall and a top surface of the fin. A metal gate covers the capacitor dielectric layer and serves as a second electrode plate of the MOS capacitor.

IPC Classes  ?

• H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS

Abstract

An interconnect for physically unclonable function (PUF), comprised of multiple arranged PUF cells. Each PUF cell includes at least two L-shaped metal line, wherein each L-shaped metal line includes a first part and a second part and is adjacent to a dummy metal line, and the first part of one L-shaped metal line is electrically connected to adjacent second part of another L-shaped metal line through via in vertical direction.

IPC Classes  ?

• G06F 13/14 - Handling requests for interconnection or transfer

Abstract

A method of forming a semiconductor structure. A memory structure is formed on a substrate in the memory array region. A dielectric layer is deposited over the memory array region and peripheral region to cover the memory structure. A reverse etching process is performed to remove part of the dielectric layer from the central area of the memory array region, thereby forming an upwardly protruding wall structure along perimeter of the memory array region. The remaining thickness of the dielectric layer in the central area is equal to the sum of a polishing buffer thickness and a target thickness. A first polishing process is performed to remove the upwardly protruding wall structure from the memory array region. A second polishing process is performed to remove upper portion of the dielectric layer with the polishing buffer thickness from the memory array region.

IPC Classes  ?

• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

Abstract

A method of forming a semiconductor structure is disclosed. A substrate is provided having a memory array area and a peripheral region. A memory structure is formed on the substrate in the memory array area. A step height is formed between the memory array area and the peripheral region. A dielectric layer is deposited. The dielectric layer covers the memory structure. A reverse etching process is performed to remove part of the dielectric layer from the memory array area, thereby forming an upwardly protruding wall structure along the perimeter of the memory array area, wherein the thickness of the dielectric layer in the memory array area increases from the central area of the memory array area to the periphery of the memory array area. A polishing process is performed on the dielectric layer to remove the upwardly protruding wall structure from the memory array area.

IPC Classes  ?

• H10N 50/01 - Manufacture or treatment
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/80 - Constructional details

Abstract

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.

IPC Classes  ?

• H10D 64/01 - Manufacture or treatment
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/321 - After-treatment
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H10D 30/01 - Manufacture or treatment
• H10D 30/60 - Insulated-gate field-effect transistors [IGFET]
• H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
• H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator

Abstract

Provided is a manufacturing method of an NMOS structure that includes a semiconductor substrate, a dielectric structure, a source/drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.

IPC Classes  ?

• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

IPC Classes  ?

• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
• H01L 21/311 - Etching the insulating layers
• H01L 21/762 - Dielectric regions
• H10D 30/01 - Manufacture or treatment
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 86/01 - Manufacture or treatment
• H10D 89/10 - Integrated device layouts

Abstract

A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.

IPC Classes  ?

• H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment

Abstract

The invention provide an edge structure of a semiconductor wafer, which comprise a first substrate, an edge region and a device region are defined on that first substrate, a first material layer covers a first surface and a side surface of the edge region, and a second material layer covers the first material layer, the cross-sectional structure of the second material layer gradually decreases from the device region to the edge region.

IPC Classes  ?

• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
• H01L 21/3065 - Plasma etchingReactive-ion etching
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A semiconductor structure including a substrate, a pad, a passivation layer, a stress buffer layer, and a bump is provided. The pad is located on the substrate. The passivation layer is located on the substrate. The passivation layer covers a portion of the pad. The stress buffer layer covers the passivation layer. The bump is located on the pad and the stress buffer layer. There is a first recess at an edge of the pad. A bottom surface of the first recess is lower than a top surface of the pad. The stress buffer layer fills the first recess.

IPC Classes  ?

• H01L 23/18 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A high electron mobility transistor includes a channel layer disposed on a substrate, a barrier layer disposed on the channel layer, a gate structure disposed on the barrier layer, a source contact structure and a drain contact structure disposed on the barrier layer at two sides of the gate structure, and extending through the barrier layer to directly contact the channel layer, and a gate contact structure disposed on the gate structure. The source contact structure, the drain contact structure, and the gate contact structure respectively include a liner and a metal layer directly disposed on the liner. The metal layer comprises a metal material doped with a first additive, and a weight percentage of the first additive in the metal layer is between 0% and 2%.

IPC Classes  ?

• H10D 30/01 - Manufacture or treatment
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
• H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs

Abstract

A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

IPC Classes  ?

• H10N 50/10 - Magnetoresistive devices
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/80 - Constructional details
• H10N 50/85 - Materials of the active region

Abstract

A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

IPC Classes  ?

• H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
• H10D 64/01 - Manufacture or treatment
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

A one-time programmable memory structure includes semiconductor substrate of a first conductivity type and a fin disposed on the semiconductor substrate. The fin extends along a first direction, wherein the fin includes a first portion and a second portion that is contiguous with the first portion. The first portion and the second portion have different cross-sectional profiles. A gate extends on the fin along a second direction. The gate partially overlaps the first portion of the fin and partially overlaps the second portion of the fin.

IPC Classes  ?

• H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

An RRAM structure includes an RRAM. The RRAM includes a bottom electrode, a variable resistive layer and a top electrode stacked from bottom to top, wherein the bottom electrode is composed of titanium oxide (TiOx), 0

IPC Classes  ?

• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

A controlling method for semiconductor process auxiliary apparatus, a control assembly and a manufacturing system are provided. The controlling method includes the following steps. At least one manufacturing parameter of a semiconductor manufacturing processing apparatus are obtained. An energy adjusting signal is generated according to the manufacturing parameter. An auxiliary apparatus controlling signal is generated according to the energy adjusting signal. The semiconductor process auxiliary apparatus is controlled according to the semiconductor auxiliary apparatus controlling signal.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

A method for fabricating semiconductor device includes the steps of first providing a substrate having a core region and an input/output (I/O) region and then forming a first metal gate on the core region and a second metal gate on the I/O region. Preferably, the first metal gate includes a first gate dielectric layer, the second metal gate includes a second gate dielectric layer, the first gate dielectric layer and the second gate dielectric layer having different shapes such that the first gate dielectric layer includes an I-shape and the second gate dielectric layer includes a U-shape.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A method for fabricating a semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to the gate structure; performing a first cleaning process; performing a first rapid thermal anneal (RTA) process to remove oxygen cluster in the substrate; forming a metal layer on the source/drain region; and performing a second RTA process to transform the metal layer into a silicide layer.

IPC Classes  ?

• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
• H01L 21/762 - Dielectric regions
• H10D 30/01 - Manufacture or treatment
• H10D 30/60 - Insulated-gate field-effect transistors [IGFET]
• H10D 64/01 - Manufacture or treatment

Abstract

An electronic device including a substrate with a trench and an inductor disposed on the substrate is provided. The inductor includes a first conductive layer and a second conductive layer. The first conductive layer is conformally disposed on the substrate. At least a portion of the first conductive layer is disposed in the trench. The first conductive layer has a first end portion and a second end portion. The second conductive layer is conformally disposed on the first conductive layer. The second conductive layer has a first end portion and a second end portion on the first end portion of the first conductive layer and the second end portion of the first conductive layer, respectively. The first end portion of the second conductive layer is electrically connected with the second end portion of the first conductive layer.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS

Abstract

A FinFET LDMOS device includes a semiconductor substrate; juxtaposed first well and second well in the semiconductor substrate; semiconductor fins extending on the semiconductor substrate along a first direction, the semiconductor fins including a first fin portion in the first well and a second fin portion in the second well; an extra semiconductor body adjoining the first fin portion and the second fin portion and extending along a second direction; a source region on the first fin portion; a drain region on the second fin portion; a gate covering the semiconductor fin and extending along the second direction, wherein the gate partially overlaps the first fin portion and partially overlaps the second fin portion, and the extra semiconductor body is covered by the gate; and a single-diffusion break structure embedded in the second fin portion and between the gate and drain region.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A manufacturing method of a semiconductor device includes the following steps. A III-V compound semiconductor layer is formed on a first device region and a second device region of a substrate. A III-V compound barrier layer is formed on the III-V compound semiconductor layer. A lamination structure is formed on the III-V compound barrier layer. The lamination structure includes a p-type doped III-V compound layer and a first mask layer disposed thereon. A patterning process is performed to the lamination structure. A first portion of the lamination structure located above the first device region is patterned by the patterning process. A second portion of the lamination structure located above the second device region is removed by the patterning process. A thickness of the second portion of the lamination structure is greater than a thickness of the first portion of the lamination structure before the patterning process.

IPC Classes  ?

• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
• H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
• H01L 29/66 - Types of semiconductor device
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

Abstract

A projection system is provided. The projection system includes at least one micro LED line and a scan optical system. The micro LED line is configured for emitting lights with a changing frequency of X times per second. The scan optical system is disposed at a downstream side of the at least one micro LED line. The scan optical system is configured to scan the lights emitted from the micro LED line with a scan rate of M seconds per scan and to project images formed of the lights to corresponding positions on a target projection plane. The projection system has a horizontal resolution of N lines. A total number n of the at least one micro LED line is smaller than N. Also, X=M*(N/n).

IPC Classes  ?

• G02B 26/10 - Scanning systems
• G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light

Abstract

A flash memory structure is provided in the present invention, including an active area and STIs, wherein the diffusion doped region includes a source line doped region extending in a first direction and multiple branch doped regions extending in a second direction at two sides of the source line doped region and alternately arranged along the first direction, and these branch doped regions are isolated by the STIs. An erase gate are on the source line doped region and extends in the first direction, multiple floating gates are on the branch doped regions at two sides of the erase gate, and two word lines respectively at outer sides of the floating gates and extend through multiple branch doped regions in the first direction.

IPC Classes  ?

• H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
• G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout

Abstract

A semiconductor device with a light-shielding layer includes a dielectric layer. A conductive plug penetrates the dielectric layer. A first anode is disposed on a top surface of the dielectric layer and the first anode contacts an end of the conductive plug. A light-shielding layer is embedded in the dielectric layer, wherein the light-shielding layer is located at one side of the conductive plug and a top surface of the light-shielding layer is aligned with the end of the conductive plug. The light-shielding layer includes titanium nitride, silver, aluminum, silicon nitride, silicon carbon nitride or silicon oxynitride. A switching element is electrically connected to the conductive plug.

IPC Classes  ?

• H10K 59/80 - Constructional details
• H10K 71/20 - Changing the shape of the active layer in the devices, e.g. patterning
• H10K 71/60 - Forming conductive regions or layers, e.g. electrodes

Abstract

A method for fabricating a physically unclonable function (PUF) device includes the steps of first providing a PUF cell array having a plurality of unit cells, in which each of the unit cells includes a transistor and a first metal-oxide semiconductor capacitor (MOSCAP) and a second MOSCAP coupled to the transistor. Next, a voltage is transmitted through the transistor to the first MOSCAP and the second MOSCAP and whether the first MOSCAP or the second MOSCAP reaches a breakdown is determined.

IPC Classes  ?

• H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS

Abstract

An embedded flash memory structure, including a semiconductor substrate, an erase gate on the semiconductor substrate, two floating gates respectively at two sides of the erase gate on the semiconductor substrate, two word lines respectively at outer sides of the two floating gates, and two metal control gates respectively on the two floating gates, wherein a sacrificial layer is at at least one side of the metal control gate, and the sacrificial layer is between the metal control gate and the erase gate or between the metal control gate and the word line.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Abstract

A method for fabricating semiconductor device includes the steps of first providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region, forming a first gate structure on the HV region and a second gate structure on the LV region, forming a first lightly doped drain (LDD) adjacent to one side of the first gate structure and a second LDD adjacent to another side of the first gate structure, and then forming a third lightly doped drain (LDD) adjacent to one side of the second gate structure and a fourth LDD adjacent to another side of the second gate structure. Preferably, the first LDD and the second LDD are asymmetrical, the third LDD and the fourth LDD are asymmetrical, and the second LDD and the third LDD are symmetrical.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A semiconductor package includes a RDL interposer having a first surface and a second surface; fanout pads and peripheral pads on the second surface; a first semiconductor die on the first surface and electrically connected to the fanout pads; a molding compound surrounding the first semiconductor die and the first surface of the RDL interposer; through mold vias in the molding compound around the first semiconductor die; peripheral solder bumps within the through mold vias and directly disposed on the peripheral pads; through silicon via pads on the rear surface of the first semiconductor die; a second semiconductor die bonded to the through silicon via pads of the first semiconductor die and the peripheral solder bumps within the through mold vias.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

The invention provides a layout pattern of static random-access memory (SRAM), which comprises a substrate, wherein a plurality of diffusion regions and a plurality of gate structures are located on the substrate to form a plurality of transistors, wherein the plurality of gate structures comprise a first gate structure, which has a stepped shape when viewed from a top view, and the first gate structure spans a first diffusion region and a second diffusion region to form a first access transistor (PG1), wherein the first diffusion region is adjacent to and in direct contact with the second diffusion region.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

A radio-frequency (RF) device includes a gate structure extending along a first direction on a substrate, a source/drain region adjacent to two sides of the gate structure, a shallow trench isolation (STI) around the source/drain region, and a shielding structure extending from the gate structure and overlapping an edge of the STI. The gate structure includes a T-shape, in which the T-shape further includes a vertical portion extending along the first direction and a horizontal portion extending along a second direction. The RF device further includes a body region adjacent to the horizontal portion, in which the body region and the source/drain region have different conductive type.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 23/552 - Protection against radiation, e.g. light

Abstract

The invention provides a capacitor structure with a fin structure, which comprises a fin structure located on a substrate, a lower electrode layer, a high dielectric constant layer and an upper electrode layer stacked on the fin structure in sequence, and an ion doped region located in the substrate below the fin structure, and a top surface of the ion doped region is aligned with a bottom surface of the fin structure.

IPC Classes  ?

• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Abstract

Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first electrode, a second electrode, an insulating layer, a channel layer, a gate dielectric layer, a source electrode and a drain electrode. The first electrode is disposed on a substrate. The second electrode is disposed on the first electrode. The insulating layer is disposed between the first electrode and the second electrode. The channel layer is disposed on the second electrode. The gate dielectric layer is disposed between the channel layer and the second electrode. The source electrode is electrically connected to the first electrode and the channel layer. The drain electrode is electrically connected to the channel layer.

IPC Classes  ?

• H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS
• H01L 29/66 - Types of semiconductor device
• H01L 29/786 - Thin-film transistors

Abstract

The invention provides a layout pattern cell of a static random access memory (SRAM), which at least comprises a first SRAM cell, a plurality of gate structures spanning a plurality of fin structures, so as to form a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first access transistor, a second access transistor, a third access transistor, a fourth access transistor, a first parasitic transistor and a second parasitic transistor located on a substrate, the first parasitic transistor and the first pull-down transistor span the same fin structure, and the fin structure spanned by the first parasitic transistor and the first pull-down transistor is a continuous structure.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices
• G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Abstract

A semiconductor device includes a substrate having a medium-voltage (MV) region and an one time programmable (OTP) capacitor region, a MV device on the MV region, and an OTP capacitor on the OTP capacitor region. Preferably, the MV device includes a first gate dielectric layer on the substrate, a first gate electrode on the first gate dielectric layer, and a shallow trench isolation (STI) adjacent to two sides of the first gate electrode. The OTP capacitor includes a fin-shaped structure on the substrate, a doped region in the fin-shaped structure, a second gate dielectric layer on the doped region, and a second gate electrode on the second gate dielectric layer.

IPC Classes  ?

• H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A semiconductor structure includes a SOI substrate having a device layer and a buried oxide layer contiguous with the device layer; a transistor disposed on the device layer; a dielectric layer surrounding the transistor; an interconnect structure disposed on the dielectric layer and electrically connected to a gate of the transistor; a charge trapping layer contiguous with the buried oxide layer; a capping layer contiguous with the charge trapping layer; and a conductive via penetrating through the capping layer, the charge trapping layer, the buried oxide layer, the device layer, and the dielectric layer. The conductive via is electrically connected to the interconnect structure.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H01L 29/66 - Types of semiconductor device
• H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor

Abstract

A wafer structure includes a substrate having a pre-bonding structure thereon. The pre-bonding structure includes an outer dielectric layer covering a central region of the substrate and a ring-shaped absorbent layer within a ring-shaped peripheral region of the substrate. The ring-shaped absorbent layer is contiguous with the outer dielectric layer.

IPC Classes  ?

• H01L 23/26 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

Provided are a capacitor device and a manufacturing method thereof. The capacitor device includes a first electrode, a second electrode, an insulating layer, a first dielectric layer, a second dielectric layer, a third electrode and a fourth electrode. The first electrode is disposed on a substrate. The second electrode is disposed on the first electrode. The insulating layer is disposed between the first electrode and the second electrode. The first dielectric layer is disposed on the substrate and covers the first electrode, the second electrode and the insulating layer. The second dielectric layer is disposed on the first dielectric layer. The third electrode and the fourth electrode are disposed in the second dielectric layer and separated from each other. The third electrode is electrically connected to the first electrode, and the fourth electrode is electrically connected to the second electrode.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A planarization method includes the following steps. A silicon layer is deposited on a substrate, and a top surface of the silicon layer includes a lower portion and a bump portion protruding upwards from the lower portion. An ion bombardment etching process is performed to the silicon layer for reducing a surface step height of the silicon layer. The top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process. Subsequently, a chemical mechanical polishing process is performed to the post-etching top surface of the silicon layer.

IPC Classes  ?

• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
• H01L 21/321 - After-treatment
• H01L 29/66 - Types of semiconductor device

Abstract

A resistive memory structure including a transistor device and a resistive memory device is provided. The transistor device includes a gate. The resistive memory device is electrically connected to the gate of the transistor device.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

A semiconductor device includes a device layer, an interlayer dielectric layer disposed above the device layer, a first interconnection structure, a second interconnection structure, and a first dielectric layer. The interlayer dielectric layer includes a first portion and a second portion disposed above a first device region and a second device region, respectively. A top surface of the first portion is lower than a top surface of the second portion in a vertical direction. The first interconnection structure includes first conductive lines partly located in the first portion. The second interconnection structure includes second conductive lines located in the second portion. The first dielectric layer is disposed on the first portion, a part of the first dielectric layer is sandwiched between two adjacent first conductive lines, and a bottom surface of the first dielectric layer is lower than the top surface of the second portion in the vertical direction.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A variable resistor and a digital-to-analog converter are provided. The variable resistor includes a main resistor, a plurality of switches, and a plurality of redundancy resistors. The switches are respectively constituted by a plurality of non-volatile memory cells. The switches are coupled to the main resistor. The redundancy resistors are respectively coupled to the main resistor through the switches.

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
• H01C 10/50 - Adjustable resistors structurally combined with switching arrangement

Abstract

Provided are a memory structure and a manufacturing method thereof. The memory structure includes first and second gates, a dielectric hump, a first spacer, a charge storage layer, a gate dielectric layer, a high-k layer and doped regions. The first and the second gates are disposed on a substrate. The dielectric hump is disposed on the substrate between the first gate and the second gate. The first spacer is disposed on a sidewall of the dielectric hump. The charge storage layer is disposed between the first gate and the substrate. The gate dielectric layer is disposed between the second gate and the substrate. The high-k layer is disposed between the first gate and the charge storage layer and between the second gate and the gate dielectric layer. The doped regions are disposed in the substrate at two sides of the first gate and at two sides of the second gate.

IPC Classes  ?

• H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Abstract

A memory device includes a first memory cell, a second memory cell, a word line, a bit line, a first source line and a second source line. The first memory cell includes a control terminal, a data terminal and a source terminal. The first memory cell includes a control terminal, a data terminal and a source terminal. The word line is coupled to the control terminal of the first memory cell and the control terminal of the second memory cell. The bit line is coupled to the data terminal of the first memory cell and the data terminal of the second memory cell. The first source line is coupled to the source terminal of the first memory cell for receiving a first source voltage. The second source line is coupled to the source terminal of the second memory cell for receiving a second source voltage.

IPC Classes  ?

• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

Abstract

An MRAM structure includes a first memory unit and a second memory unit. A conductive line is disposed between the first memory unit and the second memory unit. An SOT metal conductive line contacts and electrically connects an end of the first memory unit, an end of the conductive line and an end of the second memory unit. A first switch element is electrically connected to an end of the SOT metal conductive line, and a second switch element is electrically connected to the other end of the SOT metal conductive line. A third switch element is electrically connected to the other end of the first memory unit. A fourth switch element is electrically connected to the other end of the conductive line. A fifth switch element is electrically connected to the other end of the second memory unit.

IPC Classes  ?

• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• H10N 50/01 - Manufacture or treatment
• H10N 50/20 - Spin-polarised current-controlled devices
• H10N 50/85 - Materials of the active region

Abstract

An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A semiconductor device includes a resistive random access memory (RRAM) device, a dual damascene structure, and a spacer. The dual damascene structure is disposed near the RRAM device, and the spacer is disposed in a sidewall of the RRAM device. The RRAM device includes a lower electrode, a metal oxide layer, and an upper electrode. The metal oxide layer is disposed on the lower electrode, and the upper electrode is disposed on the metal oxide layer. The dual damascene structure includes a via and a wire disposed on the via, in which a top part of the wire is coplanar with a top part of the upper electrode in the RRAM device.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure

Abstract

A semiconductor device includes an aluminum (Al) pad on a substrate, a wire bonded onto the Al pad, a cobalt (Co) layer between and directly contacting the Al pad and the wire, and a Co—Pd alloy on the Al pad and divide the Co layer into a first portion, a second portion, and a third portion. Preferably, the wire includes a copper (Cu) wire and a palladium (Pd) layer coated on the Cu wire.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a buffer layer on the substrate, forming a mesa isolation on the HEMT region, forming a HEMT on the mesa isolation, and then forming a capacitor on the capacitor region. Preferably, a bottom electrode of the capacitor contacts the buffer layer directly.

IPC Classes  ?

• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/66 - Types of semiconductor device

Abstract

A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

IPC Classes  ?

• H01L 21/8234 - MIS technology
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

IPC Classes  ?

• H10N 50/10 - Magnetoresistive devices
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment
• H10N 50/80 - Constructional details
• H10N 50/85 - Materials of the active region

Abstract

A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

IPC Classes  ?

• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment
• H10N 50/80 - Constructional details

Abstract

Provided are a memory structure and a manufacturing method thereof. The memory structure includes a substrate having first and second regions, first and second isolation structures in the substrate, a charge storage layer on the substrate, first and second gates and doped regions. The first isolation structures define first active areas in the first region. A top surface of the first isolation structure is higher than that of the substrate. The second isolation structures define second active areas in the second region. A top surface of the second isolation structure is lower than that of the substrate. The first gate is on the charge storage layer in the first active area. The second gate is on the charge storage layer in the second active area. The doped regions are in the substrate at two sides of the first gate and at two sides of the second gate.

IPC Classes  ?

• H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Abstract

A method for fabricating a radio-frequency (RF) device includes the steps of first providing a substrate comprising a core region and a non-core region, forming a shallow trench isolation (STI) in the substrate between the core region and the non-core region, forming a first gate oxide layer on the core region and the non-core region, forming a patterned mask on the non-core region and the STI, removing the first gate oxide layer on the core region, and then forming a second gate oxide layer on the core region.

IPC Classes  ?

• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• H01L 21/8234 - MIS technology
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

The invention provides a semiconductor structure, which comprises a first chip and a second chip attached to each other, wherein the first chip comprises a quantum dot pattern, and the second chip comprises a through silicon via (TSV), wherein the quantum dot pattern and the through silicon via are aligned with each other.

IPC Classes  ?

• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

IPC Classes  ?

• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/10 - Magnetoresistive devices
• H10N 50/80 - Constructional details

Abstract

A semiconductor structure includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a first passivation layer on the insulating layer, a contact structure disposed on the first passivation layer and extending through the first passivation layer to directly contact a portion of the barrier layer, and an insulating layer interposed between the barrier layer and the first passivation layer and comprising an extending portion protruding toward a bottom corner of the contact structure.

IPC Classes  ?

• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
• H01L 21/311 - Etching the insulating layers
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/66 - Types of semiconductor device

Abstract

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.

IPC Classes  ?

• H10N 50/80 - Constructional details
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment
• H10N 50/85 - Materials of the active region

Abstract

The invention provides a metal oxide semiconductor (MOS) capacitor structure, which includes a counter-doping region in the channel region directly below the gate. Between the deep ion well and the counter-doping region is a semiconductor region. The doping concentration of the semiconductor region is lower than that of the deep ion well. The P-type well ion implantation processes in the active region of the device can be omitted, so the production cost is lower, and the dosage of the counter-doping region can be reduced, which improves the time-dependent dielectric collapse (TDDB) issue.

IPC Classes  ?

• H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

The invention provides an exposure method of semiconductor patterns, which comprises the following steps: providing a substrate, performing a first exposure step with a first photomask, forming a first pattern in a first region on the substrate, and performing a second exposure step with a second photomask, forming a second pattern in a second region on the substrate, the first pattern and the second pattern are in contact with each other, and at an interface of the first region And the second region, the first pattern and the second pattern are aligned with each other.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers

Abstract

An ESD guard ring structure includes numerous first fin structures, numerous second fin structures, numerous first polysilicon conductive lines, numerous second polysilicon conductive lines, numerous third polysilicon conductive lines and numerous single diffusion breaks. Each of the first fin structures includes at least one single diffusion break therein. Each of the single diffusion breaks overlaps one of the third polysilicon conductive lines.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A semiconductor device includes a first fin-shaped structure and a second fin-shaped structure on a substrate, a bump between the first fin-shaped structure and the second fin-shaped structure, a first recess between the first fin-shaped structure and the bump, and a second recess between the second fin-shaped structure and the bump. Preferably, a top surface of the bump includes a curve concave upward, a width of the bump is greater than twice the width of the first fin-shaped structure, and a height of the bump is less than one fourth of the height of the first fin-shaped structure.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 21/8234 - MIS technology
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A semiconductor device includes a substrate; a first well region disposed in the substrate and with a first electrical property; a second well region with the first electrical property disposed in the substrate and separated from the first well region; a first gate dielectric layer disposed on the first well region and having a first thickness; a second gate dielectric layer, disposed on the second well region, separated from the first gate dielectric layer and having a second thickness less than the first thickness; a first gate electrode disposed on the first gate dielectric layer; a second gate electrode disposed on the second gate dielectric layer and separated from the first gate electrode; a drain region disposed in the first well region; and a source region disposed in the second well region.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/40 - Electrodes
• H01L 29/66 - Types of semiconductor device

Abstract

A manufacturing method of the semiconductor structure including the following is provided. Gate structures are formed on a substrate. Each gate structure includes a gate, a first spacer, and a second spacer. The gate is disposed on the substrate. The first spacer is disposed on a sidewall of the gate. The second spacer is disposed on the first spacer. In a region between two adjacent gate structures, the first spacers are separated from each other, and the second spacers are separated from each other. A protective layer is formed between the two adjacent gate structures. The protective layer covers lower portions of the second spacers and exposes upper portions of the second spacers. A part of the upper portions of the second spacers is removed using the protective layer as a mask to enlarge a distance between the upper portions of the second spacers. The protective layer is removed.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 21/8234 - MIS technology
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/40 - Electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

IPC Classes  ?

• G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

A semiconductor device includes a gate structure on a substrate, a source/drain region adjacent to the gate structure, an interlayer dielectric (ILD) layer around the gate structure, a contact plug in the ILD layer and adjacent to the gate structure, an air gap around the contact plug, a barrier layer on and sealing the air gap, a metal layer on the barrier layer, a stop layer adjacent to the barrier layer and on the ILD layer, and an inter-metal dielectric (IMD) layer on the ILD layer. Preferably, bottom surfaces of the barrier layer and the stop layer are coplanar and top surfaces of the IMD layer and the barrier layer are coplanar.

IPC Classes  ?

• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 29/40 - Electrodes
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

IPC Classes  ?

• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 29/40 - Electrodes
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

IPC Classes  ?

• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 29/40 - Electrodes
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A random access memory, including a first gate crossing over a first doped region to constitute a write transistor, a second gate crossing over a second doped region to constitute a first read transistor, a third gate crossing over the first doped region and the second doped region to constitute a second read transistor, a metal bridge electrically connected to the second gate and the third gate, and a junction of the first source, the second gate and the third gate is a storage node.

IPC Classes  ?

• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• G11C 11/408 - Address circuits
• G11C 11/4094 - Bit-line management or control circuits

Abstract

A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a contact etch stop layer (CESL) adjacent to the metal gate, and an interlayer dielectric (ILD) layer around the gate structure, performing a first etching process to remove the ILD layer, performing a second etching process to remove the CESL for forming a first contact hole, and then forming a first contact plug in the first contact hole. Preferably, a width of the first contact plug adjacent to the CESL is less than a width of the first contact plug under the CESL.

IPC Classes  ?

• H01L 29/40 - Electrodes
• H01L 21/311 - Etching the insulating layers
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

Abstract

A resistive random access memory device includes a substrate; a dielectric layer disposed on the substrate; a conductive via disposed in the dielectric layer; a metal nitride layer disposed on the conductive via, wherein the metal nitride has a gradient nitrogen concentration along a thickness direction of the metal nitride layer; a resistive switching layer disposed on the metal nitride layer; and a metal oxynitride layer disposed on the resistive switching layer, wherein the metal oxynitride layer has a gradient nitrogen concentration along a thickness direction of the metal oxynitride layer.

IPC Classes  ?

• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

A manufacturing method of a semiconductor structure includes the following steps. A first wafer is provided. The first wafer includes a first substrate and a first device layer. A second wafer is provided. The second wafer includes a second substrate and a second device layer. The second device layer is bonded to the first device layer. An edge trimming process is performed on the first wafer and the second wafer to expose a first upper surface of the first substrate and a second upper surface of the first substrate and to form a damaged region in the first substrate below the first upper surface and the second upper surface. The second upper surface is higher than the first upper surface. A first photoresist layer is formed. The first photoresist layer is located on the second wafer and the second upper surface and exposes the first upper surface and the damaged region. The damaged region is removed by using the first photoresist layer as a mask. The first photoresist layer is removed.

IPC Classes  ?

• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/762 - Dielectric regions

Abstract

A semiconductor includes a substrate. A gate structure is disposed on the substrate. A liner oxide contacts a side of the gate structure. A silicon oxide spacer contacts the liner oxide. An end of the silicon oxide spacer forms a kink profile. A silicon nitride spacer contacts the silicon oxide spacer and a tail of the silicon nitride spacer covers part of the kink profile. A stressor covers the silicon nitride spacer and the substrate.

IPC Classes  ?

• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/45 - Ohmic electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A TSV structure includes a substrate. A through via penetrates the substrate. A copper layer fills the through via. A trench is embedded in the substrate and surrounds the copper layer, and a material layer fills the trench. The material layer includes W, Cr, Ir, Re, Zr, SiOC glass, hydrogen-containing silicon oxynitride, silicon oxide or spin-on glass.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for