Micron Technology, Inc.

United States of America

New patents and trademarks in the last week

Last updated : 2026-07-18

Summary

Patents

Trademarks
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trademarks


patents

# ID Jurisdiction Title
1 19431903 TECHNIQUES FOR BIT LINE CONTACT ACTIVE AREA REDUCTION
2 19406941 APPARATUS WITH THERMAL DISTRIBUTION NETWORK AND METHODS FOR OPERATING THE SAME
3 19563337 MANAGING NAMESPACE MAPPING IN A MEMORY SUB-SYSTEM
4 19018808 WORKLOAD ADAPTIVE L2P TABLE DEALLOCATION
5 19564823 ON-DIE CAPACITOR BANKS
6 19437898 EFFICIENT READ DISTURB SCANNING
7 19020698 PEC-BASED DIE READ LEVEL READ OFFSET
8 19435556 ERROR CONTROL FOR COMPRESSED AND UNCOMPRESSED REGIONS OF MEMORY
9 19443154 MANAGING ERROR CONTROL INFORMATION USING A REGISTER
10 19562552 BLOCK REPLACEMENT USING COMBINED BLOCKS
11 19561233 DUAL INTERFACE HIGH-SPEED MEMORY SUBSYSTEM
12 19016025 VERIFICATION OF MODIFIED DIRTY PAGE BITMAP
13 19020524 BOUNDARY OFFSET CONTROL FOR MEMORY BLOCK READING
14 19437819 SUB-CHANNEL SWITCHING USING REDUNDANT PINS
15 19559574 SELF-CALIBRATION IN A MEMORY DEVICE
16 19426044 PROGRAMMABLE NEAR MEMORY PROCESSING ENGINE FOR A MANAGED MEMORY SYSTEM
17 19444929 SEQUENTIALIZING DATA OF A MEMORY SYSTEM
18 19020595 EMBEDDED SILICON GERMANIUM WITH IMPLANT THROUGH SPACER FLOW
19 19550912 ADAPTIVE TEMPERATURE COMPENSATION FOR A MEMORY DEVICE
20 US2026010494 SELECTIVE BLOCK RETIREMENT FOR A MEMORY DEVICE
21 19015993 Performing Serialized Update Procedures during a Refresh Period
22 19416558 CROSS MEMORY PLANE DATA BUFFER TRANSFER
23 19437828 ACCESSING DUMMY WORD LINES USING A THROUGH-SILICON VIA
24 19561360 MANAGING NAMESPACE MAPPING, TRUSTED COMPUTING GROUP RANGES, AND ENCRYPTIONS IN A MEMORY SUB-SYSTEM
25 19564865 READ OPERATIONS WITH OFFSET FOR SLOW CHARGE LOSS
26 19020653 ENHANCED STATUS POLLING FOR MEMORY DEVICES
27 19022632 MEMORY DEVICE INCLUDING SPLIT MEMORY CELLS
28 19415261 3D DRAM WITH CMOS-BASED SECONDARY MEMORY
29 19394726 INCREASED ACTIVE AREA FOR SEMICONDUCTOR PILLARS
30 19431768 ERROR CORRECTION CODE COVERAGE EXTENSION IN A MEMORY SYSTEM
31 19413144 METHODS, SYSTEMS, AND APPARATUSES TO OUTPUT DATA FROM A MEMORY DEVICE
32 19444021 MULTI-TIER CACHE FOR A MEMORY SYSTEM
33 19563442 DIELECTRIC INTERPOSER WITH ELECTRICAL-CONNECTION CUT-IN
34 19444040 MANUFACTURING A CHARGE TRAP MEMORY SYSTEM
35 19436964 TECHNIQUES FOR CONCURRENTLY-FORMED CAVITIES IN THREE-DIMENSIONAL MEMORY ARRAYS
36 19431843 CHARGE TRAPPING FLASH NOR MEMORY IN MEMORY SYSTEMS
37 19559711 PAGE REQUEST INTERFACE SUPPORT IN HANDLING POINTER FETCH WITH CACHING HOST MEMORY ADDRESS TRANSLATION DATA
38 US2026010288 CHARGE TRAPPING FLASH NOR MEMORY IN MEMORY SYSTEMS
39 US2026010244 MICROELECTRONIC DEVICES HAVING SPLIT SOURCE DESIGNS, AND RELATED METHODS AND ELECTRONIC SYSTEMS
40 US2026010160 ALLOCATION OF MEMORY FROM A MEMORY SPACE OF A MEMORY SUB-SYSTEM TO ACCESS A STORAGE SPACE OF THE MEMORY SUB-SYSTEM
41 US2026010164 RELEASE OF RESOURCES ALLOCATED AND/OR USED IN ACCESSING A STORAGE SPACE OF A MEMORY SUB-SYSTEM