Micron Technology, Inc.

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Nouveaux brevets et marques déposées la semaine dernière

Dernière mise à jour : 2026-07-11

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brevets

# ID Juridiction Title
1 19342194 Conductive Interconnects and Methods of Forming Conductive Interconnects
2 19013783 MEMORY DEVICE RELIABILITY VIA READ NOISE CANCELLATION
3 19553101 SYSTEM FOR HANDLING REPEATED PROGRAMMING ERRORS
4 19412543 MEMORY WRITE PERFORMANCE TECHNIQUES
5 19552422 MEMORY APPARATUS FOR PROVIDING RELIABILITY, AVAILABILITY, AND SERVICEABILITY
6 19015070 Release of Resources Allocated and/or Used in Accessing a Storage Space of a Memory Sub-System
7 19558309 VIRTUAL MACHINE REGISTER IN A COMPUTER PROCESSOR
8 19550828 PROGRAM VERIFY COMPENSATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK
9 19559814 RELIABILITY GAIN IN MEMORY DEVICES WITH ADAPTIVELY SELECTED ERASE POLICIES
10 19012432 PROGRAM PULSE OVERDRIVE FOR PERFORMANCE GAIN IN A MEMORY DEVICE
11 19555235 MEMORY MITIGATING SCL AFFECTS DURING POWER-ON
12 19550176 FILLING CRACKS ON A SUBSTRATE VIA
13 19416620 THREE-DIMENSIONAL DYNAMIC RAM WORD LINE COMB STRUCTURE
14 19552585 ENHANCED ERROR HANDLING IN MEMORY SYSTEMS
15 19407737 COLD MEMORY TRACKING FOR POWER SAVING ON CXL DEVICES
16 19015283 HEALTH SCAN OF A MEMORY DEVICE USING A CODE WORD ERROR RATE MACHINE LEARNING MODEL
17 19015038 Allocation of Memory from a Memory Space of a Memory Sub-System in Response to a Request to Access a Storage Space of the Memory Sub-System
18 19552797 Integrated Assemblies and Methods of Forming Integrated Assemblies
19 19015000 Allocation of Memory from a Memory Space of a Memory Sub-System to Access a Storage Space of the Memory Sub-System
20 19010503 METHODS OF MANUFACTURING AN ELECTRONIC CIRCUIT HAVING AIR GAPS BETWEEN CONDUCTIVE LINES
21 19407781 OFF-DIE ERROR CORRECTION FOR MEMORY DEVICES
22 19557559 APPARATUSES, SYSTEMS, AND METHODS FOR STORING ERROR INFORMATION AND PROVIDING RECOMMENDATIONS BASED ON SAME
23 US2025061850 SHARDED CHECKPOINTING USING NON-VOLATILE MEMORY (NVM) DIES IN CACHE ON COMPUTE DEVICE
24 US2025061429 DEDICATED CHANNELS FOR DATA TRANSMISSION
25 US2025060024 MEMORY SUB-SYSTEM OPERABLE WITH MULTIPLE CONNECTIONS FOR CONCURRENT STORAGE ACCESS COMMUNICATIONS AND MEMORY ACCESS COMMUNICATIONS
26 US2025060023 MEMORY SUB-SYSTEM HAVING A CONNECTION TO A HOST SYSTEM FOR STORAGE SPACE ACCESS AND FOR MEMORY SPACE ACCESS
27 US2025060022 ACCESSING A STORAGE SPACE OF A MEMORY SUB-SYSTEM VIA A MEMORY SPACE OF THE MEMORY SUB-SYSTEM
28 US2025061736 COMBINED NON-VOLATILE MEMORY (NVM) AND DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICE
29 US2025061752 TRAFFIC LOAD MANAGEMENT BETWEEN HIGH-BANDWIDTH MEMORY (HBM) AND NON-VOLATILE MEMORY (NVM) ON A SINGLE DIE
30 US2025061755 PREFETCHING AND CACHING BETWEEN HIGH BANDWIDTH MEMORY (HBM) AND NON-VOLATILE (NVM) CACHE ON PROCESSING DIE
31 US2025060228 VERTICAL THREE-DIMENSIONAL (3D) DRAM ARRAY WITH DIGITLINE SELECT CIRCUITRY
32 19557706 READ PASS VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
33 19557003 MULTIPLE WRITE PROGRAMMING FOR A SEGMENT OF A MEMORY DEVICE
34 19559218 OPTIMIZING DATABASE CURSOR OPERATIONS IN KEY-VALUE STORES
35 19558951 VERTICAL DIGIT LINES FOR SEMICONDUCTOR DEVICES
36 19560813 ERROR CONTROL IN MEMORY SYSTEMS USING COMBINATIONAL CIRCUITS
37 19554376 SEMICONDUCTOR DEVICE CIRCUITRY FORMED FROM REMOTE RESERVOIRS
38 19554136 MEMORY APPARATUS AND METHODS INCLUDING MERGED PROCESS FOR MEMORY CELL PILLAR AND SOURCE STRUCTURE
39 19012629 SELECTIVE BLOCK RETIREMENT FOR A MEMORY DEVICE
40 19557635 BLOOM FILTER INTEGRATION INTO A CONTROLLER
41 19556929 CONCURRENTLY WRITING LESS-DENSELY-PROGRAMMED AND MORE-DENSELY-PROGRAMMED MEMORY WITHOUT ADDITIONAL HARDWARE
42 19414032 MICROELECTRONIC DEVICES HAVING SPLIT SOURCE DESIGNS, AND RELATED METHODS AND ELECTRONIC SYSTEMS
43 19559152 SLOW CHARGE LOSS MONITOR FOR POWER UP PERFORMANCE BOOSTING
44 19436915 TECHNIQUES TO CONFIGURE ZONAL ARCHITECTURES OF MEMORY SYSTEMS
45 19406471 TECHNIQUES FOR EFFICIENTLY HANDLING MISALIGNED SEQUENTIAL READS
46 19550900 BALANCING WEAR ACROSS MULTIPLE RECLAIM GROUPS
47 19392470 BIT CONTACT LANDING AREA
48 19392464 MULTIPLE PASS TRAINING PROCEDURES
49 US2025061431 BUFFER CHIP FOR ROUTING COMMAND/ADDRESS AND DATA SIGNALS TO A STACK OF MEMORY DIES WITHIN A MEMORY SYSTEM
50 US2025061432 THERMAL DISTRIBUTION IN COUPLED SEMICONDUCTOR SYSTEMS
51 US2025061873 SELECTIVELY ENABLING NON-VOLATILE MEMORY (NVM) DIES IN CACHE ON COMPUTE DEVICE
52 US2025061741 ADDRESS TRANSLATION FOR COMBINED NON-VOLATILE MEMORY (NVM) AND DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICE
53 US2025061747 DIRECT TRANSFER BETWEEN INTERNAL MEMORY AND EXTERNAL MEMORY
54 US2025061521 MECHANISMS OF DATA TRANSFER BETWEEN VOLATILE MEMORY AND NON-VOLATILE MEMORY IN A HYBRID COMPUTE DEVICE
55 US2025061522 DEDICATED INTERFACE FOR FOLDING DATA FROM VOLATILE MEMORY (VM) DIES TO STACKED NON-VOLATILE MEMORY (NVM) DIE