|
2025
|
Invention
|
Logging guest physical address for memory access faults.
Systems and methods are disclosed for l... |
|
|
Invention
|
Transfer buffer between a scalar pipeline and vector pipeline.
Systems and methods are disclosed... |
|
|
Invention
|
Using renamed registers to support multiple vset{i}vl{i} instructions.
A method for renaming arc... |
|
|
Invention
|
Bundling and dynamic allocation of register blocks for vector instructions.
Apparatus and method... |
|
|
Invention
|
Tracking of store operations.
Apparatus and methods for tracking sub-micro-operations and groups... |
|
|
Invention
|
Concurrent support for multiple cache inclusivity schemes using low priority evict operations.
S... |
|
|
Invention
|
Dependency tracking and chaining for vector instructions.
Apparatus and methods for dependency t... |
|
|
Invention
|
Eviction operations based on eviction message types of different priorities.
An agent may be con... |
|
|
Invention
|
Memory protection for gather-scatter operations.
Systems and methods are disclosed for memory pr... |
|
|
Invention
|
Orderability of operations.
A method for managing orders of operations between one or more clien... |
|
|
Invention
|
Address boundary functions for physical and localized addresses.
An integrated circuit for trans... |
|
|
Invention
|
Canceling prefetch of cache blocks based on an address and a bit field.
Prefetch circuitry may b... |
|
2024
|
Invention
|
Downgrading a permission associated with data stored in a cache.
Cache circuitry may be configur... |
|
|
Invention
|
Integrated circuit design using metadata.
An integrated circuit design may be generated for an i... |
|
|
Invention
|
Integrated circuit design verification with module swapping.
An integrated circuit design may be... |
|
|
Invention
|
Selectable and hierarchical power management.
Described are systems and methods for power manage... |
|
|
Invention
|
Combining data channels to determine camera pose. A system can include a memory and a processing ... |
|
|
Invention
|
Prefetcher with out-of-order filtered prefetcher training queue.
Described is a system and metho... |
|
|
Invention
|
Cycle accurate tracing of vector instructions.
Systems and methods are disclosed for cycle accur... |
|
|
Invention
|
Page table entry caches with multiple tag lengths.
Systems and methods are disclosed for page ta... |
|
|
Invention
|
Integrated circuit generation with improved interconnect.
Disclosed are systems and methods that... |
|
|
Invention
|
Configuring a prefetcher associated with a processor core.
Disclosed are systems and methods for... |
|
|
Invention
|
Integrated circuit generation with composable interconnect.
Disclosed are systems and methods th... |
|
|
Invention
|
Store-to-load forwarding for processor pipelines.
Systems and methods are disclosed for store-to... |
|
|
Invention
|
Systems and methods for clock gating. Described are systems and methods for clock gating componen... |
|
|
Invention
|
Hybrid fixed-point and floating-point computations for improved neural network accuracy.
Systems... |
|
|
Invention
|
Window-based control for instruction issue in an out-of-order processor. A window-based constrain... |
|
|
Invention
|
Quad narrowing operation.
Systems and methods are disclosed for implementing a quad narrowing op... |
|
|
Invention
|
Event tracing.
Systems and methods are disclosed for debug event tracing. For example, an integr... |
|
|
Invention
|
Integrated circuit design with protection based on protected declaration and annotation.
The pre... |
|
|
Invention
|
Macro-op fusion for pipelined architectures.
Systems and methods are disclosed for macro-op fusi... |
|
|
Invention
|
Integrated circuit design verification with object model.
Test verification code generation may ... |
|
|
Invention
|
Partitioning a cache for application of a replacement policy.
Systems and methods are disclosed ... |
|
2023
|
Invention
|
Hardware test mode for processor core.
Systems and methods are disclosed for implementing a hard... |
|
|
Invention
|
Address boundary functions for physical and localized addresses. An integrated circuit for transl... |
|
|
Invention
|
Serial wire timer distribution.
Systems and methods are disclosed for serial wire timer distribu... |
|
|
Invention
|
Measuring performance associated with processing instructions.
A system may include a processor ... |
|
|
Invention
|
Translation lookaside buffer probing prevention. Described are methods, logic, and circuitry whic... |
|
|
Invention
|
Processing for vector load or store micro-operation with inactive mask elements. Apparatus and me... |
|
|
Invention
|
Tracking of store operations. Apparatus and methods for tracking sub-micro-operations and groups ... |
|
|
Invention
|
Cache replacement policy state structure with extra states for prefetch and non-temporal loads.
... |
|
|
Invention
|
Determining an error handling mode. A first circuitry may have a first interface. A response circ... |
|
|
Invention
|
Bundling and dynamic allocation of register blocks for vector instructions. Apparatus and methods... |
|
|
Invention
|
Vector instruction processing after primary decode.
Apparatus and methods for cracking and proce... |
|
|
Invention
|
Address range encoding in system on a chip with securely partitioned memory space. Systems and me... |
|
|
G/S
|
Semiconductor chips; integrated circuits; microprocessors; microcontrollers; printed circuit boar... |
|
2022
|
Invention
|
Nested loop optimization with vector memory instructions.
A program sequence, comprising an inne... |
|
|
Invention
|
Processor crash analysis using register sampling.
Systems and methods are disclosed for processo... |
|
|
Invention
|
Error management in system on a chip with securely partitioned memory space.
Systems and methods... |
|
|
Invention
|
Debug in system on a chip with securely partitioned memory space. Systems and methods are disclos... |
|
2020
|
G/S
|
Semiconductor chips; integrated circuits; microprocessors;
microcontrollers; printed circuit boa... |
|
|
G/S
|
Semiconductor chips; integrated circuits; microprocessors;
microcontrollers; printed circuit boar... |
|
2019
|
G/S
|
Printed circuit boards; user-configurable circuit boards; semiconductor chips; integrated circuit... |
|
|
G/S
|
Printed circuit boards; user-configurable circuit boards;
semiconductor chips; integrated circui... |
|
2016
|
G/S
|
Semiconductor chips; integrated circuits; microprocessors |
