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2024
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Invention
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Downgrading a permission associated with data stored in a cache.
Cache circuitry may be configur... |
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Invention
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Integrated circuit design using metadata.
An integrated circuit design may be generated for an i... |
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Invention
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Integrated circuit design verification with module swapping.
An integrated circuit design may be... |
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Invention
|
Selectable and hierarchical power management.
Described are systems and methods for power manage... |
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Invention
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Combining data channels to determine camera pose. A system can include a memory and a processing ... |
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Invention
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Prefetcher with out-of-order filtered prefetcher training queue.
Described is a system and metho... |
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Invention
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Cycle accurate tracing of vector instructions.
Systems and methods are disclosed for cycle accur... |
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Invention
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Page table entry caches with multiple tag lengths.
Systems and methods are disclosed for page ta... |
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Invention
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Integrated circuit generation with improved interconnect.
Disclosed are systems and methods that... |
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Invention
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Configuring a prefetcher associated with a processor core.
Disclosed are systems and methods for... |
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Invention
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Integrated circuit generation with composable interconnect.
Disclosed are systems and methods th... |
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Invention
|
Store-to-load forwarding for processor pipelines.
Systems and methods are disclosed for store-to... |
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Invention
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Systems and methods for clock gating.
Described are systems and methods for clock gating compone... |
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Invention
|
Hybrid fixed-point and floating-point computations for improved neural network accuracy.
Systems... |
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Invention
|
Quad narrowing operation.
Systems and methods are disclosed for implementing a quad narrowing op... |
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Invention
|
Event tracing.
Systems and methods are disclosed for debug event tracing. For example, an integr... |
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Invention
|
Macro-op fusion for pipelined architectures.
Systems and methods are disclosed for macro-op fusi... |
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Invention
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Partitioning a cache for application of a replacement policy.
Systems and methods are disclosed ... |
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2023
|
Invention
|
Concurrent support for multiple cache inclusivity schemes using low priority evict operations. Sy... |
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Invention
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Variable depth pipeline for error correction.
Systems and methods are disclosed for variable dep... |
|
|
Invention
|
Transfer buffer between a scalar pipeline and vector pipeline.
Systems and methods are disclosed... |
|
|
Invention
|
Vector load store operations in a vector pipeline using a single operation in a load store unit. ... |
|
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Invention
|
Accelerated vector reduction operations.
Systems and methods are disclosed for accelerated vecto... |
|
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Invention
|
Data storage in non-inclusive cache.
Systems and methods are disclosed for data storage in a non... |
|
|
Invention
|
Debug trace circuitry configured to generate a record including an address pair and a counter val... |
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Invention
|
Bit pattern matching hardware prefetcher.
Described herein is a bit pattern matching hardware pr... |
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Invention
|
Flexible power management interface.
Systems and methods are described for a flexible and select... |
|
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Invention
|
Address boundary functions for physical and localized addresses. An integrated circuit for transl... |
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Invention
|
Serial wire timer distribution.
Systems and methods are disclosed for serial wire timer distribu... |
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Invention
|
Measuring performance associated with processing instructions.
A system may include a processor ... |
|
|
Invention
|
Translation lookaside buffer probing prevention. Described are methods, logic, and circuitry whic... |
|
|
Invention
|
Speculative request indicator in request message.
A method and apparatus for a speculative reque... |
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Invention
|
Eviction operations based on eviction message types of different priorities. An agent may be conf... |
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Invention
|
Re-triggering wake-up to handle time skew between scalar and vector sides. A method for re-trigge... |
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Invention
|
Processing for vector load or store micro-operation with inactive mask elements. Apparatus and me... |
|
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Invention
|
Tracking of store operations.
Apparatus and methods for tracking sub-micro-operations and groups... |
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|
Invention
|
Cache replacement policy state structure with extra states for prefetch and non-temporal loads.
... |
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Invention
|
Integrated circuit generator using a provider.
A system may provide a placeholder for a componen... |
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Invention
|
Determining an error handling mode.
A first circuitry may have a first interface. A response cir... |
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Invention
|
Making circuitry having an attribute.
A system may generate an annotation based on an attribute ... |
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Invention
|
Bundling and dynamic allocation of register blocks for vector instructions.
Apparatus and method... |
|
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Invention
|
Dependency tracking and chaining for vector instructions.
Apparatus and methods for dependency t... |
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Invention
|
Canceling prefetch of cache blocks based on an address and a bit field. Prefetch circuitry may be... |
|
|
Invention
|
Prefetching cache blocks based on an address for a group and a bit field.
Prefetch circuitry may... |
|
|
Invention
|
Vector instruction processing after primary decode.
Apparatus and methods for cracking and proce... |
|
|
Invention
|
Address range encoding in system on a chip with securely partitioned memory space.
Systems and m... |
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P/S
|
Semiconductor chips; integrated circuits; microprocessors; microcontrollers; printed circuit boar... |
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2022
|
Invention
|
Nested loop optimization with vector memory instructions.
A program sequence, comprising an inne... |
|
|
Invention
|
Processor crash analysis using register sampling.
Systems and methods are disclosed for processo... |
|
|
Invention
|
Error management in system on a chip with securely partitioned memory space.
Systems and methods... |
|
|
Invention
|
Debug in system on a chip with securely partitioned memory space.
Systems and methods are disclo... |
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2020
|
P/S
|
Semiconductor chips; integrated circuits; microprocessors;
microcontrollers; printed circuit boa... |
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|
P/S
|
Semiconductor chips; integrated circuits; microprocessors;
microcontrollers; printed circuit boar... |
|
2019
|
P/S
|
Printed circuit boards; user-configurable circuit boards; semiconductor chips; integrated circuit... |
|
|
P/S
|
Printed circuit boards; user-configurable circuit boards;
semiconductor chips; integrated circui... |
|
2016
|
P/S
|
Semiconductor chips; integrated circuits; microprocessors |
