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2024
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Invention
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Verifying or reading a cell in an analog neural memory in a deep learning artificial neural netwo... |
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Invention
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Neural network classifier using array of three-gate non-volatile memory cells.
A neural network ... |
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Invention
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Erasing of a word or a page of non-volatile memory cells in an analog neural memory system.
In o... |
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2023
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Invention
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Voltage generator for analog neural memory array.
In one example, a system comprises an analog n... |
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Invention
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Adaptive bias decoder for non-volatile memory system.
In one example, a non-volatile memory syst... |
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Invention
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Programming of a selected non-volatile memory cell by changing programming pulse characteristics.... |
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Invention
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Output circuit.
In one example, a circuit comprises an input transistor comprising a first termi... |
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Invention
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Neural network device.
In one example, a neural network device comprises a first plurality of sy... |
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Invention
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Word line driver for vector-by-matrix multiplication array.
In one example, a system comprises a... |
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Invention
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Input and output blocks for an array of memory cells.
In one example, a system comprises an arra... |
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Invention
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Determination of a bias voltage to apply to one or more memory cells in a neural network.
A firs... |
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Invention
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Memory device formed on silicon-on-insulator substrate, and method of making same. A memory devic... |
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Invention
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Memory device formed on silicon-on-insulator substrate, and method of making same.
A memory devi... |
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Invention
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Analog computation-in-memory engine and digital computation-in-memory engine to perform operation... |
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Invention
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Masking sparse inputs and outputs in neural network array. Numerous examples are disclosed of a m... |
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Invention
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Masking sparse inputs and outputs in neural network array.
Numerous examples are disclosed of a ... |
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Invention
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Row decoder and row address scheme in a memory system. mmnprtruvmuunvvptt. |
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Invention
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Row decoder and row address scheme in a memory system.
Numerous examples are disclosed of a row ... |
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Invention
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Split array architecture for analog neural memory in a deep learning artificial neural network. N... |
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Invention
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Output block for a vector-by-matrix multiplication array of non-volatile memory cells. A system c... |
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Invention
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Output block for array of non-volatile memory cells.
In one example, a system comprises an array... |
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Invention
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Neural network array comprising one or more coarse cells and one or more fine cells. In one examp... |
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Invention
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Pumping controller for a plurality of charge pump units. In one example, a system comprises a plu... |
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Invention
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Multiplexors for neural network array. Numerous examples are disclosed of multiplexors coupled to... |
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Invention
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Current-to-voltage converter comprising common mode circuit. In one example, a system comprises a... |
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Invention
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Redundancy for an array of non-volatile memory cells using tag registers and for a redundant arra... |
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Invention
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Current-to-voltage converter comprising common mode circuit.
In one example, a system comprises ... |
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Invention
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Pumping controller for a plurality of charge pump units.
In one example, a system comprises a pl... |
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Invention
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Multiplexors for neural network array.
Numerous examples are disclosed of multiplexors coupled t... |
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Invention
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Redundancy for an array of non-volatile memory cells using tag registers.
Numerous examples are ... |
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Invention
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Semiconductor device with communication ring. A semiconductor device includes a semiconductor sub... |
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Invention
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Dual-path charge pump. Examples of improved charge pumps are disclosed. In one example, a system ... |
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Invention
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Semiconductor device with communication ring.
A semiconductor device includes a semiconductor su... |
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Invention
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Dual-path charge pump.
Examples of improved charge pumps are disclosed. In one example, a system... |
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Invention
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Grouping and error correction for non-volatile memory cells. Numerous examples are disclosed of a... |
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Invention
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Memory cell array with row direction gap between erase gate lines and dummy floating gates. A mem... |
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Invention
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Grouping and error correction for non-volatile memory cells.
Numerous examples are disclosed of ... |
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2022
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Invention
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Input circuit for artificial neural network array. Numerous examples are disclosed of input circu... |
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Invention
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Multiple row programming operation in artificial neural network array. Numerous examples are disc... |
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Invention
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Output circuit for artificial neural network array. Numerous examples are disclosed of output cir... |
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Invention
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Verification method and system in artificial neural network array. of the vector-by-matrix multip... |
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Invention
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Verification method and system in artificial neural network array.
Numerous examples are disclos... |
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Invention
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Output circuit for artificial neural network array.
Numerous examples are disclosed of output ci... |
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Invention
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Input circuit for artificial neural network array.
Numerous examples are disclosed of input circ... |
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Invention
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Multiple row programming operation in artificial neural network array.
Numerous examples are dis... |
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2003
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G/S
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Computer hardware, peripherals and integrated circuit components for digital, networking, wireles... |
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1998
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G/S
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Embedded controllers. Instructional manuals. |
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1991
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G/S
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computer hardware, peripherals, integrated circuit components and related documentation; namely, ... |
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1990
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G/S
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integrated circuit memories and related instruction manuals sold together as a unit |
