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2025
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Invention
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Pillar capacitor structure for high density memory applications.
The memory bit-cell formed usin... |
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2024
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Invention
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Planar ferroelectric memory device.
Approaches for integrating FE memory arrays into a processor... |
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Invention
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Non-linear polar material based multi-capacitor bit-cell with shared gain element and access tran... |
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Invention
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Non-linear polar material based multi-capacitor bit-cell with multi-way sharing of gain element w... |
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Invention
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Method of forming ferroelectric chiplet in a multi-dimensional packaging with i/o switch embedded... |
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Invention
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Ferroelectric capacitor integrated with a logic device.
Ferroelectric capacitor is formed by con... |
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Invention
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Non-linear polar material based multi-capacitor bit-cell with shared gain element with series tra... |
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Invention
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Method of forming a majority gate based low power ferroelectric based adder with reset mechanism.... |
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Invention
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Method of memory device fabrication through iterative multilayer stack development.
A method to ... |
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Invention
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Doped polar layers and semiconductor device incorporating same.
The disclosed technology general... |
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2023
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Invention
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Multiplier with non-linear polar material. A new class of multiplier cells (analog or digital) is... |
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Invention
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Exclusive-or logic gate with non-linear input capacitors. A class of complex logic gates are pres... |
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Invention
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Area oriented logic synthesis. A computer-aided design (CAD) tool is provided for logic optimizat... |
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Invention
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Random swap injection. Endurance mechanisms are introduced for memories such as non-volatile memo... |
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Invention
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Multi-die mapping matrix multiplication. Matrix multiplication process is segregated between two ... |
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Invention
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High density ferroelectric random access memory (feram) devices and methods of fabrication. Non l... |
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Invention
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Method of forming stacked capacitors through wafer bonding.
A method of fabricating a device com... |
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Invention
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Embedded memory adjacent to non-memory. A process integration and patterning flow used to pattern... |
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Invention
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Non-linear polar material based flip-flop. A low power sequential circuit (e.g., latch) uses a no... |
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Invention
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Method for conditioning majority or minority gate. A new class of logic gates are presented that ... |
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Invention
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Capacitor integrated with a transistor for logic and memory applications. A method of fabricating... |
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2022
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Invention
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Memory array with buried or backside word-line. A memory is described having a plurality of bit-c... |
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Invention
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Stacked capacitors with shared electrodes and methods of fabrication. A method of fabricating a s... |
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Invention
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Method of fabricating transistors and stacked planar capacitors for memory and logic applications... |
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Invention
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Read disturb mitigation for non-linear polar material based multi-capacitor bit-cell. A disturb m... |
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Invention
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Write disturb mitigation for column multiplexed non-linear polar material based multi-capacitor b... |
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Invention
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Nc for memory and logic applications. A device structure comprises a first conductive interconnec... |
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Invention
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Trench capacitors with shared electrode. A device structure comprises a first conductive intercon... |
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Invention
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Planar capacitors with shared electrode and methods of fabrication. A device structure comprises ... |
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Invention
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Multi-input threshold gate having stacked and folded non-planar capacitors. A configuration for e... |
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Invention
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Multi-input threshold gate having stacked and folded planar capacitors with and without offset. A... |
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Invention
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Memory bit-cell with stacked and folded planar capacitors. A configuration for efficiently placin... |
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2021
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Invention
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Multi-function threshold gate with input based adaptive threshold and with stacked non-planar par... |
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Invention
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Method of adjusting threshold of a linear capacitive-input circuit. An apparatus and configuring ... |
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Invention
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Stacked planar capacitors based multi-function linear threshold gate with input based adaptive th... |
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Invention
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Multi-function linear threshold gate with input based adaptive threshold. An apparatus and config... |
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Invention
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Devices with continuous electrode plate and methods of fabrication. An integration process includ... |
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Invention
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Memory devices with dual encapsulation layers and methods of fabrication. An integration process ... |
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Invention
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Reset mechanism for an adder or a multiplier having paraelectric material. A multiplier cell is d... |
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Invention
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Low power multiplier with non-linear polar material based reset mechanism with sequential reset. ... |
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Invention
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3d stack of split graphics processing logic dies. A packaging technology to improve performance o... |
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Invention
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Majority or minority based low power checkerboard carry save multiplier with inverted multiplier ... |
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Invention
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Area optimized ferroelectric or paraelectric based low power multiplier. A low power adder uses a... |
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Invention
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Ferroelectric or paraelectric based low power multiplier array. A low power adder uses a non-line... |
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Invention
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Ripple carry adder with inverted ferroelectric or paraelectric based adders. A low power adder us... |
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Invention
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Ultra high-bandwidth artificial intelligence (ai) processor with dram under the processor. Descri... |
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Invention
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Method of forming an artificial intelligence processor with three-dimensional stacked memory. Des... |
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Invention
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Ferroelectric memory chiplet in a multi-dimensional packaging with i/o switch embedded in a subst... |
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Invention
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Ferroelectric memory chiplet in a multi-dimensional packaging. A ferroelectric memory chiplet in ... |
