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2024
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Invention
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Non-linear polar material based multi-capacitor bit-cell with shared gain element and access tran... |
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Invention
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Non-linear polar material based multi-capacitor bit-cell with multi-way sharing of gain element w... |
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Invention
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Method of forming ferroelectric chiplet in a multi-dimensional packaging with i/o switch embedded... |
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Invention
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Ferroelectric capacitor integrated with a logic device.
Ferroelectric capacitor is formed by con... |
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Invention
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Non-linear polar material based multi-capacitor bit-cell with shared gain element with series tra... |
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Invention
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Method of forming a majority gate based low power ferroelectric based adder with reset mechanism.... |
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Invention
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Method of memory device fabrication through iterative multilayer stack development.
A method to ... |
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Invention
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Doped polar layers and semiconductor device incorporating same.
The disclosed technology general... |
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Invention
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Non-linear polar material based multi-capacitor high density bit-cell. Described herein is a memo... |
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2023
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Invention
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Area oriented logic synthesis. A computer-aided design (CAD) tool is provided for logic optimizat... |
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Invention
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Method of fabricating memory devices including b-site dopants and logic devices through wafer bon... |
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Invention
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Method of forming capacitors through wafer bonding.
A method of fabricating a device comprises f... |
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Invention
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Method of forming stacked capacitors through wafer bonding.
A method of fabricating a device com... |
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Invention
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Iterative monetization of precursor in process development of non-linear polar material and devic... |
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Invention
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Iterative process development of non-linear polar material and devices. A method for monetizing f... |
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Invention
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Method for conditioning majority or minority gate. A new class of logic gates are presented that ... |
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Invention
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Non-linear polar material based multi-capacitor high density bit-cell.
Described herein is a mem... |
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2022
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Invention
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Iterative method of multilayer stack development for device applications. A method to deposit a m... |
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Invention
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Read disturb mitigation for non-linear polar material based multi-capacitor bit-cell. A disturb m... |
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Invention
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Write disturb mitigation for column multiplexed non-linear polar material based multi-capacitor b... |
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Invention
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Majority or minority logic gate with non-linear input capacitors without reset. A class of comple... |
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Invention
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Multi-input threshold gate having stacked and folded non-planar capacitors. A configuration for e... |
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Invention
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Planar capacitors with non-linear polar material staggered on a shared electrode. A configuration... |
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Invention
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Multi-input threshold gate having stacked and folded planar capacitors with and without offset. A... |
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Invention
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1tnc memory bit-cell having stacked and folded non-planar capacitors. A configuration for efficie... |
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Invention
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1tnc memory bit-cell having stacked and folded planar capacitors with lateral offset. A configura... |
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Invention
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Memory bit-cell with stacked and folded planar capacitors. A configuration for efficiently placin... |
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Invention
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Asynchronous consensus circuit with stacked ferroelectric non-planar capacitors. Asynchronous cir... |
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Invention
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Asynchronous consensus circuit with majority gate based on non-linear capacitors. Asynchronous ci... |
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2021
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Invention
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Multi-level hydrogen barrier layers for memory applications and methods of fabrication. A device ... |
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Invention
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Planar and trench capacitors with hydrogen barrier dielectric for logic and memory applications a... |
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Invention
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Planar and trench capacitors for logic and memory applications and methods of fabrication. A devi... |
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Invention
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Planar and trench capacitors for logic and memory applications. A device includes, in a first reg... |
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Invention
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Pocket flow for trench capacitors integrated with planar capacitors on a same substrate and metho... |
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Invention
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Planar and trench capacitors with hydrogen barrier dielectric for logic and memory applications. ... |
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Invention
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Multi-function threshold gate with input based adaptive threshold and with stacked non-planar fer... |
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Invention
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Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic stru... |
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Invention
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Devices with continuous electrode plate and methods of fabrication. An integration process includ... |
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Invention
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Memory devices with dual encapsulation layers and methods of fabrication. An integration process ... |
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Invention
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Reset mechanism for an adder or a multiplier having paraelectric material. A multiplier cell is d... |
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Invention
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Low power multiplier with non-linear polar material based reset mechanism with sequential reset. ... |
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Invention
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Method and apparatus for heuristic-based power gating of non-cmos logic and cmos based logic. A p... |
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Invention
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Ripple carry adder with inverted ferroelectric or paraelectric based adders. A low power adder us... |
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Invention
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Method and apparatus for managing power in a multi-dimensional packaging. A packaging technology ... |
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Invention
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Method and apparatus for managing power of ferroelectric or paraelectric logic and cmos based log... |
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Invention
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Method of forming an artificial intelligence processor with three-dimensional stacked memory. Des... |
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Invention
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Ferroelectric memory chiplet in a multi-dimensional packaging with i/o switch embedded in a subst... |
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Invention
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Ferroelectric memory chiplet in a multi-dimensional packaging. A ferroelectric memory chiplet in ... |
