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2025
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Invention
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Configuring an h-tree associated with a bounding box. In some implementations, a computing device... |
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Invention
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Plane transitioning at a global switch box. In some implementations, a first global switch box (G... |
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Invention
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Plane transitioning at a global switch box.
In some implementations, a first global switch box (... |
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Invention
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Configuring an h-tree associated with a bounding box.
In some implementations, a computing devic... |
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Invention
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Language servers for high-level synthesis. A non-transitory computer readable memory (CRM) is pro... |
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Invention
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Co-debugging for system-on-chip having a cpu and an accelerator portion. A non-transitory compute... |
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2024
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Invention
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Safety verification for programmable logic devices, and related methods, apparatuses, and systems... |
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Invention
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Configuration memory cell. An apparatus may include a configuration memory cell. The configuratio... |
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Invention
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Configuration memory cell.
An apparatus may include a configuration memory cell. The configurati... |
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Invention
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Device and method for signal retiming. A device and method is provided with a first portion of th... |
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Invention
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Self-learning data linearizer. A circuit, and method for using same comprising, a first intermedi... |
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Invention
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Self-learning data linearizer.
A circuit, and method for using same comprising, a first intermed... |
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Invention
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Method and apparatus for dual edge memory write operation. An apparatus for dual edge memory writ... |
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Invention
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Method and apparatus for dual edge memory write operation.
An apparatus for dual edge memory wri... |
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Invention
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Reram memory array that includes reram memory cells having a reram device and two series-connecte... |
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Invention
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Language servers for high-level synthesis.
A non-transitory computer readable memory (CRM) is pr... |
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|
Invention
|
Device and method for signal retiming.
A device and method is provided with a first portion of t... |
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Invention
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Co-simulation for system-on-chip.
A non-transitory computer readable medium is provided comprisi... |
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Invention
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A configuration memory cell.
An apparatus may include a first inverter, a second inverter, a fir... |
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Invention
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A configuration memory cell. An apparatus may include a first inverter, a second inverter, a firs... |
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Invention
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Apparatus including a cmos pass gate circuit and a bootstrap circuit.
One or more examples relat... |
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Invention
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Cmos memory cell for high voltage applications.
A memory cell comprises a plurality of n-type me... |
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2023
|
Invention
|
Tamper detector based on power network electrical characteristic. Methods and systems for tamper ... |
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Invention
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Tamper detector based on power network electrical characteristic.
Methods and systems for tamper... |
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Invention
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High-level-synthesis for risc-v system-on-chip generation for field programmable gate arrays.
An... |
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2022
|
Invention
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Generating rtl for a circuit using dsp blocks. A method may create RTL for a circuit design utili... |
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Invention
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Generating rtl for a circuit using dsp blocks.
A method may create RTL for a circuit design util... |
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2021
|
Invention
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Method for combining analog neural net with fpga routing in a monolithic integrated circuit. A me... |
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Invention
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Method for erasing a reram memory cell. A method for erasing a ReRAM memory cell that includes a ... |
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2019
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Invention
|
Circuitry and methods for programming resistive random access memory devices. A method for progra... |
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Invention
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Metal filament reram cell with current limiting during program and erase. A ReRAM memory cell inc... |
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Invention
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Single event upset stabilized memory cells. A single-event-upset (SEU) stabilized memory cell inc... |
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Invention
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Apparatus and method for combining analog neural net with fpga routing in a monolithic integrated... |
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Invention
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Fpga logic cell with improved support for counters. A logic cell for a programmable logic integra... |
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Invention
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Reram memory cell having dual word line control. A ReRAM memory cell includes a ReRAM device incl... |
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Invention
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Reram programming method including low-current pre-programming for program time reduction. A meth... |
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Invention
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Seu stabilized memory cells. A single-event-upset (SEU) stabilized memory cell includes a latch p... |
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Invention
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Front to back resistive random-access memory cells. A resistive random-access memory device forme... |
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Invention
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Hybrid configuration memory cell. A configuration memory cell includes a latch portion including ... |
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Invention
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Seu inhibit sram cell. A static random-access memory (SRAM) cell includes a non-inverting logic e... |
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Invention
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Vertical resistor based sram cells.
A static random-access memory (SRAM) cell includes a non-inv... |
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2018
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Invention
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Circuit and layout for resistive random-access memory arrays having two bit lines per column. A l... |
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Invention
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Circuit and layout for resistive random-access memory arrays. A ReRAM memory array includes rows ... |
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G/S
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Electronic circuits; semiconductor chips; computer chips;
integrated circuits; field programmabl... |
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2017
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G/S
|
Electronic circuits; semiconductor chips; computer chips; integrated circuits; field programmable... |
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2016
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G/S
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Integrated circuits. |
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G/S
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Integrated circuits |
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2010
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G/S
|
Integrated circuits; integrated circuit intellectual
property cores; computer software for opera... |
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2009
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G/S
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Integrated circuits; computer hardware for programming and debugging integrated circuits |
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2003
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G/S
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Integrated circuits and manuals and data sheets sold therewith as a unit |
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2001
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G/S
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Computer software for designing, synthesizing, simulating, placing and routing circuits implement... |
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1996
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G/S
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Integrated circuits; integrated circuits being field programmable gate arrays and system programm... |
