ReRAM MEMORY ARRAY THAT INCLUDES ReRAM MEMORY CELLS HAVING A ReRAM DEVICE AND TWO SERIES-CONNECTED SELECT TRANSISTORS THAT CAN BE SELECTED FOR PROGRAMMING
A ReRAM memory array includes ReRAM memory cells and a select circuit having first and second series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for programming, the bit line coupled to the ReRAM memory cell(s) to be programmed is biased at a first voltage potential and the source line coupled to the ReRAM memory cell(s) to be programmed is biased at a second voltage potential less than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to program the ReRAM device. The gates of first and second series-connected select transistors of ReRAM memory cell(s) to be programmed are supplied with positive voltage pulses. The gates of second series-connected select transistors of respective ReRAM memory cell(s) unselected for programming are supplied with a voltage potential insufficient to turn them on.
Methods and systems for tamper detection based on power network electrical characteristic by storing a reference electrical signature of a power distribution network comprising the integrated circuit, generating in the integrated circuit a current stimulus waveform by sigma-delta based noise shaping, and providing the waveform to the power distribution network comprising the integrated circuit, sampling the power distribution network with a voltage-to-digital converter in the integrated circuit and estimating based at least partially on the sampled power distribution network a response electrical signature of the power distribution network responsive to the stimulus waveform, comparing on the integrated circuit the estimated response electrical signature and the reference electrical signature, and triggering by the integrated circuit a penalty based on a comparison of the response electrical signature and the reference electrical signature.
G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
G06F 17/14 - Fourier, Walsh or analogous domain transformations
H03M 3/00 - Conversion of analogue values to or from differential modulation
3.
TAMPER DETECTOR BASED ON POWER NETWORK ELECTRICAL CHARACTERISTIC
Methods and systems for tamper detection based on power network electrical characteristic by storing a reference electrical signature of a power distribution network comprising the integrated circuit, generating in the integrated circuit a current stimulus waveform by sigma¬ delta based noise shaping, and providing the waveform to the power distribution network comprising the integrated circuit, sampling the power distribution network with a voltage-to- digital converter in the integrated circuit and estimating based at least partially on the sampled power distribution network a response electrical signature of the power distribution network responsive to the stimulus waveform, comparing on the integrated circuit the estimated response electrical signature and the reference electrical signature, and triggering by the integrated circuit a penalty based on a comparison of the response electrical signature and the reference electrical signature.
An article of manufacture includes a medium with instructions that when read and executed by a processor, cause the processor to identify a code stream to be executed by a system-on-a-chip (SoC). The SoC is to include an open standard processor and hardware accelerators implemented in reprogrammable hardware. The processor is to, from the code stream, identify a first portion of the code stream to be executed as software by the open standard processor and a second portion to be executed in the accelerators, compile the first portion into a binary for execution by the open standard processor, and generate a hardware description for the second portion to be implemented by the hardware accelerators. The hardware description and the binary are to exchange data during execution of the code stream.
A method may create RTL for a circuit design utilizing DSP blocks by receiving a software program comprising a multiplication statement to multiply a first number by a second number, the first number having a first data type and a first bit width, the second number having a second data type and a second bit width; determining a number of DSP blocks for implementing the statement based at least on the first bit width, the second bit width, a first DSP bit width corresponding to a bit width of a first operand of the DSP blocks, and a second DSP bit width corresponding to a bit width of a second operand of the DSP blocks, wherein the number of DSP blocks is two or more; and generating RTL for the statement, the RTL comprises a plurality of distinct portions corresponding to each of the two or more DSP blocks.
A method may create RTL for a circuit design utilizing DSP blocks by receiving a software program comprising a multiplication statement to multiply a first number by a second number, the first number having a first data type and a first bit width, the second number having a second data type and a second bit width; determining a number of DSP blocks for implementing the statement based at least on the first bit width, the second bit width, a first DSP bit width corresponding to a bit width of a first operand of the DSP blocks, and a second DSP bit width corresponding to a bit width of a second operand of the DSP blocks, wherein the number of DSP blocks is two or more; and generating RTL for the statement, the RTL comprises a plurality of distinct portions corresponding to each of the two or more DSP blocks.
A ReRAM memory array includes ReRAM memory cells having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors of the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors of the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on.
A method for implementing a neural network system in an integrated circuit includes presenting digital pulses to word line inputs of a matrix vector multiplier including a plurality of word lines, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line, each digital pulse having a pulse width proportional to an analog quantity. During a charge collection time frame charge collected on each of the summing bit lines from current flowing in the programmable Vt transistor is summed. During a pulse generating time frame digital pulses are generated having pulse widths proportional to the amount of charge that was collected on each summing bit line during the charge collection time frame.
G06G 7/161 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for multiplication or division with pulse modulation, e.g. modulation of amplitude, width, frequency, phase, or form
G06G 7/22 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for evaluating trigonometric functionsArrangements for performing computing operations, e.g. amplifiers specially adapted therefor for conversion of co-ordinatesArrangements for performing computing operations, e.g. amplifiers specially adapted therefor for computations involving vector quantities
G06N 3/04 - Architecture, e.g. interconnection topology
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
A method for erasing a ReRAM memory cell that includes a ReRAM device having a select circuit with two series-connected select transistors. The method includes determining if the ReRAM cell is selected for erasing. If the ReRAM cell is selected for erasing, the bit line node is biased at a first voltage potential, the source line node is biased at a second voltage potential greater than the first voltage potential and the gates of the series-connected select transistors are supplied with positive voltage pulses. The difference between the first voltage potential and the second voltage potential is sufficient to erase the ReRAM device in the ReRAM cell. If the ReRAM cell is unselected for erasing, the gate of the one of the series-connected select transistors having its drain connected to an electrode of the ReRAM device is supplied with a voltage potential insufficient to turn it on.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
10.
Metal filament ReRAM cell with current limiting during program and erase
A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell. The programming circuit path is separate from the erase circuit path.
A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
12.
ReRAM programming method including low-current pre-programming for program time reduction
A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.
A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G11C 29/44 - Indication or identification of errors, e.g. for repair
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 29/04 - Detection or location of defective memory elements
A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
H01L 27/11 - Static random access memory structures
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
15.
APPARATUS AND METHOD FOR COMBINING ANALOG NEURAL NET WITH FPGA ROUTING IN A MONOLITHIC INTEGRATED CIRCUIT
A user programmable integrated circuit includes a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements. A plurality of matrix vector multipliers, each have a plurality of word lines, each word line coupled to a different first one of the one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line. A charge-to-pulse-width converter circuit is associated with each one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G06G 7/161 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for multiplication or division with pulse modulation, e.g. modulation of amplitude, width, frequency, phase, or form
A user programmable integrated circuit includes a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements. A plurality of matrix vector multipliers, each have a plurality of word lines, each word line coupled to a different first one of the one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line. A charge-to-pulse-width converter circuit is associated with each one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network.
G06G 7/161 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for multiplication or division with pulse modulation, e.g. modulation of amplitude, width, frequency, phase, or form
G06G 7/22 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for evaluating trigonometric functionsArrangements for performing computing operations, e.g. amplifiers specially adapted therefor for conversion of co-ordinatesArrangements for performing computing operations, e.g. amplifiers specially adapted therefor for computations involving vector quantities
G06N 3/04 - Architecture, e.g. interconnection topology
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
17.
FPGA LOGIC CELL WITH IMPROVED SUPPORT FOR COUNTERS
A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 of the K inputs.
H03K 19/003 - Modifications for increasing the reliability
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 of the K inputs.
G06F 7/506 - AddingSubtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
H03K 19/17736 - Structural details of routing resources
H03K 19/17728 - Reconfigurable logic blocks, e.g. lookup tables
19.
Circuitry and methods for programming resistive random access memory devices
A method for programming a ReRAM cell including a ReRAM device connected in series with an access transistor includes biasing the ReRAM cell with a programming potential that configures the access transistor in a common-source configuration and applying at least one programming voltage pulse to a gate of the access transistor, the programming voltage pulse having a magnitude selected to limit programming current to a preselected value.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
20.
Front to back resistive random-access memory cells
A resistive random-access memory device formed on a semiconductor substrate includes a first interlayer dielectric formed over the semiconductor substrate and includes a first via. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A lower metal layer formed in the first via has a top surface extending above a top surface of the chemical-mechanical-polishing stop layer. A dielectric layer is formed over the chemical-mechanical-polishing stop layer and is in electrical contact with the lower metal layer. A barrier metal layer is formed over the dielectric layer. Edges of the dielectric layer and the first barrier metal layer extend beyond outer edges of the first via. A second interlayer dielectric layer including a second via is formed over the dielectric layer. An upper metal layer formed in the second via in electrical contact with the barrier metal layer.
H03K 19/1776 - Structural details of configuration resources for memories
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
A layout is presented for a ReRAM memory cell array including rows and columns of ReRAM cells, each ReRAM cell is in a row and column of ReRAM cells. Each ReRAM cell includes a ReRAM device. A first transistor is coupled between the ReRAM device and a first bit line associated with the column containing the ReRAM cell. The first transistor has a gate coupled to a first word line associated with the row containing the ReRAM cell. A second transistor is coupled between the ReRAM device and a second bit line associated with the column containing the ReRAM cell. The second transistor has a gate coupled to a second word line associated with the row containing the ReRAM cell.
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
22.
Circuit and layout for resistive random-access memory arrays
A ReRAM memory array includes rows and columns of ReRAM cells. Each ReRAM cell in a row and column of the array includes a ReRAM device having an ion source end coupled to a bias line associated with the row of the array containing the ReRAM device. A first transistor is coupled between the solid electrolyte end of the ReRAM device and a bit line associated with the column of the array containing the ReRAM cell. The first transistor has a gate coupled to a first word line associated with the row containing the ReRAM cell. A second transistor is coupled between the solid electrolyte end of the ReRAM device and the bit line associated with the column of the array containing the ReRAM cell. The second transistor has a gate coupled to a second word line associated with the row containing the ReRAM cell.
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
23.
CIRCUIT AND LAYOUT FOR RESISTIVE RANDOM-ACCESS MEMORY ARRAYS HAVING TWO BIT LINES PER COLUMN
A layout is presented for a ReRAM memory cell array including rows and columns of ReRAM cells, each ReRAM cell is in a row and column of ReRAM cells. Each ReRAM cell includes a ReRAM device. A first transistor is coupled between the ReRAM device and a first bit line associated with the column containing the ReRAM cell. The first transistor has a gate coupled to a first word line associated with the row containing the ReRAM cell. A second transistor is coupled between the ReRAM device and a second bit line associated with the column containing the ReRAM cell. The second transistor has a gate coupled to a second word line associated with the row containing the ReRAM cell.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
24.
CIRCUIT AND LAYOUT FOR RESISTIVE RANDOM-ACCESS MEMORY ARRAYS
A ReRAM memory array includes rows and columns of ReRAM cells. Each ReRAM cell in a row and column of the array includes a ReRAM device having an ion source end coupled to a bias line associated with the row of the array containing the ReRAM device. A first transistor is coupled between the solid electrolyte end of the ReRAM device and a bit line associated with the column of the array containing the ReRAM cell. The first transistor has a gate coupled to a first word line associated with the row containing the ReRAM cell. A second transistor is coupled between the solid electrolyte end of the ReRAM device and the bit line associated with the column of the array containing the ReRAM cell. The second transistor has a gate coupled to a second word line associated with the row containing the ReRAM cell.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
A configuration memory cell includes a latch portion including a cross-coupled latch having complementary output nodes, and a programmable read-only memory (PROM) portion coupled to one of the complementary output nodes of the latch portion, the PROM portion including a programmable and erasable ReRAM device.
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
A configuration memory cell includes a latch portion including a cross-coupled latch having complementary output nodes, and a programmable read-only memory (PROM) portion coupled to one of the complementary output nodes of the latch portion, the PROM portion including a programmable and erasable ReRAM device.
G11C 17/00 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
A static random-access memory (SRAM) cell includes a non-inverting logic element having an input and an output. A vertical resistor feedback device is connected between the output and the input of the non-inverting logic element.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
G11C 11/41 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
A nonvolatile memory cell includes a first voltage supply node, a second voltage supply node, an output node, a resistive random access memory device having a first electrode and a second electrode, the first electrode connected to the first voltage supply node, at least one p-channel transistor connected between the second electrode of the resistive random access memory device and the output node, at least one n-channel transistor connected between the output node and the second voltage supply node, and an inverter connected between the output node and a gate of the at least one n-channel transistor.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H03K 19/094 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors
H03K 19/1776 - Structural details of configuration resources for memories
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
29.
APPARATUS AND METHOD FOR SENSORLESS DETECTION OF LOAD TORQUE OF A STEPPER MOTOR AND FOR OPTIMIZING DRIVE CURRENT FOR EFFICIENT OPERATION
A method for controlling the drive current in a stepper motor includes measuring stepper motor current, computing a load angle of the stepper motor, calculating a torque ratio of the stepper motor, generating a reference current as a function of the torque ratio and a maximum current setting for the stepper motor, and setting the drive current of the stepper motor as a function of the reference current.
An architecture in a user-programmable integrated circuit includes a hard logic block having inputs and outputs, a first group of user-configurable general-purpose routing resources coupled to first selected ones of the inputs of the hard logic block, a soft logic block having inputs and outputs, first selected ones of the inputs of the soft logic block coupled to the first group of user-configurable general-purpose routing resources, first selected ones of the outputs of the soft logic block having dedicated connections to second selected ones of the inputs to the hard logic block, and a second group of user-configurable general-purpose routing resources coupled to second selected ones of the outputs of the soft logic block and to first selected ones of the outputs of the hard logic block.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
31.
Apparatus and method for sensorless detection of load torque of a stepper motor and for optimizing drive current for efficient operation
A method for controlling the drive current in a stepper motor includes measuring stepper motor current, computing a load angle of the stepper motor, calculating a torque ratio of the stepper motor, generating a reference current as a function of the torque ratio and a maximum current setting for the stepper motor, and setting the drive current of the stepper motor as a function of the reference current.
l w,ww, the high-voltage FinFET transistors having a second threshold voltage channel implant greater than the first threshold voltage channel implant and second gate dielectric thickness greater than the first gate dielectric thickness.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
An integrated circuit includes a plurality of low-voltage FinFET transistors each having a channel length l and a channel width w, the low-voltage FinFET transistors having a first threshold voltage channel implant and a first gate dielectric thickness. The integrated circuit also includes a plurality of high-voltage FinFET transistors each having the channel length l and the channel width w, the high-voltage FinFET transistors having a second threshold voltage channel implant greater than the first threshold voltage channel implant and second gate dielectric thickness greater than the first gate dielectric thickness.
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/11 - Static random access memory structures
H01L 21/26 - Bombardment with wave or particle radiation
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
34.
SRAM configuration cell for low-power field programmable gate arrays
A random-access memory cell includes first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with the memory cell, and a word line associated with the memory cell. Pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors are connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
H03K 19/1776 - Structural details of configuration resources for memories
A 4-input lookup table module including eight first-rank 2-input multiplexers, four second-rank multiplexers, two third-rank multiplexers, and one fourth-rank multiplexer, the first-rank through fourth-rank multiplexers forming a tree structure. A select input of the fourth-rank multiplexer is coupled to a first input node. Select inputs of the third-rank multiplexers are coupled to a second input node. Select inputs of a first and a second adjacent ones of the second rank 2-input multiplexers are electrically isolated from select inputs of a third and a fourth adjacent ones of the second rank 2-input multiplexers. Select inputs of a first through a fourth adjacent ones of the first rank 2-input multiplexers are electrically isolated from select inputs of a fifth through an eighth adjacent ones of the first rank 2-input multiplexers.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
36.
Circuitry and methods for programming resistive random access memory devices
A method for programming a ReRAM cell including a ReRAM device connected in series with an access transistor includes biasing the ReRAM cell with a programming potential that configures the access transistor in a common-source configuration and applying at least one programming voltage pulse to a gate of the access transistor, the programming voltage pulse having a magnitude selected to limit programming current to a preselected value.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
37.
CIRCUITRY AND METHODS FOR PROGRAMMING RESISTIVE RANDOM ACCESS MEMORY DEVICES
A method for programming a ReRAM cell including a ReRAM device connected in series with an access transistor includes biasing the ReRAM cell with a programming potential that configures the access transistor in a common-source configuration and applying at least one programming voltage pulse to a gate of the access transistor, the programming voltage pulse having a magnitude selected to limit programming current to a preselected value.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
38.
Front to back resistive random access memory cells
A resistive random-access memory device formed on a semiconductor substrate includes an interlayer dielectric formed over the semiconductor substrate and includes a first via. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A lower metal layer formed in the first via presents a substantially planar top surface. A dielectric layer is formed over the chemical-mechanical-polishing stop layer and is in electrical contact with the lower metal layer. A barrier metal layer is formed over the dielectric layer. Edges of the dielectric layer and the first barrier metal layer form an aligned stack having edges extending beyond outer edges of the first via. A dielectric barrier layer including a second via is formed over the aligned stack and at least a portion of the chemical-mechanical-polishing stop layer. An upper metal layer formed in the second via in electrical contact with the barrier metal layer.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
H03K 5/1252 - Suppression or limitation of noise or interference
G01R 29/027 - Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
H03K 5/04 - Shaping pulses by increasing durationShaping pulses by decreasing duration
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
A resistive random access memory cell includes three resistive random access memory devices (102, 104, 106), each resistive random access memory device having an ion source layer (156, 166, 186) and a solid electrolyte layer (154, 164, 188). The first and second resistive random access memory devices are connected in series such that either both ion source layers or both solid electrolyte layers are adjacent to one another. The third resistive random access memory device is connected in series with the first and second resistive random access memory devices.
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
A resistive random access memory cell includes three resistive random access memory devices, each resistive random access memory device having an ion source layer and a solid electrolyte layer. The first and second resistive random access memory devices are connected in series such that either both ion source layers or both solid electrolyte layers are adjacent to one another. A third resistive random access memory device is connected in series with the first and second resistive random access memory devices.
A method for preventing over-programming of resistive random access (ReRAM) based memory cells in a ReRAM memory array includes applying a programming voltage in a programming circuit path including a ReRAM memory cell to be programmed, sensing programming current drawn by the ReRAM cell while the programming voltage is applied across the memory cell, and decreasing the programming current as a function of a rise in programming current.
A method for preventing over-programming of resistive random access (ReRAM) based memory cells in a ReRAM memory array includes applying a programming voltage in a programming circuit path including a ReRAM memory cell to be programmed, sensing programming current drawn by the ReRAM cell while the programming voltage is applied across the memory cell, and decreasing the programming current as a function of a rise in programming current.
A ReRAM cell array has rows and columns and includes first and second complementary bit lines for each row, a first, second and third word lines for each column and a source bit line for each row. A ReRAM cell at each row and column includes a first resistive memory element, its first end connected to the first complementary bit line of its row, a p-channel transistor, its source connected to a second end of the first resistive memory element, its drain connected to a switch node, its gate connected to the first word line of its column, a second resistive memory element, its first end connected to the second complementary bit line of its row, an n-channel transistor, its source connected to a second end of the second resistive memory element, its drain connected to the switch node, its gate connected to the second word line of its column, and a programming transistor having a drain connected to the switch node, a source connected to the source bit line of its row and a gate connected to the third word line of its column.
A ReRAM cell array has having at least one row and one column includes first and second complementary bit lines for each row, a word line, a p-word line, and an n-word line for each column. A ReRAM cell at each row and column of the array includes a first ReRAM device, its first end connected to the first complementary bit line of its row, a p-channel transistor, its source connected to a second end of the first ReRAM device, its drain connected to a switch node, its gate connected to the p-channel word line of its column, a second ReRAM device, its first end connected to the second complementary bit line of its row, an n-channel transistor, its source connected to a second end of the second ReRAM device, its drain connected to the switch node, its gate connected to the n-channel word line of its column.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H03K 19/094 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
48.
FPGA RAM blocks optimized for use as register files
A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
A pair of adjacent ReRAM cells in an array includes a first bit line for a row of the array, a second bit line for the row of the array, a p-channel word line associated with two adjacent columns in the array, and an n-channel word line associated with the two adjacent columns. A pair of ReRAM cells in the adjacent columns in the row each includes a switch node, a first ReRAM device connected between the first bit line and the source of a p-channel transistor. The drain of the p-channel transistor is connected to the switch node, and its gate is connected to the p-channel word line. A second ReRAM device is connected between the second bit line and the source of an n-channel transistor. The drain of the n-channel transistor is connected to the switch node, and its gate is connected to the n-channel word line.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 23/528 - Layout of the interconnection structure
51.
LOW LEAKAGE RESISTIVE RANDOM ACCESS MEMORY CELLS AND PROCESSES FOR FABRICATING SAME
A resistive random access memory device is formed in an integrated circuit between a first metal layer and a second metal layer and includes a first barrier layer disposed over the first metal layer, a tunneling dielectric layer disposed over the first barrier layer, a solid electrolyte layer disposed over the tunneling dielectric layer, an ion source layer disposed over the solid electrolyte layer, and a second barrier layer disposed over the ion source layer.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H03K 19/094 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 23/00 - Details of semiconductor or other solid state devices
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
54.
Apparatus and methods for in-application programming of flash-based programmable logic devices
An architecture disposed in an integrated circuit for in-application programming of flash-based programmable logic devices includes a processor coupled to a processor system bus. An I/O peripheral is coupled to the processor over the system bus and is also coupled to an off-chip data source. A programmable logic device fabric includes flash-based programmable devices. A program controller is coupled to the flash-based programmable devices. An in-application programming controller is coupled to the program controller and is coupled to the processor over the system bus.
A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at an output signal frequency, and a phase comparator configured to compare the output signal or a signal derived from the output signal, with a reference signal at a reference signal frequency or a signal derived from the reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator. A frequency error measuring circuit produces a frequency error signal that directly represents a frequency difference between the output signal frequency and the reference signal frequency. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and providing the combined control signals to the digital controlled oscillator.
H03L 7/00 - Automatic control of frequency or phaseSynchronisation
H03L 7/10 - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
56.
Circuit and method to detect failure of speed estimation/speed measurement of a multi-phase AC motor
A method for detecting failure of speed measurement of a multi-phase AC motor includes (1) sensing current drawn by the motor, (2) sensing voltage magnitude supplied to the motor, (3) measuring motor speed, (4) calculating motor speed, (5) determining whether the difference between the measured motor speed and the calculated motor speed is greater than a predetermined threshold, if the difference between the measured motor speed and the calculated motor speed is not greater than a predetermined threshold, repeating (1) through (5), if the difference between the measured motor speed and the calculated motor speed is greater than a predetermined threshold, indicating a fault, if a fault is indicated, performing a predetermined number of restart attempts, if the motor is successfully restarted, repeating (1) through (5), if the motor is not successfully restarted, indicating a restart failure.
A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
58.
HYBRID PHASE LOCKED LOOP HAVING WIDE LOCKING RANGE
A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at a frequency. A phase comparator compares the output signal, or a signal derived therefrom, with a reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator from an output of the phase comparator. A frequency error measuring circuit coupled to the output of the phase comparator produces a frequency error signal. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and provides the combined control signals to the digital controlled oscillator.
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
59.
Hybrid phase locked loop having wide locking range
A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at a frequency. A phase comparator compares the output signal, or a signal derived therefrom, with a reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator from an output of the phase comparator. A frequency error measuring circuit coupled to the output of the phase comparator produces a frequency error signal. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and provides the combined control signals to the digital controlled oscillator.
H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/10 - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
A push-pull resistive random access memory cell circuit includes an output node, a word line, and first and second bit lines. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
A hybrid input/output pad driver includes an input node in a first voltage supply domain coupled to a p-device driver in the second voltage supply domain and an n-device driver in the second voltage domain. A p-channel pullup transistor is coupled between a voltage potential in a third voltage domain and an input/output pad. Its gate is coupled to the output of the p-device driver. An n-channel pulldown transistor is coupled between ground and the input/output pad. Its gate is coupled to the output of the n-device driver. An n-channel pullup transistor has a source coupled to the input/output pad, a drain coupled to the voltage potential in the third voltage supply domain. An inverter in the second voltage supply domain is programmably connectable between the output of the p-driver circuit and the gate of the n-channel pullup transistor.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
A r a level shifter circuit includes a first p-channel kick transistor connected directly across a first cross-coupled p-channel transistor, a second p-channel kick transistor connected directly across a second cross-coupled p-channel transistor, a first gate drive circuit coupled to the gate of the first p-channel kick transistor and configured to turn on first p-channel kick transistor to pull up the first output node in response to a rising edge of a signal at the input node, and a second gate drive circuit coupled to the gate of the second p-channel kick transistor and configured to turn on second p-channel kick transistor to pull up the second output node in response to a falling edge of a signal at the input node.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
65.
High voltage device fabricated using low-voltage processes
A method for fabricating a high-voltage transistor on a semiconductor substrate includes defining and forming shallow trench isolation regions for all of the transistors, defining and forming well regions for all of the transistors, forming a gate oxide layer in the well regions for all of the transistor, forming gates for all of the transistors over the gate oxide layer, implanting a dopant to form lightly-doped drain regions for all of the transistors, the lightly-doped drain regions for at least drains of the high-voltage transistors being spaced apart from an inner edge of the shallow trench isolation regions, forming gate spacers at sides of the gates of all of the transistors, and implanting a dopant to form sources and drains for all of the transistors, the drains of the high-voltage transistors being formed completely surrounded by the lightly-doped drain regions of the high-voltage transistors.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A multi-state static RAM cell includes N NOR gates. Each NOR gate has N−1 inputs and one output. The output of each NOR gate is coupled to a different bit line. Each NOR gate has its inputs connected to the outputs of each of the other NOR gates.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
A non-volatile memory cell includes a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel and an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel. In at least one of the p-channel non-volatile transistor and the n-channel non-volatile transistor, a lightly-doped drain region extends from the drain into the channel.
H01L 27/11521 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 23/528 - Layout of the interconnection structure
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
68.
Security method and apparatus to prevent replay of external memory data to integrated circuits having only one-time programmable non-volatile memory
A method for generating a secure nonce using a one-time programmable (OTP) memory within an integrated circuit to provide persistence, the method including randomly selecting k currently-unprogrammed bits in the OTP memory, creating a data set using data derived from current contents of the OTP memory altered by changing the states of the k currently-unprogrammed bits of the OTP memory, and employing as the secure nonce the data set or data derived from the data set. The selected k bits are programmed in the OTP memory.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
A circuit internal to a programmable integrated circuit for preventing laser interrogation of the programmable integrated circuit includes a sense resistor connected between a deep n-well and a source of bias voltage for the deep n-well. A voltage-sensing circuit is coupled across the sense resistor to measure voltage across the sense resistor. A tamper trigger circuit responsive to the voltage sensing circuit generates a tamper signal in response to a voltage sensed in the voltage sensing circuit having a magnitude greater than a threshold value.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
71.
Identifying integrated circuit origin using tooling signature
A method for determining if an individual integrated circuit was manufactured using an individual instance of tooling includes collecting from the individual integrated circuit first data representing at least one attribute that varies as a function of the tooling used to manufacture the individual integrated circuit and second data identifying the integrated circuit as having been manufactured using the individual instance of tooling. The first data is compared to a signature of the individual instance of tooling identified by the second data. The signature is derived from the at least one attribute measured from a population of integrated circuits that were manufactured using the individual instance of tooling. The individual integrated circuit is identified as having been manufactured using the individual instance of tooling identified in the second data collected from the individual integrated circuit if the first data correlates to the signature by a predetermined threshold.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
A layout arrangement for a resistive random access memory cell includes an active area, a polysilicon row address line over the active region, a metal column address line running orthogonal to the row address line and having an active region contact portion extending over the active region and having a contact to the active region. A metal output line runs parallel to the column address line over the active region. A first cell contact region intersects with the output line and has a contact to the active region. A first metal cell contact region forms an intersection with the first cell contact region. A first resistive random access memory device is formed at the intersection of the first cell contact region and the output line. A second resistive random access memory device is formed at the intersection of the first cell contact region and the first cell contact region.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
73.
Circuit and method for reducing BVii on highly overdriven devices
An integrated circuit is formed on a p-type semiconductor substrate connected to ground potential. A deep n-well is disposed in the p-type substrate. A p-well is disposed in the deep n-well. An n+ drain region and an n+ source region are disposed in the p-well, the n+ source region connected to a common potential. A p-type contact is disposed in the p-well and is connected to ground potential through a resistor.
H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A gate-boosting transmission gate includes an input node and an output node. An n-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the n-channel transistor having a low threshold. A p-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the p-channel transistor having a very low threshold.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 17/0412 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
75.
Methods for controlling the use of intellectual property in individual integrated circuit devices
A method for controlling the use of intellectual property (IP) in an individual integrated circuit includes loading data including the IP into the individual integrated circuit, loading an IP license certificate into the individual integrated circuit, the certificate including identification of the IP authorized for the individual integrated circuit, determining inside the individual integrated circuit whether the IP is authorized for the individual integrated circuit, enabling operation of the individual integrated circuit if the IP circuit is authorized for use in the individual integrated circuit, and imposing a penalty on operation of the individual integrated circuit if the IP is not authorized for use in the individual integrated circuit.
G06F 21/51 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
A layout arrangement for a resistive random access memory cell includes an active area, a polysilicon row address line over the active region, a metal column address line running orthogonal to the row address line and having an active region contact portion extending over the active region and having a contact to the active region. A metal output line runs parallel to the column address line over the active region. A first cell contact region intersects with the output line and has a contact to the active region. A first metal cell contact region forms an intersection with the first cell contact region. A first resistive random access memory device is formed at the intersection of the first cell contact region and the output line. A second resistive random access memory device is formed at the intersection of the first cell contact region and the first cell contact region.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
77.
HIGH VOLTAGE DEVICE FABRICATED USING LOW-VOLTAGE PROCESSES
A high-voltage transistor includes an active region including a diffused region of a first conductivity type defined by inner edges of a border of shallow trench isolation. Gate having side edges and end edges is disposed over the active region. Spaced apart source and drain regions of a second conductivity type opposite the first conductivity type are disposed in the active region outwardly with respect to the side edges of the gate. Lightly-doped regions of the second conductivity type more lightly-doped than the source and drain regions surround the source and drain regions and extend inwardly between the source and drain regions towards the gate to define a channel, and outwardly towards all of the inner edges of the shallow trench isolation. Outer edges of the lightly-doped region from at least the drain region are spaced apart from the inner edges of the shallow trench isolation.
A high-voltage transistor includes an active region including a diffused region of a first conductivity type defined by inner edges of a border of shallow trench isolation. A gate having side edges and end edges is disposed over the active region. Spaced apart source and drain regions of a second conductivity type opposite the first conductivity type are disposed in the active region outwardly with respect to the side edges of the gate. Lightly-doped regions of the second conductivity type more lightly-doped than the source and drain regions surround the source and drain regions and extend inwardly between the source and drain regions towards the gate to define a channel, and outwardly towards all of the inner edges of the shallow trench isolation. Outer edges of the lightly-doped region from at least the drain region are spaced apart from the inner edges of the shallow trench isolation.
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
79.
Method of improving FPGA security using authorization codes
A method for securely programming a population of authorized FPGAs includes defining the population of authorized FPGAs, generating an encrypted configuration bitstream for the population of authorized FPGAs, generating an individual Authorization Code for each FPGA in the population of authorized FPGAs, feeding the individual Authorization Codes into the FPGAs in the population of FPGAs, feeding the encrypted configuration bitstream into all of the FPGAs in the population of FPGAs, and in each FPGA using the Authorization Code to decrypt the encrypted configuration bitstream to program the FPGA.
H04L 29/06 - Communication control; Communication processing characterised by a protocol
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
A method for fast data erasing an FPGA including a programmable logic core controlled by a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, which includes detecting tampering with the FPGA, disconnecting power from the programmable logic core, and simultaneously programming the n-channel device and erasing the p-channel device in all cells.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
G06F 12/14 - Protection against unauthorised use of memory
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
81.
SONOS FPGA architecture having fast data erase and disable feature
A method for fast data erasing an FPGA including a programmable logic core controlled by a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, which includes detecting tampering with the FPGA, disconnecting power from the programmable logic core, and simultaneously programming the n-channel device and erasing the p-channel device in all cells.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
A method for programming a cluster-based field programmable gate array (FPGA) device includes providing a netlist and cluster size information, translating the netlist into a hypergraph, partitioning the hypergraph into multiple partitions and optimizing the Rent characteristic, translating the partitions into clusters, placing the clusters on the FPGA device, routing interconnects using a pre-fabricated routing resource on the FPGA device, generating a programming bitstream in response to the placing and routing, and providing the programming bitstream to the FPGA device to realize the user design.
Method for securely booting target processor in target system using a secure root of trust to verify a returned message authentication code recreated by the target processor
A method for securely booting a target processor in a target system from a secure root of trust includes computing a message authentication code from boot code to be provided to the target processor, including an obfuscated algorithm for recreating the message authentication code in the target processor, serving the boot code to the target processor, executing the boot code to recreate the message authentication code in the target processor, serving the message authentication code back to the root of trust, comparing the returned message authentication code with the message authentication code generated in the root of trust, continuing execution of the boot code data if the returned message authentication code matches the message authentication code, and applying at least one penalty to the target system if the returned message authentication code does not match the message authentication code generated in the root of trust.
G06F 9/00 - Arrangements for program control, e.g. control units
G06F 15/177 - Initialisation or configuration control
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material. Spaced-apart source and drain regions are disposed in the active region, forming a channel therebetween. A polysilicon gate is disposed above, aligned with, and insulated from the channel region. A p-type isolation ring is disposed in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region. A body contact is disposed in the p-type isolation ring.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
85.
System on a chip FPGA spatial debugging using single snapshot
A method for performing on-chip spatial debugging of a user circuit programmed into a user-programmable integrated circuit includes halting an internal clock driving synchronous logic elements in the integrated circuit and reading the states of all synchronous logic elements programmed into the integrated circuit while the internal clock is halted. An interrupt to an embedded processor in the integrated circuit running a user application can also be generated. The output of at least one synchronous logic element can be forced to a desired state while the internal clock is halted. The clock can then be restarted or stepped.
G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
A method for automatically refreshing a non-volatile memory array in the background without memory interruption includes selecting an unrefreshed segment of the memory, reading data from each row in the selected segment during memory dead time and storing the data read from each row in a local temporary storage memory until an entire segment is read out, remapping all memory addresses in the selected segment to the temporary storage memory, isolating column lines in the selected segment from global column lines, erasing the data in the selected segment without disturbing the column lines, rewriting memory data in each row of the selected segment, remapping all memory addresses in the selected segment to the memory, and repeating the process until all segments have been refreshed.
G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 11/23 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using electrostatic storage on a common layer, e.g. Forrester-Haeff tubes
87.
Non-volatile push-pull non-volatile memory cell having reduced operation disturb and process for manufacturing same
A non-volatile memory cell includes a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel and an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel. In at least one of the p-channel non-volatile transistor and the n-channel non-volatile transistor, a lightly-doped drain region extends from the drain into the channel.
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
A resistive random access memory cell formed in an integrated circuit includes first and second resistive random access memory devices, each including an anode and a cathode. The anode of the second resistive random access memory device is connected to the anode of the first resistive random access memory device. A programming transistor has a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anodes of the first and second resistive random access memory devices, and a gate connected to a program-enable node.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
89.
Non-volatile programmable memory cell and array for programmable logic array
A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
An integrated programmable logic circuit having a read/write probe includes a plurality of programmable logic circuits having internal circuit nodes and a plurality of flip flops, each having an asynchronous data input line, an asynchronous load line, and a data output connected to an internal circuit node, a probe-data line, an address circuit for selecting one of the internal circuit nodes, a read-probe enable line for selectively coupling the selected one of the internal circuit nodes to the probe-data line, a data input path to the asynchronous data input line of each flip flop, a write- probe data input path to the asynchronous data input line of each flip flop, a write- probe enable line, and selection circuitry, responsive to the address circuit and the write-probe enable line, to couple one of the data input path and the write-probe data input path to the asynchronous data input of a selected flip flop.
An integrated circuit includes a clock input, a first output, and a second output. A programmable pulse generator has a programmable pulse counter coupled to the clock input at least one control input for receiving count information. A fixed delay element is coupled to the programmable pulse counter. A programmable delay element is coupled to the programmable pulse counter and has at least one control input for receiving delay information. A first multiplexer is coupled to the fixed delay element, the programmable delay element and to the first output. A second multiplexer is coupled to the programmable delay element, the output of the fixed delay element and the second output.
An integrated programmable logic circuit having a read/write probe includes a plurality of programmable logic circuits having internal circuit nodes and a plurality of flip flops, each having an asynchronous data input line, an asynchronous load line, and a data output connected to an internal circuit node, a probe-data line, an address circuit for selecting one of the internal circuit nodes, a read-probe enable line for selectively coupling the selected one of the internal circuit nodes to the probe-data line, a data input path to the asynchronous data input line of each flip flop, a write-probe data input path to the asynchronous data input line of each flip flop, a write-probe enable line, and selection circuitry, responsive to the address circuit and the write-probe enable line, to couple one of the data input path and the write-probe data input path to the asynchronous data input of a selected flip flop.
A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material. Spaced-apart source and drain regions are disposed in the active region, forming a channel therebetween. A polysilicon gate is disposed above, aligned with, and insulated from the channel region. A p-type isolation ring is disposed in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
94.
COMPACT TID HARDENING NMOS DEVICE AND FABRICATION PROCESS
A radiation-hardened transistor is formed in a p-type semiconductor body having an active region doped to a first level and surrounded by a dielectric filled shallow trench isolation region. N-type source/drain regions are disposed in the active region and spaced apart to define a channel. A gate is disposed above the channel, and is self-aligned with the source/drain regions. First and second p-type regions are disposed in the p-type semiconductor body on either side of one of the source/drain regions and are doped to a second level higher than the first doping level. The first and second p-type regions are self aligned with and extend outwardly from a first side edge of the gate. The ends of the gate extend past the first and second p-type regions.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/336 - Field-effect transistors with an insulated gate
95.
Apparatus and methods for a tamper resistant bus for secure lock bit transfer
A tamper-resistant bus architecture for secure lock bit transfer in an integrated circuit includes a nonvolatile memory having an n-bit storage region for storing encoded lock bits, A plurality of read access circuits are coupled to the nonvolatile memory. An n-bit tamper-resistant bus is coupled to the read access circuits. A decoder is coupled to the tamper-resistant bus. A k-bit decoded lock signal bus is coupled to the decoder. A controller is coupled to the k-bit decoded lock signal bus.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
96.
FPGA RAM blocks optimized for use as register files
A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
97.
Non-volatile memory array architecture optimized for hi-reliability and commercial markets
A sense amplifier arrangement includes a first sense amplifier having a first input and a second input. A second sense amplifier has a first input and a second input. A switching circuit is configured to selectively couple the first input of the first sense amplifier to a first bit line in the array and the second input of the first sense amplifier to a first bit line in the array to selectively couple the first input of the first sense amplifier to the first bit line in the array, the first input of the second sense amplifier to the second bit line in the array, and the second inputs of the first and second sense amplifiers to a reference voltage.
A sense amplifier arrangement includes a first sense amplifier having a first input and a second input. A second sense amplifier has a first input and a second input. A switching circuit is configured to selectively couple the first input of the first sense amplifier to a first bit line in the array and the second input of the first sense amplifier to a first bit line in the array to selectively couple the first input of the first sense amplifier to the first bit line in the array, the first input of the second sense amplifier to the second bit line in the array, and the second inputs of the first and second sense amplifiers to a reference voltage.
A resistive random access memory cell formed in an integrated circuit includes a first resistive random access memory device including an anode and a cathode, a second resistive random access memory device including an anode and a cathode, the cathode of the second resistive random access memory device connected to the anode of the first resistive random access memory device, a programming transistor having a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anode of the first resistive random access memory device and the cathode of the second resistive random access memory device, and a gate connected to a program-enable nod, and at least one switch transistor having a gate connected to the anode of the first resistive random access memory device and the cathode of the second resistive random access memory device.
A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
