An area efficient readable and resettable configuration memory latch maintains latch data integrity through read and write operations and includes a non-terminated inout bit line (BL). During write operations, enabled by a Word Line Write (WLW) signal, the non-terminated inout BL drives data to be written, while, during read operations, enabled by a Word Line Read (WLR) signal, the state of the BL is indicative of a data stored in the latch. A pull-down network is activated when the WLR signal is asserted and the stored data is logic one and, when activated, operates to pull down the BL to logic zero; the pull-down network is inactive otherwise. A weak pull-up operates to pull up the BL when the pull-down network is inactive. A sensing block is configured to sense the state of the BL when the WLR signal and a read enable signal are both asserted.
H03K 19/1776 - Détails structurels des ressources de configuration pour les mémoires
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
2.
PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY
A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.
G11C 29/12 - Dispositions intégrées pour les tests, p. ex. auto-test intégré [BIST]
G11C 29/20 - Dispositifs pour la génération d'adressesDispositifs pour l'accès aux mémoires, p. ex. détails de circuits d'adressage utilisant des compteurs ou des registres à décalage à rétroaction linéaire [LFSR]
H03K 19/173 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
H03K 19/17728 - Blocs logiques reconfigurables, p. ex. tables de consultation
3.
SECTIONAL CONFIGURATION FOR PROGRAMMABLE LOGIC DEVICES
A bit line (BL) may be coupled at a first end to a BL driver (BLD) and at a second end to a BL receiver (BLR). The BL include a plurality of sections and each BL section may be coupled to at least one corresponding sectional configuration memory latch controlled by: at least one sectional word line write (WLW-k) signal, which when asserted enables data to be written into the at least one corresponding sectional configuration memory latch when a corresponding tri-stateable sectional driver (SD-k) is activated, and at least one sectional word line read (WLR-k) signal, which when asserted enables data to be from the at least one corresponding sectional configuration memory latch when the corresponding sectional pull-up (PU-k) is activated.
H03K 19/1776 - Détails structurels des ressources de configuration pour les mémoires
H03K 19/17736 - Détails structurels des ressources de routage
H03K 19/17704 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle les fonctions logiques étant réalisées par l'interconnexion des lignes et des colonnes
4.
Area-efficient configuration latch for programmable logic device
An area efficient input terminated readable and resettable configuration memory latch is disclosed. A pull-up network and a pair of pull-down networks operate to set the value of an internal node based, in part, on the state of the input terminated bit line and a word line write input. The internal node is inverted to form the output of the configuration memory latch. A reset line operates to reset the latch and a reset cycle is initiated prior to each write cycle. In some embodiments, the configuration memory latch includes a scan mode input, which, when asserted, facilitates automated testing of a programmable logic device that includes the configuration memory latch. Asserting the scan mode input enables Design for Test functionality. A sensing block is configured to sense the state of the bit when a word line read signal and a read enable signal are both asserted.
G11C 7/00 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/12 - Circuits de commande de lignes de bits, p. ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, circuits d'égalisation, pour lignes de bits
G11C 8/08 - Circuits de commande de lignes de mots, p. ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots
H03K 19/017 - Modifications pour accélérer la commutation dans les circuits à transistor à effet de champ
5.
Programmable logic device with design for test functionality
A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.
G11C 29/20 - Dispositifs pour la génération d'adressesDispositifs pour l'accès aux mémoires, p. ex. détails de circuits d'adressage utilisant des compteurs ou des registres à décalage à rétroaction linéaire [LFSR]
G11C 29/12 - Dispositions intégrées pour les tests, p. ex. auto-test intégré [BIST]
H03K 19/173 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
H03K 19/17728 - Blocs logiques reconfigurables, p. ex. tables de consultation
An area efficient readable and resettable configuration memory latch is disclosed that maintains latch data integrity through read and write operations and includes a non-terminated inout bit line (BL). During write operations, enabled by a Word Line Write (WLW) signal, the non-terminated inout BL drives data to be written, while, during read operations, enabled by a Word Line Read (WLR) signal, the state of the BL is indicative of a data stored in the latch. A pull-down network is activated when the WLR signal is asserted and the stored data is logic one and, when activated, operates to pull down the BL to logic zero; the pull-down network is inactive otherwise. A weak pull-up operates to pull up the BL when the pull-down network is inactive. A sensing block is configured to sense the state of the BL when the WLR signal and a read enable signal are both asserted.
H03K 19/1776 - Détails structurels des ressources de configuration pour les mémoires
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
7.
Sectional configuration for programmable logic devices
A bit line (BL) may be coupled at a first end to a BL driver (BLD) and at a second end to a BL receiver (BLR). The BL include a plurality of sections and each BL section may be coupled to at least one corresponding sectional configuration memory latch controlled by: at least one sectional word line write (WLW-k) signal, which when asserted enables data to be written into the at least one corresponding sectional configuration memory latch when a corresponding tri-stateable sectional driver (SD-k) is activated, and at least one sectional word line read (WLR-k) signal, which when asserted enables data to be from the at least one corresponding sectional configuration memory latch when the corresponding sectional pull-up (PU-k) is activated.
H03K 19/1776 - Détails structurels des ressources de configuration pour les mémoires
H03K 19/17704 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle les fonctions logiques étant réalisées par l'interconnexion des lignes et des colonnes
H03K 19/17736 - Détails structurels des ressources de routage
8.
Switchable power islands having configurably on routing paths
A programmable logic device uses power island based design partitioning. Each power islands includes a plurality of programmable logic cells and a programmable routing network configurable to interconnect the plurality of programmable logic cells and configurable to interconnect with at least one other power island. When a power island is in an OFF state, the programmable logic cells within the power island are powered OFF. Feed-through routing connectors in the power island, however, may be statically or dynamically powered ON independently of the powered OFF state of the power island.
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
A sensor hub includes a bit packer that receives sensor data from a plurality of sensors and bit packs the sensor data so that the sensor ID, time stamp and each axis of the measured data is stored contiguously. The bit packer may compress the sensor data by removing the sensor ID and/or the time stamp in the sensor data. The bit packed sensor data is stored in batching memory. A bit unpacker receives the sensor data from the batching memory and unpacks the sensor data, e.g., so that the sensor ID, time stamp and each axis of the measured data is stored in its own word. Additionally, the bit unpacker may decompress the bit packed sensor data by reinserting the sensor ID and/or time stamp in the sensor data.
G01D 9/32 - Enregistrement de valeurs mesurées produisant un ou plusieurs enregistrements, chaque enregistrement étant celui des valeurs de plusieurs variables différentes comprenant un élément enregistreur commun pour plusieurs variables
H03M 7/30 - CompressionExpansionÉlimination de données inutiles, p. ex. réduction de redondance
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 9/46 - Dispositions pour la multiprogrammation
G01D 21/02 - Mesure de plusieurs variables par des moyens non couverts par une seule autre sous-classe
End-user software is used to select lists of values of control signals from a predetermined design of a processor, and a unique value of an opcode is assigned to each selected list of values of control signals. The assignments, of opcode values to lists of values of control signals, are used to create a new processor design customized for the end-user software, followed by synthesis, place and route, and netlist generation based on the new processor design, followed by configuring an FPGA based on the netlist, followed by execution of the end-user software in customized processor implemented by the FPGA. Different end-user software may be used as input to generate different assignments, of opcode values to lists of control signal values, followed by generation of different netlists. The different netlists may be used at different times, to reconfigure the same FPGA, to execute different end-user software optimally at different times.
A routing network is associated with a logic island in a logic block of a programmable logic device and includes switches for each of feedback, street, and highway networks. Some of the switches include multiple stages. The street network switch receives the signals from the feedback network switch, signals from neighboring highway network switches, and direct feedback from selected logic island outputs and provides outputs to the logic island. The street network switch includes multiple stages, where outputs to the logic island are provided directly by each stage in the street network switch. The output terminals of a first stage of the street network switch that are connected to the logic island are also connected to the second stage of the street network switch. The second stage of the street network switch receives feedback output signals from the feedback network and directly from the associated logic island.
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface
A wrist worn heart rate monitor includes a photoplethysmogram (PPG) sensor and an inertial sensor. Signals from the inertial sensor are used to identify and remove noise from the PPG signals. An initial heart rate value is selected from a number of heart rate candidates that remain in the resulting PPG spectrum and is used to track the heart rate of the user. The PPG spectrum is monitored while tracking the heart rate to determine if the selected initial heart rate value is in error. The PPG spectrum may be monitored by determining a correlation of possible heart rate candidates in each PPG spectrum to the previous heart rate candidates and resetting the heart rate value accordingly. Additionally or alternatively, the PPG spectrum may be monitored by determining when only a single heart rate candidate is present in consecutive PPG spectra and resetting the heart rate value accordingly.
A wrist worn pedometer includes a multiple axis inertial sensor. Signals from each axis of the multiple axis inertial sensor are received and are separately analyzed to determine which axis is producing a stable periodic signal, which is selected as the counting axis, i.e., the axis to be used for counting steps. Additionally, the pedometer determines whether the counting axis is registering arm movement or footsteps. The user's steps are counted based on the detected events, e.g., detected peaks or intervals between peaks, on the signal from the counting axis. One step per detected event is counted if the counting axis is registering footsteps and two steps per detected event are counted if the counting axis is registering arm movement. If the stability of the selected counting axis is lost, another axis is selected as the counting axis if it is producing a stable periodic signal.
G01C 22/00 - Mesure de la distance parcourue sur le sol par des véhicules, des personnes, des animaux ou autres corps solides en mouvement, p. ex. en utilisant des odomètres ou en utilisant des podomètres
G01C 21/12 - NavigationInstruments de navigation non prévus dans les groupes en utilisant des mesures de la vitesse ou de l'accélération exécutées à bord de l'objet navigantNavigation à l'estime
A logic cell in a programmable logic device receives an external signal from a routing network that serves as a select signal that selects a combinatorial logic signal via a first multiplexor as well as a data input to a second multiplexor. The second multiplexor selects between the combinatorial logic signal and the external signal and provides an output signal to a register. Accordingly, the logic cell has the flexibility to support a combinatorial and/or sequential function using minimal routing resources. A third multiplexor may select the output from the register or another signal as the output signal from the logic cell. A clock signal to the register may be gated off when the register output is not selected as the output signal, thereby reducing dynamic power consumption. The programmable logic device may include a number of super logic cells, each of which includes a plurality of logic cells.
H03K 19/173 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
H03K 19/00 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion
A routing network is associated with a logic island in a logic block of a programmable logic device and includes switches for each of feedback, street, and highway and clock networks. Some of the switches include multiple stages. The feedback network switch receives signals from the logic island as well as from neighboring logic blocks and provides an output to one or more stages of the street network switch. The street network switch receives the signals from the feedback network switch and signals from neighboring highway network switches and provides an output to the logic island. A clock network switch may receive dedicated clock signals or high fan out signals as inputs and provides outputs to the street network switch. The highway network switch receives signals from the logic island and from neighboring highway network switches and provides an output to neighboring highway network switches.
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface
09 - Appareils et instruments scientifiques et électriques
Produits et services
(1) Integrated circuits, computer program stored for collecting, assimilating, and sharing large amounts of sensor data, software and firmware for designing with integrated circuits and for programming programmable integrated circuits.
09 - Appareils et instruments scientifiques et électriques
Produits et services
(1) Integrated circuits, computer program stored for collecting, assimilating, and sharing large amounts of sensor data, software and firmware for designing with integrated circuits and for programming programmable integrated circuits.
09 - Appareils et instruments scientifiques et électriques
38 - Services de télécommunications
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Integrated circuits, software algorithms, software and firmware for designing with integrated circuits and for programming programmable integrated circuits; Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments; Apparatus and instruments for conducting, switching, transforming, accumulating, regulating or controlling electricity; Apparatus for recording, transmission or reproduction of sound or images; Magnetic data carriers, recording discs; Compact discs, DVDs and other digital recording media; Mechanisms for coin-operated apparatus; Cash registers, calculating machines, data processing equipment, computers; Computer software; Fire-extinguishing apparatus. Telecommunications. Scientific and technological services and research and design relating thereto; Industrial analysis and research services; Design and development of computer hardware and software.
09 - Appareils et instruments scientifiques et électriques
38 - Services de télécommunications
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Integrated circuits, software algorithms, software and firmware for designing with integrated circuits and for programming programmable integrated circuits; Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments; Apparatus and instruments for conducting, switching, transforming, accumulating, regulating or controlling electricity; Apparatus for recording, transmission or reproduction of sound or images; Magnetic data carriers, recording discs; Compact discs, DVDs and other digital recording media; Mechanisms for coin-operated apparatus; Cash registers, calculating machines, data processing equipment, computers; Computer software; Fire-extinguishing apparatus. Telecommunications. Scientific and technological services and research and design relating thereto; Industrial analysis and research services; Design and development of computer hardware and software.
An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.
H03K 19/173 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
Embodiments of the present invention provide a unique capability of implementing a pair of pseudo-PHY interfaces using a bridge. From the host and device perspectives, the host and device communicate through a PHY interface. The bridge, however, avoids actually using a USB PHY interface. This PHY-less bridge allows communication between a host and a device at high speeds without high-power transceivers associated with a USB PHY interface. In accordance with the present invention, a host and a device may be coupled together using a PHY-less bridge using the same interface or translating between different interfaces by using a wrapper. Such PHY-less bridges include a UTMI-to-UTMI bridge, a UTMI-to-ULPI bridge, a ULPI-to-UTMI bridge and a ULPI-to-ULPI bridge, each avoiding the need for a USB PHY interface.
G06F 13/36 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs
G06F 3/00 - Dispositions d'entrée pour le transfert de données destinées à être traitées sous une forme maniable par le calculateurDispositions de sortie pour le transfert de données de l'unité de traitement à l'unité de sortie, p. ex. dispositions d'interface
G06F 15/16 - Associations de plusieurs calculateurs numériques comportant chacun au moins une unité arithmétique, une unité programme et un registre, p. ex. pour le traitement simultané de plusieurs programmes
H04J 3/16 - Systèmes multiplex à division de temps dans lesquels le temps attribué à chacun des canaux au cours d'un cycle de transmission est variable, p. ex. pour tenir compte de la complexité variable des signaux, pour adapter le nombre de canaux transmis
An implementation of an apparatus and method to generate a dynamically controlled clock is provided. The resulting clock reduces otherwise produced narrow clock pulses and allows for control from two separate control signals. A first control signal indicates a low power mode, for example a chip-wide low power mode. A second control signal indicates a user-selected mode to shutdown a selected clock.
Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic. Some embodiments of the present invention provide for a method for testing functional logic block of an application-specific standard product (ASSP) in a programmable logic device, the method comprising: storing an input value into a register; passing the input value from the register to combinatorial logic; producing an output value from the combinatorial logic; passing the output value from the combinatorial logic to the register; saving the output value in the register; and reading the output value out of the register.
An apparatus and method of reducing power consumption across a switch, such as an unprogrammed antifuse, is provided. The invention applies to antifuses, other switches such as transistor based switches, (e.g., FLASH, EEPROM and/or SRAM) and other devices exhibiting a leakage current, especially during a sleep or stand-by mode. During a sleep mode, such switches or other devices may be uncoupled from signals driving the switches, then terminals of each switch may be coupled to a common potential or allowed to float to a common potential thereby eliminating or reducing leakage currents through the switches.
G06F 7/38 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale
H03K 19/173 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
j, where j=m*2. The multiplexer functionality may be implemented using a programmable device having one or more macrocells, an inverter and switches such as antifuses.
G06F 7/38 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
28.
Adjustable interface buffer circuit between a programmable logic device and a dedicated device
An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.
H03K 19/173 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
A differential charge pump includes a transient reducing circuit that provides multiple switching current paths to reduce transients caused by the charge transfer as the charge pump is switched. The differential charge pump includes separate current sources in the transient reducing circuit that are switchably coupled to the non-active current source in the charge pump. In one embodiment, each current sources include a static current source and a variable current source that is controlled by a common mode feedback circuit. The variable current source may produce a current with less magnitude than the current produced by the static current source.
09 - Appareils et instruments scientifiques et électriques
16 - Papier, carton et produits en ces matières
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Computer hardware, computer firmware and computer software; computer peripherals; integrated circuits, gate arrays and computer software for design and development thereof; user and instruction manuals in electronic format. Printed matter; newspapers, magazines and periodical publications; brochures, catalogues and leaflets; user and instruction manuals; all the aforesaid goods relating to computer products and technology. Research, design and consultancy services relating to computer products; installation, support and maintenance services for computer software; computer programming.
